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hw/omap2.c : separate gptimer module
[qemu.git] / hw / omap2.c
blob5ad5a98070def4eb53b2cb421c28d5114b358227
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "blockdev.h"
22 #include "hw.h"
23 #include "arm-misc.h"
24 #include "omap.h"
25 #include "sysemu.h"
26 #include "qemu-timer.h"
27 #include "qemu-char.h"
28 #include "flash.h"
29 #include "soc_dma.h"
30 #include "audio/audio.h"
31
32 /* 32-kHz Sync Timer of the OMAP2 */
33 static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {
34 return muldiv64(qemu_get_clock(vm_clock), 0x8000, get_ticks_per_sec());
35 }
36
37 static void omap_synctimer_reset(struct omap_synctimer_s *s)
38 {
39 s->val = omap_synctimer_read(s);
40 }
41
42 static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
43 {
44 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
45
46 switch (addr) {
47 case 0x00: /* 32KSYNCNT_REV */
48 return 0x21;
49
50 case 0x10: /* CR */
51 return omap_synctimer_read(s) - s->val;
52 }
53
54 OMAP_BAD_REG(addr);
55 return 0;
56 }
57
58 static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
59 {
60 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
61 uint32_t ret;
62
63 if (addr & 2)
64 return s->readh;
65 else {
66 ret = omap_synctimer_readw(opaque, addr);
67 s->readh = ret >> 16;
68 return ret & 0xffff;
69 }
70 }
71
72 static CPUReadMemoryFunc * const omap_synctimer_readfn[] = {
73 omap_badwidth_read32,
74 omap_synctimer_readh,
75 omap_synctimer_readw,
76 };
77
78 static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
79 uint32_t value)
80 {
81 OMAP_BAD_REG(addr);
82 }
83
84 static CPUWriteMemoryFunc * const omap_synctimer_writefn[] = {
85 omap_badwidth_write32,
86 omap_synctimer_write,
87 omap_synctimer_write,
88 };
89
90 void omap_synctimer_init(struct omap_target_agent_s *ta,
91 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk)
92 {
93 struct omap_synctimer_s *s = &mpu->synctimer;
94
95 omap_synctimer_reset(s);
96 omap_l4_attach(ta, 0, l4_register_io_memory(
97 omap_synctimer_readfn, omap_synctimer_writefn, s));
98 }
99
100 /* Multichannel SPI */
101 struct omap_mcspi_s {
102 qemu_irq irq;
103 int chnum;
104
105 uint32_t sysconfig;
106 uint32_t systest;
107 uint32_t irqst;
108 uint32_t irqen;
109 uint32_t wken;
110 uint32_t control;
111
112 struct omap_mcspi_ch_s {
113 qemu_irq txdrq;
114 qemu_irq rxdrq;
115 uint32_t (*txrx)(void *opaque, uint32_t, int);
116 void *opaque;
117
118 uint32_t tx;
119 uint32_t rx;
120
121 uint32_t config;
122 uint32_t status;
123 uint32_t control;
124 } ch[4];
125 };
126
127 static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
128 {
129 qemu_set_irq(s->irq, s->irqst & s->irqen);
130 }
131
132 static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
133 {
134 qemu_set_irq(ch->txdrq,
135 (ch->control & 1) && /* EN */
136 (ch->config & (1 << 14)) && /* DMAW */
137 (ch->status & (1 << 1)) && /* TXS */
138 ((ch->config >> 12) & 3) != 1); /* TRM */
139 qemu_set_irq(ch->rxdrq,
140 (ch->control & 1) && /* EN */
141 (ch->config & (1 << 15)) && /* DMAW */
142 (ch->status & (1 << 0)) && /* RXS */
143 ((ch->config >> 12) & 3) != 2); /* TRM */
144 }
145
146 static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
147 {
148 struct omap_mcspi_ch_s *ch = s->ch + chnum;
149
150 if (!(ch->control & 1)) /* EN */
151 return;
152 if ((ch->status & (1 << 0)) && /* RXS */
153 ((ch->config >> 12) & 3) != 2 && /* TRM */
154 !(ch->config & (1 << 19))) /* TURBO */
155 goto intr_update;
156 if ((ch->status & (1 << 1)) && /* TXS */
157 ((ch->config >> 12) & 3) != 1) /* TRM */
158 goto intr_update;
159
160 if (!(s->control & 1) || /* SINGLE */
161 (ch->config & (1 << 20))) { /* FORCE */
162 if (ch->txrx)
163 ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
164 1 + (0x1f & (ch->config >> 7)));
165 }
166
167 ch->tx = 0;
168 ch->status |= 1 << 2; /* EOT */
169 ch->status |= 1 << 1; /* TXS */
170 if (((ch->config >> 12) & 3) != 2) /* TRM */
171 ch->status |= 1 << 0; /* RXS */
172
173 intr_update:
174 if ((ch->status & (1 << 0)) && /* RXS */
175 ((ch->config >> 12) & 3) != 2 && /* TRM */
176 !(ch->config & (1 << 19))) /* TURBO */
177 s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
178 if ((ch->status & (1 << 1)) && /* TXS */
179 ((ch->config >> 12) & 3) != 1) /* TRM */
180 s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
181 omap_mcspi_interrupt_update(s);
182 omap_mcspi_dmarequest_update(ch);
183 }
184
185 static void omap_mcspi_reset(struct omap_mcspi_s *s)
186 {
187 int ch;
188
189 s->sysconfig = 0;
190 s->systest = 0;
191 s->irqst = 0;
192 s->irqen = 0;
193 s->wken = 0;
194 s->control = 4;
195
196 for (ch = 0; ch < 4; ch ++) {
197 s->ch[ch].config = 0x060000;
198 s->ch[ch].status = 2; /* TXS */
199 s->ch[ch].control = 0;
200
201 omap_mcspi_dmarequest_update(s->ch + ch);
202 }
203
204 omap_mcspi_interrupt_update(s);
205 }
206
207 static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
208 {
209 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
210 int ch = 0;
211 uint32_t ret;
212
213 switch (addr) {
214 case 0x00: /* MCSPI_REVISION */
215 return 0x91;
216
217 case 0x10: /* MCSPI_SYSCONFIG */
218 return s->sysconfig;
219
220 case 0x14: /* MCSPI_SYSSTATUS */
221 return 1; /* RESETDONE */
222
223 case 0x18: /* MCSPI_IRQSTATUS */
224 return s->irqst;
225
226 case 0x1c: /* MCSPI_IRQENABLE */
227 return s->irqen;
228
229 case 0x20: /* MCSPI_WAKEUPENABLE */
230 return s->wken;
231
232 case 0x24: /* MCSPI_SYST */
233 return s->systest;
234
235 case 0x28: /* MCSPI_MODULCTRL */
236 return s->control;
237
238 case 0x68: ch ++;
239 case 0x54: ch ++;
240 case 0x40: ch ++;
241 case 0x2c: /* MCSPI_CHCONF */
242 return s->ch[ch].config;
243
244 case 0x6c: ch ++;
245 case 0x58: ch ++;
246 case 0x44: ch ++;
247 case 0x30: /* MCSPI_CHSTAT */
248 return s->ch[ch].status;
249
250 case 0x70: ch ++;
251 case 0x5c: ch ++;
252 case 0x48: ch ++;
253 case 0x34: /* MCSPI_CHCTRL */
254 return s->ch[ch].control;
255
256 case 0x74: ch ++;
257 case 0x60: ch ++;
258 case 0x4c: ch ++;
259 case 0x38: /* MCSPI_TX */
260 return s->ch[ch].tx;
261
262 case 0x78: ch ++;
263 case 0x64: ch ++;
264 case 0x50: ch ++;
265 case 0x3c: /* MCSPI_RX */
266 s->ch[ch].status &= ~(1 << 0); /* RXS */
267 ret = s->ch[ch].rx;
268 omap_mcspi_transfer_run(s, ch);
269 return ret;
270 }
271
272 OMAP_BAD_REG(addr);
273 return 0;
274 }
275
276 static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
277 uint32_t value)
278 {
279 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
280 int ch = 0;
281
282 switch (addr) {
283 case 0x00: /* MCSPI_REVISION */
284 case 0x14: /* MCSPI_SYSSTATUS */
285 case 0x30: /* MCSPI_CHSTAT0 */
286 case 0x3c: /* MCSPI_RX0 */
287 case 0x44: /* MCSPI_CHSTAT1 */
288 case 0x50: /* MCSPI_RX1 */
289 case 0x58: /* MCSPI_CHSTAT2 */
290 case 0x64: /* MCSPI_RX2 */
291 case 0x6c: /* MCSPI_CHSTAT3 */
292 case 0x78: /* MCSPI_RX3 */
293 OMAP_RO_REG(addr);
294 return;
295
296 case 0x10: /* MCSPI_SYSCONFIG */
297 if (value & (1 << 1)) /* SOFTRESET */
298 omap_mcspi_reset(s);
299 s->sysconfig = value & 0x31d;
300 break;
301
302 case 0x18: /* MCSPI_IRQSTATUS */
303 if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
304 s->irqst &= ~value;
305 omap_mcspi_interrupt_update(s);
306 }
307 break;
308
309 case 0x1c: /* MCSPI_IRQENABLE */
310 s->irqen = value & 0x1777f;
311 omap_mcspi_interrupt_update(s);
312 break;
313
314 case 0x20: /* MCSPI_WAKEUPENABLE */
315 s->wken = value & 1;
316 break;
317
318 case 0x24: /* MCSPI_SYST */
319 if (s->control & (1 << 3)) /* SYSTEM_TEST */
320 if (value & (1 << 11)) { /* SSB */
321 s->irqst |= 0x1777f;
322 omap_mcspi_interrupt_update(s);
323 }
324 s->systest = value & 0xfff;
325 break;
326
327 case 0x28: /* MCSPI_MODULCTRL */
328 if (value & (1 << 3)) /* SYSTEM_TEST */
329 if (s->systest & (1 << 11)) { /* SSB */
330 s->irqst |= 0x1777f;
331 omap_mcspi_interrupt_update(s);
332 }
333 s->control = value & 0xf;
334 break;
335
336 case 0x68: ch ++;
337 case 0x54: ch ++;
338 case 0x40: ch ++;
339 case 0x2c: /* MCSPI_CHCONF */
340 if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
341 omap_mcspi_dmarequest_update(s->ch + ch);
342 if (((value >> 12) & 3) == 3) /* TRM */
343 fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
344 if (((value >> 7) & 0x1f) < 3) /* WL */
345 fprintf(stderr, "%s: invalid WL value (%i)\n",
346 __FUNCTION__, (value >> 7) & 0x1f);
347 s->ch[ch].config = value & 0x7fffff;
348 break;
349
350 case 0x70: ch ++;
351 case 0x5c: ch ++;
352 case 0x48: ch ++;
353 case 0x34: /* MCSPI_CHCTRL */
354 if (value & ~s->ch[ch].control & 1) { /* EN */
355 s->ch[ch].control |= 1;
356 omap_mcspi_transfer_run(s, ch);
357 } else
358 s->ch[ch].control = value & 1;
359 break;
360
361 case 0x74: ch ++;
362 case 0x60: ch ++;
363 case 0x4c: ch ++;
364 case 0x38: /* MCSPI_TX */
365 s->ch[ch].tx = value;
366 s->ch[ch].status &= ~(1 << 1); /* TXS */
367 omap_mcspi_transfer_run(s, ch);
368 break;
369
370 default:
371 OMAP_BAD_REG(addr);
372 return;
373 }
374 }
375
376 static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
377 omap_badwidth_read32,
378 omap_badwidth_read32,
379 omap_mcspi_read,
380 };
381
382 static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
383 omap_badwidth_write32,
384 omap_badwidth_write32,
385 omap_mcspi_write,
386 };
387
388 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
389 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
390 {
391 int iomemtype;
392 struct omap_mcspi_s *s = (struct omap_mcspi_s *)
393 qemu_mallocz(sizeof(struct omap_mcspi_s));
394 struct omap_mcspi_ch_s *ch = s->ch;
395
396 s->irq = irq;
397 s->chnum = chnum;
398 while (chnum --) {
399 ch->txdrq = *drq ++;
400 ch->rxdrq = *drq ++;
401 ch ++;
402 }
403 omap_mcspi_reset(s);
404
405 iomemtype = l4_register_io_memory(omap_mcspi_readfn,
406 omap_mcspi_writefn, s);
407 omap_l4_attach(ta, 0, iomemtype);
408
409 return s;
410 }
411
412 void omap_mcspi_attach(struct omap_mcspi_s *s,
413 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
414 int chipselect)
415 {
416 if (chipselect < 0 || chipselect >= s->chnum)
417 hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
418
419 s->ch[chipselect].txrx = txrx;
420 s->ch[chipselect].opaque = opaque;
421 }
422
423 /* Enhanced Audio Controller (CODEC only) */
424 struct omap_eac_s {
425 qemu_irq irq;
426
427 uint16_t sysconfig;
428 uint8_t config[4];
429 uint8_t control;
430 uint8_t address;
431 uint16_t data;
432 uint8_t vtol;
433 uint8_t vtsl;
434 uint16_t mixer;
435 uint16_t gain[4];
436 uint8_t att;
437 uint16_t max[7];
438
439 struct {
440 qemu_irq txdrq;
441 qemu_irq rxdrq;
442 uint32_t (*txrx)(void *opaque, uint32_t, int);
443 void *opaque;
444
445 #define EAC_BUF_LEN 1024
446 uint32_t rxbuf[EAC_BUF_LEN];
447 int rxoff;
448 int rxlen;
449 int rxavail;
450 uint32_t txbuf[EAC_BUF_LEN];
451 int txlen;
452 int txavail;
453
454 int enable;
455 int rate;
456
457 uint16_t config[4];
458
459 /* These need to be moved to the actual codec */
460 QEMUSoundCard card;
461 SWVoiceIn *in_voice;
462 SWVoiceOut *out_voice;
463 int hw_enable;
464 } codec;
465
466 struct {
467 uint8_t control;
468 uint16_t config;
469 } modem, bt;
470 };
471
472 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
473 {
474 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
475 }
476
477 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
478 {
479 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
480 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
481 }
482
483 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
484 {
485 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
486 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
487 }
488
489 static inline void omap_eac_in_refill(struct omap_eac_s *s)
490 {
491 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
492 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
493 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
494 int recv = 1;
495 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
496
497 left -= leftwrap;
498 start = 0;
499 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
500 leftwrap)) > 0) { /* Be defensive */
501 start += recv;
502 leftwrap -= recv;
503 }
504 if (recv <= 0)
505 s->codec.rxavail = 0;
506 else
507 s->codec.rxavail -= start >> 2;
508 s->codec.rxlen += start >> 2;
509
510 if (recv > 0 && left > 0) {
511 start = 0;
512 while (left && (recv = AUD_read(s->codec.in_voice,
513 (uint8_t *) s->codec.rxbuf + start,
514 left)) > 0) { /* Be defensive */
515 start += recv;
516 left -= recv;
517 }
518 if (recv <= 0)
519 s->codec.rxavail = 0;
520 else
521 s->codec.rxavail -= start >> 2;
522 s->codec.rxlen += start >> 2;
523 }
524 }
525
526 static inline void omap_eac_out_empty(struct omap_eac_s *s)
527 {
528 int left = s->codec.txlen << 2;
529 int start = 0;
530 int sent = 1;
531
532 while (left && (sent = AUD_write(s->codec.out_voice,
533 (uint8_t *) s->codec.txbuf + start,
534 left)) > 0) { /* Be defensive */
535 start += sent;
536 left -= sent;
537 }
538
539 if (!sent) {
540 s->codec.txavail = 0;
541 omap_eac_out_dmarequest_update(s);
542 }
543
544 if (start)
545 s->codec.txlen = 0;
546 }
547
548 static void omap_eac_in_cb(void *opaque, int avail_b)
549 {
550 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
551
552 s->codec.rxavail = avail_b >> 2;
553 omap_eac_in_refill(s);
554 /* TODO: possibly discard current buffer if overrun */
555 omap_eac_in_dmarequest_update(s);
556 }
557
558 static void omap_eac_out_cb(void *opaque, int free_b)
559 {
560 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
561
562 s->codec.txavail = free_b >> 2;
563 if (s->codec.txlen)
564 omap_eac_out_empty(s);
565 else
566 omap_eac_out_dmarequest_update(s);
567 }
568
569 static void omap_eac_enable_update(struct omap_eac_s *s)
570 {
571 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
572 (s->codec.config[1] & 2) && /* AUDEN */
573 s->codec.hw_enable;
574 }
575
576 static const int omap_eac_fsint[4] = {
577 8000,
578 11025,
579 22050,
580 44100,
581 };
582
583 static const int omap_eac_fsint2[8] = {
584 8000,
585 11025,
586 22050,
587 44100,
588 48000,
589 0, 0, 0,
590 };
591
592 static const int omap_eac_fsint3[16] = {
593 8000,
594 11025,
595 16000,
596 22050,
597 24000,
598 32000,
599 44100,
600 48000,
601 0, 0, 0, 0, 0, 0, 0, 0,
602 };
603
604 static void omap_eac_rate_update(struct omap_eac_s *s)
605 {
606 int fsint[3];
607
608 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
609 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
610 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
611 if (fsint[2] < 0xf)
612 s->codec.rate = omap_eac_fsint3[fsint[2]];
613 else if (fsint[1] < 0x7)
614 s->codec.rate = omap_eac_fsint2[fsint[1]];
615 else
616 s->codec.rate = omap_eac_fsint[fsint[0]];
617 }
618
619 static void omap_eac_volume_update(struct omap_eac_s *s)
620 {
621 /* TODO */
622 }
623
624 static void omap_eac_format_update(struct omap_eac_s *s)
625 {
626 struct audsettings fmt;
627
628 /* The hardware buffers at most one sample */
629 if (s->codec.rxlen)
630 s->codec.rxlen = 1;
631
632 if (s->codec.in_voice) {
633 AUD_set_active_in(s->codec.in_voice, 0);
634 AUD_close_in(&s->codec.card, s->codec.in_voice);
635 s->codec.in_voice = NULL;
636 }
637 if (s->codec.out_voice) {
638 omap_eac_out_empty(s);
639 AUD_set_active_out(s->codec.out_voice, 0);
640 AUD_close_out(&s->codec.card, s->codec.out_voice);
641 s->codec.out_voice = NULL;
642 s->codec.txavail = 0;
643 }
644 /* Discard what couldn't be written */
645 s->codec.txlen = 0;
646
647 omap_eac_enable_update(s);
648 if (!s->codec.enable)
649 return;
650
651 omap_eac_rate_update(s);
652 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
653 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
654 fmt.freq = s->codec.rate;
655 /* TODO: signedness possibly depends on the CODEC hardware - or
656 * does I2S specify it? */
657 /* All register writes are 16 bits so we we store 16-bit samples
658 * in the buffers regardless of AGCFR[B8_16] value. */
659 fmt.fmt = AUD_FMT_U16;
660
661 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
662 "eac.codec.in", s, omap_eac_in_cb, &fmt);
663 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
664 "eac.codec.out", s, omap_eac_out_cb, &fmt);
665
666 omap_eac_volume_update(s);
667
668 AUD_set_active_in(s->codec.in_voice, 1);
669 AUD_set_active_out(s->codec.out_voice, 1);
670 }
671
672 static void omap_eac_reset(struct omap_eac_s *s)
673 {
674 s->sysconfig = 0;
675 s->config[0] = 0x0c;
676 s->config[1] = 0x09;
677 s->config[2] = 0xab;
678 s->config[3] = 0x03;
679 s->control = 0x00;
680 s->address = 0x00;
681 s->data = 0x0000;
682 s->vtol = 0x00;
683 s->vtsl = 0x00;
684 s->mixer = 0x0000;
685 s->gain[0] = 0xe7e7;
686 s->gain[1] = 0x6767;
687 s->gain[2] = 0x6767;
688 s->gain[3] = 0x6767;
689 s->att = 0xce;
690 s->max[0] = 0;
691 s->max[1] = 0;
692 s->max[2] = 0;
693 s->max[3] = 0;
694 s->max[4] = 0;
695 s->max[5] = 0;
696 s->max[6] = 0;
697
698 s->modem.control = 0x00;
699 s->modem.config = 0x0000;
700 s->bt.control = 0x00;
701 s->bt.config = 0x0000;
702 s->codec.config[0] = 0x0649;
703 s->codec.config[1] = 0x0000;
704 s->codec.config[2] = 0x0007;
705 s->codec.config[3] = 0x1ffc;
706 s->codec.rxoff = 0;
707 s->codec.rxlen = 0;
708 s->codec.txlen = 0;
709 s->codec.rxavail = 0;
710 s->codec.txavail = 0;
711
712 omap_eac_format_update(s);
713 omap_eac_interrupt_update(s);
714 }
715
716 static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
717 {
718 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
719 uint32_t ret;
720
721 switch (addr) {
722 case 0x000: /* CPCFR1 */
723 return s->config[0];
724 case 0x004: /* CPCFR2 */
725 return s->config[1];
726 case 0x008: /* CPCFR3 */
727 return s->config[2];
728 case 0x00c: /* CPCFR4 */
729 return s->config[3];
730
731 case 0x010: /* CPTCTL */
732 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
733 ((s->codec.txlen < s->codec.txavail) << 5);
734
735 case 0x014: /* CPTTADR */
736 return s->address;
737 case 0x018: /* CPTDATL */
738 return s->data & 0xff;
739 case 0x01c: /* CPTDATH */
740 return s->data >> 8;
741 case 0x020: /* CPTVSLL */
742 return s->vtol;
743 case 0x024: /* CPTVSLH */
744 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
745 case 0x040: /* MPCTR */
746 return s->modem.control;
747 case 0x044: /* MPMCCFR */
748 return s->modem.config;
749 case 0x060: /* BPCTR */
750 return s->bt.control;
751 case 0x064: /* BPMCCFR */
752 return s->bt.config;
753 case 0x080: /* AMSCFR */
754 return s->mixer;
755 case 0x084: /* AMVCTR */
756 return s->gain[0];
757 case 0x088: /* AM1VCTR */
758 return s->gain[1];
759 case 0x08c: /* AM2VCTR */
760 return s->gain[2];
761 case 0x090: /* AM3VCTR */
762 return s->gain[3];
763 case 0x094: /* ASTCTR */
764 return s->att;
765 case 0x098: /* APD1LCR */
766 return s->max[0];
767 case 0x09c: /* APD1RCR */
768 return s->max[1];
769 case 0x0a0: /* APD2LCR */
770 return s->max[2];
771 case 0x0a4: /* APD2RCR */
772 return s->max[3];
773 case 0x0a8: /* APD3LCR */
774 return s->max[4];
775 case 0x0ac: /* APD3RCR */
776 return s->max[5];
777 case 0x0b0: /* APD4R */
778 return s->max[6];
779 case 0x0b4: /* ADWR */
780 /* This should be write-only? Docs list it as read-only. */
781 return 0x0000;
782 case 0x0b8: /* ADRDR */
783 if (likely(s->codec.rxlen > 1)) {
784 ret = s->codec.rxbuf[s->codec.rxoff ++];
785 s->codec.rxlen --;
786 s->codec.rxoff &= EAC_BUF_LEN - 1;
787 return ret;
788 } else if (s->codec.rxlen) {
789 ret = s->codec.rxbuf[s->codec.rxoff ++];
790 s->codec.rxlen --;
791 s->codec.rxoff &= EAC_BUF_LEN - 1;
792 if (s->codec.rxavail)
793 omap_eac_in_refill(s);
794 omap_eac_in_dmarequest_update(s);
795 return ret;
796 }
797 return 0x0000;
798 case 0x0bc: /* AGCFR */
799 return s->codec.config[0];
800 case 0x0c0: /* AGCTR */
801 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
802 case 0x0c4: /* AGCFR2 */
803 return s->codec.config[2];
804 case 0x0c8: /* AGCFR3 */
805 return s->codec.config[3];
806 case 0x0cc: /* MBPDMACTR */
807 case 0x0d0: /* MPDDMARR */
808 case 0x0d8: /* MPUDMARR */
809 case 0x0e4: /* BPDDMARR */
810 case 0x0ec: /* BPUDMARR */
811 return 0x0000;
812
813 case 0x100: /* VERSION_NUMBER */
814 return 0x0010;
815
816 case 0x104: /* SYSCONFIG */
817 return s->sysconfig;
818
819 case 0x108: /* SYSSTATUS */
820 return 1 | 0xe; /* RESETDONE | stuff */
821 }
822
823 OMAP_BAD_REG(addr);
824 return 0;
825 }
826
827 static void omap_eac_write(void *opaque, target_phys_addr_t addr,
828 uint32_t value)
829 {
830 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
831
832 switch (addr) {
833 case 0x098: /* APD1LCR */
834 case 0x09c: /* APD1RCR */
835 case 0x0a0: /* APD2LCR */
836 case 0x0a4: /* APD2RCR */
837 case 0x0a8: /* APD3LCR */
838 case 0x0ac: /* APD3RCR */
839 case 0x0b0: /* APD4R */
840 case 0x0b8: /* ADRDR */
841 case 0x0d0: /* MPDDMARR */
842 case 0x0d8: /* MPUDMARR */
843 case 0x0e4: /* BPDDMARR */
844 case 0x0ec: /* BPUDMARR */
845 case 0x100: /* VERSION_NUMBER */
846 case 0x108: /* SYSSTATUS */
847 OMAP_RO_REG(addr);
848 return;
849
850 case 0x000: /* CPCFR1 */
851 s->config[0] = value & 0xff;
852 omap_eac_format_update(s);
853 break;
854 case 0x004: /* CPCFR2 */
855 s->config[1] = value & 0xff;
856 omap_eac_format_update(s);
857 break;
858 case 0x008: /* CPCFR3 */
859 s->config[2] = value & 0xff;
860 omap_eac_format_update(s);
861 break;
862 case 0x00c: /* CPCFR4 */
863 s->config[3] = value & 0xff;
864 omap_eac_format_update(s);
865 break;
866
867 case 0x010: /* CPTCTL */
868 /* Assuming TXF and TXE bits are read-only... */
869 s->control = value & 0x5f;
870 omap_eac_interrupt_update(s);
871 break;
872
873 case 0x014: /* CPTTADR */
874 s->address = value & 0xff;
875 break;
876 case 0x018: /* CPTDATL */
877 s->data &= 0xff00;
878 s->data |= value & 0xff;
879 break;
880 case 0x01c: /* CPTDATH */
881 s->data &= 0x00ff;
882 s->data |= value << 8;
883 break;
884 case 0x020: /* CPTVSLL */
885 s->vtol = value & 0xf8;
886 break;
887 case 0x024: /* CPTVSLH */
888 s->vtsl = value & 0x9f;
889 break;
890 case 0x040: /* MPCTR */
891 s->modem.control = value & 0x8f;
892 break;
893 case 0x044: /* MPMCCFR */
894 s->modem.config = value & 0x7fff;
895 break;
896 case 0x060: /* BPCTR */
897 s->bt.control = value & 0x8f;
898 break;
899 case 0x064: /* BPMCCFR */
900 s->bt.config = value & 0x7fff;
901 break;
902 case 0x080: /* AMSCFR */
903 s->mixer = value & 0x0fff;
904 break;
905 case 0x084: /* AMVCTR */
906 s->gain[0] = value & 0xffff;
907 break;
908 case 0x088: /* AM1VCTR */
909 s->gain[1] = value & 0xff7f;
910 break;
911 case 0x08c: /* AM2VCTR */
912 s->gain[2] = value & 0xff7f;
913 break;
914 case 0x090: /* AM3VCTR */
915 s->gain[3] = value & 0xff7f;
916 break;
917 case 0x094: /* ASTCTR */
918 s->att = value & 0xff;
919 break;
920
921 case 0x0b4: /* ADWR */
922 s->codec.txbuf[s->codec.txlen ++] = value;
923 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
924 s->codec.txlen == s->codec.txavail)) {
925 if (s->codec.txavail)
926 omap_eac_out_empty(s);
927 /* Discard what couldn't be written */
928 s->codec.txlen = 0;
929 }
930 break;
931
932 case 0x0bc: /* AGCFR */
933 s->codec.config[0] = value & 0x07ff;
934 omap_eac_format_update(s);
935 break;
936 case 0x0c0: /* AGCTR */
937 s->codec.config[1] = value & 0x780f;
938 omap_eac_format_update(s);
939 break;
940 case 0x0c4: /* AGCFR2 */
941 s->codec.config[2] = value & 0x003f;
942 omap_eac_format_update(s);
943 break;
944 case 0x0c8: /* AGCFR3 */
945 s->codec.config[3] = value & 0xffff;
946 omap_eac_format_update(s);
947 break;
948 case 0x0cc: /* MBPDMACTR */
949 case 0x0d4: /* MPDDMAWR */
950 case 0x0e0: /* MPUDMAWR */
951 case 0x0e8: /* BPDDMAWR */
952 case 0x0f0: /* BPUDMAWR */
953 break;
954
955 case 0x104: /* SYSCONFIG */
956 if (value & (1 << 1)) /* SOFTRESET */
957 omap_eac_reset(s);
958 s->sysconfig = value & 0x31d;
959 break;
960
961 default:
962 OMAP_BAD_REG(addr);
963 return;
964 }
965 }
966
967 static CPUReadMemoryFunc * const omap_eac_readfn[] = {
968 omap_badwidth_read16,
969 omap_eac_read,
970 omap_badwidth_read16,
971 };
972
973 static CPUWriteMemoryFunc * const omap_eac_writefn[] = {
974 omap_badwidth_write16,
975 omap_eac_write,
976 omap_badwidth_write16,
977 };
978
979 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
980 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
981 {
982 int iomemtype;
983 struct omap_eac_s *s = (struct omap_eac_s *)
984 qemu_mallocz(sizeof(struct omap_eac_s));
985
986 s->irq = irq;
987 s->codec.rxdrq = *drq ++;
988 s->codec.txdrq = *drq;
989 omap_eac_reset(s);
990
991 AUD_register_card("OMAP EAC", &s->codec.card);
992
993 iomemtype = cpu_register_io_memory(omap_eac_readfn,
994 omap_eac_writefn, s);
995 omap_l4_attach(ta, 0, iomemtype);
996
997 return s;
998 }
999
1000 /* STI/XTI (emulation interface) console - reverse engineered only */
1001 struct omap_sti_s {
1002 qemu_irq irq;
1003 CharDriverState *chr;
1004
1005 uint32_t sysconfig;
1006 uint32_t systest;
1007 uint32_t irqst;
1008 uint32_t irqen;
1009 uint32_t clkcontrol;
1010 uint32_t serial_config;
1011 };
1012
1013 #define STI_TRACE_CONSOLE_CHANNEL 239
1014 #define STI_TRACE_CONTROL_CHANNEL 253
1015
1016 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
1017 {
1018 qemu_set_irq(s->irq, s->irqst & s->irqen);
1019 }
1020
1021 static void omap_sti_reset(struct omap_sti_s *s)
1022 {
1023 s->sysconfig = 0;
1024 s->irqst = 0;
1025 s->irqen = 0;
1026 s->clkcontrol = 0;
1027 s->serial_config = 0;
1028
1029 omap_sti_interrupt_update(s);
1030 }
1031
1032 static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
1033 {
1034 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1035
1036 switch (addr) {
1037 case 0x00: /* STI_REVISION */
1038 return 0x10;
1039
1040 case 0x10: /* STI_SYSCONFIG */
1041 return s->sysconfig;
1042
1043 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
1044 return 0x00;
1045
1046 case 0x18: /* STI_IRQSTATUS */
1047 return s->irqst;
1048
1049 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
1050 return s->irqen;
1051
1052 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
1053 case 0x28: /* STI_RX_DR / XTI_RXDATA */
1054 /* TODO */
1055 return 0;
1056
1057 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
1058 return s->clkcontrol;
1059
1060 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
1061 return s->serial_config;
1062 }
1063
1064 OMAP_BAD_REG(addr);
1065 return 0;
1066 }
1067
1068 static void omap_sti_write(void *opaque, target_phys_addr_t addr,
1069 uint32_t value)
1070 {
1071 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1072
1073 switch (addr) {
1074 case 0x00: /* STI_REVISION */
1075 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
1076 OMAP_RO_REG(addr);
1077 return;
1078
1079 case 0x10: /* STI_SYSCONFIG */
1080 if (value & (1 << 1)) /* SOFTRESET */
1081 omap_sti_reset(s);
1082 s->sysconfig = value & 0xfe;
1083 break;
1084
1085 case 0x18: /* STI_IRQSTATUS */
1086 s->irqst &= ~value;
1087 omap_sti_interrupt_update(s);
1088 break;
1089
1090 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
1091 s->irqen = value & 0xffff;
1092 omap_sti_interrupt_update(s);
1093 break;
1094
1095 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
1096 s->clkcontrol = value & 0xff;
1097 break;
1098
1099 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
1100 s->serial_config = value & 0xff;
1101 break;
1102
1103 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
1104 case 0x28: /* STI_RX_DR / XTI_RXDATA */
1105 /* TODO */
1106 return;
1107
1108 default:
1109 OMAP_BAD_REG(addr);
1110 return;
1111 }
1112 }
1113
1114 static CPUReadMemoryFunc * const omap_sti_readfn[] = {
1115 omap_badwidth_read32,
1116 omap_badwidth_read32,
1117 omap_sti_read,
1118 };
1119
1120 static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
1121 omap_badwidth_write32,
1122 omap_badwidth_write32,
1123 omap_sti_write,
1124 };
1125
1126 static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
1127 {
1128 OMAP_BAD_REG(addr);
1129 return 0;
1130 }
1131
1132 static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
1133 uint32_t value)
1134 {
1135 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1136 int ch = addr >> 6;
1137 uint8_t byte = value;
1138
1139 if (ch == STI_TRACE_CONTROL_CHANNEL) {
1140 /* Flush channel <i>value</i>. */
1141 qemu_chr_write(s->chr, (const uint8_t *) "\r", 1);
1142 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
1143 if (value == 0xc0 || value == 0xc3) {
1144 /* Open channel <i>ch</i>. */
1145 } else if (value == 0x00)
1146 qemu_chr_write(s->chr, (const uint8_t *) "\n", 1);
1147 else
1148 qemu_chr_write(s->chr, &byte, 1);
1149 }
1150 }
1151
1152 static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = {
1153 omap_sti_fifo_read,
1154 omap_badwidth_read8,
1155 omap_badwidth_read8,
1156 };
1157
1158 static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
1159 omap_sti_fifo_write,
1160 omap_badwidth_write8,
1161 omap_badwidth_write8,
1162 };
1163
1164 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
1165 target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
1166 CharDriverState *chr)
1167 {
1168 int iomemtype;
1169 struct omap_sti_s *s = (struct omap_sti_s *)
1170 qemu_mallocz(sizeof(struct omap_sti_s));
1171
1172 s->irq = irq;
1173 omap_sti_reset(s);
1174
1175 s->chr = chr ?: qemu_chr_open("null", "null", NULL);
1176
1177 iomemtype = l4_register_io_memory(omap_sti_readfn,
1178 omap_sti_writefn, s);
1179 omap_l4_attach(ta, 0, iomemtype);
1180
1181 iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
1182 omap_sti_fifo_writefn, s);
1183 cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
1184
1185 return s;
1186 }
1187
1188 /* L4 Interconnect */
1189 struct omap_target_agent_s {
1190 struct omap_l4_s *bus;
1191 int regions;
1192 struct omap_l4_region_s *start;
1193 target_phys_addr_t base;
1194 uint32_t component;
1195 uint32_t control;
1196 uint32_t status;
1197 };
1198
1199 struct omap_l4_s {
1200 target_phys_addr_t base;
1201 int ta_num;
1202 struct omap_target_agent_s ta[0];
1203 };
1204
1205 #ifdef L4_MUX_HACK
1206 static int omap_l4_io_entries;
1207 static int omap_cpu_io_entry;
1208 static struct omap_l4_entry {
1209 CPUReadMemoryFunc * const *mem_read;
1210 CPUWriteMemoryFunc * const *mem_write;
1211 void *opaque;
1212 } *omap_l4_io_entry;
1213 static CPUReadMemoryFunc * const *omap_l4_io_readb_fn;
1214 static CPUReadMemoryFunc * const *omap_l4_io_readh_fn;
1215 static CPUReadMemoryFunc * const *omap_l4_io_readw_fn;
1216 static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn;
1217 static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn;
1218 static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn;
1219 static void **omap_l4_io_opaque;
1220
1221 int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
1222 CPUWriteMemoryFunc * const *mem_write, void *opaque)
1223 {
1224 omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
1225 omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
1226 omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
1227
1228 return omap_l4_io_entries ++;
1229 }
1230
1231 static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
1232 {
1233 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
1234
1235 return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
1236 }
1237
1238 static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
1239 {
1240 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
1241
1242 return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
1243 }
1244
1245 static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
1246 {
1247 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
1248
1249 return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
1250 }
1251
1252 static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
1253 uint32_t value)
1254 {
1255 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
1256
1257 return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
1258 }
1259
1260 static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
1261 uint32_t value)
1262 {
1263 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
1264
1265 return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
1266 }
1267
1268 static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
1269 uint32_t value)
1270 {
1271 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
1272
1273 return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
1274 }
1275
1276 static CPUReadMemoryFunc * const omap_l4_io_readfn[] = {
1277 omap_l4_io_readb,
1278 omap_l4_io_readh,
1279 omap_l4_io_readw,
1280 };
1281
1282 static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
1283 omap_l4_io_writeb,
1284 omap_l4_io_writeh,
1285 omap_l4_io_writew,
1286 };
1287 #endif
1288
1289 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
1290 {
1291 struct omap_l4_s *bus = qemu_mallocz(
1292 sizeof(*bus) + ta_num * sizeof(*bus->ta));
1293
1294 bus->ta_num = ta_num;
1295 bus->base = base;
1296
1297 #ifdef L4_MUX_HACK
1298 omap_l4_io_entries = 1;
1299 omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
1300
1301 omap_cpu_io_entry =
1302 cpu_register_io_memory(omap_l4_io_readfn,
1303 omap_l4_io_writefn, bus);
1304 # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
1305 omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
1306 omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
1307 omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
1308 omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
1309 omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
1310 omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
1311 omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
1312 #endif
1313
1314 return bus;
1315 }
1316
1317 static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
1318 {
1319 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1320
1321 switch (addr) {
1322 case 0x00: /* COMPONENT */
1323 return s->component;
1324
1325 case 0x20: /* AGENT_CONTROL */
1326 return s->control;
1327
1328 case 0x28: /* AGENT_STATUS */
1329 return s->status;
1330 }
1331
1332 OMAP_BAD_REG(addr);
1333 return 0;
1334 }
1335
1336 static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
1337 uint32_t value)
1338 {
1339 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1340
1341 switch (addr) {
1342 case 0x00: /* COMPONENT */
1343 case 0x28: /* AGENT_STATUS */
1344 OMAP_RO_REG(addr);
1345 break;
1346
1347 case 0x20: /* AGENT_CONTROL */
1348 s->control = value & 0x01000700;
1349 if (value & 1) /* OCP_RESET */
1350 s->status &= ~1; /* REQ_TIMEOUT */
1351 break;
1352
1353 default:
1354 OMAP_BAD_REG(addr);
1355 }
1356 }
1357
1358 static CPUReadMemoryFunc * const omap_l4ta_readfn[] = {
1359 omap_badwidth_read16,
1360 omap_l4ta_read,
1361 omap_badwidth_read16,
1362 };
1363
1364 static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
1365 omap_badwidth_write32,
1366 omap_badwidth_write32,
1367 omap_l4ta_write,
1368 };
1369
1370 #define L4TA(n) (n)
1371 #define L4TAO(n) ((n) + 39)
1372
1373 static struct omap_l4_region_s {
1374 target_phys_addr_t offset;
1375 size_t size;
1376 int access;
1377 } omap_l4_region[125] = {
1378 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
1379 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
1380 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
1381 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
1382 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
1383 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
1384 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
1385 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
1386 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
1387 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
1388 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
1389 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
1390 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
1391 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
1392 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
1393 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
1394 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
1395 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
1396 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
1397 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
1398 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
1399 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
1400 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
1401 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
1402 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
1403 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
1404 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
1405 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
1406 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
1407 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
1408 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
1409 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
1410 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
1411 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
1412 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
1413 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
1414 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
1415 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
1416 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
1417 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
1418 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
1419 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
1420 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
1421 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
1422 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
1423 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
1424 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
1425 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
1426 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
1427 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
1428 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
1429 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
1430 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
1431 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
1432 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
1433 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
1434 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
1435 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
1436 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
1437 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
1438 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
1439 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
1440 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
1441 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
1442 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
1443 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
1444 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
1445 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
1446 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
1447 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
1448 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
1449 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
1450 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
1451 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
1452 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
1453 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
1454 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
1455 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
1456 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
1457 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
1458 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
1459 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
1460 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
1461 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
1462 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
1463 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
1464 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
1465 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
1466 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
1467 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
1468 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
1469 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
1470 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
1471 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
1472 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
1473 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
1474 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
1475 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
1476 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
1477 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
1478 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
1479 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
1480 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
1481 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
1482 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
1483 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
1484 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
1485 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
1486 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
1487 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
1488 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
1489 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
1490 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
1491 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
1492 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
1493 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
1494 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
1495 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
1496 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
1497 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
1498 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
1499 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
1500 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
1501 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
1502 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
1503 };
1504
1505 static struct omap_l4_agent_info_s {
1506 int ta;
1507 int region;
1508 int regions;
1509 int ta_region;
1510 } omap_l4_agent_info[54] = {
1511 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
1512 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
1513 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
1514 { L4TAO(3), 7, 3, 2 }, /* PRCM */
1515 { L4TA(1), 10, 2, 1 }, /* BCM */
1516 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
1517 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
1518 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
1519 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
1520 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
1521 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
1522 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
1523 { L4TA(12), 38, 2, 1 }, /* sDMA */
1524 { L4TA(13), 40, 5, 4 }, /* SSI */
1525 { L4TAO(4), 45, 2, 1 }, /* USB */
1526 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
1527 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
1528 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
1529 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
1530 { L4TA(18), 55, 2, 1 }, /* XTI */
1531 { L4TA(19), 57, 2, 1 }, /* UART1 */
1532 { L4TA(20), 59, 2, 1 }, /* UART2 */
1533 { L4TA(21), 61, 2, 1 }, /* UART3 */
1534 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
1535 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
1536 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
1537 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
1538 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
1539 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
1540 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
1541 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
1542 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
1543 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
1544 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
1545 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
1546 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
1547 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
1548 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
1549 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
1550 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
1551 { L4TA(32), 97, 2, 1 }, /* EAC */
1552 { L4TA(33), 99, 2, 1 }, /* FAC */
1553 { L4TA(34), 101, 2, 1 }, /* IPC */
1554 { L4TA(35), 103, 2, 1 }, /* SPI1 */
1555 { L4TA(36), 105, 2, 1 }, /* SPI2 */
1556 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
1557 { L4TAO(10), 109, 2, 1 },
1558 { L4TAO(11), 111, 2, 1 }, /* RNG */
1559 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
1560 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
1561 { L4TA(37), 117, 2, 1 }, /* AES */
1562 { L4TA(38), 119, 2, 1 }, /* PKA */
1563 { -1, 121, 2, 1 },
1564 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
1565 };
1566
1567 #define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
1568 #define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
1569
1570 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
1571 {
1572 int i, iomemtype;
1573 struct omap_target_agent_s *ta = NULL;
1574 struct omap_l4_agent_info_s *info = NULL;
1575
1576 for (i = 0; i < bus->ta_num; i ++)
1577 if (omap_l4_agent_info[i].ta == cs) {
1578 ta = &bus->ta[i];
1579 info = &omap_l4_agent_info[i];
1580 break;
1581 }
1582 if (!ta) {
1583 fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
1584 exit(-1);
1585 }
1586
1587 ta->bus = bus;
1588 ta->start = &omap_l4_region[info->region];
1589 ta->regions = info->regions;
1590
1591 ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1592 ta->status = 0x00000000;
1593 ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
1594
1595 iomemtype = l4_register_io_memory(omap_l4ta_readfn,
1596 omap_l4ta_writefn, ta);
1597 ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
1598
1599 return ta;
1600 }
1601
1602 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
1603 int iotype)
1604 {
1605 target_phys_addr_t base;
1606 ssize_t size;
1607 #ifdef L4_MUX_HACK
1608 int i;
1609 #endif
1610
1611 if (region < 0 || region >= ta->regions) {
1612 fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
1613 exit(-1);
1614 }
1615
1616 base = ta->bus->base + ta->start[region].offset;
1617 size = ta->start[region].size;
1618 if (iotype) {
1619 #ifndef L4_MUX_HACK
1620 cpu_register_physical_memory(base, size, iotype);
1621 #else
1622 cpu_register_physical_memory(base, size, omap_cpu_io_entry);
1623 i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
1624 for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
1625 omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
1626 omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
1627 omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
1628 omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
1629 omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
1630 omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
1631 omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
1632 }
1633 #endif
1634 }
1635
1636 return base;
1637 }
1638
1639 /* TEST-Chip-level TAP */
1640 static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
1641 {
1642 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1643
1644 switch (addr) {
1645 case 0x204: /* IDCODE_reg */
1646 switch (s->mpu_model) {
1647 case omap2420:
1648 case omap2422:
1649 case omap2423:
1650 return 0x5b5d902f; /* ES 2.2 */
1651 case omap2430:
1652 return 0x5b68a02f; /* ES 2.2 */
1653 case omap3430:
1654 return 0x1b7ae02f; /* ES 2 */
1655 default:
1656 hw_error("%s: Bad mpu model\n", __FUNCTION__);
1657 }
1658
1659 case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
1660 case 0x210: /* PRODUCTION_ID_reg for OMAP3 */
1661 switch (s->mpu_model) {
1662 case omap2420:
1663 return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */
1664 case omap2422:
1665 return 0x000400f0;
1666 case omap2423:
1667 return 0x000800f0;
1668 case omap2430:
1669 return 0x000000f0;
1670 case omap3430:
1671 return 0x000000f0;
1672 default:
1673 hw_error("%s: Bad mpu model\n", __FUNCTION__);
1674 }
1675
1676 case 0x20c:
1677 switch (s->mpu_model) {
1678 case omap2420:
1679 case omap2422:
1680 case omap2423:
1681 return 0xcafeb5d9; /* ES 2.2 */
1682 case omap2430:
1683 return 0xcafeb68a; /* ES 2.2 */
1684 case omap3430:
1685 return 0xcafeb7ae; /* ES 2 */
1686 default:
1687 hw_error("%s: Bad mpu model\n", __FUNCTION__);
1688 }
1689
1690 case 0x218: /* DIE_ID_reg */
1691 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1692 case 0x21c: /* DIE_ID_reg */
1693 return 0x54 << 24;
1694 case 0x220: /* DIE_ID_reg */
1695 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1696 case 0x224: /* DIE_ID_reg */
1697 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1698 }
1699
1700 OMAP_BAD_REG(addr);
1701 return 0;
1702 }
1703
1704 static void omap_tap_write(void *opaque, target_phys_addr_t addr,
1705 uint32_t value)
1706 {
1707 OMAP_BAD_REG(addr);
1708 }
1709
1710 static CPUReadMemoryFunc * const omap_tap_readfn[] = {
1711 omap_badwidth_read32,
1712 omap_badwidth_read32,
1713 omap_tap_read,
1714 };
1715
1716 static CPUWriteMemoryFunc * const omap_tap_writefn[] = {
1717 omap_badwidth_write32,
1718 omap_badwidth_write32,
1719 omap_tap_write,
1720 };
1721
1722 void omap_tap_init(struct omap_target_agent_s *ta,
1723 struct omap_mpu_state_s *mpu)
1724 {
1725 omap_l4_attach(ta, 0, l4_register_io_memory(
1726 omap_tap_readfn, omap_tap_writefn, mpu));
1727 }
1728
1729 /* Power, Reset, and Clock Management */
1730 struct omap_prcm_s {
1731 qemu_irq irq[3];
1732 struct omap_mpu_state_s *mpu;
1733
1734 uint32_t irqst[3];
1735 uint32_t irqen[3];
1736
1737 uint32_t sysconfig;
1738 uint32_t voltctrl;
1739 uint32_t scratch[20];
1740
1741 uint32_t clksrc[1];
1742 uint32_t clkout[1];
1743 uint32_t clkemul[1];
1744 uint32_t clkpol[1];
1745 uint32_t clksel[8];
1746 uint32_t clken[12];
1747 uint32_t clkctrl[4];
1748 uint32_t clkidle[7];
1749 uint32_t setuptime[2];
1750
1751 uint32_t wkup[3];
1752 uint32_t wken[3];
1753 uint32_t wkst[3];
1754 uint32_t rst[4];
1755 uint32_t rstctrl[1];
1756 uint32_t power[4];
1757 uint32_t rsttime_wkup;
1758
1759 uint32_t ev;
1760 uint32_t evtime[2];
1761
1762 int dpll_lock, apll_lock[2];
1763 };
1764
1765 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1766 {
1767 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1768 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1769 }
1770
1771 static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
1772 {
1773 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1774 uint32_t ret;
1775
1776 switch (addr) {
1777 case 0x000: /* PRCM_REVISION */
1778 return 0x10;
1779
1780 case 0x010: /* PRCM_SYSCONFIG */
1781 return s->sysconfig;
1782
1783 case 0x018: /* PRCM_IRQSTATUS_MPU */
1784 return s->irqst[0];
1785
1786 case 0x01c: /* PRCM_IRQENABLE_MPU */
1787 return s->irqen[0];
1788
1789 case 0x050: /* PRCM_VOLTCTRL */
1790 return s->voltctrl;
1791 case 0x054: /* PRCM_VOLTST */
1792 return s->voltctrl & 3;
1793
1794 case 0x060: /* PRCM_CLKSRC_CTRL */
1795 return s->clksrc[0];
1796 case 0x070: /* PRCM_CLKOUT_CTRL */
1797 return s->clkout[0];
1798 case 0x078: /* PRCM_CLKEMUL_CTRL */
1799 return s->clkemul[0];
1800 case 0x080: /* PRCM_CLKCFG_CTRL */
1801 case 0x084: /* PRCM_CLKCFG_STATUS */
1802 return 0;
1803
1804 case 0x090: /* PRCM_VOLTSETUP */
1805 return s->setuptime[0];
1806
1807 case 0x094: /* PRCM_CLKSSETUP */
1808 return s->setuptime[1];
1809
1810 case 0x098: /* PRCM_POLCTRL */
1811 return s->clkpol[0];
1812
1813 case 0x0b0: /* GENERAL_PURPOSE1 */
1814 case 0x0b4: /* GENERAL_PURPOSE2 */
1815 case 0x0b8: /* GENERAL_PURPOSE3 */
1816 case 0x0bc: /* GENERAL_PURPOSE4 */
1817 case 0x0c0: /* GENERAL_PURPOSE5 */
1818 case 0x0c4: /* GENERAL_PURPOSE6 */
1819 case 0x0c8: /* GENERAL_PURPOSE7 */
1820 case 0x0cc: /* GENERAL_PURPOSE8 */
1821 case 0x0d0: /* GENERAL_PURPOSE9 */
1822 case 0x0d4: /* GENERAL_PURPOSE10 */
1823 case 0x0d8: /* GENERAL_PURPOSE11 */
1824 case 0x0dc: /* GENERAL_PURPOSE12 */
1825 case 0x0e0: /* GENERAL_PURPOSE13 */
1826 case 0x0e4: /* GENERAL_PURPOSE14 */
1827 case 0x0e8: /* GENERAL_PURPOSE15 */
1828 case 0x0ec: /* GENERAL_PURPOSE16 */
1829 case 0x0f0: /* GENERAL_PURPOSE17 */
1830 case 0x0f4: /* GENERAL_PURPOSE18 */
1831 case 0x0f8: /* GENERAL_PURPOSE19 */
1832 case 0x0fc: /* GENERAL_PURPOSE20 */
1833 return s->scratch[(addr - 0xb0) >> 2];
1834
1835 case 0x140: /* CM_CLKSEL_MPU */
1836 return s->clksel[0];
1837 case 0x148: /* CM_CLKSTCTRL_MPU */
1838 return s->clkctrl[0];
1839
1840 case 0x158: /* RM_RSTST_MPU */
1841 return s->rst[0];
1842 case 0x1c8: /* PM_WKDEP_MPU */
1843 return s->wkup[0];
1844 case 0x1d4: /* PM_EVGENCTRL_MPU */
1845 return s->ev;
1846 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1847 return s->evtime[0];
1848 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1849 return s->evtime[1];
1850 case 0x1e0: /* PM_PWSTCTRL_MPU */
1851 return s->power[0];
1852 case 0x1e4: /* PM_PWSTST_MPU */
1853 return 0;
1854
1855 case 0x200: /* CM_FCLKEN1_CORE */
1856 return s->clken[0];
1857 case 0x204: /* CM_FCLKEN2_CORE */
1858 return s->clken[1];
1859 case 0x210: /* CM_ICLKEN1_CORE */
1860 return s->clken[2];
1861 case 0x214: /* CM_ICLKEN2_CORE */
1862 return s->clken[3];
1863 case 0x21c: /* CM_ICLKEN4_CORE */
1864 return s->clken[4];
1865
1866 case 0x220: /* CM_IDLEST1_CORE */
1867 /* TODO: check the actual iclk status */
1868 return 0x7ffffff9;
1869 case 0x224: /* CM_IDLEST2_CORE */
1870 /* TODO: check the actual iclk status */
1871 return 0x00000007;
1872 case 0x22c: /* CM_IDLEST4_CORE */
1873 /* TODO: check the actual iclk status */
1874 return 0x0000001f;
1875
1876 case 0x230: /* CM_AUTOIDLE1_CORE */
1877 return s->clkidle[0];
1878 case 0x234: /* CM_AUTOIDLE2_CORE */
1879 return s->clkidle[1];
1880 case 0x238: /* CM_AUTOIDLE3_CORE */
1881 return s->clkidle[2];
1882 case 0x23c: /* CM_AUTOIDLE4_CORE */
1883 return s->clkidle[3];
1884
1885 case 0x240: /* CM_CLKSEL1_CORE */
1886 return s->clksel[1];
1887 case 0x244: /* CM_CLKSEL2_CORE */
1888 return s->clksel[2];
1889
1890 case 0x248: /* CM_CLKSTCTRL_CORE */
1891 return s->clkctrl[1];
1892
1893 case 0x2a0: /* PM_WKEN1_CORE */
1894 return s->wken[0];
1895 case 0x2a4: /* PM_WKEN2_CORE */
1896 return s->wken[1];
1897
1898 case 0x2b0: /* PM_WKST1_CORE */
1899 return s->wkst[0];
1900 case 0x2b4: /* PM_WKST2_CORE */
1901 return s->wkst[1];
1902 case 0x2c8: /* PM_WKDEP_CORE */
1903 return 0x1e;
1904
1905 case 0x2e0: /* PM_PWSTCTRL_CORE */
1906 return s->power[1];
1907 case 0x2e4: /* PM_PWSTST_CORE */
1908 return 0x000030 | (s->power[1] & 0xfc00);
1909
1910 case 0x300: /* CM_FCLKEN_GFX */
1911 return s->clken[5];
1912 case 0x310: /* CM_ICLKEN_GFX */
1913 return s->clken[6];
1914 case 0x320: /* CM_IDLEST_GFX */
1915 /* TODO: check the actual iclk status */
1916 return 0x00000001;
1917 case 0x340: /* CM_CLKSEL_GFX */
1918 return s->clksel[3];
1919 case 0x348: /* CM_CLKSTCTRL_GFX */
1920 return s->clkctrl[2];
1921 case 0x350: /* RM_RSTCTRL_GFX */
1922 return s->rstctrl[0];
1923 case 0x358: /* RM_RSTST_GFX */
1924 return s->rst[1];
1925 case 0x3c8: /* PM_WKDEP_GFX */
1926 return s->wkup[1];
1927
1928 case 0x3e0: /* PM_PWSTCTRL_GFX */
1929 return s->power[2];
1930 case 0x3e4: /* PM_PWSTST_GFX */
1931 return s->power[2] & 3;
1932
1933 case 0x400: /* CM_FCLKEN_WKUP */
1934 return s->clken[7];
1935 case 0x410: /* CM_ICLKEN_WKUP */
1936 return s->clken[8];
1937 case 0x420: /* CM_IDLEST_WKUP */
1938 /* TODO: check the actual iclk status */
1939 return 0x0000003f;
1940 case 0x430: /* CM_AUTOIDLE_WKUP */
1941 return s->clkidle[4];
1942 case 0x440: /* CM_CLKSEL_WKUP */
1943 return s->clksel[4];
1944 case 0x450: /* RM_RSTCTRL_WKUP */
1945 return 0;
1946 case 0x454: /* RM_RSTTIME_WKUP */
1947 return s->rsttime_wkup;
1948 case 0x458: /* RM_RSTST_WKUP */
1949 return s->rst[2];
1950 case 0x4a0: /* PM_WKEN_WKUP */
1951 return s->wken[2];
1952 case 0x4b0: /* PM_WKST_WKUP */
1953 return s->wkst[2];
1954
1955 case 0x500: /* CM_CLKEN_PLL */
1956 return s->clken[9];
1957 case 0x520: /* CM_IDLEST_CKGEN */
1958 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
1959 if (!(s->clksel[6] & 3))
1960 /* Core uses 32-kHz clock */
1961 ret |= 3 << 0;
1962 else if (!s->dpll_lock)
1963 /* DPLL not locked, core uses ref_clk */
1964 ret |= 1 << 0;
1965 else
1966 /* Core uses DPLL */
1967 ret |= 2 << 0;
1968 return ret;
1969 case 0x530: /* CM_AUTOIDLE_PLL */
1970 return s->clkidle[5];
1971 case 0x540: /* CM_CLKSEL1_PLL */
1972 return s->clksel[5];
1973 case 0x544: /* CM_CLKSEL2_PLL */
1974 return s->clksel[6];
1975
1976 case 0x800: /* CM_FCLKEN_DSP */
1977 return s->clken[10];
1978 case 0x810: /* CM_ICLKEN_DSP */
1979 return s->clken[11];
1980 case 0x820: /* CM_IDLEST_DSP */
1981 /* TODO: check the actual iclk status */
1982 return 0x00000103;
1983 case 0x830: /* CM_AUTOIDLE_DSP */
1984 return s->clkidle[6];
1985 case 0x840: /* CM_CLKSEL_DSP */
1986 return s->clksel[7];
1987 case 0x848: /* CM_CLKSTCTRL_DSP */
1988 return s->clkctrl[3];
1989 case 0x850: /* RM_RSTCTRL_DSP */
1990 return 0;
1991 case 0x858: /* RM_RSTST_DSP */
1992 return s->rst[3];
1993 case 0x8c8: /* PM_WKDEP_DSP */
1994 return s->wkup[2];
1995 case 0x8e0: /* PM_PWSTCTRL_DSP */
1996 return s->power[3];
1997 case 0x8e4: /* PM_PWSTST_DSP */
1998 return 0x008030 | (s->power[3] & 0x3003);
1999
2000 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
2001 return s->irqst[1];
2002 case 0x8f4: /* PRCM_IRQENABLE_DSP */
2003 return s->irqen[1];
2004
2005 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
2006 return s->irqst[2];
2007 case 0x8fc: /* PRCM_IRQENABLE_IVA */
2008 return s->irqen[2];
2009 }
2010
2011 OMAP_BAD_REG(addr);
2012 return 0;
2013 }
2014
2015 static void omap_prcm_apll_update(struct omap_prcm_s *s)
2016 {
2017 int mode[2];
2018
2019 mode[0] = (s->clken[9] >> 6) & 3;
2020 s->apll_lock[0] = (mode[0] == 3);
2021 mode[1] = (s->clken[9] >> 2) & 3;
2022 s->apll_lock[1] = (mode[1] == 3);
2023 /* TODO: update clocks */
2024
2025 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
2026 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
2027 __FUNCTION__);
2028 }
2029
2030 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
2031 {
2032 omap_clk dpll = omap_findclk(s->mpu, "dpll");
2033 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
2034 omap_clk core = omap_findclk(s->mpu, "core_clk");
2035 int mode = (s->clken[9] >> 0) & 3;
2036 int mult, div;
2037
2038 mult = (s->clksel[5] >> 12) & 0x3ff;
2039 div = (s->clksel[5] >> 8) & 0xf;
2040 if (mult == 0 || mult == 1)
2041 mode = 1; /* Bypass */
2042
2043 s->dpll_lock = 0;
2044 switch (mode) {
2045 case 0:
2046 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
2047 break;
2048 case 1: /* Low-power bypass mode (Default) */
2049 case 2: /* Fast-relock bypass mode */
2050 omap_clk_setrate(dpll, 1, 1);
2051 omap_clk_setrate(dpll_x2, 1, 1);
2052 break;
2053 case 3: /* Lock mode */
2054 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
2055
2056 omap_clk_setrate(dpll, div + 1, mult);
2057 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
2058 break;
2059 }
2060
2061 switch ((s->clksel[6] >> 0) & 3) {
2062 case 0:
2063 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
2064 break;
2065 case 1:
2066 omap_clk_reparent(core, dpll);
2067 break;
2068 case 2:
2069 /* Default */
2070 omap_clk_reparent(core, dpll_x2);
2071 break;
2072 case 3:
2073 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
2074 break;
2075 }
2076 }
2077
2078 static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
2079 uint32_t value)
2080 {
2081 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2082
2083 switch (addr) {
2084 case 0x000: /* PRCM_REVISION */
2085 case 0x054: /* PRCM_VOLTST */
2086 case 0x084: /* PRCM_CLKCFG_STATUS */
2087 case 0x1e4: /* PM_PWSTST_MPU */
2088 case 0x220: /* CM_IDLEST1_CORE */
2089 case 0x224: /* CM_IDLEST2_CORE */
2090 case 0x22c: /* CM_IDLEST4_CORE */
2091 case 0x2c8: /* PM_WKDEP_CORE */
2092 case 0x2e4: /* PM_PWSTST_CORE */
2093 case 0x320: /* CM_IDLEST_GFX */
2094 case 0x3e4: /* PM_PWSTST_GFX */
2095 case 0x420: /* CM_IDLEST_WKUP */
2096 case 0x520: /* CM_IDLEST_CKGEN */
2097 case 0x820: /* CM_IDLEST_DSP */
2098 case 0x8e4: /* PM_PWSTST_DSP */
2099 OMAP_RO_REG(addr);
2100 return;
2101
2102 case 0x010: /* PRCM_SYSCONFIG */
2103 s->sysconfig = value & 1;
2104 break;
2105
2106 case 0x018: /* PRCM_IRQSTATUS_MPU */
2107 s->irqst[0] &= ~value;
2108 omap_prcm_int_update(s, 0);
2109 break;
2110 case 0x01c: /* PRCM_IRQENABLE_MPU */
2111 s->irqen[0] = value & 0x3f;
2112 omap_prcm_int_update(s, 0);
2113 break;
2114
2115 case 0x050: /* PRCM_VOLTCTRL */
2116 s->voltctrl = value & 0xf1c3;
2117 break;
2118
2119 case 0x060: /* PRCM_CLKSRC_CTRL */
2120 s->clksrc[0] = value & 0xdb;
2121 /* TODO update clocks */
2122 break;
2123
2124 case 0x070: /* PRCM_CLKOUT_CTRL */
2125 s->clkout[0] = value & 0xbbbb;
2126 /* TODO update clocks */
2127 break;
2128
2129 case 0x078: /* PRCM_CLKEMUL_CTRL */
2130 s->clkemul[0] = value & 1;
2131 /* TODO update clocks */
2132 break;
2133
2134 case 0x080: /* PRCM_CLKCFG_CTRL */
2135 break;
2136
2137 case 0x090: /* PRCM_VOLTSETUP */
2138 s->setuptime[0] = value & 0xffff;
2139 break;
2140 case 0x094: /* PRCM_CLKSSETUP */
2141 s->setuptime[1] = value & 0xffff;
2142 break;
2143
2144 case 0x098: /* PRCM_POLCTRL */
2145 s->clkpol[0] = value & 0x701;
2146 break;
2147
2148 case 0x0b0: /* GENERAL_PURPOSE1 */
2149 case 0x0b4: /* GENERAL_PURPOSE2 */
2150 case 0x0b8: /* GENERAL_PURPOSE3 */
2151 case 0x0bc: /* GENERAL_PURPOSE4 */
2152 case 0x0c0: /* GENERAL_PURPOSE5 */
2153 case 0x0c4: /* GENERAL_PURPOSE6 */
2154 case 0x0c8: /* GENERAL_PURPOSE7 */
2155 case 0x0cc: /* GENERAL_PURPOSE8 */
2156 case 0x0d0: /* GENERAL_PURPOSE9 */
2157 case 0x0d4: /* GENERAL_PURPOSE10 */
2158 case 0x0d8: /* GENERAL_PURPOSE11 */
2159 case 0x0dc: /* GENERAL_PURPOSE12 */
2160 case 0x0e0: /* GENERAL_PURPOSE13 */
2161 case 0x0e4: /* GENERAL_PURPOSE14 */
2162 case 0x0e8: /* GENERAL_PURPOSE15 */
2163 case 0x0ec: /* GENERAL_PURPOSE16 */
2164 case 0x0f0: /* GENERAL_PURPOSE17 */
2165 case 0x0f4: /* GENERAL_PURPOSE18 */
2166 case 0x0f8: /* GENERAL_PURPOSE19 */
2167 case 0x0fc: /* GENERAL_PURPOSE20 */
2168 s->scratch[(addr - 0xb0) >> 2] = value;
2169 break;
2170
2171 case 0x140: /* CM_CLKSEL_MPU */
2172 s->clksel[0] = value & 0x1f;
2173 /* TODO update clocks */
2174 break;
2175 case 0x148: /* CM_CLKSTCTRL_MPU */
2176 s->clkctrl[0] = value & 0x1f;
2177 break;
2178
2179 case 0x158: /* RM_RSTST_MPU */
2180 s->rst[0] &= ~value;
2181 break;
2182 case 0x1c8: /* PM_WKDEP_MPU */
2183 s->wkup[0] = value & 0x15;
2184 break;
2185
2186 case 0x1d4: /* PM_EVGENCTRL_MPU */
2187 s->ev = value & 0x1f;
2188 break;
2189 case 0x1d8: /* PM_EVEGENONTIM_MPU */
2190 s->evtime[0] = value;
2191 break;
2192 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
2193 s->evtime[1] = value;
2194 break;
2195
2196 case 0x1e0: /* PM_PWSTCTRL_MPU */
2197 s->power[0] = value & 0xc0f;
2198 break;
2199
2200 case 0x200: /* CM_FCLKEN1_CORE */
2201 s->clken[0] = value & 0xbfffffff;
2202 /* TODO update clocks */
2203 /* The EN_EAC bit only gets/puts func_96m_clk. */
2204 break;
2205 case 0x204: /* CM_FCLKEN2_CORE */
2206 s->clken[1] = value & 0x00000007;
2207 /* TODO update clocks */
2208 break;
2209 case 0x210: /* CM_ICLKEN1_CORE */
2210 s->clken[2] = value & 0xfffffff9;
2211 /* TODO update clocks */
2212 /* The EN_EAC bit only gets/puts core_l4_iclk. */
2213 break;
2214 case 0x214: /* CM_ICLKEN2_CORE */
2215 s->clken[3] = value & 0x00000007;
2216 /* TODO update clocks */
2217 break;
2218 case 0x21c: /* CM_ICLKEN4_CORE */
2219 s->clken[4] = value & 0x0000001f;
2220 /* TODO update clocks */
2221 break;
2222
2223 case 0x230: /* CM_AUTOIDLE1_CORE */
2224 s->clkidle[0] = value & 0xfffffff9;
2225 /* TODO update clocks */
2226 break;
2227 case 0x234: /* CM_AUTOIDLE2_CORE */
2228 s->clkidle[1] = value & 0x00000007;
2229 /* TODO update clocks */
2230 break;
2231 case 0x238: /* CM_AUTOIDLE3_CORE */
2232 s->clkidle[2] = value & 0x00000007;
2233 /* TODO update clocks */
2234 break;
2235 case 0x23c: /* CM_AUTOIDLE4_CORE */
2236 s->clkidle[3] = value & 0x0000001f;
2237 /* TODO update clocks */
2238 break;
2239
2240 case 0x240: /* CM_CLKSEL1_CORE */
2241 s->clksel[1] = value & 0x0fffbf7f;
2242 /* TODO update clocks */
2243 break;
2244
2245 case 0x244: /* CM_CLKSEL2_CORE */
2246 s->clksel[2] = value & 0x00fffffc;
2247 /* TODO update clocks */
2248 break;
2249
2250 case 0x248: /* CM_CLKSTCTRL_CORE */
2251 s->clkctrl[1] = value & 0x7;
2252 break;
2253
2254 case 0x2a0: /* PM_WKEN1_CORE */
2255 s->wken[0] = value & 0x04667ff8;
2256 break;
2257 case 0x2a4: /* PM_WKEN2_CORE */
2258 s->wken[1] = value & 0x00000005;
2259 break;
2260
2261 case 0x2b0: /* PM_WKST1_CORE */
2262 s->wkst[0] &= ~value;
2263 break;
2264 case 0x2b4: /* PM_WKST2_CORE */
2265 s->wkst[1] &= ~value;
2266 break;
2267
2268 case 0x2e0: /* PM_PWSTCTRL_CORE */
2269 s->power[1] = (value & 0x00fc3f) | (1 << 2);
2270 break;
2271
2272 case 0x300: /* CM_FCLKEN_GFX */
2273 s->clken[5] = value & 6;
2274 /* TODO update clocks */
2275 break;
2276 case 0x310: /* CM_ICLKEN_GFX */
2277 s->clken[6] = value & 1;
2278 /* TODO update clocks */
2279 break;
2280 case 0x340: /* CM_CLKSEL_GFX */
2281 s->clksel[3] = value & 7;
2282 /* TODO update clocks */
2283 break;
2284 case 0x348: /* CM_CLKSTCTRL_GFX */
2285 s->clkctrl[2] = value & 1;
2286 break;
2287 case 0x350: /* RM_RSTCTRL_GFX */
2288 s->rstctrl[0] = value & 1;
2289 /* TODO: reset */
2290 break;
2291 case 0x358: /* RM_RSTST_GFX */
2292 s->rst[1] &= ~value;
2293 break;
2294 case 0x3c8: /* PM_WKDEP_GFX */
2295 s->wkup[1] = value & 0x13;
2296 break;
2297 case 0x3e0: /* PM_PWSTCTRL_GFX */
2298 s->power[2] = (value & 0x00c0f) | (3 << 2);
2299 break;
2300
2301 case 0x400: /* CM_FCLKEN_WKUP */
2302 s->clken[7] = value & 0xd;
2303 /* TODO update clocks */
2304 break;
2305 case 0x410: /* CM_ICLKEN_WKUP */
2306 s->clken[8] = value & 0x3f;
2307 /* TODO update clocks */
2308 break;
2309 case 0x430: /* CM_AUTOIDLE_WKUP */
2310 s->clkidle[4] = value & 0x0000003f;
2311 /* TODO update clocks */
2312 break;
2313 case 0x440: /* CM_CLKSEL_WKUP */
2314 s->clksel[4] = value & 3;
2315 /* TODO update clocks */
2316 break;
2317 case 0x450: /* RM_RSTCTRL_WKUP */
2318 /* TODO: reset */
2319 if (value & 2)
2320 qemu_system_reset_request();
2321 break;
2322 case 0x454: /* RM_RSTTIME_WKUP */
2323 s->rsttime_wkup = value & 0x1fff;
2324 break;
2325 case 0x458: /* RM_RSTST_WKUP */
2326 s->rst[2] &= ~value;
2327 break;
2328 case 0x4a0: /* PM_WKEN_WKUP */
2329 s->wken[2] = value & 0x00000005;
2330 break;
2331 case 0x4b0: /* PM_WKST_WKUP */
2332 s->wkst[2] &= ~value;
2333 break;
2334
2335 case 0x500: /* CM_CLKEN_PLL */
2336 if (value & 0xffffff30)
2337 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
2338 "future compatiblity\n", __FUNCTION__);
2339 if ((s->clken[9] ^ value) & 0xcc) {
2340 s->clken[9] &= ~0xcc;
2341 s->clken[9] |= value & 0xcc;
2342 omap_prcm_apll_update(s);
2343 }
2344 if ((s->clken[9] ^ value) & 3) {
2345 s->clken[9] &= ~3;
2346 s->clken[9] |= value & 3;
2347 omap_prcm_dpll_update(s);
2348 }
2349 break;
2350 case 0x530: /* CM_AUTOIDLE_PLL */
2351 s->clkidle[5] = value & 0x000000cf;
2352 /* TODO update clocks */
2353 break;
2354 case 0x540: /* CM_CLKSEL1_PLL */
2355 if (value & 0xfc4000d7)
2356 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
2357 "future compatiblity\n", __FUNCTION__);
2358 if ((s->clksel[5] ^ value) & 0x003fff00) {
2359 s->clksel[5] = value & 0x03bfff28;
2360 omap_prcm_dpll_update(s);
2361 }
2362 /* TODO update the other clocks */
2363
2364 s->clksel[5] = value & 0x03bfff28;
2365 break;
2366 case 0x544: /* CM_CLKSEL2_PLL */
2367 if (value & ~3)
2368 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
2369 "future compatiblity\n", __FUNCTION__);
2370 if (s->clksel[6] != (value & 3)) {
2371 s->clksel[6] = value & 3;
2372 omap_prcm_dpll_update(s);
2373 }
2374 break;
2375
2376 case 0x800: /* CM_FCLKEN_DSP */
2377 s->clken[10] = value & 0x501;
2378 /* TODO update clocks */
2379 break;
2380 case 0x810: /* CM_ICLKEN_DSP */
2381 s->clken[11] = value & 0x2;
2382 /* TODO update clocks */
2383 break;
2384 case 0x830: /* CM_AUTOIDLE_DSP */
2385 s->clkidle[6] = value & 0x2;
2386 /* TODO update clocks */
2387 break;
2388 case 0x840: /* CM_CLKSEL_DSP */
2389 s->clksel[7] = value & 0x3fff;
2390 /* TODO update clocks */
2391 break;
2392 case 0x848: /* CM_CLKSTCTRL_DSP */
2393 s->clkctrl[3] = value & 0x101;
2394 break;
2395 case 0x850: /* RM_RSTCTRL_DSP */
2396 /* TODO: reset */
2397 break;
2398 case 0x858: /* RM_RSTST_DSP */
2399 s->rst[3] &= ~value;
2400 break;
2401 case 0x8c8: /* PM_WKDEP_DSP */
2402 s->wkup[2] = value & 0x13;
2403 break;
2404 case 0x8e0: /* PM_PWSTCTRL_DSP */
2405 s->power[3] = (value & 0x03017) | (3 << 2);
2406 break;
2407
2408 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
2409 s->irqst[1] &= ~value;
2410 omap_prcm_int_update(s, 1);
2411 break;
2412 case 0x8f4: /* PRCM_IRQENABLE_DSP */
2413 s->irqen[1] = value & 0x7;
2414 omap_prcm_int_update(s, 1);
2415 break;
2416
2417 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
2418 s->irqst[2] &= ~value;
2419 omap_prcm_int_update(s, 2);
2420 break;
2421 case 0x8fc: /* PRCM_IRQENABLE_IVA */
2422 s->irqen[2] = value & 0x7;
2423 omap_prcm_int_update(s, 2);
2424 break;
2425
2426 default:
2427 OMAP_BAD_REG(addr);
2428 return;
2429 }
2430 }
2431
2432 static CPUReadMemoryFunc * const omap_prcm_readfn[] = {
2433 omap_badwidth_read32,
2434 omap_badwidth_read32,
2435 omap_prcm_read,
2436 };
2437
2438 static CPUWriteMemoryFunc * const omap_prcm_writefn[] = {
2439 omap_badwidth_write32,
2440 omap_badwidth_write32,
2441 omap_prcm_write,
2442 };
2443
2444 static void omap_prcm_reset(struct omap_prcm_s *s)
2445 {
2446 s->sysconfig = 0;
2447 s->irqst[0] = 0;
2448 s->irqst[1] = 0;
2449 s->irqst[2] = 0;
2450 s->irqen[0] = 0;
2451 s->irqen[1] = 0;
2452 s->irqen[2] = 0;
2453 s->voltctrl = 0x1040;
2454 s->ev = 0x14;
2455 s->evtime[0] = 0;
2456 s->evtime[1] = 0;
2457 s->clkctrl[0] = 0;
2458 s->clkctrl[1] = 0;
2459 s->clkctrl[2] = 0;
2460 s->clkctrl[3] = 0;
2461 s->clken[1] = 7;
2462 s->clken[3] = 7;
2463 s->clken[4] = 0;
2464 s->clken[5] = 0;
2465 s->clken[6] = 0;
2466 s->clken[7] = 0xc;
2467 s->clken[8] = 0x3e;
2468 s->clken[9] = 0x0d;
2469 s->clken[10] = 0;
2470 s->clken[11] = 0;
2471 s->clkidle[0] = 0;
2472 s->clkidle[2] = 7;
2473 s->clkidle[3] = 0;
2474 s->clkidle[4] = 0;
2475 s->clkidle[5] = 0x0c;
2476 s->clkidle[6] = 0;
2477 s->clksel[0] = 0x01;
2478 s->clksel[1] = 0x02100121;
2479 s->clksel[2] = 0x00000000;
2480 s->clksel[3] = 0x01;
2481 s->clksel[4] = 0;
2482 s->clksel[7] = 0x0121;
2483 s->wkup[0] = 0x15;
2484 s->wkup[1] = 0x13;
2485 s->wkup[2] = 0x13;
2486 s->wken[0] = 0x04667ff8;
2487 s->wken[1] = 0x00000005;
2488 s->wken[2] = 5;
2489 s->wkst[0] = 0;
2490 s->wkst[1] = 0;
2491 s->wkst[2] = 0;
2492 s->power[0] = 0x00c;
2493 s->power[1] = 4;
2494 s->power[2] = 0x0000c;
2495 s->power[3] = 0x14;
2496 s->rstctrl[0] = 1;
2497 s->rst[3] = 1;
2498 omap_prcm_apll_update(s);
2499 omap_prcm_dpll_update(s);
2500 }
2501
2502 static void omap_prcm_coldreset(struct omap_prcm_s *s)
2503 {
2504 s->setuptime[0] = 0;
2505 s->setuptime[1] = 0;
2506 memset(&s->scratch, 0, sizeof(s->scratch));
2507 s->rst[0] = 0x01;
2508 s->rst[1] = 0x00;
2509 s->rst[2] = 0x01;
2510 s->clken[0] = 0;
2511 s->clken[2] = 0;
2512 s->clkidle[1] = 0;
2513 s->clksel[5] = 0;
2514 s->clksel[6] = 2;
2515 s->clksrc[0] = 0x43;
2516 s->clkout[0] = 0x0303;
2517 s->clkemul[0] = 0;
2518 s->clkpol[0] = 0x100;
2519 s->rsttime_wkup = 0x1002;
2520
2521 omap_prcm_reset(s);
2522 }
2523
2524 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
2525 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
2526 struct omap_mpu_state_s *mpu)
2527 {
2528 int iomemtype;
2529 struct omap_prcm_s *s = (struct omap_prcm_s *)
2530 qemu_mallocz(sizeof(struct omap_prcm_s));
2531
2532 s->irq[0] = mpu_int;
2533 s->irq[1] = dsp_int;
2534 s->irq[2] = iva_int;
2535 s->mpu = mpu;
2536 omap_prcm_coldreset(s);
2537
2538 iomemtype = l4_register_io_memory(omap_prcm_readfn,
2539 omap_prcm_writefn, s);
2540 omap_l4_attach(ta, 0, iomemtype);
2541 omap_l4_attach(ta, 1, iomemtype);
2542
2543 return s;
2544 }
2545
2546 /* System and Pinout control */
2547 struct omap_sysctl_s {
2548 struct omap_mpu_state_s *mpu;
2549
2550 uint32_t sysconfig;
2551 uint32_t devconfig;
2552 uint32_t psaconfig;
2553 uint32_t padconf[0x45];
2554 uint8_t obs;
2555 uint32_t msuspendmux[5];
2556 };
2557
2558 static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
2559 {
2560
2561 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2562 int pad_offset, byte_offset;
2563 int value;
2564
2565 switch (addr) {
2566 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2567 pad_offset = (addr - 0x30) >> 2;
2568 byte_offset = (addr - 0x30) & (4 - 1);
2569
2570 value = s->padconf[pad_offset];
2571 value = (value >> (byte_offset * 8)) & 0xff;
2572
2573 return value;
2574
2575 default:
2576 break;
2577 }
2578
2579 OMAP_BAD_REG(addr);
2580 return 0;
2581 }
2582
2583 static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
2584 {
2585 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2586
2587 switch (addr) {
2588 case 0x000: /* CONTROL_REVISION */
2589 return 0x20;
2590
2591 case 0x010: /* CONTROL_SYSCONFIG */
2592 return s->sysconfig;
2593
2594 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2595 return s->padconf[(addr - 0x30) >> 2];
2596
2597 case 0x270: /* CONTROL_DEBOBS */
2598 return s->obs;
2599
2600 case 0x274: /* CONTROL_DEVCONF */
2601 return s->devconfig;
2602
2603 case 0x28c: /* CONTROL_EMU_SUPPORT */
2604 return 0;
2605
2606 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2607 return s->msuspendmux[0];
2608 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2609 return s->msuspendmux[1];
2610 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2611 return s->msuspendmux[2];
2612 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2613 return s->msuspendmux[3];
2614 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2615 return s->msuspendmux[4];
2616 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2617 return 0;
2618
2619 case 0x2b8: /* CONTROL_PSA_CTRL */
2620 return s->psaconfig;
2621 case 0x2bc: /* CONTROL_PSA_CMD */
2622 case 0x2c0: /* CONTROL_PSA_VALUE */
2623 return 0;
2624
2625 case 0x2b0: /* CONTROL_SEC_CTRL */
2626 return 0x800000f1;
2627 case 0x2d0: /* CONTROL_SEC_EMU */
2628 return 0x80000015;
2629 case 0x2d4: /* CONTROL_SEC_TAP */
2630 return 0x8000007f;
2631 case 0x2b4: /* CONTROL_SEC_TEST */
2632 case 0x2f0: /* CONTROL_SEC_STATUS */
2633 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2634 /* Secure mode is not present on general-pusrpose device. Outside
2635 * secure mode these values cannot be read or written. */
2636 return 0;
2637
2638 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2639 return 0xff;
2640 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2641 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2642 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2643 /* No secure mode so no Extended Secure RAM present. */
2644 return 0;
2645
2646 case 0x2f8: /* CONTROL_STATUS */
2647 /* Device Type => General-purpose */
2648 return 0x0300;
2649 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2650
2651 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2652 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2653 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2654 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2655 return 0xdecafbad;
2656
2657 case 0x310: /* CONTROL_RAND_KEY_0 */
2658 case 0x314: /* CONTROL_RAND_KEY_1 */
2659 case 0x318: /* CONTROL_RAND_KEY_2 */
2660 case 0x31c: /* CONTROL_RAND_KEY_3 */
2661 case 0x320: /* CONTROL_CUST_KEY_0 */
2662 case 0x324: /* CONTROL_CUST_KEY_1 */
2663 case 0x330: /* CONTROL_TEST_KEY_0 */
2664 case 0x334: /* CONTROL_TEST_KEY_1 */
2665 case 0x338: /* CONTROL_TEST_KEY_2 */
2666 case 0x33c: /* CONTROL_TEST_KEY_3 */
2667 case 0x340: /* CONTROL_TEST_KEY_4 */
2668 case 0x344: /* CONTROL_TEST_KEY_5 */
2669 case 0x348: /* CONTROL_TEST_KEY_6 */
2670 case 0x34c: /* CONTROL_TEST_KEY_7 */
2671 case 0x350: /* CONTROL_TEST_KEY_8 */
2672 case 0x354: /* CONTROL_TEST_KEY_9 */
2673 /* Can only be accessed in secure mode and when C_FieldAccEnable
2674 * bit is set in CONTROL_SEC_CTRL.
2675 * TODO: otherwise an interconnect access error is generated. */
2676 return 0;
2677 }
2678
2679 OMAP_BAD_REG(addr);
2680 return 0;
2681 }
2682
2683 static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
2684 uint32_t value)
2685 {
2686 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2687 int pad_offset, byte_offset;
2688 int prev_value;
2689
2690 switch (addr) {
2691 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2692 pad_offset = (addr - 0x30) >> 2;
2693 byte_offset = (addr - 0x30) & (4 - 1);
2694
2695 prev_value = s->padconf[pad_offset];
2696 prev_value &= ~(0xff << (byte_offset * 8));
2697 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
2698 s->padconf[pad_offset] = prev_value;
2699 break;
2700
2701 default:
2702 OMAP_BAD_REG(addr);
2703 break;
2704 }
2705 }
2706
2707 static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
2708 uint32_t value)
2709 {
2710 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2711
2712 switch (addr) {
2713 case 0x000: /* CONTROL_REVISION */
2714 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2715 case 0x2c0: /* CONTROL_PSA_VALUE */
2716 case 0x2f8: /* CONTROL_STATUS */
2717 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2718 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2719 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2720 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2721 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2722 case 0x310: /* CONTROL_RAND_KEY_0 */
2723 case 0x314: /* CONTROL_RAND_KEY_1 */
2724 case 0x318: /* CONTROL_RAND_KEY_2 */
2725 case 0x31c: /* CONTROL_RAND_KEY_3 */
2726 case 0x320: /* CONTROL_CUST_KEY_0 */
2727 case 0x324: /* CONTROL_CUST_KEY_1 */
2728 case 0x330: /* CONTROL_TEST_KEY_0 */
2729 case 0x334: /* CONTROL_TEST_KEY_1 */
2730 case 0x338: /* CONTROL_TEST_KEY_2 */
2731 case 0x33c: /* CONTROL_TEST_KEY_3 */
2732 case 0x340: /* CONTROL_TEST_KEY_4 */
2733 case 0x344: /* CONTROL_TEST_KEY_5 */
2734 case 0x348: /* CONTROL_TEST_KEY_6 */
2735 case 0x34c: /* CONTROL_TEST_KEY_7 */
2736 case 0x350: /* CONTROL_TEST_KEY_8 */
2737 case 0x354: /* CONTROL_TEST_KEY_9 */
2738 OMAP_RO_REG(addr);
2739 return;
2740
2741 case 0x010: /* CONTROL_SYSCONFIG */
2742 s->sysconfig = value & 0x1e;
2743 break;
2744
2745 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2746 /* XXX: should check constant bits */
2747 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
2748 break;
2749
2750 case 0x270: /* CONTROL_DEBOBS */
2751 s->obs = value & 0xff;
2752 break;
2753
2754 case 0x274: /* CONTROL_DEVCONF */
2755 s->devconfig = value & 0xffffc7ff;
2756 break;
2757
2758 case 0x28c: /* CONTROL_EMU_SUPPORT */
2759 break;
2760
2761 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2762 s->msuspendmux[0] = value & 0x3fffffff;
2763 break;
2764 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2765 s->msuspendmux[1] = value & 0x3fffffff;
2766 break;
2767 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2768 s->msuspendmux[2] = value & 0x3fffffff;
2769 break;
2770 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2771 s->msuspendmux[3] = value & 0x3fffffff;
2772 break;
2773 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2774 s->msuspendmux[4] = value & 0x3fffffff;
2775 break;
2776
2777 case 0x2b8: /* CONTROL_PSA_CTRL */
2778 s->psaconfig = value & 0x1c;
2779 s->psaconfig |= (value & 0x20) ? 2 : 1;
2780 break;
2781 case 0x2bc: /* CONTROL_PSA_CMD */
2782 break;
2783
2784 case 0x2b0: /* CONTROL_SEC_CTRL */
2785 case 0x2b4: /* CONTROL_SEC_TEST */
2786 case 0x2d0: /* CONTROL_SEC_EMU */
2787 case 0x2d4: /* CONTROL_SEC_TAP */
2788 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2789 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2790 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2791 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2792 case 0x2f0: /* CONTROL_SEC_STATUS */
2793 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2794 break;
2795
2796 default:
2797 OMAP_BAD_REG(addr);
2798 return;
2799 }
2800 }
2801
2802 static CPUReadMemoryFunc * const omap_sysctl_readfn[] = {
2803 omap_sysctl_read8,
2804 omap_badwidth_read32, /* TODO */
2805 omap_sysctl_read,
2806 };
2807
2808 static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = {
2809 omap_sysctl_write8,
2810 omap_badwidth_write32, /* TODO */
2811 omap_sysctl_write,
2812 };
2813
2814 static void omap_sysctl_reset(struct omap_sysctl_s *s)
2815 {
2816 /* (power-on reset) */
2817 s->sysconfig = 0;
2818 s->obs = 0;
2819 s->devconfig = 0x0c000000;
2820 s->msuspendmux[0] = 0x00000000;
2821 s->msuspendmux[1] = 0x00000000;
2822 s->msuspendmux[2] = 0x00000000;
2823 s->msuspendmux[3] = 0x00000000;
2824 s->msuspendmux[4] = 0x00000000;
2825 s->psaconfig = 1;
2826
2827 s->padconf[0x00] = 0x000f0f0f;
2828 s->padconf[0x01] = 0x00000000;
2829 s->padconf[0x02] = 0x00000000;
2830 s->padconf[0x03] = 0x00000000;
2831 s->padconf[0x04] = 0x00000000;
2832 s->padconf[0x05] = 0x00000000;
2833 s->padconf[0x06] = 0x00000000;
2834 s->padconf[0x07] = 0x00000000;
2835 s->padconf[0x08] = 0x08080800;
2836 s->padconf[0x09] = 0x08080808;
2837 s->padconf[0x0a] = 0x08080808;
2838 s->padconf[0x0b] = 0x08080808;
2839 s->padconf[0x0c] = 0x08080808;
2840 s->padconf[0x0d] = 0x08080800;
2841 s->padconf[0x0e] = 0x08080808;
2842 s->padconf[0x0f] = 0x08080808;
2843 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2844 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2845 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2846 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2847 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2848 s->padconf[0x15] = 0x18181818;
2849 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2850 s->padconf[0x17] = 0x1f001f00;
2851 s->padconf[0x18] = 0x1f1f1f1f;
2852 s->padconf[0x19] = 0x00000000;
2853 s->padconf[0x1a] = 0x1f180000;
2854 s->padconf[0x1b] = 0x00001f1f;
2855 s->padconf[0x1c] = 0x1f001f00;
2856 s->padconf[0x1d] = 0x00000000;
2857 s->padconf[0x1e] = 0x00000000;
2858 s->padconf[0x1f] = 0x08000000;
2859 s->padconf[0x20] = 0x08080808;
2860 s->padconf[0x21] = 0x08080808;
2861 s->padconf[0x22] = 0x0f080808;
2862 s->padconf[0x23] = 0x0f0f0f0f;
2863 s->padconf[0x24] = 0x000f0f0f;
2864 s->padconf[0x25] = 0x1f1f1f0f;
2865 s->padconf[0x26] = 0x080f0f1f;
2866 s->padconf[0x27] = 0x070f1808;
2867 s->padconf[0x28] = 0x0f070707;
2868 s->padconf[0x29] = 0x000f0f1f;
2869 s->padconf[0x2a] = 0x0f0f0f1f;
2870 s->padconf[0x2b] = 0x08000000;
2871 s->padconf[0x2c] = 0x0000001f;
2872 s->padconf[0x2d] = 0x0f0f1f00;
2873 s->padconf[0x2e] = 0x1f1f0f0f;
2874 s->padconf[0x2f] = 0x0f1f1f1f;
2875 s->padconf[0x30] = 0x0f0f0f0f;
2876 s->padconf[0x31] = 0x0f1f0f1f;
2877 s->padconf[0x32] = 0x0f0f0f0f;
2878 s->padconf[0x33] = 0x0f1f0f1f;
2879 s->padconf[0x34] = 0x1f1f0f0f;
2880 s->padconf[0x35] = 0x0f0f1f1f;
2881 s->padconf[0x36] = 0x0f0f1f0f;
2882 s->padconf[0x37] = 0x0f0f0f0f;
2883 s->padconf[0x38] = 0x1f18180f;
2884 s->padconf[0x39] = 0x1f1f1f1f;
2885 s->padconf[0x3a] = 0x00001f1f;
2886 s->padconf[0x3b] = 0x00000000;
2887 s->padconf[0x3c] = 0x00000000;
2888 s->padconf[0x3d] = 0x0f0f0f0f;
2889 s->padconf[0x3e] = 0x18000f0f;
2890 s->padconf[0x3f] = 0x00070000;
2891 s->padconf[0x40] = 0x00000707;
2892 s->padconf[0x41] = 0x0f1f0700;
2893 s->padconf[0x42] = 0x1f1f070f;
2894 s->padconf[0x43] = 0x0008081f;
2895 s->padconf[0x44] = 0x00000800;
2896 }
2897
2898 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
2899 omap_clk iclk, struct omap_mpu_state_s *mpu)
2900 {
2901 int iomemtype;
2902 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
2903 qemu_mallocz(sizeof(struct omap_sysctl_s));
2904
2905 s->mpu = mpu;
2906 omap_sysctl_reset(s);
2907
2908 iomemtype = l4_register_io_memory(omap_sysctl_readfn,
2909 omap_sysctl_writefn, s);
2910 omap_l4_attach(ta, 0, iomemtype);
2911
2912 return s;
2913 }
2914
2915 /* SDRAM Controller Subsystem */
2916 struct omap_sdrc_s {
2917 uint8_t config;
2918 };
2919
2920 static void omap_sdrc_reset(struct omap_sdrc_s *s)
2921 {
2922 s->config = 0x10;
2923 }
2924
2925 static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
2926 {
2927 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
2928
2929 switch (addr) {
2930 case 0x00: /* SDRC_REVISION */
2931 return 0x20;
2932
2933 case 0x10: /* SDRC_SYSCONFIG */
2934 return s->config;
2935
2936 case 0x14: /* SDRC_SYSSTATUS */
2937 return 1; /* RESETDONE */
2938
2939 case 0x40: /* SDRC_CS_CFG */
2940 case 0x44: /* SDRC_SHARING */
2941 case 0x48: /* SDRC_ERR_ADDR */
2942 case 0x4c: /* SDRC_ERR_TYPE */
2943 case 0x60: /* SDRC_DLLA_SCTRL */
2944 case 0x64: /* SDRC_DLLA_STATUS */
2945 case 0x68: /* SDRC_DLLB_CTRL */
2946 case 0x6c: /* SDRC_DLLB_STATUS */
2947 case 0x70: /* SDRC_POWER */
2948 case 0x80: /* SDRC_MCFG_0 */
2949 case 0x84: /* SDRC_MR_0 */
2950 case 0x88: /* SDRC_EMR1_0 */
2951 case 0x8c: /* SDRC_EMR2_0 */
2952 case 0x90: /* SDRC_EMR3_0 */
2953 case 0x94: /* SDRC_DCDL1_CTRL */
2954 case 0x98: /* SDRC_DCDL2_CTRL */
2955 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
2956 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
2957 case 0xa4: /* SDRC_RFR_CTRL_0 */
2958 case 0xa8: /* SDRC_MANUAL_0 */
2959 case 0xb0: /* SDRC_MCFG_1 */
2960 case 0xb4: /* SDRC_MR_1 */
2961 case 0xb8: /* SDRC_EMR1_1 */
2962 case 0xbc: /* SDRC_EMR2_1 */
2963 case 0xc0: /* SDRC_EMR3_1 */
2964 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
2965 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
2966 case 0xd4: /* SDRC_RFR_CTRL_1 */
2967 case 0xd8: /* SDRC_MANUAL_1 */
2968 return 0x00;
2969 }
2970
2971 OMAP_BAD_REG(addr);
2972 return 0;
2973 }
2974
2975 static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
2976 uint32_t value)
2977 {
2978 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
2979
2980 switch (addr) {
2981 case 0x00: /* SDRC_REVISION */
2982 case 0x14: /* SDRC_SYSSTATUS */
2983 case 0x48: /* SDRC_ERR_ADDR */
2984 case 0x64: /* SDRC_DLLA_STATUS */
2985 case 0x6c: /* SDRC_DLLB_STATUS */
2986 OMAP_RO_REG(addr);
2987 return;
2988
2989 case 0x10: /* SDRC_SYSCONFIG */
2990 if ((value >> 3) != 0x2)
2991 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
2992 __FUNCTION__, value >> 3);
2993 if (value & 2)
2994 omap_sdrc_reset(s);
2995 s->config = value & 0x18;
2996 break;
2997
2998 case 0x40: /* SDRC_CS_CFG */
2999 case 0x44: /* SDRC_SHARING */
3000 case 0x4c: /* SDRC_ERR_TYPE */
3001 case 0x60: /* SDRC_DLLA_SCTRL */
3002 case 0x68: /* SDRC_DLLB_CTRL */
3003 case 0x70: /* SDRC_POWER */
3004 case 0x80: /* SDRC_MCFG_0 */
3005 case 0x84: /* SDRC_MR_0 */
3006 case 0x88: /* SDRC_EMR1_0 */
3007 case 0x8c: /* SDRC_EMR2_0 */
3008 case 0x90: /* SDRC_EMR3_0 */
3009 case 0x94: /* SDRC_DCDL1_CTRL */
3010 case 0x98: /* SDRC_DCDL2_CTRL */
3011 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3012 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3013 case 0xa4: /* SDRC_RFR_CTRL_0 */
3014 case 0xa8: /* SDRC_MANUAL_0 */
3015 case 0xb0: /* SDRC_MCFG_1 */
3016 case 0xb4: /* SDRC_MR_1 */
3017 case 0xb8: /* SDRC_EMR1_1 */
3018 case 0xbc: /* SDRC_EMR2_1 */
3019 case 0xc0: /* SDRC_EMR3_1 */
3020 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
3021 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
3022 case 0xd4: /* SDRC_RFR_CTRL_1 */
3023 case 0xd8: /* SDRC_MANUAL_1 */
3024 break;
3025
3026 default:
3027 OMAP_BAD_REG(addr);
3028 return;
3029 }
3030 }
3031
3032 static CPUReadMemoryFunc * const omap_sdrc_readfn[] = {
3033 omap_badwidth_read32,
3034 omap_badwidth_read32,
3035 omap_sdrc_read,
3036 };
3037
3038 static CPUWriteMemoryFunc * const omap_sdrc_writefn[] = {
3039 omap_badwidth_write32,
3040 omap_badwidth_write32,
3041 omap_sdrc_write,
3042 };
3043
3044 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
3045 {
3046 int iomemtype;
3047 struct omap_sdrc_s *s = (struct omap_sdrc_s *)
3048 qemu_mallocz(sizeof(struct omap_sdrc_s));
3049
3050 omap_sdrc_reset(s);
3051
3052 iomemtype = cpu_register_io_memory(omap_sdrc_readfn,
3053 omap_sdrc_writefn, s);
3054 cpu_register_physical_memory(base, 0x1000, iomemtype);
3055
3056 return s;
3057 }
3058
3059 /* General-Purpose Memory Controller */
3060 struct omap_gpmc_s {
3061 qemu_irq irq;
3062
3063 uint8_t sysconfig;
3064 uint16_t irqst;
3065 uint16_t irqen;
3066 uint16_t timeout;
3067 uint16_t config;
3068 uint32_t prefconfig[2];
3069 int prefcontrol;
3070 int preffifo;
3071 int prefcount;
3072 struct omap_gpmc_cs_file_s {
3073 uint32_t config[7];
3074 target_phys_addr_t base;
3075 size_t size;
3076 int iomemtype;
3077 void (*base_update)(void *opaque, target_phys_addr_t new);
3078 void (*unmap)(void *opaque);
3079 void *opaque;
3080 } cs_file[8];
3081 int ecc_cs;
3082 int ecc_ptr;
3083 uint32_t ecc_cfg;
3084 ECCState ecc[9];
3085 };
3086
3087 static void omap_gpmc_int_update(struct omap_gpmc_s *s)
3088 {
3089 qemu_set_irq(s->irq, s->irqen & s->irqst);
3090 }
3091
3092 static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
3093 {
3094 /* TODO: check for overlapping regions and report access errors */
3095 if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) ||
3096 (base < 0 || base >= 0x40) ||
3097 (base & 0x0f & ~mask)) {
3098 fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
3099 __FUNCTION__);
3100 return;
3101 }
3102
3103 if (!f->opaque)
3104 return;
3105
3106 f->base = base << 24;
3107 f->size = (0x0fffffff & ~(mask << 24)) + 1;
3108 /* TODO: rather than setting the size of the mapping (which should be
3109 * constant), the mask should cause wrapping of the address space, so
3110 * that the same memory becomes accessible at every <i>size</i> bytes
3111 * starting from <i>base</i>. */
3112 if (f->iomemtype)
3113 cpu_register_physical_memory(f->base, f->size, f->iomemtype);
3114
3115 if (f->base_update)
3116 f->base_update(f->opaque, f->base);
3117 }
3118
3119 static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
3120 {
3121 if (f->size) {
3122 if (f->unmap)
3123 f->unmap(f->opaque);
3124 if (f->iomemtype)
3125 cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
3126 f->base = 0;
3127 f->size = 0;
3128 }
3129 }
3130
3131 static void omap_gpmc_reset(struct omap_gpmc_s *s)
3132 {
3133 int i;
3134
3135 s->sysconfig = 0;
3136 s->irqst = 0;
3137 s->irqen = 0;
3138 omap_gpmc_int_update(s);
3139 s->timeout = 0;
3140 s->config = 0xa00;
3141 s->prefconfig[0] = 0x00004000;
3142 s->prefconfig[1] = 0x00000000;
3143 s->prefcontrol = 0;
3144 s->preffifo = 0;
3145 s->prefcount = 0;
3146 for (i = 0; i < 8; i ++) {
3147 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
3148 omap_gpmc_cs_unmap(s->cs_file + i);
3149 s->cs_file[i].config[0] = i ? 1 << 12 : 0;
3150 s->cs_file[i].config[1] = 0x101001;
3151 s->cs_file[i].config[2] = 0x020201;
3152 s->cs_file[i].config[3] = 0x10031003;
3153 s->cs_file[i].config[4] = 0x10f1111;
3154 s->cs_file[i].config[5] = 0;
3155 s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
3156 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
3157 omap_gpmc_cs_map(&s->cs_file[i],
3158 s->cs_file[i].config[6] & 0x1f, /* MASKADDR */
3159 (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */
3160 }
3161 omap_gpmc_cs_map(s->cs_file, 0, 0xf);
3162 s->ecc_cs = 0;
3163 s->ecc_ptr = 0;
3164 s->ecc_cfg = 0x3fcff000;
3165 for (i = 0; i < 9; i ++)
3166 ecc_reset(&s->ecc[i]);
3167 }
3168
3169 static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
3170 {
3171 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
3172 int cs;
3173 struct omap_gpmc_cs_file_s *f;
3174
3175 switch (addr) {
3176 case 0x000: /* GPMC_REVISION */
3177 return 0x20;
3178
3179 case 0x010: /* GPMC_SYSCONFIG */
3180 return s->sysconfig;
3181
3182 case 0x014: /* GPMC_SYSSTATUS */
3183 return 1; /* RESETDONE */
3184
3185 case 0x018: /* GPMC_IRQSTATUS */
3186 return s->irqst;
3187
3188 case 0x01c: /* GPMC_IRQENABLE */
3189 return s->irqen;
3190
3191 case 0x040: /* GPMC_TIMEOUT_CONTROL */
3192 return s->timeout;
3193
3194 case 0x044: /* GPMC_ERR_ADDRESS */
3195 case 0x048: /* GPMC_ERR_TYPE */
3196 return 0;
3197
3198 case 0x050: /* GPMC_CONFIG */
3199 return s->config;
3200
3201 case 0x054: /* GPMC_STATUS */
3202 return 0x001;
3203
3204 case 0x060 ... 0x1d4:
3205 cs = (addr - 0x060) / 0x30;
3206 addr -= cs * 0x30;
3207 f = s->cs_file + cs;
3208 switch (addr) {
3209 case 0x60: /* GPMC_CONFIG1 */
3210 return f->config[0];
3211 case 0x64: /* GPMC_CONFIG2 */
3212 return f->config[1];
3213 case 0x68: /* GPMC_CONFIG3 */
3214 return f->config[2];
3215 case 0x6c: /* GPMC_CONFIG4 */
3216 return f->config[3];
3217 case 0x70: /* GPMC_CONFIG5 */
3218 return f->config[4];
3219 case 0x74: /* GPMC_CONFIG6 */
3220 return f->config[5];
3221 case 0x78: /* GPMC_CONFIG7 */
3222 return f->config[6];
3223 case 0x84: /* GPMC_NAND_DATA */
3224 return 0;
3225 }
3226 break;
3227
3228 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
3229 return s->prefconfig[0];
3230 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
3231 return s->prefconfig[1];
3232 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
3233 return s->prefcontrol;
3234 case 0x1f0: /* GPMC_PREFETCH_STATUS */
3235 return (s->preffifo << 24) |
3236 ((s->preffifo >
3237 ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
3238 s->prefcount;
3239
3240 case 0x1f4: /* GPMC_ECC_CONFIG */
3241 return s->ecc_cs;
3242 case 0x1f8: /* GPMC_ECC_CONTROL */
3243 return s->ecc_ptr;
3244 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
3245 return s->ecc_cfg;
3246 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
3247 cs = (addr & 0x1f) >> 2;
3248 /* TODO: check correctness */
3249 return
3250 ((s->ecc[cs].cp & 0x07) << 0) |
3251 ((s->ecc[cs].cp & 0x38) << 13) |
3252 ((s->ecc[cs].lp[0] & 0x1ff) << 3) |
3253 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
3254
3255 case 0x230: /* GPMC_TESTMODE_CTRL */
3256 return 0;
3257 case 0x234: /* GPMC_PSA_LSB */
3258 case 0x238: /* GPMC_PSA_MSB */
3259 return 0x00000000;
3260 }
3261
3262 OMAP_BAD_REG(addr);
3263 return 0;
3264 }
3265
3266 static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
3267 uint32_t value)
3268 {
3269 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
3270 int cs;
3271 struct omap_gpmc_cs_file_s *f;
3272
3273 switch (addr) {
3274 case 0x000: /* GPMC_REVISION */
3275 case 0x014: /* GPMC_SYSSTATUS */
3276 case 0x054: /* GPMC_STATUS */
3277 case 0x1f0: /* GPMC_PREFETCH_STATUS */
3278 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
3279 case 0x234: /* GPMC_PSA_LSB */
3280 case 0x238: /* GPMC_PSA_MSB */
3281 OMAP_RO_REG(addr);
3282 break;
3283
3284 case 0x010: /* GPMC_SYSCONFIG */
3285 if ((value >> 3) == 0x3)
3286 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
3287 __FUNCTION__, value >> 3);
3288 if (value & 2)
3289 omap_gpmc_reset(s);
3290 s->sysconfig = value & 0x19;
3291 break;
3292
3293 case 0x018: /* GPMC_IRQSTATUS */
3294 s->irqen = ~value;
3295 omap_gpmc_int_update(s);
3296 break;
3297
3298 case 0x01c: /* GPMC_IRQENABLE */
3299 s->irqen = value & 0xf03;
3300 omap_gpmc_int_update(s);
3301 break;
3302
3303 case 0x040: /* GPMC_TIMEOUT_CONTROL */
3304 s->timeout = value & 0x1ff1;
3305 break;
3306
3307 case 0x044: /* GPMC_ERR_ADDRESS */
3308 case 0x048: /* GPMC_ERR_TYPE */
3309 break;
3310
3311 case 0x050: /* GPMC_CONFIG */
3312 s->config = value & 0xf13;
3313 break;
3314
3315 case 0x060 ... 0x1d4:
3316 cs = (addr - 0x060) / 0x30;
3317 addr -= cs * 0x30;
3318 f = s->cs_file + cs;
3319 switch (addr) {
3320 case 0x60: /* GPMC_CONFIG1 */
3321 f->config[0] = value & 0xffef3e13;
3322 break;
3323 case 0x64: /* GPMC_CONFIG2 */
3324 f->config[1] = value & 0x001f1f8f;
3325 break;
3326 case 0x68: /* GPMC_CONFIG3 */
3327 f->config[2] = value & 0x001f1f8f;
3328 break;
3329 case 0x6c: /* GPMC_CONFIG4 */
3330 f->config[3] = value & 0x1f8f1f8f;
3331 break;
3332 case 0x70: /* GPMC_CONFIG5 */
3333 f->config[4] = value & 0x0f1f1f1f;
3334 break;
3335 case 0x74: /* GPMC_CONFIG6 */
3336 f->config[5] = value & 0x00000fcf;
3337 break;
3338 case 0x78: /* GPMC_CONFIG7 */
3339 if ((f->config[6] ^ value) & 0xf7f) {
3340 if (f->config[6] & (1 << 6)) /* CSVALID */
3341 omap_gpmc_cs_unmap(f);
3342 if (value & (1 << 6)) /* CSVALID */
3343 omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */
3344 (value >> 8 & 0xf)); /* BASEADDR */
3345 }
3346 f->config[6] = value & 0x00000f7f;
3347 break;
3348 case 0x7c: /* GPMC_NAND_COMMAND */
3349 case 0x80: /* GPMC_NAND_ADDRESS */
3350 case 0x84: /* GPMC_NAND_DATA */
3351 break;
3352
3353 default:
3354 goto bad_reg;
3355 }
3356 break;
3357
3358 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
3359 s->prefconfig[0] = value & 0x7f8f7fbf;
3360 /* TODO: update interrupts, fifos, dmas */
3361 break;
3362
3363 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
3364 s->prefconfig[1] = value & 0x3fff;
3365 break;
3366
3367 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
3368 s->prefcontrol = value & 1;
3369 if (s->prefcontrol) {
3370 if (s->prefconfig[0] & 1)
3371 s->preffifo = 0x40;
3372 else
3373 s->preffifo = 0x00;
3374 }
3375 /* TODO: start */
3376 break;
3377
3378 case 0x1f4: /* GPMC_ECC_CONFIG */
3379 s->ecc_cs = 0x8f;
3380 break;
3381 case 0x1f8: /* GPMC_ECC_CONTROL */
3382 if (value & (1 << 8))
3383 for (cs = 0; cs < 9; cs ++)
3384 ecc_reset(&s->ecc[cs]);
3385 s->ecc_ptr = value & 0xf;
3386 if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
3387 s->ecc_ptr = 0;
3388 s->ecc_cs &= ~1;
3389 }
3390 break;
3391 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
3392 s->ecc_cfg = value & 0x3fcff1ff;
3393 break;
3394 case 0x230: /* GPMC_TESTMODE_CTRL */
3395 if (value & 7)
3396 fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
3397 break;
3398
3399 default:
3400 bad_reg:
3401 OMAP_BAD_REG(addr);
3402 return;
3403 }
3404 }
3405
3406 static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
3407 omap_badwidth_read32, /* TODO */
3408 omap_badwidth_read32, /* TODO */
3409 omap_gpmc_read,
3410 };
3411
3412 static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
3413 omap_badwidth_write32, /* TODO */
3414 omap_badwidth_write32, /* TODO */
3415 omap_gpmc_write,
3416 };
3417
3418 struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
3419 {
3420 int iomemtype;
3421 struct omap_gpmc_s *s = (struct omap_gpmc_s *)
3422 qemu_mallocz(sizeof(struct omap_gpmc_s));
3423
3424 omap_gpmc_reset(s);
3425
3426 iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
3427 omap_gpmc_writefn, s);
3428 cpu_register_physical_memory(base, 0x1000, iomemtype);
3429
3430 return s;
3431 }
3432
3433 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
3434 void (*base_upd)(void *opaque, target_phys_addr_t new),
3435 void (*unmap)(void *opaque), void *opaque)
3436 {
3437 struct omap_gpmc_cs_file_s *f;
3438
3439 if (cs < 0 || cs >= 8) {
3440 fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
3441 exit(-1);
3442 }
3443 f = &s->cs_file[cs];
3444
3445 f->iomemtype = iomemtype;
3446 f->base_update = base_upd;
3447 f->unmap = unmap;
3448 f->opaque = opaque;
3449
3450 if (f->config[6] & (1 << 6)) /* CSVALID */
3451 omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */
3452 (f->config[6] >> 8 & 0xf)); /* BASEADDR */
3453 }
3454
3455 /* General chip reset */
3456 static void omap2_mpu_reset(void *opaque)
3457 {
3458 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3459
3460 omap_inth_reset(mpu->ih[0]);
3461 omap_dma_reset(mpu->dma);
3462 omap_prcm_reset(mpu->prcm);
3463 omap_sysctl_reset(mpu->sysc);
3464 omap_gp_timer_reset(mpu->gptimer[0]);
3465 omap_gp_timer_reset(mpu->gptimer[1]);
3466 omap_gp_timer_reset(mpu->gptimer[2]);
3467 omap_gp_timer_reset(mpu->gptimer[3]);
3468 omap_gp_timer_reset(mpu->gptimer[4]);
3469 omap_gp_timer_reset(mpu->gptimer[5]);
3470 omap_gp_timer_reset(mpu->gptimer[6]);
3471 omap_gp_timer_reset(mpu->gptimer[7]);
3472 omap_gp_timer_reset(mpu->gptimer[8]);
3473 omap_gp_timer_reset(mpu->gptimer[9]);
3474 omap_gp_timer_reset(mpu->gptimer[10]);
3475 omap_gp_timer_reset(mpu->gptimer[11]);
3476 omap_synctimer_reset(&mpu->synctimer);
3477 omap_sdrc_reset(mpu->sdrc);
3478 omap_gpmc_reset(mpu->gpmc);
3479 omap_dss_reset(mpu->dss);
3480 omap_uart_reset(mpu->uart[0]);
3481 omap_uart_reset(mpu->uart[1]);
3482 omap_uart_reset(mpu->uart[2]);
3483 omap_mmc_reset(mpu->mmc);
3484 omap_gpif_reset(mpu->gpif);
3485 omap_mcspi_reset(mpu->mcspi[0]);
3486 omap_mcspi_reset(mpu->mcspi[1]);
3487 omap_i2c_reset(mpu->i2c[0]);
3488 omap_i2c_reset(mpu->i2c[1]);
3489 cpu_reset(mpu->env);
3490 }
3491
3492 static int omap2_validate_addr(struct omap_mpu_state_s *s,
3493 target_phys_addr_t addr)
3494 {
3495 return 1;
3496 }
3497
3498 static const struct dma_irq_map omap2_dma_irq_map[] = {
3499 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
3500 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
3501 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
3502 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
3503 };
3504
3505 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
3506 const char *core)
3507 {
3508 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
3509 qemu_mallocz(sizeof(struct omap_mpu_state_s));
3510 ram_addr_t sram_base, q2_base;
3511 qemu_irq *cpu_irq;
3512 qemu_irq dma_irqs[4];
3513 omap_clk gpio_clks[4];
3514 DriveInfo *dinfo;
3515 int i;
3516
3517 /* Core */
3518 s->mpu_model = omap2420;
3519 s->env = cpu_init(core ?: "arm1136-r2");
3520 if (!s->env) {
3521 fprintf(stderr, "Unable to find CPU definition\n");
3522 exit(1);
3523 }
3524 s->sdram_size = sdram_size;
3525 s->sram_size = OMAP242X_SRAM_SIZE;
3526
3527 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
3528
3529 /* Clocks */
3530 omap_clk_init(s);
3531
3532 /* Memory-mapped stuff */
3533 cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
3534 (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
3535 cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
3536 (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
3537
3538 s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
3539
3540 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
3541 cpu_irq = arm_pic_init_cpu(s->env);
3542 s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
3543 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
3544 omap_findclk(s, "mpu_intc_fclk"),
3545 omap_findclk(s, "mpu_intc_iclk"));
3546
3547 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
3548 s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
3549
3550 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
3551 omap_findclk(s, "omapctrl_iclk"), s);
3552
3553 for (i = 0; i < 4; i ++)
3554 dma_irqs[i] =
3555 s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
3556 s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
3557 omap_findclk(s, "sdma_iclk"),
3558 omap_findclk(s, "sdma_fclk"));
3559 s->port->addr_valid = omap2_validate_addr;
3560
3561 /* Register SDRAM and SRAM ports for fast DMA transfers. */
3562 soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
3563 soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
3564
3565 s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
3566 s->irq[0][OMAP_INT_24XX_UART1_IRQ],
3567 omap_findclk(s, "uart1_fclk"),
3568 omap_findclk(s, "uart1_iclk"),
3569 s->drq[OMAP24XX_DMA_UART1_TX],
3570 s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
3571 s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
3572 s->irq[0][OMAP_INT_24XX_UART2_IRQ],
3573 omap_findclk(s, "uart2_fclk"),
3574 omap_findclk(s, "uart2_iclk"),
3575 s->drq[OMAP24XX_DMA_UART2_TX],
3576 s->drq[OMAP24XX_DMA_UART2_RX],
3577 serial_hds[0] ? serial_hds[1] : NULL);
3578 s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
3579 s->irq[0][OMAP_INT_24XX_UART3_IRQ],
3580 omap_findclk(s, "uart3_fclk"),
3581 omap_findclk(s, "uart3_iclk"),
3582 s->drq[OMAP24XX_DMA_UART3_TX],
3583 s->drq[OMAP24XX_DMA_UART3_RX],
3584 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
3585
3586 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
3587 s->irq[0][OMAP_INT_24XX_GPTIMER1],
3588 omap_findclk(s, "wu_gpt1_clk"),
3589 omap_findclk(s, "wu_l4_iclk"));
3590 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
3591 s->irq[0][OMAP_INT_24XX_GPTIMER2],
3592 omap_findclk(s, "core_gpt2_clk"),
3593 omap_findclk(s, "core_l4_iclk"));
3594 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
3595 s->irq[0][OMAP_INT_24XX_GPTIMER3],
3596 omap_findclk(s, "core_gpt3_clk"),
3597 omap_findclk(s, "core_l4_iclk"));
3598 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
3599 s->irq[0][OMAP_INT_24XX_GPTIMER4],
3600 omap_findclk(s, "core_gpt4_clk"),
3601 omap_findclk(s, "core_l4_iclk"));
3602 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
3603 s->irq[0][OMAP_INT_24XX_GPTIMER5],
3604 omap_findclk(s, "core_gpt5_clk"),
3605 omap_findclk(s, "core_l4_iclk"));
3606 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
3607 s->irq[0][OMAP_INT_24XX_GPTIMER6],
3608 omap_findclk(s, "core_gpt6_clk"),
3609 omap_findclk(s, "core_l4_iclk"));
3610 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
3611 s->irq[0][OMAP_INT_24XX_GPTIMER7],
3612 omap_findclk(s, "core_gpt7_clk"),
3613 omap_findclk(s, "core_l4_iclk"));
3614 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
3615 s->irq[0][OMAP_INT_24XX_GPTIMER8],
3616 omap_findclk(s, "core_gpt8_clk"),
3617 omap_findclk(s, "core_l4_iclk"));
3618 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
3619 s->irq[0][OMAP_INT_24XX_GPTIMER9],
3620 omap_findclk(s, "core_gpt9_clk"),
3621 omap_findclk(s, "core_l4_iclk"));
3622 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
3623 s->irq[0][OMAP_INT_24XX_GPTIMER10],
3624 omap_findclk(s, "core_gpt10_clk"),
3625 omap_findclk(s, "core_l4_iclk"));
3626 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
3627 s->irq[0][OMAP_INT_24XX_GPTIMER11],
3628 omap_findclk(s, "core_gpt11_clk"),
3629 omap_findclk(s, "core_l4_iclk"));
3630 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
3631 s->irq[0][OMAP_INT_24XX_GPTIMER12],
3632 omap_findclk(s, "core_gpt12_clk"),
3633 omap_findclk(s, "core_l4_iclk"));
3634
3635 omap_tap_init(omap_l4ta(s->l4, 2), s);
3636
3637 omap_synctimer_init(omap_l4tao(s->l4, 2), s,
3638 omap_findclk(s, "clk32-kHz"),
3639 omap_findclk(s, "core_l4_iclk"));
3640
3641 s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
3642 s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
3643 &s->drq[OMAP24XX_DMA_I2C1_TX],
3644 omap_findclk(s, "i2c1.fclk"),
3645 omap_findclk(s, "i2c1.iclk"));
3646 s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
3647 s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
3648 &s->drq[OMAP24XX_DMA_I2C2_TX],
3649 omap_findclk(s, "i2c2.fclk"),
3650 omap_findclk(s, "i2c2.iclk"));
3651
3652 gpio_clks[0] = omap_findclk(s, "gpio1_dbclk");
3653 gpio_clks[1] = omap_findclk(s, "gpio2_dbclk");
3654 gpio_clks[2] = omap_findclk(s, "gpio3_dbclk");
3655 gpio_clks[3] = omap_findclk(s, "gpio4_dbclk");
3656 s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
3657 &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
3658 gpio_clks, omap_findclk(s, "gpio_iclk"), 4);
3659
3660 s->sdrc = omap_sdrc_init(0x68009000);
3661 s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
3662
3663 dinfo = drive_get(IF_SD, 0, 0);
3664 if (!dinfo) {
3665 fprintf(stderr, "qemu: missing SecureDigital device\n");
3666 exit(1);
3667 }
3668 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
3669 s->irq[0][OMAP_INT_24XX_MMC_IRQ],
3670 &s->drq[OMAP24XX_DMA_MMC1_TX],
3671 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
3672
3673 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
3674 s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
3675 &s->drq[OMAP24XX_DMA_SPI1_TX0],
3676 omap_findclk(s, "spi1_fclk"),
3677 omap_findclk(s, "spi1_iclk"));
3678 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
3679 s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
3680 &s->drq[OMAP24XX_DMA_SPI2_TX0],
3681 omap_findclk(s, "spi2_fclk"),
3682 omap_findclk(s, "spi2_iclk"));
3683
3684 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
3685 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
3686 s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
3687 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
3688 omap_findclk(s, "dss_54m_clk"),
3689 omap_findclk(s, "dss_l3_iclk"),
3690 omap_findclk(s, "dss_l4_iclk"));
3691
3692 omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
3693 s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
3694 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
3695 serial_hds[3] : NULL);
3696
3697 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
3698 s->irq[0][OMAP_INT_24XX_EAC_IRQ],
3699 /* Ten consecutive lines */
3700 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
3701 omap_findclk(s, "func_96m_clk"),
3702 omap_findclk(s, "core_l4_iclk"));
3703
3704 /* All register mappings (includin those not currenlty implemented):
3705 * SystemControlMod 48000000 - 48000fff
3706 * SystemControlL4 48001000 - 48001fff
3707 * 32kHz Timer Mod 48004000 - 48004fff
3708 * 32kHz Timer L4 48005000 - 48005fff
3709 * PRCM ModA 48008000 - 480087ff
3710 * PRCM ModB 48008800 - 48008fff
3711 * PRCM L4 48009000 - 48009fff
3712 * TEST-BCM Mod 48012000 - 48012fff
3713 * TEST-BCM L4 48013000 - 48013fff
3714 * TEST-TAP Mod 48014000 - 48014fff
3715 * TEST-TAP L4 48015000 - 48015fff
3716 * GPIO1 Mod 48018000 - 48018fff
3717 * GPIO Top 48019000 - 48019fff
3718 * GPIO2 Mod 4801a000 - 4801afff
3719 * GPIO L4 4801b000 - 4801bfff
3720 * GPIO3 Mod 4801c000 - 4801cfff
3721 * GPIO4 Mod 4801e000 - 4801efff
3722 * WDTIMER1 Mod 48020000 - 48010fff
3723 * WDTIMER Top 48021000 - 48011fff
3724 * WDTIMER2 Mod 48022000 - 48012fff
3725 * WDTIMER L4 48023000 - 48013fff
3726 * WDTIMER3 Mod 48024000 - 48014fff
3727 * WDTIMER3 L4 48025000 - 48015fff
3728 * WDTIMER4 Mod 48026000 - 48016fff
3729 * WDTIMER4 L4 48027000 - 48017fff
3730 * GPTIMER1 Mod 48028000 - 48018fff
3731 * GPTIMER1 L4 48029000 - 48019fff
3732 * GPTIMER2 Mod 4802a000 - 4801afff
3733 * GPTIMER2 L4 4802b000 - 4801bfff
3734 * L4-Config AP 48040000 - 480407ff
3735 * L4-Config IP 48040800 - 48040fff
3736 * L4-Config LA 48041000 - 48041fff
3737 * ARM11ETB Mod 48048000 - 48049fff
3738 * ARM11ETB L4 4804a000 - 4804afff
3739 * DISPLAY Top 48050000 - 480503ff
3740 * DISPLAY DISPC 48050400 - 480507ff
3741 * DISPLAY RFBI 48050800 - 48050bff
3742 * DISPLAY VENC 48050c00 - 48050fff
3743 * DISPLAY L4 48051000 - 48051fff
3744 * CAMERA Top 48052000 - 480523ff
3745 * CAMERA core 48052400 - 480527ff
3746 * CAMERA DMA 48052800 - 48052bff
3747 * CAMERA MMU 48052c00 - 48052fff
3748 * CAMERA L4 48053000 - 48053fff
3749 * SDMA Mod 48056000 - 48056fff
3750 * SDMA L4 48057000 - 48057fff
3751 * SSI Top 48058000 - 48058fff
3752 * SSI GDD 48059000 - 48059fff
3753 * SSI Port1 4805a000 - 4805afff
3754 * SSI Port2 4805b000 - 4805bfff
3755 * SSI L4 4805c000 - 4805cfff
3756 * USB Mod 4805e000 - 480fefff
3757 * USB L4 4805f000 - 480fffff
3758 * WIN_TRACER1 Mod 48060000 - 48060fff
3759 * WIN_TRACER1 L4 48061000 - 48061fff
3760 * WIN_TRACER2 Mod 48062000 - 48062fff
3761 * WIN_TRACER2 L4 48063000 - 48063fff
3762 * WIN_TRACER3 Mod 48064000 - 48064fff
3763 * WIN_TRACER3 L4 48065000 - 48065fff
3764 * WIN_TRACER4 Top 48066000 - 480660ff
3765 * WIN_TRACER4 ETT 48066100 - 480661ff
3766 * WIN_TRACER4 WT 48066200 - 480662ff
3767 * WIN_TRACER4 L4 48067000 - 48067fff
3768 * XTI Mod 48068000 - 48068fff
3769 * XTI L4 48069000 - 48069fff
3770 * UART1 Mod 4806a000 - 4806afff
3771 * UART1 L4 4806b000 - 4806bfff
3772 * UART2 Mod 4806c000 - 4806cfff
3773 * UART2 L4 4806d000 - 4806dfff
3774 * UART3 Mod 4806e000 - 4806efff
3775 * UART3 L4 4806f000 - 4806ffff
3776 * I2C1 Mod 48070000 - 48070fff
3777 * I2C1 L4 48071000 - 48071fff
3778 * I2C2 Mod 48072000 - 48072fff
3779 * I2C2 L4 48073000 - 48073fff
3780 * McBSP1 Mod 48074000 - 48074fff
3781 * McBSP1 L4 48075000 - 48075fff
3782 * McBSP2 Mod 48076000 - 48076fff
3783 * McBSP2 L4 48077000 - 48077fff
3784 * GPTIMER3 Mod 48078000 - 48078fff
3785 * GPTIMER3 L4 48079000 - 48079fff
3786 * GPTIMER4 Mod 4807a000 - 4807afff
3787 * GPTIMER4 L4 4807b000 - 4807bfff
3788 * GPTIMER5 Mod 4807c000 - 4807cfff
3789 * GPTIMER5 L4 4807d000 - 4807dfff
3790 * GPTIMER6 Mod 4807e000 - 4807efff
3791 * GPTIMER6 L4 4807f000 - 4807ffff
3792 * GPTIMER7 Mod 48080000 - 48080fff
3793 * GPTIMER7 L4 48081000 - 48081fff
3794 * GPTIMER8 Mod 48082000 - 48082fff
3795 * GPTIMER8 L4 48083000 - 48083fff
3796 * GPTIMER9 Mod 48084000 - 48084fff
3797 * GPTIMER9 L4 48085000 - 48085fff
3798 * GPTIMER10 Mod 48086000 - 48086fff
3799 * GPTIMER10 L4 48087000 - 48087fff
3800 * GPTIMER11 Mod 48088000 - 48088fff
3801 * GPTIMER11 L4 48089000 - 48089fff
3802 * GPTIMER12 Mod 4808a000 - 4808afff
3803 * GPTIMER12 L4 4808b000 - 4808bfff
3804 * EAC Mod 48090000 - 48090fff
3805 * EAC L4 48091000 - 48091fff
3806 * FAC Mod 48092000 - 48092fff
3807 * FAC L4 48093000 - 48093fff
3808 * MAILBOX Mod 48094000 - 48094fff
3809 * MAILBOX L4 48095000 - 48095fff
3810 * SPI1 Mod 48098000 - 48098fff
3811 * SPI1 L4 48099000 - 48099fff
3812 * SPI2 Mod 4809a000 - 4809afff
3813 * SPI2 L4 4809b000 - 4809bfff
3814 * MMC/SDIO Mod 4809c000 - 4809cfff
3815 * MMC/SDIO L4 4809d000 - 4809dfff
3816 * MS_PRO Mod 4809e000 - 4809efff
3817 * MS_PRO L4 4809f000 - 4809ffff
3818 * RNG Mod 480a0000 - 480a0fff
3819 * RNG L4 480a1000 - 480a1fff
3820 * DES3DES Mod 480a2000 - 480a2fff
3821 * DES3DES L4 480a3000 - 480a3fff
3822 * SHA1MD5 Mod 480a4000 - 480a4fff
3823 * SHA1MD5 L4 480a5000 - 480a5fff
3824 * AES Mod 480a6000 - 480a6fff
3825 * AES L4 480a7000 - 480a7fff
3826 * PKA Mod 480a8000 - 480a9fff
3827 * PKA L4 480aa000 - 480aafff
3828 * MG Mod 480b0000 - 480b0fff
3829 * MG L4 480b1000 - 480b1fff
3830 * HDQ/1-wire Mod 480b2000 - 480b2fff
3831 * HDQ/1-wire L4 480b3000 - 480b3fff
3832 * MPU interrupt 480fe000 - 480fefff
3833 * STI channel base 54000000 - 5400ffff
3834 * IVA RAM 5c000000 - 5c01ffff
3835 * IVA ROM 5c020000 - 5c027fff
3836 * IMG_BUF_A 5c040000 - 5c040fff
3837 * IMG_BUF_B 5c042000 - 5c042fff
3838 * VLCDS 5c048000 - 5c0487ff
3839 * IMX_COEF 5c049000 - 5c04afff
3840 * IMX_CMD 5c051000 - 5c051fff
3841 * VLCDQ 5c053000 - 5c0533ff
3842 * VLCDH 5c054000 - 5c054fff
3843 * SEQ_CMD 5c055000 - 5c055fff
3844 * IMX_REG 5c056000 - 5c0560ff
3845 * VLCD_REG 5c056100 - 5c0561ff
3846 * SEQ_REG 5c056200 - 5c0562ff
3847 * IMG_BUF_REG 5c056300 - 5c0563ff
3848 * SEQIRQ_REG 5c056400 - 5c0564ff
3849 * OCP_REG 5c060000 - 5c060fff
3850 * SYSC_REG 5c070000 - 5c070fff
3851 * MMU_REG 5d000000 - 5d000fff
3852 * sDMA R 68000400 - 680005ff
3853 * sDMA W 68000600 - 680007ff
3854 * Display Control 68000800 - 680009ff
3855 * DSP subsystem 68000a00 - 68000bff
3856 * MPU subsystem 68000c00 - 68000dff
3857 * IVA subsystem 68001000 - 680011ff
3858 * USB 68001200 - 680013ff
3859 * Camera 68001400 - 680015ff
3860 * VLYNQ (firewall) 68001800 - 68001bff
3861 * VLYNQ 68001e00 - 68001fff
3862 * SSI 68002000 - 680021ff
3863 * L4 68002400 - 680025ff
3864 * DSP (firewall) 68002800 - 68002bff
3865 * DSP subsystem 68002e00 - 68002fff
3866 * IVA (firewall) 68003000 - 680033ff
3867 * IVA 68003600 - 680037ff
3868 * GFX 68003a00 - 68003bff
3869 * CMDWR emulation 68003c00 - 68003dff
3870 * SMS 68004000 - 680041ff
3871 * OCM 68004200 - 680043ff
3872 * GPMC 68004400 - 680045ff
3873 * RAM (firewall) 68005000 - 680053ff
3874 * RAM (err login) 68005400 - 680057ff
3875 * ROM (firewall) 68005800 - 68005bff
3876 * ROM (err login) 68005c00 - 68005fff
3877 * GPMC (firewall) 68006000 - 680063ff
3878 * GPMC (err login) 68006400 - 680067ff
3879 * SMS (err login) 68006c00 - 68006fff
3880 * SMS registers 68008000 - 68008fff
3881 * SDRC registers 68009000 - 68009fff
3882 * GPMC registers 6800a000 6800afff
3883 */
3884
3885 qemu_register_reset(omap2_mpu_reset, s);
3886
3887 return s;
3888 }
QEmu