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usb-ehci: improve mmio tracing
[qemu.git] / hw / usb-ehci.c
blobb9204ab457d4d4fba5aca9e2ddb9a6d2a70b273f
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 *
24 * TODO:
25 * o Downstream port handoff
26 */
27
28 #include "hw.h"
29 #include "qemu-timer.h"
30 #include "usb.h"
31 #include "pci.h"
32 #include "monitor.h"
33 #include "trace.h"
34
35 #define EHCI_DEBUG 0
36
37 #if EHCI_DEBUG
38 #define DPRINTF printf
39 #else
40 #define DPRINTF(...)
41 #endif
42
43 /* internal processing - reset HC to try and recover */
44 #define USB_RET_PROCERR (-99)
45
46 #define MMIO_SIZE 0x1000
47
48 /* Capability Registers Base Address - section 2.2 */
49 #define CAPREGBASE 0x0000
50 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54 #define EECP HCCPARAMS + 1
55 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
57
58 #define OPREGBASE 0x0020 // Operational Registers Base Address
59
60 #define USBCMD OPREGBASE + 0x0000
61 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
62 #define USBCMD_HCRESET (1 << 1) // HC Reset
63 #define USBCMD_FLS (3 << 2) // Frame List Size
64 #define USBCMD_FLS_SH 2 // Frame List Size Shift
65 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
73
74 #define USBSTS OPREGBASE + 0x0004
75 #define USBSTS_RO_MASK 0x0000003f
76 #define USBSTS_INT (1 << 0) // USB Interrupt
77 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
78 #define USBSTS_PCD (1 << 2) // Port Change Detect
79 #define USBSTS_FLR (1 << 3) // Frame List Rollover
80 #define USBSTS_HSE (1 << 4) // Host System Error
81 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82 #define USBSTS_HALT (1 << 12) // HC Halted
83 #define USBSTS_REC (1 << 13) // Reclamation
84 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86
87 /*
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
90 */
91 #define USBINTR OPREGBASE + 0x0008
92 #define USBINTR_MASK 0x0000003f
93
94 #define FRINDEX OPREGBASE + 0x000c
95 #define CTRLDSSEGMENT OPREGBASE + 0x0010
96 #define PERIODICLISTBASE OPREGBASE + 0x0014
97 #define ASYNCLISTADDR OPREGBASE + 0x0018
98 #define ASYNCLISTADDR_MASK 0xffffffe0
99
100 #define CONFIGFLAG OPREGBASE + 0x0040
101
102 #define PORTSC (OPREGBASE + 0x0044)
103 #define PORTSC_BEGIN PORTSC
104 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
105 /*
106 * Bits that are reserverd or are read-only are masked out of values
107 * written to us by software
108 */
109 #define PORTSC_RO_MASK 0x007021c5
110 #define PORTSC_RWC_MASK 0x0000002a
111 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114 #define PORTSC_PTC (15 << 16) // Port Test Control
115 #define PORTSC_PTC_SH 16 // Port Test Control shift
116 #define PORTSC_PIC (3 << 14) // Port Indicator Control
117 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118 #define PORTSC_POWNER (1 << 13) // Port Owner
119 #define PORTSC_PPOWER (1 << 12) // Port Power
120 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
121 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122 #define PORTSC_PRESET (1 << 8) // Port Reset
123 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
124 #define PORTSC_FPRES (1 << 6) // Force Port Resume
125 #define PORTSC_OCC (1 << 5) // Over Current Change
126 #define PORTSC_OCA (1 << 4) // Over Current Active
127 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128 #define PORTSC_PED (1 << 2) // Port Enable/Disable
129 #define PORTSC_CSC (1 << 1) // Connect Status Change
130 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
131
132 #define FRAME_TIMER_FREQ 1000
133 #define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
134
135 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136 #define NB_PORTS 4 // Number of downstream ports
137 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139 #define MAX_QH 100 // Max allowable queue heads in a chain
140
141 /* Internal periodic / asynchronous schedule state machine states
142 */
143 typedef enum {
144 EST_INACTIVE = 1000,
145 EST_ACTIVE,
146 EST_EXECUTING,
147 EST_SLEEPING,
148 /* The following states are internal to the state machine function
149 */
150 EST_WAITLISTHEAD,
151 EST_FETCHENTRY,
152 EST_FETCHQH,
153 EST_FETCHITD,
154 EST_ADVANCEQUEUE,
155 EST_FETCHQTD,
156 EST_EXECUTE,
157 EST_WRITEBACK,
158 EST_HORIZONTALQH
159 } EHCI_STATES;
160
161 /* macros for accessing fields within next link pointer entry */
162 #define NLPTR_GET(x) ((x) & 0xffffffe0)
163 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
165
166 /* link pointer types */
167 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168 #define NLPTR_TYPE_QH 1 // queue head
169 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
171
172
173 /* EHCI spec version 1.0 Section 3.3
174 */
175 typedef struct EHCIitd {
176 uint32_t next;
177
178 uint32_t transact[8];
179 #define ITD_XACT_ACTIVE (1 << 31)
180 #define ITD_XACT_DBERROR (1 << 30)
181 #define ITD_XACT_BABBLE (1 << 29)
182 #define ITD_XACT_XACTERR (1 << 28)
183 #define ITD_XACT_LENGTH_MASK 0x0fff0000
184 #define ITD_XACT_LENGTH_SH 16
185 #define ITD_XACT_IOC (1 << 15)
186 #define ITD_XACT_PGSEL_MASK 0x00007000
187 #define ITD_XACT_PGSEL_SH 12
188 #define ITD_XACT_OFFSET_MASK 0x00000fff
189
190 uint32_t bufptr[7];
191 #define ITD_BUFPTR_MASK 0xfffff000
192 #define ITD_BUFPTR_SH 12
193 #define ITD_BUFPTR_EP_MASK 0x00000f00
194 #define ITD_BUFPTR_EP_SH 8
195 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196 #define ITD_BUFPTR_DEVADDR_SH 0
197 #define ITD_BUFPTR_DIRECTION (1 << 11)
198 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199 #define ITD_BUFPTR_MAXPKT_SH 0
200 #define ITD_BUFPTR_MULT_MASK 0x00000003
201 } EHCIitd;
202
203 /* EHCI spec version 1.0 Section 3.4
204 */
205 typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208 #define SITD_EPCHAR_IO (1 << 31)
209 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210 #define SITD_EPCHAR_PORTNUM_SH 24
211 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212 #define SITD_EPCHAR_HUBADDR_SH 16
213 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214 #define SITD_EPCHAR_EPNUM_SH 8
215 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
219 #define SITD_UFRAME_CMASK_SH 8
220 #define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223 #define SITD_RESULTS_IOC (1 << 31)
224 #define SITD_RESULTS_PGSEL (1 << 30)
225 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226 #define SITD_RESULTS_TYBYTES_SH 16
227 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228 #define SITD_RESULTS_CPROGMASK_SH 8
229 #define SITD_RESULTS_ACTIVE (1 << 7)
230 #define SITD_RESULTS_ERR (1 << 6)
231 #define SITD_RESULTS_DBERR (1 << 5)
232 #define SITD_RESULTS_BABBLE (1 << 4)
233 #define SITD_RESULTS_XACTERR (1 << 3)
234 #define SITD_RESULTS_MISSEDUF (1 << 2)
235 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238 #define SITD_BUFPTR_MASK 0xfffff000
239 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240 #define SITD_BUFPTR_TPOS_MASK 0x00000018
241 #define SITD_BUFPTR_TPOS_SH 3
242 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245 } EHCIsitd;
246
247 /* EHCI spec version 1.0 Section 3.5
248 */
249 typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253 #define QTD_TOKEN_DTOGGLE (1 << 31)
254 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255 #define QTD_TOKEN_TBYTES_SH 16
256 #define QTD_TOKEN_IOC (1 << 15)
257 #define QTD_TOKEN_CPAGE_MASK 0x00007000
258 #define QTD_TOKEN_CPAGE_SH 12
259 #define QTD_TOKEN_CERR_MASK 0x00000c00
260 #define QTD_TOKEN_CERR_SH 10
261 #define QTD_TOKEN_PID_MASK 0x00000300
262 #define QTD_TOKEN_PID_SH 8
263 #define QTD_TOKEN_ACTIVE (1 << 7)
264 #define QTD_TOKEN_HALT (1 << 6)
265 #define QTD_TOKEN_DBERR (1 << 5)
266 #define QTD_TOKEN_BABBLE (1 << 4)
267 #define QTD_TOKEN_XACTERR (1 << 3)
268 #define QTD_TOKEN_MISSEDUF (1 << 2)
269 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
270 #define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273 #define QTD_BUFPTR_MASK 0xfffff000
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct {
338 PCIDevice dev;
339 qemu_irq irq;
340 target_phys_addr_t mem_base;
341 int mem;
342 int num_ports;
343 /*
344 * EHCI spec version 1.0 Section 2.3
345 * Host Controller Operational Registers
346 */
347 union {
348 uint8_t mmio[MMIO_SIZE];
349 struct {
350 uint8_t cap[OPREGBASE];
351 uint32_t usbcmd;
352 uint32_t usbsts;
353 uint32_t usbintr;
354 uint32_t frindex;
355 uint32_t ctrldssegment;
356 uint32_t periodiclistbase;
357 uint32_t asynclistaddr;
358 uint32_t notused[9];
359 uint32_t configflag;
360 uint32_t portsc[NB_PORTS];
361 };
362 };
363 /*
364 * Internal states, shadow registers, etc
365 */
366 uint32_t sofv;
367 QEMUTimer *frame_timer;
368 int attach_poll_counter;
369 int astate; // Current state in asynchronous schedule
370 int pstate; // Current state in periodic schedule
371 USBPort ports[NB_PORTS];
372 uint8_t buffer[BUFF_SIZE];
373 uint32_t usbsts_pending;
374
375 /* cached data from guest - needs to be flushed
376 * when guest removes an entry (doorbell, handshake sequence)
377 */
378 EHCIqh qh; // copy of current QH (being worked on)
379 uint32_t qhaddr; // address QH read from
380
381 EHCIqtd qtd; // copy of current QTD (being worked on)
382 uint32_t qtdaddr; // address QTD read from
383
384 uint32_t itdaddr; // current ITD
385
386 uint32_t fetch_addr; // which address to look at next
387
388 USBBus bus;
389 USBPacket usb_packet;
390 int async_complete;
391 uint32_t tbytes;
392 int pid;
393 int exec_status;
394 int isoch_pause;
395 uint32_t last_run_usec;
396 uint32_t frame_end_usec;
397 } EHCIState;
398
399 #define SET_LAST_RUN_CLOCK(s) \
400 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
401
402 /* nifty macros from Arnon's EHCI version */
403 #define get_field(data, field) \
404 (((data) & field##_MASK) >> field##_SH)
405
406 #define set_field(data, newval, field) do { \
407 uint32_t val = *data; \
408 val &= ~ field##_MASK; \
409 val |= ((newval) << field##_SH) & field##_MASK; \
410 *data = val; \
411 } while(0)
412
413 static const char *ehci_state_names[] = {
414 [ EST_INACTIVE ] = "INACTIVE",
415 [ EST_ACTIVE ] = "ACTIVE",
416 [ EST_EXECUTING ] = "EXECUTING",
417 [ EST_SLEEPING ] = "SLEEPING",
418 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
419 [ EST_FETCHENTRY ] = "FETCH ENTRY",
420 [ EST_FETCHQH ] = "FETCH QH",
421 [ EST_FETCHITD ] = "FETCH ITD",
422 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
423 [ EST_FETCHQTD ] = "FETCH QTD",
424 [ EST_EXECUTE ] = "EXECUTE",
425 [ EST_WRITEBACK ] = "WRITEBACK",
426 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
427 };
428
429 static const char *ehci_mmio_names[] = {
430 [ CAPLENGTH ] = "CAPLENGTH",
431 [ HCIVERSION ] = "HCIVERSION",
432 [ HCSPARAMS ] = "HCSPARAMS",
433 [ HCCPARAMS ] = "HCCPARAMS",
434 [ USBCMD ] = "USBCMD",
435 [ USBSTS ] = "USBSTS",
436 [ USBINTR ] = "USBINTR",
437 [ FRINDEX ] = "FRINDEX",
438 [ PERIODICLISTBASE ] = "P-LIST BASE",
439 [ ASYNCLISTADDR ] = "A-LIST ADDR",
440 [ PORTSC_BEGIN ] = "PORTSC #0",
441 [ PORTSC_BEGIN + 4] = "PORTSC #1",
442 [ PORTSC_BEGIN + 8] = "PORTSC #2",
443 [ PORTSC_BEGIN + 12] = "PORTSC #3",
444 [ CONFIGFLAG ] = "CONFIGFLAG",
445 };
446
447 static const char *nr2str(const char **n, size_t len, uint32_t nr)
448 {
449 if (nr < len && n[nr] != NULL) {
450 return n[nr];
451 } else {
452 return "unknown";
453 }
454 }
455
456 static const char *state2str(uint32_t state)
457 {
458 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
459 }
460
461 static const char *addr2str(target_phys_addr_t addr)
462 {
463 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
464 }
465
466 static void ehci_trace_usbsts(uint32_t mask, int state)
467 {
468 /* interrupts */
469 if (mask & USBSTS_INT) {
470 trace_usb_ehci_usbsts("INT", state);
471 }
472 if (mask & USBSTS_ERRINT) {
473 trace_usb_ehci_usbsts("ERRINT", state);
474 }
475 if (mask & USBSTS_PCD) {
476 trace_usb_ehci_usbsts("PCD", state);
477 }
478 if (mask & USBSTS_FLR) {
479 trace_usb_ehci_usbsts("FLR", state);
480 }
481 if (mask & USBSTS_HSE) {
482 trace_usb_ehci_usbsts("HSE", state);
483 }
484 if (mask & USBSTS_IAA) {
485 trace_usb_ehci_usbsts("IAA", state);
486 }
487
488 /* status */
489 if (mask & USBSTS_HALT) {
490 trace_usb_ehci_usbsts("HALT", state);
491 }
492 if (mask & USBSTS_REC) {
493 trace_usb_ehci_usbsts("REC", state);
494 }
495 if (mask & USBSTS_PSS) {
496 trace_usb_ehci_usbsts("PSS", state);
497 }
498 if (mask & USBSTS_ASS) {
499 trace_usb_ehci_usbsts("ASS", state);
500 }
501 }
502
503 static inline void ehci_set_usbsts(EHCIState *s, int mask)
504 {
505 if ((s->usbsts & mask) == mask) {
506 return;
507 }
508 ehci_trace_usbsts(mask, 1);
509 s->usbsts |= mask;
510 }
511
512 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
513 {
514 if ((s->usbsts & mask) == 0) {
515 return;
516 }
517 ehci_trace_usbsts(mask, 0);
518 s->usbsts &= ~mask;
519 }
520
521 static inline void ehci_set_interrupt(EHCIState *s, int intr)
522 {
523 int level = 0;
524
525 // TODO honour interrupt threshold requests
526
527 ehci_set_usbsts(s, intr);
528
529 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
530 level = 1;
531 }
532
533 qemu_set_irq(s->irq, level);
534 }
535
536 static inline void ehci_record_interrupt(EHCIState *s, int intr)
537 {
538 s->usbsts_pending |= intr;
539 }
540
541 static inline void ehci_commit_interrupt(EHCIState *s)
542 {
543 if (!s->usbsts_pending) {
544 return;
545 }
546 ehci_set_interrupt(s, s->usbsts_pending);
547 s->usbsts_pending = 0;
548 }
549
550 static void ehci_set_state(EHCIState *s, int async, int state)
551 {
552 if (async) {
553 trace_usb_ehci_state("async", state2str(state));
554 s->astate = state;
555 } else {
556 trace_usb_ehci_state("periodic", state2str(state));
557 s->pstate = state;
558 }
559 }
560
561 static int ehci_get_state(EHCIState *s, int async)
562 {
563 return async ? s->astate : s->pstate;
564 }
565
566 static void ehci_trace_qh(EHCIState *s, target_phys_addr_t addr, EHCIqh *qh)
567 {
568 trace_usb_ehci_qh(addr, qh->next,
569 qh->current_qtd, qh->next_qtd, qh->altnext_qtd,
570 get_field(qh->epchar, QH_EPCHAR_RL),
571 get_field(qh->epchar, QH_EPCHAR_MPLEN),
572 get_field(qh->epchar, QH_EPCHAR_EPS),
573 get_field(qh->epchar, QH_EPCHAR_EP),
574 get_field(qh->epchar, QH_EPCHAR_DEVADDR),
575 (bool)(qh->epchar & QH_EPCHAR_C),
576 (bool)(qh->epchar & QH_EPCHAR_H),
577 (bool)(qh->epchar & QH_EPCHAR_DTC),
578 (bool)(qh->epchar & QH_EPCHAR_I));
579 }
580
581 static void ehci_trace_qtd(EHCIState *s, target_phys_addr_t addr, EHCIqtd *qtd)
582 {
583 trace_usb_ehci_qtd(addr, qtd->next, qtd->altnext,
584 get_field(qtd->token, QTD_TOKEN_TBYTES),
585 get_field(qtd->token, QTD_TOKEN_CPAGE),
586 get_field(qtd->token, QTD_TOKEN_CERR),
587 get_field(qtd->token, QTD_TOKEN_PID),
588 (bool)(qtd->token & QTD_TOKEN_IOC),
589 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
590 (bool)(qtd->token & QTD_TOKEN_HALT),
591 (bool)(qtd->token & QTD_TOKEN_BABBLE),
592 (bool)(qtd->token & QTD_TOKEN_XACTERR));
593 }
594
595 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
596 {
597 trace_usb_ehci_itd(addr, itd->next);
598 }
599
600 /* Attach or detach a device on root hub */
601
602 static void ehci_attach(USBPort *port)
603 {
604 EHCIState *s = port->opaque;
605 uint32_t *portsc = &s->portsc[port->index];
606
607 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
608
609 *portsc |= PORTSC_CONNECT;
610 *portsc |= PORTSC_CSC;
611
612 /*
613 * If a high speed device is attached then we own this port(indicated
614 * by zero in the PORTSC_POWNER bit field) so set the status bit
615 * and set an interrupt if enabled.
616 */
617 if ( !(*portsc & PORTSC_POWNER)) {
618 ehci_set_interrupt(s, USBSTS_PCD);
619 }
620 }
621
622 static void ehci_detach(USBPort *port)
623 {
624 EHCIState *s = port->opaque;
625 uint32_t *portsc = &s->portsc[port->index];
626
627 trace_usb_ehci_port_detach(port->index);
628
629 *portsc &= ~PORTSC_CONNECT;
630 *portsc |= PORTSC_CSC;
631
632 /*
633 * If a high speed device is attached then we own this port(indicated
634 * by zero in the PORTSC_POWNER bit field) so set the status bit
635 * and set an interrupt if enabled.
636 */
637 if ( !(*portsc & PORTSC_POWNER)) {
638 ehci_set_interrupt(s, USBSTS_PCD);
639 }
640 }
641
642 /* 4.1 host controller initialization */
643 static void ehci_reset(void *opaque)
644 {
645 EHCIState *s = opaque;
646 uint8_t *pci_conf;
647 int i;
648
649 trace_usb_ehci_reset();
650 pci_conf = s->dev.config;
651
652 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
653
654 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
655 s->usbsts = USBSTS_HALT;
656
657 s->astate = EST_INACTIVE;
658 s->pstate = EST_INACTIVE;
659 s->async_complete = 0;
660 s->isoch_pause = -1;
661 s->attach_poll_counter = 0;
662
663 for(i = 0; i < NB_PORTS; i++) {
664 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
665
666 if (s->ports[i].dev) {
667 usb_attach(&s->ports[i], s->ports[i].dev);
668 }
669 }
670 }
671
672 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
673 {
674 EHCIState *s = ptr;
675 uint32_t val;
676
677 val = s->mmio[addr];
678
679 return val;
680 }
681
682 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
683 {
684 EHCIState *s = ptr;
685 uint32_t val;
686
687 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
688
689 return val;
690 }
691
692 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
693 {
694 EHCIState *s = ptr;
695 uint32_t val;
696
697 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
698 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
699
700 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
701 return val;
702 }
703
704 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
705 {
706 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
707 exit(1);
708 }
709
710 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
711 {
712 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
713 exit(1);
714 }
715
716 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
717 {
718 uint32_t *portsc = &s->portsc[port];
719 int rwc;
720 USBDevice *dev = s->ports[port].dev;
721
722 rwc = val & PORTSC_RWC_MASK;
723 val &= PORTSC_RO_MASK;
724
725 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
726
727 *portsc &= ~rwc;
728
729 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
730 trace_usb_ehci_port_reset(port, 1);
731 }
732
733 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
734 trace_usb_ehci_port_reset(port, 0);
735 usb_attach(&s->ports[port], dev);
736
737 // TODO how to handle reset of ports with no device
738 if (dev) {
739 usb_send_msg(dev, USB_MSG_RESET);
740 }
741
742 if (s->ports[port].dev) {
743 *portsc &= ~PORTSC_CSC;
744 }
745
746 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
747 * to SW that this port has a high speed device attached
748 *
749 * TODO - when to disable?
750 */
751 val |= PORTSC_PED;
752 val |= PORTSC_PEDC;
753 }
754
755 *portsc &= ~PORTSC_RO_MASK;
756 *portsc |= val;
757 }
758
759 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
760 {
761 EHCIState *s = ptr;
762 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
763 uint32_t old = *mmio;
764 int i;
765
766 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
767
768 /* Only aligned reads are allowed on OHCI */
769 if (addr & 3) {
770 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
771 TARGET_FMT_plx "\n", addr);
772 return;
773 }
774
775 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
776 handle_port_status_write(s, (addr-PORTSC)/4, val);
777 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
778 return;
779 }
780
781 if (addr < OPREGBASE) {
782 fprintf(stderr, "usb-ehci: write attempt to read-only register"
783 TARGET_FMT_plx "\n", addr);
784 return;
785 }
786
787
788 /* Do any register specific pre-write processing here. */
789 switch(addr) {
790 case USBCMD:
791 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
792 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
793 SET_LAST_RUN_CLOCK(s);
794 ehci_clear_usbsts(s, USBSTS_HALT);
795 }
796
797 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
798 qemu_del_timer(s->frame_timer);
799 // TODO - should finish out some stuff before setting halt
800 ehci_set_usbsts(s, USBSTS_HALT);
801 }
802
803 if (val & USBCMD_HCRESET) {
804 ehci_reset(s);
805 val &= ~USBCMD_HCRESET;
806 }
807
808 /* not supporting dynamic frame list size at the moment */
809 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
810 fprintf(stderr, "attempt to set frame list size -- value %d\n",
811 val & USBCMD_FLS);
812 val &= ~USBCMD_FLS;
813 }
814 break;
815
816 case USBSTS:
817 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
818 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
819 val = s->usbsts;
820 ehci_set_interrupt(s, 0);
821 break;
822
823 case USBINTR:
824 val &= USBINTR_MASK;
825 break;
826
827 case FRINDEX:
828 s->sofv = val >> 3;
829 break;
830
831 case CONFIGFLAG:
832 val &= 0x1;
833 if (val) {
834 for(i = 0; i < NB_PORTS; i++)
835 s->portsc[i] &= ~PORTSC_POWNER;
836 }
837 break;
838
839 case PERIODICLISTBASE:
840 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
841 fprintf(stderr,
842 "ehci: PERIODIC list base register set while periodic schedule\n"
843 " is enabled and HC is enabled\n");
844 }
845 break;
846
847 case ASYNCLISTADDR:
848 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
849 fprintf(stderr,
850 "ehci: ASYNC list address register set while async schedule\n"
851 " is enabled and HC is enabled\n");
852 }
853 break;
854 }
855
856 *mmio = val;
857 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
858 }
859
860
861 // TODO : Put in common header file, duplication from usb-ohci.c
862
863 /* Get an array of dwords from main memory */
864 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
865 {
866 int i;
867
868 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
869 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
870 *buf = le32_to_cpu(*buf);
871 }
872
873 return 1;
874 }
875
876 /* Put an array of dwords in to main memory */
877 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
878 {
879 int i;
880
881 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
882 uint32_t tmp = cpu_to_le32(*buf);
883 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
884 }
885
886 return 1;
887 }
888
889 // 4.10.2
890
891 static int ehci_qh_do_overlay(EHCIState *ehci, EHCIqh *qh, EHCIqtd *qtd)
892 {
893 int i;
894 int dtoggle;
895 int ping;
896 int eps;
897 int reload;
898
899 // remember values in fields to preserve in qh after overlay
900
901 dtoggle = qh->token & QTD_TOKEN_DTOGGLE;
902 ping = qh->token & QTD_TOKEN_PING;
903
904 DPRINTF("setting qh.current from %08X to 0x%08X\n", qh->current_qtd,
905 ehci->qtdaddr);
906 qh->current_qtd = ehci->qtdaddr;
907 qh->next_qtd = qtd->next;
908 qh->altnext_qtd = qtd->altnext;
909 qh->token = qtd->token;
910
911
912 eps = get_field(qh->epchar, QH_EPCHAR_EPS);
913 if (eps == EHCI_QH_EPS_HIGH) {
914 qh->token &= ~QTD_TOKEN_PING;
915 qh->token |= ping;
916 }
917
918 reload = get_field(qh->epchar, QH_EPCHAR_RL);
919 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
920
921 for (i = 0; i < 5; i++) {
922 qh->bufptr[i] = qtd->bufptr[i];
923 }
924
925 if (!(qh->epchar & QH_EPCHAR_DTC)) {
926 // preserve QH DT bit
927 qh->token &= ~QTD_TOKEN_DTOGGLE;
928 qh->token |= dtoggle;
929 }
930
931 qh->bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
932 qh->bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
933
934 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
935
936 return 0;
937 }
938
939 static int ehci_buffer_rw(uint8_t *buffer, EHCIqh *qh, int bytes, int rw)
940 {
941 int bufpos = 0;
942 int cpage, offset;
943 uint32_t head;
944 uint32_t tail;
945
946
947 if (!bytes) {
948 return 0;
949 }
950
951 cpage = get_field(qh->token, QTD_TOKEN_CPAGE);
952 if (cpage > 4) {
953 fprintf(stderr, "cpage out of range (%d)\n", cpage);
954 return USB_RET_PROCERR;
955 }
956
957 offset = qh->bufptr[0] & ~QTD_BUFPTR_MASK;
958 DPRINTF("ehci_buffer_rw: %sing %d bytes %08x cpage %d offset %d\n",
959 rw ? "writ" : "read", bytes, qh->bufptr[0], cpage, offset);
960
961 do {
962 /* start and end of this page */
963 head = qh->bufptr[cpage] & QTD_BUFPTR_MASK;
964 tail = head + ~QTD_BUFPTR_MASK + 1;
965 /* add offset into page */
966 head |= offset;
967
968 if (bytes <= (tail - head)) {
969 tail = head + bytes;
970 }
971
972 DPRINTF("DATA %s cpage:%d head:%08X tail:%08X target:%08X\n",
973 rw ? "WRITE" : "READ ", cpage, head, tail, bufpos);
974
975 cpu_physical_memory_rw(head, &buffer[bufpos], tail - head, rw);
976
977 bufpos += (tail - head);
978 bytes -= (tail - head);
979
980 if (bytes > 0) {
981 cpage++;
982 offset = 0;
983 }
984 } while (bytes > 0);
985
986 /* save cpage */
987 set_field(&qh->token, cpage, QTD_TOKEN_CPAGE);
988
989 /* save offset into cpage */
990 offset = tail - head;
991 qh->bufptr[0] &= ~QTD_BUFPTR_MASK;
992 qh->bufptr[0] |= offset;
993
994 return 0;
995 }
996
997 static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
998 {
999 EHCIState *ehci = container_of(packet, EHCIState, usb_packet);
1000
1001 DPRINTF("Async packet complete\n");
1002 ehci->async_complete = 1;
1003 ehci->exec_status = packet->len;
1004 }
1005
1006 static int ehci_execute_complete(EHCIState *ehci, EHCIqh *qh, int ret)
1007 {
1008 int c_err, reload;
1009
1010 if (ret == USB_RET_ASYNC && !ehci->async_complete) {
1011 DPRINTF("not done yet\n");
1012 return ret;
1013 }
1014
1015 ehci->async_complete = 0;
1016
1017 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1018 ehci->qhaddr, qh->next, ehci->qtdaddr, ret);
1019
1020 if (ret < 0) {
1021 err:
1022 /* TO-DO: put this is in a function that can be invoked below as well */
1023 c_err = get_field(qh->token, QTD_TOKEN_CERR);
1024 c_err--;
1025 set_field(&qh->token, c_err, QTD_TOKEN_CERR);
1026
1027 switch(ret) {
1028 case USB_RET_NODEV:
1029 fprintf(stderr, "USB no device\n");
1030 break;
1031 case USB_RET_STALL:
1032 fprintf(stderr, "USB stall\n");
1033 qh->token |= QTD_TOKEN_HALT;
1034 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1035 break;
1036 case USB_RET_NAK:
1037 /* 4.10.3 */
1038 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1039 if ((ehci->pid == USB_TOKEN_IN) && reload) {
1040 int nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1041 nakcnt--;
1042 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1043 } else if (!reload) {
1044 return USB_RET_NAK;
1045 }
1046 break;
1047 case USB_RET_BABBLE:
1048 fprintf(stderr, "USB babble TODO\n");
1049 qh->token |= QTD_TOKEN_BABBLE;
1050 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1051 break;
1052 default:
1053 fprintf(stderr, "USB invalid response %d to handle\n", ret);
1054 /* TO-DO: transaction error */
1055 ret = USB_RET_PROCERR;
1056 break;
1057 }
1058 } else {
1059 // DPRINTF("Short packet condition\n");
1060 // TODO check 4.12 for splits
1061
1062 if ((ret > ehci->tbytes) && (ehci->pid == USB_TOKEN_IN)) {
1063 ret = USB_RET_BABBLE;
1064 goto err;
1065 }
1066
1067 if (ehci->tbytes && ehci->pid == USB_TOKEN_IN) {
1068 if (ehci_buffer_rw(ehci->buffer, qh, ret, 1) != 0) {
1069 return USB_RET_PROCERR;
1070 }
1071 ehci->tbytes -= ret;
1072 } else {
1073 ehci->tbytes = 0;
1074 }
1075
1076 DPRINTF("updating tbytes to %d\n", ehci->tbytes);
1077 set_field(&qh->token, ehci->tbytes, QTD_TOKEN_TBYTES);
1078 }
1079
1080 qh->token ^= QTD_TOKEN_DTOGGLE;
1081 qh->token &= ~QTD_TOKEN_ACTIVE;
1082
1083 if ((ret >= 0) && (qh->token & QTD_TOKEN_IOC)) {
1084 ehci_record_interrupt(ehci, USBSTS_INT);
1085 }
1086
1087 return ret;
1088 }
1089
1090 // 4.10.3
1091
1092 static int ehci_execute(EHCIState *ehci, EHCIqh *qh)
1093 {
1094 USBPort *port;
1095 USBDevice *dev;
1096 int ret;
1097 int i;
1098 int endp;
1099 int devadr;
1100
1101 if ( !(qh->token & QTD_TOKEN_ACTIVE)) {
1102 fprintf(stderr, "Attempting to execute inactive QH\n");
1103 return USB_RET_PROCERR;
1104 }
1105
1106 ehci->tbytes = (qh->token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1107 if (ehci->tbytes > BUFF_SIZE) {
1108 fprintf(stderr, "Request for more bytes than allowed\n");
1109 return USB_RET_PROCERR;
1110 }
1111
1112 ehci->pid = (qh->token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1113 switch(ehci->pid) {
1114 case 0: ehci->pid = USB_TOKEN_OUT; break;
1115 case 1: ehci->pid = USB_TOKEN_IN; break;
1116 case 2: ehci->pid = USB_TOKEN_SETUP; break;
1117 default: fprintf(stderr, "bad token\n"); break;
1118 }
1119
1120 if ((ehci->tbytes && ehci->pid != USB_TOKEN_IN) &&
1121 (ehci_buffer_rw(ehci->buffer, qh, ehci->tbytes, 0) != 0)) {
1122 return USB_RET_PROCERR;
1123 }
1124
1125 endp = get_field(qh->epchar, QH_EPCHAR_EP);
1126 devadr = get_field(qh->epchar, QH_EPCHAR_DEVADDR);
1127
1128 ret = USB_RET_NODEV;
1129
1130 // TO-DO: associating device with ehci port
1131 for(i = 0; i < NB_PORTS; i++) {
1132 port = &ehci->ports[i];
1133 dev = port->dev;
1134
1135 // TODO sometime we will also need to check if we are the port owner
1136
1137 if (!(ehci->portsc[i] &(PORTSC_CONNECT))) {
1138 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1139 i, ehci->portsc[i]);
1140 continue;
1141 }
1142
1143 ehci->usb_packet.pid = ehci->pid;
1144 ehci->usb_packet.devaddr = devadr;
1145 ehci->usb_packet.devep = endp;
1146 ehci->usb_packet.data = ehci->buffer;
1147 ehci->usb_packet.len = ehci->tbytes;
1148
1149 ret = usb_handle_packet(dev, &ehci->usb_packet);
1150
1151 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1152 ehci->qhaddr, qh->next, ehci->qtdaddr, ehci->pid,
1153 ehci->usb_packet.len, ehci->tbytes, endp, ret);
1154
1155 if (ret != USB_RET_NODEV) {
1156 break;
1157 }
1158 }
1159
1160 if (ret > BUFF_SIZE) {
1161 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1162 return USB_RET_PROCERR;
1163 }
1164
1165 if (ret == USB_RET_ASYNC) {
1166 ehci->async_complete = 0;
1167 }
1168
1169 return ret;
1170 }
1171
1172 /* 4.7.2
1173 */
1174
1175 static int ehci_process_itd(EHCIState *ehci,
1176 EHCIitd *itd)
1177 {
1178 USBPort *port;
1179 USBDevice *dev;
1180 int ret;
1181 int i, j;
1182 int ptr;
1183 int pid;
1184 int pg;
1185 int len;
1186 int dir;
1187 int devadr;
1188 int endp;
1189 int maxpkt;
1190
1191 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1192 devadr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1193 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1194 maxpkt = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1195
1196 for(i = 0; i < 8; i++) {
1197 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1198 DPRINTF("ISOCHRONOUS active for frame %d, interval %d\n",
1199 ehci->frindex >> 3, i);
1200
1201 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1202 ptr = (itd->bufptr[pg] & ITD_BUFPTR_MASK) |
1203 (itd->transact[i] & ITD_XACT_OFFSET_MASK);
1204 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1205
1206 if (len > BUFF_SIZE) {
1207 return USB_RET_PROCERR;
1208 }
1209
1210 DPRINTF("ISOCH: buffer %08X len %d\n", ptr, len);
1211
1212 if (!dir) {
1213 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 0);
1214 pid = USB_TOKEN_OUT;
1215 } else
1216 pid = USB_TOKEN_IN;
1217
1218 ret = USB_RET_NODEV;
1219
1220 for (j = 0; j < NB_PORTS; j++) {
1221 port = &ehci->ports[j];
1222 dev = port->dev;
1223
1224 // TODO sometime we will also need to check if we are the port owner
1225
1226 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1227 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1228 j, ehci->portsc[j]);
1229 continue;
1230 }
1231
1232 ehci->usb_packet.pid = ehci->pid;
1233 ehci->usb_packet.devaddr = devadr;
1234 ehci->usb_packet.devep = endp;
1235 ehci->usb_packet.data = ehci->buffer;
1236 ehci->usb_packet.len = len;
1237
1238 DPRINTF("calling usb_handle_packet\n");
1239 ret = usb_handle_packet(dev, &ehci->usb_packet);
1240
1241 if (ret != USB_RET_NODEV) {
1242 break;
1243 }
1244 }
1245
1246 /* In isoch, there is no facility to indicate a NAK so let's
1247 * instead just complete a zero-byte transaction. Setting
1248 * DBERR seems too draconian.
1249 */
1250
1251 if (ret == USB_RET_NAK) {
1252 if (ehci->isoch_pause > 0) {
1253 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1254 ehci->isoch_pause--;
1255 return 0;
1256 } else if (ehci->isoch_pause == -1) {
1257 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1258 // Pause frindex for up to 50 msec waiting for data from
1259 // remote
1260 ehci->isoch_pause = 50;
1261 return 0;
1262 } else {
1263 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1264 ret = 0;
1265 }
1266 } else {
1267 DPRINTF("ISOCH: received ACK, clearing pause\n");
1268 ehci->isoch_pause = -1;
1269 }
1270
1271 if (ret >= 0) {
1272 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1273
1274 if (itd->transact[i] & ITD_XACT_IOC) {
1275 ehci_record_interrupt(ehci, USBSTS_INT);
1276 }
1277 }
1278
1279 if (ret >= 0 && dir) {
1280 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 1);
1281
1282 if (ret != len) {
1283 DPRINTF("ISOCH IN expected %d, got %d\n",
1284 len, ret);
1285 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1286 }
1287 }
1288 }
1289 }
1290 return 0;
1291 }
1292
1293 /* This state is the entry point for asynchronous schedule
1294 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1295 */
1296 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1297 {
1298 EHCIqh *qh = &ehci->qh;
1299 int i = 0;
1300 int again = 0;
1301 uint32_t entry = ehci->asynclistaddr;
1302
1303 /* set reclamation flag at start event (4.8.6) */
1304 if (async) {
1305 ehci_set_usbsts(ehci, USBSTS_REC);
1306 }
1307
1308 /* Find the head of the list (4.9.1.1) */
1309 for(i = 0; i < MAX_QH; i++) {
1310 get_dwords(NLPTR_GET(entry), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1311 ehci_trace_qh(ehci, NLPTR_GET(entry), qh);
1312
1313 if (qh->epchar & QH_EPCHAR_H) {
1314 if (async) {
1315 entry |= (NLPTR_TYPE_QH << 1);
1316 }
1317
1318 ehci->fetch_addr = entry;
1319 ehci_set_state(ehci, async, EST_FETCHENTRY);
1320 again = 1;
1321 goto out;
1322 }
1323
1324 entry = qh->next;
1325 if (entry == ehci->asynclistaddr) {
1326 break;
1327 }
1328 }
1329
1330 /* no head found for list. */
1331
1332 ehci_set_state(ehci, async, EST_ACTIVE);
1333
1334 out:
1335 return again;
1336 }
1337
1338
1339 /* This state is the entry point for periodic schedule processing as
1340 * well as being a continuation state for async processing.
1341 */
1342 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1343 {
1344 int again = 0;
1345 uint32_t entry = ehci->fetch_addr;
1346
1347 #if EHCI_DEBUG == 0
1348 if (qemu_get_clock_ns(vm_clock) / 1000 >= ehci->frame_end_usec) {
1349 if (async) {
1350 DPRINTF("FETCHENTRY: FRAME timer elapsed, exit state machine\n");
1351 goto out;
1352 } else {
1353 DPRINTF("FETCHENTRY: WARNING "
1354 "- frame timer elapsed during periodic\n");
1355 }
1356 }
1357 #endif
1358 if (entry < 0x1000) {
1359 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1360 ehci_set_state(ehci, async, EST_ACTIVE);
1361 goto out;
1362 }
1363
1364 /* section 4.8, only QH in async schedule */
1365 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1366 fprintf(stderr, "non queue head request in async schedule\n");
1367 return -1;
1368 }
1369
1370 switch (NLPTR_TYPE_GET(entry)) {
1371 case NLPTR_TYPE_QH:
1372 ehci_set_state(ehci, async, EST_FETCHQH);
1373 ehci->qhaddr = entry;
1374 again = 1;
1375 break;
1376
1377 case NLPTR_TYPE_ITD:
1378 ehci_set_state(ehci, async, EST_FETCHITD);
1379 ehci->itdaddr = entry;
1380 again = 1;
1381 break;
1382
1383 default:
1384 // TODO: handle siTD and FSTN types
1385 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1386 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1387 return -1;
1388 }
1389
1390 out:
1391 return again;
1392 }
1393
1394 static int ehci_state_fetchqh(EHCIState *ehci, int async)
1395 {
1396 EHCIqh *qh = &ehci->qh;
1397 int reload;
1398 int again = 0;
1399
1400 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1401 ehci_trace_qh(ehci, NLPTR_GET(ehci->qhaddr), qh);
1402
1403 if (async && (qh->epchar & QH_EPCHAR_H)) {
1404
1405 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1406 if (ehci->usbsts & USBSTS_REC) {
1407 ehci_clear_usbsts(ehci, USBSTS_REC);
1408 } else {
1409 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1410 " - done processing\n", ehci->qhaddr);
1411 ehci_set_state(ehci, async, EST_ACTIVE);
1412 goto out;
1413 }
1414 }
1415
1416 #if EHCI_DEBUG
1417 if (ehci->qhaddr != qh->next) {
1418 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1419 ehci->qhaddr,
1420 qh->epchar & QH_EPCHAR_H,
1421 qh->token & QTD_TOKEN_HALT,
1422 qh->token & QTD_TOKEN_ACTIVE,
1423 qh->next);
1424 }
1425 #endif
1426
1427 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1428 if (reload) {
1429 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1430 }
1431
1432 if (qh->token & QTD_TOKEN_HALT) {
1433 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1434 again = 1;
1435
1436 } else if ((qh->token & QTD_TOKEN_ACTIVE) && (qh->current_qtd > 0x1000)) {
1437 ehci->qtdaddr = qh->current_qtd;
1438 ehci_set_state(ehci, async, EST_FETCHQTD);
1439 again = 1;
1440
1441 } else {
1442 /* EHCI spec version 1.0 Section 4.10.2 */
1443 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1444 again = 1;
1445 }
1446
1447 out:
1448 return again;
1449 }
1450
1451 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1452 {
1453 EHCIitd itd;
1454
1455 get_dwords(NLPTR_GET(ehci->itdaddr),(uint32_t *) &itd,
1456 sizeof(EHCIitd) >> 2);
1457 ehci_trace_itd(ehci, ehci->itdaddr, &itd);
1458
1459 if (ehci_process_itd(ehci, &itd) != 0) {
1460 return -1;
1461 }
1462
1463 put_dwords(NLPTR_GET(ehci->itdaddr), (uint32_t *) &itd,
1464 sizeof(EHCIitd) >> 2);
1465 ehci->fetch_addr = itd.next;
1466 ehci_set_state(ehci, async, EST_FETCHENTRY);
1467
1468 return 1;
1469 }
1470
1471 /* Section 4.10.2 - paragraph 3 */
1472 static int ehci_state_advqueue(EHCIState *ehci, int async)
1473 {
1474 #if 0
1475 /* TO-DO: 4.10.2 - paragraph 2
1476 * if I-bit is set to 1 and QH is not active
1477 * go to horizontal QH
1478 */
1479 if (I-bit set) {
1480 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1481 goto out;
1482 }
1483 #endif
1484
1485 /*
1486 * want data and alt-next qTD is valid
1487 */
1488 if (((ehci->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1489 (ehci->qh.altnext_qtd > 0x1000) &&
1490 (NLPTR_TBIT(ehci->qh.altnext_qtd) == 0)) {
1491 ehci->qtdaddr = ehci->qh.altnext_qtd;
1492 ehci_set_state(ehci, async, EST_FETCHQTD);
1493
1494 /*
1495 * next qTD is valid
1496 */
1497 } else if ((ehci->qh.next_qtd > 0x1000) &&
1498 (NLPTR_TBIT(ehci->qh.next_qtd) == 0)) {
1499 ehci->qtdaddr = ehci->qh.next_qtd;
1500 ehci_set_state(ehci, async, EST_FETCHQTD);
1501
1502 /*
1503 * no valid qTD, try next QH
1504 */
1505 } else {
1506 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1507 }
1508
1509 return 1;
1510 }
1511
1512 /* Section 4.10.2 - paragraph 4 */
1513 static int ehci_state_fetchqtd(EHCIState *ehci, int async)
1514 {
1515 EHCIqtd *qtd = &ehci->qtd;
1516 int again = 0;
1517
1518 get_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) qtd, sizeof(EHCIqtd) >> 2);
1519 ehci_trace_qtd(ehci, NLPTR_GET(ehci->qtdaddr), qtd);
1520
1521 if (qtd->token & QTD_TOKEN_ACTIVE) {
1522 ehci_set_state(ehci, async, EST_EXECUTE);
1523 again = 1;
1524 } else {
1525 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1526 again = 1;
1527 }
1528
1529 return again;
1530 }
1531
1532 static int ehci_state_horizqh(EHCIState *ehci, int async)
1533 {
1534 int again = 0;
1535
1536 if (ehci->fetch_addr != ehci->qh.next) {
1537 ehci->fetch_addr = ehci->qh.next;
1538 ehci_set_state(ehci, async, EST_FETCHENTRY);
1539 again = 1;
1540 } else {
1541 ehci_set_state(ehci, async, EST_ACTIVE);
1542 }
1543
1544 return again;
1545 }
1546
1547 static int ehci_state_execute(EHCIState *ehci, int async)
1548 {
1549 EHCIqh *qh = &ehci->qh;
1550 EHCIqtd *qtd = &ehci->qtd;
1551 int again = 0;
1552 int reload, nakcnt;
1553 int smask;
1554
1555 if (ehci_qh_do_overlay(ehci, qh, qtd) != 0) {
1556 return -1;
1557 }
1558
1559 smask = get_field(qh->epcap, QH_EPCAP_SMASK);
1560
1561 if (!smask) {
1562 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1563 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1564 if (reload && !nakcnt) {
1565 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1566 again = 1;
1567 goto out;
1568 }
1569 }
1570
1571 // TODO verify enough time remains in the uframe as in 4.4.1.1
1572 // TODO write back ptr to async list when done or out of time
1573 // TODO Windows does not seem to ever set the MULT field
1574
1575 if (!async) {
1576 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1577 if (!transactCtr) {
1578 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1579 again = 1;
1580 goto out;
1581 }
1582 }
1583
1584 if (async) {
1585 ehci_set_usbsts(ehci, USBSTS_REC);
1586 }
1587
1588 ehci->exec_status = ehci_execute(ehci, qh);
1589 if (ehci->exec_status == USB_RET_PROCERR) {
1590 again = -1;
1591 goto out;
1592 }
1593 ehci_set_state(ehci, async, EST_EXECUTING);
1594
1595 if (ehci->exec_status != USB_RET_ASYNC) {
1596 again = 1;
1597 }
1598
1599 out:
1600 return again;
1601 }
1602
1603 static int ehci_state_executing(EHCIState *ehci, int async)
1604 {
1605 EHCIqh *qh = &ehci->qh;
1606 int again = 0;
1607 int reload, nakcnt;
1608
1609 ehci->exec_status = ehci_execute_complete(ehci, qh, ehci->exec_status);
1610 if (ehci->exec_status == USB_RET_ASYNC) {
1611 goto out;
1612 }
1613 if (ehci->exec_status == USB_RET_PROCERR) {
1614 again = -1;
1615 goto out;
1616 }
1617
1618 // 4.10.3
1619 if (!async) {
1620 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1621 transactCtr--;
1622 set_field(&qh->epcap, transactCtr, QH_EPCAP_MULT);
1623 // 4.10.3, bottom of page 82, should exit this state when transaction
1624 // counter decrements to 0
1625 }
1626
1627
1628 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1629 if (reload) {
1630 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1631 if (ehci->exec_status == USB_RET_NAK) {
1632 if (nakcnt) {
1633 nakcnt--;
1634 }
1635 } else {
1636 nakcnt = reload;
1637 }
1638 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1639 }
1640
1641 /*
1642 * Write the qh back to guest physical memory. This step isn't
1643 * in the EHCI spec but we need to do it since we don't share
1644 * physical memory with our guest VM.
1645 */
1646 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1647
1648 /* 4.10.5 */
1649 if ((ehci->exec_status == USB_RET_NAK) || (qh->token & QTD_TOKEN_ACTIVE)) {
1650 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1651 } else {
1652 ehci_set_state(ehci, async, EST_WRITEBACK);
1653 }
1654
1655 again = 1;
1656
1657 out:
1658 return again;
1659 }
1660
1661
1662 static int ehci_state_writeback(EHCIState *ehci, int async)
1663 {
1664 EHCIqh *qh = &ehci->qh;
1665 int again = 0;
1666
1667 /* Write back the QTD from the QH area */
1668 ehci_trace_qtd(ehci, NLPTR_GET(ehci->qtdaddr), (EHCIqtd*) &qh->next_qtd);
1669 put_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) &qh->next_qtd,
1670 sizeof(EHCIqtd) >> 2);
1671
1672 /* TODO confirm next state. For now, keep going if async
1673 * but stop after one qtd if periodic
1674 */
1675 //if (async) {
1676 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1677 again = 1;
1678 //} else {
1679 // ehci_set_state(ehci, async, EST_ACTIVE);
1680 //}
1681 return again;
1682 }
1683
1684 /*
1685 * This is the state machine that is common to both async and periodic
1686 */
1687
1688 static void ehci_advance_state(EHCIState *ehci,
1689 int async)
1690 {
1691 int again;
1692 int iter = 0;
1693
1694 do {
1695 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1696 iter++;
1697 /* if we are roaming a lot of QH without executing a qTD
1698 * something is wrong with the linked list. TO-DO: why is
1699 * this hack needed?
1700 */
1701 if (iter > MAX_ITERATIONS) {
1702 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1703 ehci_set_state(ehci, async, EST_ACTIVE);
1704 break;
1705 }
1706 }
1707 switch(ehci_get_state(ehci, async)) {
1708 case EST_WAITLISTHEAD:
1709 again = ehci_state_waitlisthead(ehci, async);
1710 break;
1711
1712 case EST_FETCHENTRY:
1713 again = ehci_state_fetchentry(ehci, async);
1714 break;
1715
1716 case EST_FETCHQH:
1717 again = ehci_state_fetchqh(ehci, async);
1718 break;
1719
1720 case EST_FETCHITD:
1721 again = ehci_state_fetchitd(ehci, async);
1722 break;
1723
1724 case EST_ADVANCEQUEUE:
1725 again = ehci_state_advqueue(ehci, async);
1726 break;
1727
1728 case EST_FETCHQTD:
1729 again = ehci_state_fetchqtd(ehci, async);
1730 break;
1731
1732 case EST_HORIZONTALQH:
1733 again = ehci_state_horizqh(ehci, async);
1734 break;
1735
1736 case EST_EXECUTE:
1737 iter = 0;
1738 again = ehci_state_execute(ehci, async);
1739 break;
1740
1741 case EST_EXECUTING:
1742 again = ehci_state_executing(ehci, async);
1743 break;
1744
1745 case EST_WRITEBACK:
1746 again = ehci_state_writeback(ehci, async);
1747 break;
1748
1749 default:
1750 fprintf(stderr, "Bad state!\n");
1751 again = -1;
1752 break;
1753 }
1754
1755 if (again < 0) {
1756 fprintf(stderr, "processing error - resetting ehci HC\n");
1757 ehci_reset(ehci);
1758 again = 0;
1759 }
1760 }
1761 while (again);
1762
1763 ehci_commit_interrupt(ehci);
1764 }
1765
1766 static void ehci_advance_async_state(EHCIState *ehci)
1767 {
1768 EHCIqh qh;
1769 int async = 1;
1770
1771 switch(ehci_get_state(ehci, async)) {
1772 case EST_INACTIVE:
1773 if (!(ehci->usbcmd & USBCMD_ASE)) {
1774 break;
1775 }
1776 ehci_set_usbsts(ehci, USBSTS_ASS);
1777 ehci_set_state(ehci, async, EST_ACTIVE);
1778 // No break, fall through to ACTIVE
1779
1780 case EST_ACTIVE:
1781 if ( !(ehci->usbcmd & USBCMD_ASE)) {
1782 ehci_clear_usbsts(ehci, USBSTS_ASS);
1783 ehci_set_state(ehci, async, EST_INACTIVE);
1784 break;
1785 }
1786
1787 /* If the doorbell is set, the guest wants to make a change to the
1788 * schedule. The host controller needs to release cached data.
1789 * (section 4.8.2)
1790 */
1791 if (ehci->usbcmd & USBCMD_IAAD) {
1792 DPRINTF("ASYNC: doorbell request acknowledged\n");
1793 ehci->usbcmd &= ~USBCMD_IAAD;
1794 ehci_set_interrupt(ehci, USBSTS_IAA);
1795 break;
1796 }
1797
1798 /* make sure guest has acknowledged */
1799 /* TO-DO: is this really needed? */
1800 if (ehci->usbsts & USBSTS_IAA) {
1801 DPRINTF("IAA status bit still set.\n");
1802 break;
1803 }
1804
1805 /* check that address register has been set */
1806 if (ehci->asynclistaddr == 0) {
1807 break;
1808 }
1809
1810 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
1811 /* fall through */
1812
1813 case EST_FETCHENTRY:
1814 /* fall through */
1815
1816 case EST_EXECUTING:
1817 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) &qh,
1818 sizeof(EHCIqh) >> 2);
1819 ehci_advance_state(ehci, async);
1820 break;
1821
1822 default:
1823 /* this should only be due to a developer mistake */
1824 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1825 "Resetting to active\n", ehci->astate);
1826 ehci_set_state(ehci, async, EST_ACTIVE);
1827 }
1828 }
1829
1830 static void ehci_advance_periodic_state(EHCIState *ehci)
1831 {
1832 uint32_t entry;
1833 uint32_t list;
1834 int async = 0;
1835
1836 // 4.6
1837
1838 switch(ehci_get_state(ehci, async)) {
1839 case EST_INACTIVE:
1840 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
1841 ehci_set_usbsts(ehci, USBSTS_PSS);
1842 ehci_set_state(ehci, async, EST_ACTIVE);
1843 // No break, fall through to ACTIVE
1844 } else
1845 break;
1846
1847 case EST_ACTIVE:
1848 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
1849 ehci_clear_usbsts(ehci, USBSTS_PSS);
1850 ehci_set_state(ehci, async, EST_INACTIVE);
1851 break;
1852 }
1853
1854 list = ehci->periodiclistbase & 0xfffff000;
1855 /* check that register has been set */
1856 if (list == 0) {
1857 break;
1858 }
1859 list |= ((ehci->frindex & 0x1ff8) >> 1);
1860
1861 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
1862 entry = le32_to_cpu(entry);
1863
1864 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
1865 ehci->frindex / 8, list, entry);
1866 ehci->fetch_addr = entry;
1867 ehci_set_state(ehci, async, EST_FETCHENTRY);
1868 ehci_advance_state(ehci, async);
1869 break;
1870
1871 case EST_EXECUTING:
1872 DPRINTF("PERIODIC state adv for executing\n");
1873 ehci_advance_state(ehci, async);
1874 break;
1875
1876 default:
1877 /* this should only be due to a developer mistake */
1878 fprintf(stderr, "ehci: Bad periodic state %d. "
1879 "Resetting to active\n", ehci->pstate);
1880 ehci_set_state(ehci, async, EST_ACTIVE);
1881 }
1882 }
1883
1884 static void ehci_frame_timer(void *opaque)
1885 {
1886 EHCIState *ehci = opaque;
1887 int64_t expire_time, t_now;
1888 int usec_elapsed;
1889 int frames;
1890 int usec_now;
1891 int i;
1892 int skipped_frames = 0;
1893
1894
1895 t_now = qemu_get_clock_ns(vm_clock);
1896 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1897 if (expire_time == t_now) {
1898 expire_time++;
1899 }
1900
1901 usec_now = t_now / 1000;
1902 usec_elapsed = usec_now - ehci->last_run_usec;
1903 frames = usec_elapsed / FRAME_TIMER_USEC;
1904 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
1905
1906 for (i = 0; i < frames; i++) {
1907 if ( !(ehci->usbsts & USBSTS_HALT)) {
1908 if (ehci->isoch_pause <= 0) {
1909 ehci->frindex += 8;
1910 }
1911
1912 if (ehci->frindex > 0x00001fff) {
1913 ehci->frindex = 0;
1914 ehci_set_interrupt(ehci, USBSTS_FLR);
1915 }
1916
1917 ehci->sofv = (ehci->frindex - 1) >> 3;
1918 ehci->sofv &= 0x000003ff;
1919 }
1920
1921 if (frames - i > 10) {
1922 skipped_frames++;
1923 } else {
1924 // TODO could this cause periodic frames to get skipped if async
1925 // active?
1926 if (ehci_get_state(ehci, 1) != EST_EXECUTING) {
1927 ehci_advance_periodic_state(ehci);
1928 }
1929 }
1930
1931 ehci->last_run_usec += FRAME_TIMER_USEC;
1932 }
1933
1934 #if 0
1935 if (skipped_frames) {
1936 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
1937 }
1938 #endif
1939
1940 /* Async is not inside loop since it executes everything it can once
1941 * called
1942 */
1943 if (ehci_get_state(ehci, 0) != EST_EXECUTING) {
1944 ehci_advance_async_state(ehci);
1945 }
1946
1947 qemu_mod_timer(ehci->frame_timer, expire_time);
1948 }
1949
1950 static CPUReadMemoryFunc *ehci_readfn[3]={
1951 ehci_mem_readb,
1952 ehci_mem_readw,
1953 ehci_mem_readl
1954 };
1955
1956 static CPUWriteMemoryFunc *ehci_writefn[3]={
1957 ehci_mem_writeb,
1958 ehci_mem_writew,
1959 ehci_mem_writel
1960 };
1961
1962 static void ehci_map(PCIDevice *pci_dev, int region_num,
1963 pcibus_t addr, pcibus_t size, int type)
1964 {
1965 EHCIState *s =(EHCIState *)pci_dev;
1966
1967 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
1968 region_num, addr, size, s->mem);
1969 s->mem_base = addr;
1970 cpu_register_physical_memory(addr, size, s->mem);
1971 }
1972
1973 static int usb_ehci_initfn(PCIDevice *dev);
1974
1975 static USBPortOps ehci_port_ops = {
1976 .attach = ehci_attach,
1977 .detach = ehci_detach,
1978 .complete = ehci_async_complete_packet,
1979 };
1980
1981 static PCIDeviceInfo ehci_info = {
1982 .qdev.name = "usb-ehci",
1983 .qdev.size = sizeof(EHCIState),
1984 .init = usb_ehci_initfn,
1985 };
1986
1987 static int usb_ehci_initfn(PCIDevice *dev)
1988 {
1989 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
1990 uint8_t *pci_conf = s->dev.config;
1991 int i;
1992
1993 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1994 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82801D);
1995 pci_set_byte(&pci_conf[PCI_REVISION_ID], 0x10);
1996 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
1997 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
1998 pci_set_byte(&pci_conf[PCI_HEADER_TYPE], PCI_HEADER_TYPE_NORMAL);
1999
2000 /* capabilities pointer */
2001 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2002 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2003
2004 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2005 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2006 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2007
2008 // pci_conf[0x50] = 0x01; // power management caps
2009
2010 pci_set_byte(&pci_conf[0x60], 0x20); // spec release number (2.1.4)
2011 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2012 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2013
2014 pci_conf[0x64] = 0x00;
2015 pci_conf[0x65] = 0x00;
2016 pci_conf[0x66] = 0x00;
2017 pci_conf[0x67] = 0x00;
2018 pci_conf[0x68] = 0x01;
2019 pci_conf[0x69] = 0x00;
2020 pci_conf[0x6a] = 0x00;
2021 pci_conf[0x6b] = 0x00; // USBLEGSUP
2022 pci_conf[0x6c] = 0x00;
2023 pci_conf[0x6d] = 0x00;
2024 pci_conf[0x6e] = 0x00;
2025 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2026
2027 // 2.2 host controller interface version
2028 s->mmio[0x00] = (uint8_t) OPREGBASE;
2029 s->mmio[0x01] = 0x00;
2030 s->mmio[0x02] = 0x00;
2031 s->mmio[0x03] = 0x01; // HC version
2032 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2033 s->mmio[0x05] = 0x00; // No companion ports at present
2034 s->mmio[0x06] = 0x00;
2035 s->mmio[0x07] = 0x00;
2036 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2037 s->mmio[0x09] = 0x68; // EECP
2038 s->mmio[0x0a] = 0x00;
2039 s->mmio[0x0b] = 0x00;
2040
2041 s->irq = s->dev.irq[3];
2042
2043 usb_bus_new(&s->bus, &s->dev.qdev);
2044 for(i = 0; i < NB_PORTS; i++) {
2045 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2046 USB_SPEED_MASK_HIGH);
2047 usb_port_location(&s->ports[i], NULL, i+1);
2048 s->ports[i].dev = 0;
2049 }
2050
2051 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2052
2053 qemu_register_reset(ehci_reset, s);
2054
2055 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2056 DEVICE_LITTLE_ENDIAN);
2057
2058 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2059 ehci_map);
2060
2061 fprintf(stderr, "*** EHCI support is under development ***\n");
2062
2063 return 0;
2064 }
2065
2066 static void ehci_register(void)
2067 {
2068 pci_qdev_register(&ehci_info);
2069 }
2070 device_init(ehci_register);
2071
2072 /*
2073 * vim: expandtab ts=4
2074 */
QEmu