Fixing tap adapter for win32
[qemu.git] / hw / pci_host.c
blob7c40155b95c2d155ad529bd62c177f8f69cf6aaf
1 /*
2 * pci_host.c
4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "pci.h"
22 #include "pci_host.h"
24 /* debug PCI */
25 //#define DEBUG_PCI
27 #ifdef DEBUG_PCI
28 #define PCI_DPRINTF(fmt, ...) \
29 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
30 #else
31 #define PCI_DPRINTF(fmt, ...)
32 #endif
35 * PCI address
36 * bit 16 - 24: bus number
37 * bit 8 - 15: devfun number
38 * bit 0 - 7: offset in configuration space of a given pci device
41 /* the helper functio to get a PCIDeice* for a given pci address */
42 static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
44 uint8_t bus_num = addr >> 16;
45 uint8_t devfn = addr >> 8;
47 return pci_find_device(bus, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
50 void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
52 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
53 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
55 if (!pci_dev)
56 return;
58 PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n",
59 __func__, pci_dev->name, config_addr, val, len);
60 pci_dev->config_write(pci_dev, config_addr, val, len);
63 uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
65 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
66 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
67 uint32_t val;
69 assert(len == 1 || len == 2 || len == 4);
70 if (!pci_dev) {
71 return ~0x0;
74 val = pci_dev->config_read(pci_dev, config_addr, len);
75 PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
76 __func__, pci_dev->name, config_addr, val, len);
78 return val;
81 static void pci_host_config_write(ReadWriteHandler *handler,
82 pcibus_t addr, uint32_t val, int len)
84 PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
86 PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
87 __func__, addr, len, val);
88 s->config_reg = val;
91 static uint32_t pci_host_config_read(ReadWriteHandler *handler,
92 pcibus_t addr, int len)
94 PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
95 uint32_t val = s->config_reg;
97 PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
98 __func__, addr, len, val);
99 return val;
102 static void pci_host_data_write(ReadWriteHandler *handler,
103 pcibus_t addr, uint32_t val, int len)
105 PCIHostState *s = container_of(handler, PCIHostState, data_handler);
106 PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
107 addr, len, val);
108 if (s->config_reg & (1u << 31))
109 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
112 static uint32_t pci_host_data_read(ReadWriteHandler *handler,
113 pcibus_t addr, int len)
115 PCIHostState *s = container_of(handler, PCIHostState, data_handler);
116 uint32_t val;
117 if (!(s->config_reg & (1 << 31)))
118 return 0xffffffff;
119 val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
120 PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
121 addr, len, val);
122 return val;
125 static void pci_host_init(PCIHostState *s)
127 s->conf_handler.write = pci_host_config_write;
128 s->conf_handler.read = pci_host_config_read;
129 s->data_handler.write = pci_host_data_write;
130 s->data_handler.read = pci_host_data_read;
133 int pci_host_conf_register_mmio(PCIHostState *s, int endian)
135 pci_host_init(s);
136 return cpu_register_io_memory_simple(&s->conf_handler, endian);
139 void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s)
141 pci_host_init(s);
142 register_ioport_simple(&s->conf_handler, ioport, 4, 4);
143 sysbus_init_ioports(&s->busdev, ioport, 4);
146 int pci_host_data_register_mmio(PCIHostState *s, int endian)
148 pci_host_init(s);
149 return cpu_register_io_memory_simple(&s->data_handler, endian);
152 void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
154 pci_host_init(s);
155 register_ioport_simple(&s->data_handler, ioport, 4, 1);
156 register_ioport_simple(&s->data_handler, ioport, 4, 2);
157 register_ioport_simple(&s->data_handler, ioport, 4, 4);
158 sysbus_init_ioports(&s->busdev, ioport, 4);