hw/i8254.c

   1 /*
   2  * QEMU 8253/8254 interval timer emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "qemu-timer.h"
  28
  29 //#define DEBUG_PIT
  30
  31 #define RW_STATE_LSB 1
  32 #define RW_STATE_MSB 2
  33 #define RW_STATE_WORD0 3
  34 #define RW_STATE_WORD1 4
  35
  36 typedef struct PITChannelState {
  37     int count; /* can be 65536 */
  38     uint16_t latched_count;
  39     uint8_t count_latched;
  40     uint8_t status_latched;
  41     uint8_t status;
  42     uint8_t read_state;
  43     uint8_t write_state;
  44     uint8_t write_latch;
  45     uint8_t rw_mode;
  46     uint8_t mode;
  47     uint8_t bcd; /* not supported */
  48     uint8_t gate; /* timer start */
  49     int64_t count_load_time;
  50     /* irq handling */
  51     int64_t next_transition_time;
  52     QEMUTimer *irq_timer;
  53     qemu_irq irq;
  54 } PITChannelState;
  55
  56 typedef struct PITState {
  57     ISADevice dev;
  58     uint32_t irq;
  59     uint32_t iobase;
  60     PITChannelState channels[3];
  61 } PITState;
  62
  63 static PITState pit_state;
  64
  65 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
  66
  67 static int pit_get_count(PITChannelState *s)
  68 {
  69     uint64_t d;
  70     int counter;
  71
  72     d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ,
  73                  get_ticks_per_sec());
  74     switch(s->mode) {
  75     case 0:
  76     case 1:
  77     case 4:
  78     case 5:
  79         counter = (s->count - d) & 0xffff;
  80         break;
  81     case 3:
  82         /* XXX: may be incorrect for odd counts */
  83         counter = s->count - ((2 * d) % s->count);
  84         break;
  85     default:
  86         counter = s->count - (d % s->count);
  87         break;
  88     }
  89     return counter;
  90 }
  91
  92 /* get pit output bit */
  93 static int pit_get_out1(PITChannelState *s, int64_t current_time)
  94 {
  95     uint64_t d;
  96     int out;
  97
  98     d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
  99                  get_ticks_per_sec());
 100     switch(s->mode) {
 101     default:
 102     case 0:
 103         out = (d >= s->count);
 104         break;
 105     case 1:
 106         out = (d < s->count);
 107         break;
 108     case 2:
 109         if ((d % s->count) == 0 && d != 0)
 110             out = 1;
 111         else
 112             out = 0;
 113         break;
 114     case 3:
 115         out = (d % s->count) < ((s->count + 1) >> 1);
 116         break;
 117     case 4:
 118     case 5:
 119         out = (d == s->count);
 120         break;
 121     }
 122     return out;
 123 }
 124
 125 int pit_get_out(ISADevice *dev, int channel, int64_t current_time)
 126 {
 127     PITState *pit = DO_UPCAST(PITState, dev, dev);
 128     PITChannelState *s = &pit->channels[channel];
 129     return pit_get_out1(s, current_time);
 130 }
 131
 132 /* return -1 if no transition will occur.  */
 133 static int64_t pit_get_next_transition_time(PITChannelState *s,
 134                                             int64_t current_time)
 135 {
 136     uint64_t d, next_time, base;
 137     int period2;
 138
 139     d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
 140                  get_ticks_per_sec());
 141     switch(s->mode) {
 142     default:
 143     case 0:
 144     case 1:
 145         if (d < s->count)
 146             next_time = s->count;
 147         else
 148             return -1;
 149         break;
 150     case 2:
 151         base = (d / s->count) * s->count;
 152         if ((d - base) == 0 && d != 0)
 153             next_time = base + s->count;
 154         else
 155             next_time = base + s->count + 1;
 156         break;
 157     case 3:
 158         base = (d / s->count) * s->count;
 159         period2 = ((s->count + 1) >> 1);
 160         if ((d - base) < period2)
 161             next_time = base + period2;
 162         else
 163             next_time = base + s->count;
 164         break;
 165     case 4:
 166     case 5:
 167         if (d < s->count)
 168             next_time = s->count;
 169         else if (d == s->count)
 170             next_time = s->count + 1;
 171         else
 172             return -1;
 173         break;
 174     }
 175     /* convert to timer units */
 176     next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(),
 177                                               PIT_FREQ);
 178     /* fix potential rounding problems */
 179     /* XXX: better solution: use a clock at PIT_FREQ Hz */
 180     if (next_time <= current_time)
 181         next_time = current_time + 1;
 182     return next_time;
 183 }
 184
 185 /* val must be 0 or 1 */
 186 void pit_set_gate(ISADevice *dev, int channel, int val)
 187 {
 188     PITState *pit = DO_UPCAST(PITState, dev, dev);
 189     PITChannelState *s = &pit->channels[channel];
 190
 191     switch(s->mode) {
 192     default:
 193     case 0:
 194     case 4:
 195         /* XXX: just disable/enable counting */
 196         break;
 197     case 1:
 198     case 5:
 199         if (s->gate < val) {
 200             /* restart counting on rising edge */
 201             s->count_load_time = qemu_get_clock(vm_clock);
 202             pit_irq_timer_update(s, s->count_load_time);
 203         }
 204         break;
 205     case 2:
 206     case 3:
 207         if (s->gate < val) {
 208             /* restart counting on rising edge */
 209             s->count_load_time = qemu_get_clock(vm_clock);
 210             pit_irq_timer_update(s, s->count_load_time);
 211         }
 212         /* XXX: disable/enable counting */
 213         break;
 214     }
 215     s->gate = val;
 216 }
 217
 218 int pit_get_gate(ISADevice *dev, int channel)
 219 {
 220     PITState *pit = DO_UPCAST(PITState, dev, dev);
 221     PITChannelState *s = &pit->channels[channel];
 222     return s->gate;
 223 }
 224
 225 int pit_get_initial_count(ISADevice *dev, int channel)
 226 {
 227     PITState *pit = DO_UPCAST(PITState, dev, dev);
 228     PITChannelState *s = &pit->channels[channel];
 229     return s->count;
 230 }
 231
 232 int pit_get_mode(ISADevice *dev, int channel)
 233 {
 234     PITState *pit = DO_UPCAST(PITState, dev, dev);
 235     PITChannelState *s = &pit->channels[channel];
 236     return s->mode;
 237 }
 238
 239 static inline void pit_load_count(PITChannelState *s, int val)
 240 {
 241     if (val == 0)
 242         val = 0x10000;
 243     s->count_load_time = qemu_get_clock(vm_clock);
 244     s->count = val;
 245     pit_irq_timer_update(s, s->count_load_time);
 246 }
 247
 248 /* if already latched, do not latch again */
 249 static void pit_latch_count(PITChannelState *s)
 250 {
 251     if (!s->count_latched) {
 252         s->latched_count = pit_get_count(s);
 253         s->count_latched = s->rw_mode;
 254     }
 255 }
 256
 257 static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 258 {
 259     PITState *pit = opaque;
 260     int channel, access;
 261     PITChannelState *s;
 262
 263     addr &= 3;
 264     if (addr == 3) {
 265         channel = val >> 6;
 266         if (channel == 3) {
 267             /* read back command */
 268             for(channel = 0; channel < 3; channel++) {
 269                 s = &pit->channels[channel];
 270                 if (val & (2 << channel)) {
 271                     if (!(val & 0x20)) {
 272                         pit_latch_count(s);
 273                     }
 274                     if (!(val & 0x10) && !s->status_latched) {
 275                         /* status latch */
 276                         /* XXX: add BCD and null count */
 277                         s->status =  (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
 278                             (s->rw_mode << 4) |
 279                             (s->mode << 1) |
 280                             s->bcd;
 281                         s->status_latched = 1;
 282                     }
 283                 }
 284             }
 285         } else {
 286             s = &pit->channels[channel];
 287             access = (val >> 4) & 3;
 288             if (access == 0) {
 289                 pit_latch_count(s);
 290             } else {
 291                 s->rw_mode = access;
 292                 s->read_state = access;
 293                 s->write_state = access;
 294
 295                 s->mode = (val >> 1) & 7;
 296                 s->bcd = val & 1;
 297                 /* XXX: update irq timer ? */
 298             }
 299         }
 300     } else {
 301         s = &pit->channels[addr];
 302         switch(s->write_state) {
 303         default:
 304         case RW_STATE_LSB:
 305             pit_load_count(s, val);
 306             break;
 307         case RW_STATE_MSB:
 308             pit_load_count(s, val << 8);
 309             break;
 310         case RW_STATE_WORD0:
 311             s->write_latch = val;
 312             s->write_state = RW_STATE_WORD1;
 313             break;
 314         case RW_STATE_WORD1:
 315             pit_load_count(s, s->write_latch | (val << 8));
 316             s->write_state = RW_STATE_WORD0;
 317             break;
 318         }
 319     }
 320 }
 321
 322 static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
 323 {
 324     PITState *pit = opaque;
 325     int ret, count;
 326     PITChannelState *s;
 327
 328     addr &= 3;
 329     s = &pit->channels[addr];
 330     if (s->status_latched) {
 331         s->status_latched = 0;
 332         ret = s->status;
 333     } else if (s->count_latched) {
 334         switch(s->count_latched) {
 335         default:
 336         case RW_STATE_LSB:
 337             ret = s->latched_count & 0xff;
 338             s->count_latched = 0;
 339             break;
 340         case RW_STATE_MSB:
 341             ret = s->latched_count >> 8;
 342             s->count_latched = 0;
 343             break;
 344         case RW_STATE_WORD0:
 345             ret = s->latched_count & 0xff;
 346             s->count_latched = RW_STATE_MSB;
 347             break;
 348         }
 349     } else {
 350         switch(s->read_state) {
 351         default:
 352         case RW_STATE_LSB:
 353             count = pit_get_count(s);
 354             ret = count & 0xff;
 355             break;
 356         case RW_STATE_MSB:
 357             count = pit_get_count(s);
 358             ret = (count >> 8) & 0xff;
 359             break;
 360         case RW_STATE_WORD0:
 361             count = pit_get_count(s);
 362             ret = count & 0xff;
 363             s->read_state = RW_STATE_WORD1;
 364             break;
 365         case RW_STATE_WORD1:
 366             count = pit_get_count(s);
 367             ret = (count >> 8) & 0xff;
 368             s->read_state = RW_STATE_WORD0;
 369             break;
 370         }
 371     }
 372     return ret;
 373 }
 374
 375 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
 376 {
 377     int64_t expire_time;
 378     int irq_level;
 379
 380     if (!s->irq_timer)
 381         return;
 382     expire_time = pit_get_next_transition_time(s, current_time);
 383     irq_level = pit_get_out1(s, current_time);
 384     qemu_set_irq(s->irq, irq_level);
 385 #ifdef DEBUG_PIT
 386     printf("irq_level=%d next_delay=%f\n",
 387            irq_level,
 388            (double)(expire_time - current_time) / get_ticks_per_sec());
 389 #endif
 390     s->next_transition_time = expire_time;
 391     if (expire_time != -1)
 392         qemu_mod_timer(s->irq_timer, expire_time);
 393     else
 394         qemu_del_timer(s->irq_timer);
 395 }
 396
 397 static void pit_irq_timer(void *opaque)
 398 {
 399     PITChannelState *s = opaque;
 400
 401     pit_irq_timer_update(s, s->next_transition_time);
 402 }
 403
 404 static const VMStateDescription vmstate_pit_channel = {
 405     .name = "pit channel",
 406     .version_id = 2,
 407     .minimum_version_id = 2,
 408     .minimum_version_id_old = 2,
 409     .fields      = (VMStateField []) {
 410         VMSTATE_INT32(count, PITChannelState),
 411         VMSTATE_UINT16(latched_count, PITChannelState),
 412         VMSTATE_UINT8(count_latched, PITChannelState),
 413         VMSTATE_UINT8(status_latched, PITChannelState),
 414         VMSTATE_UINT8(status, PITChannelState),
 415         VMSTATE_UINT8(read_state, PITChannelState),
 416         VMSTATE_UINT8(write_state, PITChannelState),
 417         VMSTATE_UINT8(write_latch, PITChannelState),
 418         VMSTATE_UINT8(rw_mode, PITChannelState),
 419         VMSTATE_UINT8(mode, PITChannelState),
 420         VMSTATE_UINT8(bcd, PITChannelState),
 421         VMSTATE_UINT8(gate, PITChannelState),
 422         VMSTATE_INT64(count_load_time, PITChannelState),
 423         VMSTATE_INT64(next_transition_time, PITChannelState),
 424         VMSTATE_END_OF_LIST()
 425     }
 426 };
 427
 428 static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
 429 {
 430     PITState *pit = opaque;
 431     PITChannelState *s;
 432     int i;
 433
 434     if (version_id != 1)
 435         return -EINVAL;
 436
 437     for(i = 0; i < 3; i++) {
 438         s = &pit->channels[i];
 439         s->count=qemu_get_be32(f);
 440         qemu_get_be16s(f, &s->latched_count);
 441         qemu_get_8s(f, &s->count_latched);
 442         qemu_get_8s(f, &s->status_latched);
 443         qemu_get_8s(f, &s->status);
 444         qemu_get_8s(f, &s->read_state);
 445         qemu_get_8s(f, &s->write_state);
 446         qemu_get_8s(f, &s->write_latch);
 447         qemu_get_8s(f, &s->rw_mode);
 448         qemu_get_8s(f, &s->mode);
 449         qemu_get_8s(f, &s->bcd);
 450         qemu_get_8s(f, &s->gate);
 451         s->count_load_time=qemu_get_be64(f);
 452         if (s->irq_timer) {
 453             s->next_transition_time=qemu_get_be64(f);
 454             qemu_get_timer(f, s->irq_timer);
 455         }
 456     }
 457     return 0;
 458 }
 459
 460 static const VMStateDescription vmstate_pit = {
 461     .name = "i8254",
 462     .version_id = 2,
 463     .minimum_version_id = 2,
 464     .minimum_version_id_old = 1,
 465     .load_state_old = pit_load_old,
 466     .fields      = (VMStateField []) {
 467         VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState),
 468         VMSTATE_TIMER(channels[0].irq_timer, PITState),
 469         VMSTATE_END_OF_LIST()
 470     }
 471 };
 472
 473 static void pit_reset(DeviceState *dev)
 474 {
 475     PITState *pit = container_of(dev, PITState, dev.qdev);
 476     PITChannelState *s;
 477     int i;
 478
 479     for(i = 0;i < 3; i++) {
 480         s = &pit->channels[i];
 481         s->mode = 3;
 482         s->gate = (i != 2);
 483         pit_load_count(s, 0);
 484     }
 485 }
 486
 487 /* When HPET is operating in legacy mode, i8254 timer0 is disabled */
 488 void hpet_pit_disable(void) {
 489     PITChannelState *s;
 490     s = &pit_state.channels[0];
 491     if (s->irq_timer)
 492         qemu_del_timer(s->irq_timer);
 493 }
 494
 495 /* When HPET is reset or leaving legacy mode, it must reenable i8254
 496  * timer 0
 497  */
 498
 499 void hpet_pit_enable(void)
 500 {
 501     PITState *pit = &pit_state;
 502     PITChannelState *s;
 503     s = &pit->channels[0];
 504     s->mode = 3;
 505     s->gate = 1;
 506     pit_load_count(s, 0);
 507 }
 508
 509 static int pit_initfn(ISADevice *dev)
 510 {
 511     PITState *pit = DO_UPCAST(PITState, dev, dev);
 512     PITChannelState *s;
 513
 514     s = &pit->channels[0];
 515     /* the timer 0 is connected to an IRQ */
 516     s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
 517     s->irq = isa_get_irq(pit->irq);
 518
 519     register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);
 520     register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit);
 521     isa_init_ioport(dev, pit->iobase);
 522
 523     return 0;
 524 }
 525
 526 static ISADeviceInfo pit_info = {
 527     .qdev.name     = "isa-pit",
 528     .qdev.size     = sizeof(PITState),
 529     .qdev.vmsd     = &vmstate_pit,
 530     .qdev.reset    = pit_reset,
 531     .qdev.no_user  = 1,
 532     .init          = pit_initfn,
 533     .qdev.props = (Property[]) {
 534         DEFINE_PROP_UINT32("irq", PITState, irq,  -1),
 535         DEFINE_PROP_HEX32("iobase", PITState, iobase,  -1),
 536         DEFINE_PROP_END_OF_LIST(),
 537     },
 538 };
 539
 540 static void pit_register(void)
 541 {
 542     isa_qdev_register(&pit_info);
 543 }
 544 device_init(pit_register)