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input: sdl: fix guest_cursor logic.
[qemu.git] / hw / pci / pci.c
blob4e0701df383779c7894e77502be563b5d6a462e8
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/pci/pci.h"
26 #include "hw/pci/pci_bridge.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/pci/pci_host.h"
29 #include "monitor/monitor.h"
30 #include "net/net.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/loader.h"
33 #include "qemu/range.h"
34 #include "qmp-commands.h"
35 #include "hw/pci/msi.h"
36 #include "hw/pci/msix.h"
37 #include "exec/address-spaces.h"
38 #include "hw/hotplug.h"
39
40 //#define DEBUG_PCI
41 #ifdef DEBUG_PCI
42 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
43 #else
44 # define PCI_DPRINTF(format, ...) do { } while (0)
45 #endif
46
47 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
48 static char *pcibus_get_dev_path(DeviceState *dev);
49 static char *pcibus_get_fw_dev_path(DeviceState *dev);
50 static void pcibus_reset(BusState *qbus);
51 static void pci_bus_finalize(Object *obj);
52
53 static Property pci_props[] = {
54 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
55 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
56 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
57 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
58 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
59 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
60 QEMU_PCI_CAP_SERR_BITNR, true),
61 DEFINE_PROP_END_OF_LIST()
62 };
63
64 static void pci_bus_class_init(ObjectClass *klass, void *data)
65 {
66 BusClass *k = BUS_CLASS(klass);
67
68 k->print_dev = pcibus_dev_print;
69 k->get_dev_path = pcibus_get_dev_path;
70 k->get_fw_dev_path = pcibus_get_fw_dev_path;
71 k->reset = pcibus_reset;
72 }
73
74 static const TypeInfo pci_bus_info = {
75 .name = TYPE_PCI_BUS,
76 .parent = TYPE_BUS,
77 .instance_size = sizeof(PCIBus),
78 .instance_finalize = pci_bus_finalize,
79 .class_init = pci_bus_class_init,
80 };
81
82 static const TypeInfo pcie_bus_info = {
83 .name = TYPE_PCIE_BUS,
84 .parent = TYPE_PCI_BUS,
85 };
86
87 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
88 static void pci_update_mappings(PCIDevice *d);
89 static void pci_irq_handler(void *opaque, int irq_num, int level);
90 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
91 static void pci_del_option_rom(PCIDevice *pdev);
92
93 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
94 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
95
96 static QLIST_HEAD(, PCIHostState) pci_host_bridges;
97
98 static const VMStateDescription vmstate_pcibus = {
99 .name = "PCIBUS",
100 .version_id = 1,
101 .minimum_version_id = 1,
102 .minimum_version_id_old = 1,
103 .fields = (VMStateField []) {
104 VMSTATE_INT32_EQUAL(nirq, PCIBus),
105 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
106 VMSTATE_END_OF_LIST()
107 }
108 };
109 static int pci_bar(PCIDevice *d, int reg)
110 {
111 uint8_t type;
112
113 if (reg != PCI_ROM_SLOT)
114 return PCI_BASE_ADDRESS_0 + reg * 4;
115
116 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
117 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
118 }
119
120 static inline int pci_irq_state(PCIDevice *d, int irq_num)
121 {
122 return (d->irq_state >> irq_num) & 0x1;
123 }
124
125 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
126 {
127 d->irq_state &= ~(0x1 << irq_num);
128 d->irq_state |= level << irq_num;
129 }
130
131 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
132 {
133 PCIBus *bus;
134 for (;;) {
135 bus = pci_dev->bus;
136 irq_num = bus->map_irq(pci_dev, irq_num);
137 if (bus->set_irq)
138 break;
139 pci_dev = bus->parent_dev;
140 }
141 bus->irq_count[irq_num] += change;
142 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
143 }
144
145 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
146 {
147 assert(irq_num >= 0);
148 assert(irq_num < bus->nirq);
149 return !!bus->irq_count[irq_num];
150 }
151
152 /* Update interrupt status bit in config space on interrupt
153 * state change. */
154 static void pci_update_irq_status(PCIDevice *dev)
155 {
156 if (dev->irq_state) {
157 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
158 } else {
159 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
160 }
161 }
162
163 void pci_device_deassert_intx(PCIDevice *dev)
164 {
165 int i;
166 for (i = 0; i < PCI_NUM_PINS; ++i) {
167 pci_irq_handler(dev, i, 0);
168 }
169 }
170
171 static void pci_do_device_reset(PCIDevice *dev)
172 {
173 int r;
174
175 dev->irq_state = 0;
176 pci_update_irq_status(dev);
177 pci_device_deassert_intx(dev);
178 /* Clear all writable bits */
179 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
180 pci_get_word(dev->wmask + PCI_COMMAND) |
181 pci_get_word(dev->w1cmask + PCI_COMMAND));
182 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
183 pci_get_word(dev->wmask + PCI_STATUS) |
184 pci_get_word(dev->w1cmask + PCI_STATUS));
185 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
186 dev->config[PCI_INTERRUPT_LINE] = 0x0;
187 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
188 PCIIORegion *region = &dev->io_regions[r];
189 if (!region->size) {
190 continue;
191 }
192
193 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
194 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
195 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
196 } else {
197 pci_set_long(dev->config + pci_bar(dev, r), region->type);
198 }
199 }
200 pci_update_mappings(dev);
201
202 msi_reset(dev);
203 msix_reset(dev);
204 }
205
206 /*
207 * This function is called on #RST and FLR.
208 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
209 */
210 void pci_device_reset(PCIDevice *dev)
211 {
212 qdev_reset_all(&dev->qdev);
213 pci_do_device_reset(dev);
214 }
215
216 /*
217 * Trigger pci bus reset under a given bus.
218 * Called via qbus_reset_all on RST# assert, after the devices
219 * have been reset qdev_reset_all-ed already.
220 */
221 static void pcibus_reset(BusState *qbus)
222 {
223 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
224 int i;
225
226 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
227 if (bus->devices[i]) {
228 pci_do_device_reset(bus->devices[i]);
229 }
230 }
231
232 for (i = 0; i < bus->nirq; i++) {
233 assert(bus->irq_count[i] == 0);
234 }
235 }
236
237 static void pci_host_bus_register(PCIBus *bus, DeviceState *parent)
238 {
239 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent);
240
241 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
242 }
243
244 PCIBus *pci_find_primary_bus(void)
245 {
246 PCIBus *primary_bus = NULL;
247 PCIHostState *host;
248
249 QLIST_FOREACH(host, &pci_host_bridges, next) {
250 if (primary_bus) {
251 /* We have multiple root buses, refuse to select a primary */
252 return NULL;
253 }
254 primary_bus = host->bus;
255 }
256
257 return primary_bus;
258 }
259
260 PCIBus *pci_device_root_bus(const PCIDevice *d)
261 {
262 PCIBus *bus = d->bus;
263
264 while ((d = bus->parent_dev) != NULL) {
265 bus = d->bus;
266 }
267
268 return bus;
269 }
270
271 const char *pci_root_bus_path(PCIDevice *dev)
272 {
273 PCIBus *rootbus = pci_device_root_bus(dev);
274 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
275 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
276
277 assert(!rootbus->parent_dev);
278 assert(host_bridge->bus == rootbus);
279
280 if (hc->root_bus_path) {
281 return (*hc->root_bus_path)(host_bridge, rootbus);
282 }
283
284 return rootbus->qbus.name;
285 }
286
287 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
288 const char *name,
289 MemoryRegion *address_space_mem,
290 MemoryRegion *address_space_io,
291 uint8_t devfn_min)
292 {
293 assert(PCI_FUNC(devfn_min) == 0);
294 bus->devfn_min = devfn_min;
295 bus->address_space_mem = address_space_mem;
296 bus->address_space_io = address_space_io;
297
298 /* host bridge */
299 QLIST_INIT(&bus->child);
300
301 pci_host_bus_register(bus, parent);
302
303 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
304 }
305
306 bool pci_bus_is_express(PCIBus *bus)
307 {
308 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
309 }
310
311 bool pci_bus_is_root(PCIBus *bus)
312 {
313 return !bus->parent_dev;
314 }
315
316 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
317 const char *name,
318 MemoryRegion *address_space_mem,
319 MemoryRegion *address_space_io,
320 uint8_t devfn_min, const char *typename)
321 {
322 qbus_create_inplace(bus, bus_size, typename, parent, name);
323 pci_bus_init(bus, parent, name, address_space_mem,
324 address_space_io, devfn_min);
325 }
326
327 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
328 MemoryRegion *address_space_mem,
329 MemoryRegion *address_space_io,
330 uint8_t devfn_min, const char *typename)
331 {
332 PCIBus *bus;
333
334 bus = PCI_BUS(qbus_create(typename, parent, name));
335 pci_bus_init(bus, parent, name, address_space_mem,
336 address_space_io, devfn_min);
337 return bus;
338 }
339
340 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
341 void *irq_opaque, int nirq)
342 {
343 bus->set_irq = set_irq;
344 bus->map_irq = map_irq;
345 bus->irq_opaque = irq_opaque;
346 bus->nirq = nirq;
347 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
348 }
349
350 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
351 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
352 void *irq_opaque,
353 MemoryRegion *address_space_mem,
354 MemoryRegion *address_space_io,
355 uint8_t devfn_min, int nirq, const char *typename)
356 {
357 PCIBus *bus;
358
359 bus = pci_bus_new(parent, name, address_space_mem,
360 address_space_io, devfn_min, typename);
361 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
362 return bus;
363 }
364
365 int pci_bus_num(PCIBus *s)
366 {
367 if (pci_bus_is_root(s))
368 return 0; /* pci host bridge */
369 return s->parent_dev->config[PCI_SECONDARY_BUS];
370 }
371
372 static void pci_bus_finalize(Object *obj)
373 {
374 PCIBus *bus = PCI_BUS(obj);
375 vmstate_unregister(NULL, &vmstate_pcibus, bus);
376 }
377
378 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
379 {
380 PCIDevice *s = container_of(pv, PCIDevice, config);
381 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
382 uint8_t *config;
383 int i;
384
385 assert(size == pci_config_size(s));
386 config = g_malloc(size);
387
388 qemu_get_buffer(f, config, size);
389 for (i = 0; i < size; ++i) {
390 if ((config[i] ^ s->config[i]) &
391 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
392 g_free(config);
393 return -EINVAL;
394 }
395 }
396 memcpy(s->config, config, size);
397
398 pci_update_mappings(s);
399 if (pc->is_bridge) {
400 PCIBridge *b = PCI_BRIDGE(s);
401 pci_bridge_update_mappings(b);
402 }
403
404 memory_region_set_enabled(&s->bus_master_enable_region,
405 pci_get_word(s->config + PCI_COMMAND)
406 & PCI_COMMAND_MASTER);
407
408 g_free(config);
409 return 0;
410 }
411
412 /* just put buffer */
413 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
414 {
415 const uint8_t **v = pv;
416 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
417 qemu_put_buffer(f, *v, size);
418 }
419
420 static VMStateInfo vmstate_info_pci_config = {
421 .name = "pci config",
422 .get = get_pci_config_device,
423 .put = put_pci_config_device,
424 };
425
426 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
427 {
428 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
429 uint32_t irq_state[PCI_NUM_PINS];
430 int i;
431 for (i = 0; i < PCI_NUM_PINS; ++i) {
432 irq_state[i] = qemu_get_be32(f);
433 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
434 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
435 irq_state[i]);
436 return -EINVAL;
437 }
438 }
439
440 for (i = 0; i < PCI_NUM_PINS; ++i) {
441 pci_set_irq_state(s, i, irq_state[i]);
442 }
443
444 return 0;
445 }
446
447 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
448 {
449 int i;
450 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
451
452 for (i = 0; i < PCI_NUM_PINS; ++i) {
453 qemu_put_be32(f, pci_irq_state(s, i));
454 }
455 }
456
457 static VMStateInfo vmstate_info_pci_irq_state = {
458 .name = "pci irq state",
459 .get = get_pci_irq_state,
460 .put = put_pci_irq_state,
461 };
462
463 const VMStateDescription vmstate_pci_device = {
464 .name = "PCIDevice",
465 .version_id = 2,
466 .minimum_version_id = 1,
467 .minimum_version_id_old = 1,
468 .fields = (VMStateField []) {
469 VMSTATE_INT32_LE(version_id, PCIDevice),
470 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
471 vmstate_info_pci_config,
472 PCI_CONFIG_SPACE_SIZE),
473 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
474 vmstate_info_pci_irq_state,
475 PCI_NUM_PINS * sizeof(int32_t)),
476 VMSTATE_END_OF_LIST()
477 }
478 };
479
480 const VMStateDescription vmstate_pcie_device = {
481 .name = "PCIEDevice",
482 .version_id = 2,
483 .minimum_version_id = 1,
484 .minimum_version_id_old = 1,
485 .fields = (VMStateField []) {
486 VMSTATE_INT32_LE(version_id, PCIDevice),
487 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
488 vmstate_info_pci_config,
489 PCIE_CONFIG_SPACE_SIZE),
490 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
491 vmstate_info_pci_irq_state,
492 PCI_NUM_PINS * sizeof(int32_t)),
493 VMSTATE_END_OF_LIST()
494 }
495 };
496
497 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
498 {
499 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
500 }
501
502 void pci_device_save(PCIDevice *s, QEMUFile *f)
503 {
504 /* Clear interrupt status bit: it is implicit
505 * in irq_state which we are saving.
506 * This makes us compatible with old devices
507 * which never set or clear this bit. */
508 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
509 vmstate_save_state(f, pci_get_vmstate(s), s);
510 /* Restore the interrupt status bit. */
511 pci_update_irq_status(s);
512 }
513
514 int pci_device_load(PCIDevice *s, QEMUFile *f)
515 {
516 int ret;
517 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
518 /* Restore the interrupt status bit. */
519 pci_update_irq_status(s);
520 return ret;
521 }
522
523 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
524 {
525 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
526 pci_default_sub_vendor_id);
527 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
528 pci_default_sub_device_id);
529 }
530
531 /*
532 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
533 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
534 */
535 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
536 unsigned int *slotp, unsigned int *funcp)
537 {
538 const char *p;
539 char *e;
540 unsigned long val;
541 unsigned long dom = 0, bus = 0;
542 unsigned int slot = 0;
543 unsigned int func = 0;
544
545 p = addr;
546 val = strtoul(p, &e, 16);
547 if (e == p)
548 return -1;
549 if (*e == ':') {
550 bus = val;
551 p = e + 1;
552 val = strtoul(p, &e, 16);
553 if (e == p)
554 return -1;
555 if (*e == ':') {
556 dom = bus;
557 bus = val;
558 p = e + 1;
559 val = strtoul(p, &e, 16);
560 if (e == p)
561 return -1;
562 }
563 }
564
565 slot = val;
566
567 if (funcp != NULL) {
568 if (*e != '.')
569 return -1;
570
571 p = e + 1;
572 val = strtoul(p, &e, 16);
573 if (e == p)
574 return -1;
575
576 func = val;
577 }
578
579 /* if funcp == NULL func is 0 */
580 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
581 return -1;
582
583 if (*e)
584 return -1;
585
586 *domp = dom;
587 *busp = bus;
588 *slotp = slot;
589 if (funcp != NULL)
590 *funcp = func;
591 return 0;
592 }
593
594 PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr)
595 {
596 int dom, bus;
597 unsigned slot;
598
599 assert(!root->parent_dev);
600
601 if (!root) {
602 fprintf(stderr, "No primary PCI bus\n");
603 return NULL;
604 }
605
606 if (!devaddr) {
607 *devfnp = -1;
608 return pci_find_bus_nr(root, 0);
609 }
610
611 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
612 return NULL;
613 }
614
615 if (dom != 0) {
616 fprintf(stderr, "No support for non-zero PCI domains\n");
617 return NULL;
618 }
619
620 *devfnp = PCI_DEVFN(slot, 0);
621 return pci_find_bus_nr(root, bus);
622 }
623
624 static void pci_init_cmask(PCIDevice *dev)
625 {
626 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
627 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
628 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
629 dev->cmask[PCI_REVISION_ID] = 0xff;
630 dev->cmask[PCI_CLASS_PROG] = 0xff;
631 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
632 dev->cmask[PCI_HEADER_TYPE] = 0xff;
633 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
634 }
635
636 static void pci_init_wmask(PCIDevice *dev)
637 {
638 int config_size = pci_config_size(dev);
639
640 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
641 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
642 pci_set_word(dev->wmask + PCI_COMMAND,
643 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
644 PCI_COMMAND_INTX_DISABLE);
645 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
646 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
647 }
648
649 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
650 config_size - PCI_CONFIG_HEADER_SIZE);
651 }
652
653 static void pci_init_w1cmask(PCIDevice *dev)
654 {
655 /*
656 * Note: It's okay to set w1cmask even for readonly bits as
657 * long as their value is hardwired to 0.
658 */
659 pci_set_word(dev->w1cmask + PCI_STATUS,
660 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
661 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
662 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
663 }
664
665 static void pci_init_mask_bridge(PCIDevice *d)
666 {
667 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
668 PCI_SEC_LETENCY_TIMER */
669 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
670
671 /* base and limit */
672 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
673 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
674 pci_set_word(d->wmask + PCI_MEMORY_BASE,
675 PCI_MEMORY_RANGE_MASK & 0xffff);
676 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
677 PCI_MEMORY_RANGE_MASK & 0xffff);
678 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
679 PCI_PREF_RANGE_MASK & 0xffff);
680 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
681 PCI_PREF_RANGE_MASK & 0xffff);
682
683 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
684 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
685
686 /* Supported memory and i/o types */
687 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
688 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
689 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
690 PCI_PREF_RANGE_TYPE_64);
691 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
692 PCI_PREF_RANGE_TYPE_64);
693
694 /*
695 * TODO: Bridges default to 10-bit VGA decoding but we currently only
696 * implement 16-bit decoding (no alias support).
697 */
698 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
699 PCI_BRIDGE_CTL_PARITY |
700 PCI_BRIDGE_CTL_SERR |
701 PCI_BRIDGE_CTL_ISA |
702 PCI_BRIDGE_CTL_VGA |
703 PCI_BRIDGE_CTL_VGA_16BIT |
704 PCI_BRIDGE_CTL_MASTER_ABORT |
705 PCI_BRIDGE_CTL_BUS_RESET |
706 PCI_BRIDGE_CTL_FAST_BACK |
707 PCI_BRIDGE_CTL_DISCARD |
708 PCI_BRIDGE_CTL_SEC_DISCARD |
709 PCI_BRIDGE_CTL_DISCARD_SERR);
710 /* Below does not do anything as we never set this bit, put here for
711 * completeness. */
712 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
713 PCI_BRIDGE_CTL_DISCARD_STATUS);
714 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
715 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
716 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
717 PCI_PREF_RANGE_TYPE_MASK);
718 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
719 PCI_PREF_RANGE_TYPE_MASK);
720 }
721
722 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
723 {
724 uint8_t slot = PCI_SLOT(dev->devfn);
725 uint8_t func;
726
727 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
728 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
729 }
730
731 /*
732 * multifunction bit is interpreted in two ways as follows.
733 * - all functions must set the bit to 1.
734 * Example: Intel X53
735 * - function 0 must set the bit, but the rest function (> 0)
736 * is allowed to leave the bit to 0.
737 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
738 *
739 * So OS (at least Linux) checks the bit of only function 0,
740 * and doesn't see the bit of function > 0.
741 *
742 * The below check allows both interpretation.
743 */
744 if (PCI_FUNC(dev->devfn)) {
745 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
746 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
747 /* function 0 should set multifunction bit */
748 error_report("PCI: single function device can't be populated "
749 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
750 return -1;
751 }
752 return 0;
753 }
754
755 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
756 return 0;
757 }
758 /* function 0 indicates single function, so function > 0 must be NULL */
759 for (func = 1; func < PCI_FUNC_MAX; ++func) {
760 if (bus->devices[PCI_DEVFN(slot, func)]) {
761 error_report("PCI: %x.0 indicates single function, "
762 "but %x.%x is already populated.",
763 slot, slot, func);
764 return -1;
765 }
766 }
767 return 0;
768 }
769
770 static void pci_config_alloc(PCIDevice *pci_dev)
771 {
772 int config_size = pci_config_size(pci_dev);
773
774 pci_dev->config = g_malloc0(config_size);
775 pci_dev->cmask = g_malloc0(config_size);
776 pci_dev->wmask = g_malloc0(config_size);
777 pci_dev->w1cmask = g_malloc0(config_size);
778 pci_dev->used = g_malloc0(config_size);
779 }
780
781 static void pci_config_free(PCIDevice *pci_dev)
782 {
783 g_free(pci_dev->config);
784 g_free(pci_dev->cmask);
785 g_free(pci_dev->wmask);
786 g_free(pci_dev->w1cmask);
787 g_free(pci_dev->used);
788 }
789
790 static void do_pci_unregister_device(PCIDevice *pci_dev)
791 {
792 pci_dev->bus->devices[pci_dev->devfn] = NULL;
793 pci_config_free(pci_dev);
794
795 address_space_destroy(&pci_dev->bus_master_as);
796 memory_region_destroy(&pci_dev->bus_master_enable_region);
797 }
798
799 /* -1 for devfn means auto assign */
800 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
801 const char *name, int devfn)
802 {
803 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
804 PCIConfigReadFunc *config_read = pc->config_read;
805 PCIConfigWriteFunc *config_write = pc->config_write;
806 AddressSpace *dma_as;
807
808 if (devfn < 0) {
809 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
810 devfn += PCI_FUNC_MAX) {
811 if (!bus->devices[devfn])
812 goto found;
813 }
814 error_report("PCI: no slot/function available for %s, all in use", name);
815 return NULL;
816 found: ;
817 } else if (bus->devices[devfn]) {
818 error_report("PCI: slot %d function %d not available for %s, in use by %s",
819 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
820 return NULL;
821 }
822
823 pci_dev->bus = bus;
824 dma_as = pci_device_iommu_address_space(pci_dev);
825
826 memory_region_init_alias(&pci_dev->bus_master_enable_region,
827 OBJECT(pci_dev), "bus master",
828 dma_as->root, 0, memory_region_size(dma_as->root));
829 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
830 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region,
831 name);
832
833 pci_dev->devfn = devfn;
834 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
835 pci_dev->irq_state = 0;
836 pci_config_alloc(pci_dev);
837
838 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
839 pci_config_set_device_id(pci_dev->config, pc->device_id);
840 pci_config_set_revision(pci_dev->config, pc->revision);
841 pci_config_set_class(pci_dev->config, pc->class_id);
842
843 if (!pc->is_bridge) {
844 if (pc->subsystem_vendor_id || pc->subsystem_id) {
845 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
846 pc->subsystem_vendor_id);
847 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
848 pc->subsystem_id);
849 } else {
850 pci_set_default_subsystem_id(pci_dev);
851 }
852 } else {
853 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
854 assert(!pc->subsystem_vendor_id);
855 assert(!pc->subsystem_id);
856 }
857 pci_init_cmask(pci_dev);
858 pci_init_wmask(pci_dev);
859 pci_init_w1cmask(pci_dev);
860 if (pc->is_bridge) {
861 pci_init_mask_bridge(pci_dev);
862 }
863 if (pci_init_multifunction(bus, pci_dev)) {
864 do_pci_unregister_device(pci_dev);
865 return NULL;
866 }
867
868 if (!config_read)
869 config_read = pci_default_read_config;
870 if (!config_write)
871 config_write = pci_default_write_config;
872 pci_dev->config_read = config_read;
873 pci_dev->config_write = config_write;
874 bus->devices[devfn] = pci_dev;
875 pci_dev->version_id = 2; /* Current pci device vmstate version */
876 return pci_dev;
877 }
878
879 static void pci_unregister_io_regions(PCIDevice *pci_dev)
880 {
881 PCIIORegion *r;
882 int i;
883
884 for(i = 0; i < PCI_NUM_REGIONS; i++) {
885 r = &pci_dev->io_regions[i];
886 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
887 continue;
888 memory_region_del_subregion(r->address_space, r->memory);
889 }
890
891 pci_unregister_vga(pci_dev);
892 }
893
894 static int pci_unregister_device(DeviceState *dev)
895 {
896 PCIDevice *pci_dev = PCI_DEVICE(dev);
897 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
898
899 pci_unregister_io_regions(pci_dev);
900 pci_del_option_rom(pci_dev);
901
902 if (pc->exit) {
903 pc->exit(pci_dev);
904 }
905
906 do_pci_unregister_device(pci_dev);
907 return 0;
908 }
909
910 void pci_register_bar(PCIDevice *pci_dev, int region_num,
911 uint8_t type, MemoryRegion *memory)
912 {
913 PCIIORegion *r;
914 uint32_t addr;
915 uint64_t wmask;
916 pcibus_t size = memory_region_size(memory);
917
918 assert(region_num >= 0);
919 assert(region_num < PCI_NUM_REGIONS);
920 if (size & (size-1)) {
921 fprintf(stderr, "ERROR: PCI region size must be pow2 "
922 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
923 exit(1);
924 }
925
926 r = &pci_dev->io_regions[region_num];
927 r->addr = PCI_BAR_UNMAPPED;
928 r->size = size;
929 r->type = type;
930 r->memory = NULL;
931
932 wmask = ~(size - 1);
933 addr = pci_bar(pci_dev, region_num);
934 if (region_num == PCI_ROM_SLOT) {
935 /* ROM enable bit is writable */
936 wmask |= PCI_ROM_ADDRESS_ENABLE;
937 }
938 pci_set_long(pci_dev->config + addr, type);
939 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
940 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
941 pci_set_quad(pci_dev->wmask + addr, wmask);
942 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
943 } else {
944 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
945 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
946 }
947 pci_dev->io_regions[region_num].memory = memory;
948 pci_dev->io_regions[region_num].address_space
949 = type & PCI_BASE_ADDRESS_SPACE_IO
950 ? pci_dev->bus->address_space_io
951 : pci_dev->bus->address_space_mem;
952 }
953
954 static void pci_update_vga(PCIDevice *pci_dev)
955 {
956 uint16_t cmd;
957
958 if (!pci_dev->has_vga) {
959 return;
960 }
961
962 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
963
964 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
965 cmd & PCI_COMMAND_MEMORY);
966 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
967 cmd & PCI_COMMAND_IO);
968 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
969 cmd & PCI_COMMAND_IO);
970 }
971
972 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
973 MemoryRegion *io_lo, MemoryRegion *io_hi)
974 {
975 assert(!pci_dev->has_vga);
976
977 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
978 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
979 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
980 QEMU_PCI_VGA_MEM_BASE, mem, 1);
981
982 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
983 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
984 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
985 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
986
987 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
988 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
989 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
990 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
991 pci_dev->has_vga = true;
992
993 pci_update_vga(pci_dev);
994 }
995
996 void pci_unregister_vga(PCIDevice *pci_dev)
997 {
998 if (!pci_dev->has_vga) {
999 return;
1000 }
1001
1002 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1003 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1004 memory_region_del_subregion(pci_dev->bus->address_space_io,
1005 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1006 memory_region_del_subregion(pci_dev->bus->address_space_io,
1007 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1008 pci_dev->has_vga = false;
1009 }
1010
1011 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1012 {
1013 return pci_dev->io_regions[region_num].addr;
1014 }
1015
1016 static pcibus_t pci_bar_address(PCIDevice *d,
1017 int reg, uint8_t type, pcibus_t size)
1018 {
1019 pcibus_t new_addr, last_addr;
1020 int bar = pci_bar(d, reg);
1021 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1022
1023 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1024 if (!(cmd & PCI_COMMAND_IO)) {
1025 return PCI_BAR_UNMAPPED;
1026 }
1027 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1028 last_addr = new_addr + size - 1;
1029 /* Check if 32 bit BAR wraps around explicitly.
1030 * TODO: make priorities correct and remove this work around.
1031 */
1032 if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) {
1033 return PCI_BAR_UNMAPPED;
1034 }
1035 return new_addr;
1036 }
1037
1038 if (!(cmd & PCI_COMMAND_MEMORY)) {
1039 return PCI_BAR_UNMAPPED;
1040 }
1041 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1042 new_addr = pci_get_quad(d->config + bar);
1043 } else {
1044 new_addr = pci_get_long(d->config + bar);
1045 }
1046 /* the ROM slot has a specific enable bit */
1047 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1048 return PCI_BAR_UNMAPPED;
1049 }
1050 new_addr &= ~(size - 1);
1051 last_addr = new_addr + size - 1;
1052 /* NOTE: we do not support wrapping */
1053 /* XXX: as we cannot support really dynamic
1054 mappings, we handle specific values as invalid
1055 mappings. */
1056 if (last_addr <= new_addr || new_addr == 0 ||
1057 last_addr == PCI_BAR_UNMAPPED) {
1058 return PCI_BAR_UNMAPPED;
1059 }
1060
1061 /* Now pcibus_t is 64bit.
1062 * Check if 32 bit BAR wraps around explicitly.
1063 * Without this, PC ide doesn't work well.
1064 * TODO: remove this work around.
1065 */
1066 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1067 return PCI_BAR_UNMAPPED;
1068 }
1069
1070 /*
1071 * OS is allowed to set BAR beyond its addressable
1072 * bits. For example, 32 bit OS can set 64bit bar
1073 * to >4G. Check it. TODO: we might need to support
1074 * it in the future for e.g. PAE.
1075 */
1076 if (last_addr >= HWADDR_MAX) {
1077 return PCI_BAR_UNMAPPED;
1078 }
1079
1080 return new_addr;
1081 }
1082
1083 static void pci_update_mappings(PCIDevice *d)
1084 {
1085 PCIIORegion *r;
1086 int i;
1087 pcibus_t new_addr;
1088
1089 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1090 r = &d->io_regions[i];
1091
1092 /* this region isn't registered */
1093 if (!r->size)
1094 continue;
1095
1096 new_addr = pci_bar_address(d, i, r->type, r->size);
1097
1098 /* This bar isn't changed */
1099 if (new_addr == r->addr)
1100 continue;
1101
1102 /* now do the real mapping */
1103 if (r->addr != PCI_BAR_UNMAPPED) {
1104 memory_region_del_subregion(r->address_space, r->memory);
1105 }
1106 r->addr = new_addr;
1107 if (r->addr != PCI_BAR_UNMAPPED) {
1108 memory_region_add_subregion_overlap(r->address_space,
1109 r->addr, r->memory, 1);
1110 }
1111 }
1112
1113 pci_update_vga(d);
1114 }
1115
1116 static inline int pci_irq_disabled(PCIDevice *d)
1117 {
1118 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1119 }
1120
1121 /* Called after interrupt disabled field update in config space,
1122 * assert/deassert interrupts if necessary.
1123 * Gets original interrupt disable bit value (before update). */
1124 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1125 {
1126 int i, disabled = pci_irq_disabled(d);
1127 if (disabled == was_irq_disabled)
1128 return;
1129 for (i = 0; i < PCI_NUM_PINS; ++i) {
1130 int state = pci_irq_state(d, i);
1131 pci_change_irq_level(d, i, disabled ? -state : state);
1132 }
1133 }
1134
1135 uint32_t pci_default_read_config(PCIDevice *d,
1136 uint32_t address, int len)
1137 {
1138 uint32_t val = 0;
1139
1140 memcpy(&val, d->config + address, len);
1141 return le32_to_cpu(val);
1142 }
1143
1144 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1145 {
1146 int i, was_irq_disabled = pci_irq_disabled(d);
1147
1148 for (i = 0; i < l; val >>= 8, ++i) {
1149 uint8_t wmask = d->wmask[addr + i];
1150 uint8_t w1cmask = d->w1cmask[addr + i];
1151 assert(!(wmask & w1cmask));
1152 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1153 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1154 }
1155 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1156 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1157 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1158 range_covers_byte(addr, l, PCI_COMMAND))
1159 pci_update_mappings(d);
1160
1161 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1162 pci_update_irq_disabled(d, was_irq_disabled);
1163 memory_region_set_enabled(&d->bus_master_enable_region,
1164 pci_get_word(d->config + PCI_COMMAND)
1165 & PCI_COMMAND_MASTER);
1166 }
1167
1168 msi_write_config(d, addr, val, l);
1169 msix_write_config(d, addr, val, l);
1170 }
1171
1172 /***********************************************************/
1173 /* generic PCI irq support */
1174
1175 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1176 static void pci_irq_handler(void *opaque, int irq_num, int level)
1177 {
1178 PCIDevice *pci_dev = opaque;
1179 int change;
1180
1181 change = level - pci_irq_state(pci_dev, irq_num);
1182 if (!change)
1183 return;
1184
1185 pci_set_irq_state(pci_dev, irq_num, level);
1186 pci_update_irq_status(pci_dev);
1187 if (pci_irq_disabled(pci_dev))
1188 return;
1189 pci_change_irq_level(pci_dev, irq_num, change);
1190 }
1191
1192 static inline int pci_intx(PCIDevice *pci_dev)
1193 {
1194 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1195 }
1196
1197 qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1198 {
1199 int intx = pci_intx(pci_dev);
1200
1201 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1202 }
1203
1204 void pci_set_irq(PCIDevice *pci_dev, int level)
1205 {
1206 int intx = pci_intx(pci_dev);
1207 pci_irq_handler(pci_dev, intx, level);
1208 }
1209
1210 /* Special hooks used by device assignment */
1211 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1212 {
1213 assert(pci_bus_is_root(bus));
1214 bus->route_intx_to_irq = route_intx_to_irq;
1215 }
1216
1217 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1218 {
1219 PCIBus *bus;
1220
1221 do {
1222 bus = dev->bus;
1223 pin = bus->map_irq(dev, pin);
1224 dev = bus->parent_dev;
1225 } while (dev);
1226
1227 if (!bus->route_intx_to_irq) {
1228 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1229 object_get_typename(OBJECT(bus->qbus.parent)));
1230 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1231 }
1232
1233 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1234 }
1235
1236 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1237 {
1238 return old->mode != new->mode || old->irq != new->irq;
1239 }
1240
1241 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1242 {
1243 PCIDevice *dev;
1244 PCIBus *sec;
1245 int i;
1246
1247 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1248 dev = bus->devices[i];
1249 if (dev && dev->intx_routing_notifier) {
1250 dev->intx_routing_notifier(dev);
1251 }
1252 }
1253
1254 QLIST_FOREACH(sec, &bus->child, sibling) {
1255 pci_bus_fire_intx_routing_notifier(sec);
1256 }
1257 }
1258
1259 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1260 PCIINTxRoutingNotifier notifier)
1261 {
1262 dev->intx_routing_notifier = notifier;
1263 }
1264
1265 /*
1266 * PCI-to-PCI bridge specification
1267 * 9.1: Interrupt routing. Table 9-1
1268 *
1269 * the PCI Express Base Specification, Revision 2.1
1270 * 2.2.8.1: INTx interrutp signaling - Rules
1271 * the Implementation Note
1272 * Table 2-20
1273 */
1274 /*
1275 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1276 * 0-origin unlike PCI interrupt pin register.
1277 */
1278 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1279 {
1280 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1281 }
1282
1283 /***********************************************************/
1284 /* monitor info on PCI */
1285
1286 typedef struct {
1287 uint16_t class;
1288 const char *desc;
1289 const char *fw_name;
1290 uint16_t fw_ign_bits;
1291 } pci_class_desc;
1292
1293 static const pci_class_desc pci_class_descriptions[] =
1294 {
1295 { 0x0001, "VGA controller", "display"},
1296 { 0x0100, "SCSI controller", "scsi"},
1297 { 0x0101, "IDE controller", "ide"},
1298 { 0x0102, "Floppy controller", "fdc"},
1299 { 0x0103, "IPI controller", "ipi"},
1300 { 0x0104, "RAID controller", "raid"},
1301 { 0x0106, "SATA controller"},
1302 { 0x0107, "SAS controller"},
1303 { 0x0180, "Storage controller"},
1304 { 0x0200, "Ethernet controller", "ethernet"},
1305 { 0x0201, "Token Ring controller", "token-ring"},
1306 { 0x0202, "FDDI controller", "fddi"},
1307 { 0x0203, "ATM controller", "atm"},
1308 { 0x0280, "Network controller"},
1309 { 0x0300, "VGA controller", "display", 0x00ff},
1310 { 0x0301, "XGA controller"},
1311 { 0x0302, "3D controller"},
1312 { 0x0380, "Display controller"},
1313 { 0x0400, "Video controller", "video"},
1314 { 0x0401, "Audio controller", "sound"},
1315 { 0x0402, "Phone"},
1316 { 0x0403, "Audio controller", "sound"},
1317 { 0x0480, "Multimedia controller"},
1318 { 0x0500, "RAM controller", "memory"},
1319 { 0x0501, "Flash controller", "flash"},
1320 { 0x0580, "Memory controller"},
1321 { 0x0600, "Host bridge", "host"},
1322 { 0x0601, "ISA bridge", "isa"},
1323 { 0x0602, "EISA bridge", "eisa"},
1324 { 0x0603, "MC bridge", "mca"},
1325 { 0x0604, "PCI bridge", "pci-bridge"},
1326 { 0x0605, "PCMCIA bridge", "pcmcia"},
1327 { 0x0606, "NUBUS bridge", "nubus"},
1328 { 0x0607, "CARDBUS bridge", "cardbus"},
1329 { 0x0608, "RACEWAY bridge"},
1330 { 0x0680, "Bridge"},
1331 { 0x0700, "Serial port", "serial"},
1332 { 0x0701, "Parallel port", "parallel"},
1333 { 0x0800, "Interrupt controller", "interrupt-controller"},
1334 { 0x0801, "DMA controller", "dma-controller"},
1335 { 0x0802, "Timer", "timer"},
1336 { 0x0803, "RTC", "rtc"},
1337 { 0x0900, "Keyboard", "keyboard"},
1338 { 0x0901, "Pen", "pen"},
1339 { 0x0902, "Mouse", "mouse"},
1340 { 0x0A00, "Dock station", "dock", 0x00ff},
1341 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1342 { 0x0c00, "Fireware contorller", "fireware"},
1343 { 0x0c01, "Access bus controller", "access-bus"},
1344 { 0x0c02, "SSA controller", "ssa"},
1345 { 0x0c03, "USB controller", "usb"},
1346 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1347 { 0x0c05, "SMBus"},
1348 { 0, NULL}
1349 };
1350
1351 static void pci_for_each_device_under_bus(PCIBus *bus,
1352 void (*fn)(PCIBus *b, PCIDevice *d,
1353 void *opaque),
1354 void *opaque)
1355 {
1356 PCIDevice *d;
1357 int devfn;
1358
1359 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1360 d = bus->devices[devfn];
1361 if (d) {
1362 fn(bus, d, opaque);
1363 }
1364 }
1365 }
1366
1367 void pci_for_each_device(PCIBus *bus, int bus_num,
1368 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1369 void *opaque)
1370 {
1371 bus = pci_find_bus_nr(bus, bus_num);
1372
1373 if (bus) {
1374 pci_for_each_device_under_bus(bus, fn, opaque);
1375 }
1376 }
1377
1378 static const pci_class_desc *get_class_desc(int class)
1379 {
1380 const pci_class_desc *desc;
1381
1382 desc = pci_class_descriptions;
1383 while (desc->desc && class != desc->class) {
1384 desc++;
1385 }
1386
1387 return desc;
1388 }
1389
1390 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1391
1392 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1393 {
1394 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1395 int i;
1396
1397 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1398 const PCIIORegion *r = &dev->io_regions[i];
1399 PciMemoryRegionList *region;
1400
1401 if (!r->size) {
1402 continue;
1403 }
1404
1405 region = g_malloc0(sizeof(*region));
1406 region->value = g_malloc0(sizeof(*region->value));
1407
1408 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1409 region->value->type = g_strdup("io");
1410 } else {
1411 region->value->type = g_strdup("memory");
1412 region->value->has_prefetch = true;
1413 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1414 region->value->has_mem_type_64 = true;
1415 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1416 }
1417
1418 region->value->bar = i;
1419 region->value->address = r->addr;
1420 region->value->size = r->size;
1421
1422 /* XXX: waiting for the qapi to support GSList */
1423 if (!cur_item) {
1424 head = cur_item = region;
1425 } else {
1426 cur_item->next = region;
1427 cur_item = region;
1428 }
1429 }
1430
1431 return head;
1432 }
1433
1434 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1435 int bus_num)
1436 {
1437 PciBridgeInfo *info;
1438
1439 info = g_malloc0(sizeof(*info));
1440
1441 info->bus.number = dev->config[PCI_PRIMARY_BUS];
1442 info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
1443 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
1444
1445 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1446 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1447 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1448
1449 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1450 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1451 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1452
1453 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1454 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1455 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1456
1457 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1458 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1459 if (child_bus) {
1460 info->has_devices = true;
1461 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1462 }
1463 }
1464
1465 return info;
1466 }
1467
1468 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1469 int bus_num)
1470 {
1471 const pci_class_desc *desc;
1472 PciDeviceInfo *info;
1473 uint8_t type;
1474 int class;
1475
1476 info = g_malloc0(sizeof(*info));
1477 info->bus = bus_num;
1478 info->slot = PCI_SLOT(dev->devfn);
1479 info->function = PCI_FUNC(dev->devfn);
1480
1481 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1482 info->class_info.q_class = class;
1483 desc = get_class_desc(class);
1484 if (desc->desc) {
1485 info->class_info.has_desc = true;
1486 info->class_info.desc = g_strdup(desc->desc);
1487 }
1488
1489 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1490 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
1491 info->regions = qmp_query_pci_regions(dev);
1492 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1493
1494 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1495 info->has_irq = true;
1496 info->irq = dev->config[PCI_INTERRUPT_LINE];
1497 }
1498
1499 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1500 if (type == PCI_HEADER_TYPE_BRIDGE) {
1501 info->has_pci_bridge = true;
1502 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1503 }
1504
1505 return info;
1506 }
1507
1508 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1509 {
1510 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1511 PCIDevice *dev;
1512 int devfn;
1513
1514 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1515 dev = bus->devices[devfn];
1516 if (dev) {
1517 info = g_malloc0(sizeof(*info));
1518 info->value = qmp_query_pci_device(dev, bus, bus_num);
1519
1520 /* XXX: waiting for the qapi to support GSList */
1521 if (!cur_item) {
1522 head = cur_item = info;
1523 } else {
1524 cur_item->next = info;
1525 cur_item = info;
1526 }
1527 }
1528 }
1529
1530 return head;
1531 }
1532
1533 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1534 {
1535 PciInfo *info = NULL;
1536
1537 bus = pci_find_bus_nr(bus, bus_num);
1538 if (bus) {
1539 info = g_malloc0(sizeof(*info));
1540 info->bus = bus_num;
1541 info->devices = qmp_query_pci_devices(bus, bus_num);
1542 }
1543
1544 return info;
1545 }
1546
1547 PciInfoList *qmp_query_pci(Error **errp)
1548 {
1549 PciInfoList *info, *head = NULL, *cur_item = NULL;
1550 PCIHostState *host_bridge;
1551
1552 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1553 info = g_malloc0(sizeof(*info));
1554 info->value = qmp_query_pci_bus(host_bridge->bus, 0);
1555
1556 /* XXX: waiting for the qapi to support GSList */
1557 if (!cur_item) {
1558 head = cur_item = info;
1559 } else {
1560 cur_item->next = info;
1561 cur_item = info;
1562 }
1563 }
1564
1565 return head;
1566 }
1567
1568 static const char * const pci_nic_models[] = {
1569 "ne2k_pci",
1570 "i82551",
1571 "i82557b",
1572 "i82559er",
1573 "rtl8139",
1574 "e1000",
1575 "pcnet",
1576 "virtio",
1577 NULL
1578 };
1579
1580 static const char * const pci_nic_names[] = {
1581 "ne2k_pci",
1582 "i82551",
1583 "i82557b",
1584 "i82559er",
1585 "rtl8139",
1586 "e1000",
1587 "pcnet",
1588 "virtio-net-pci",
1589 NULL
1590 };
1591
1592 /* Initialize a PCI NIC. */
1593 /* FIXME callers should check for failure, but don't */
1594 PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus,
1595 const char *default_model,
1596 const char *default_devaddr)
1597 {
1598 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1599 PCIBus *bus;
1600 int devfn;
1601 PCIDevice *pci_dev;
1602 DeviceState *dev;
1603 int i;
1604
1605 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1606 if (i < 0)
1607 return NULL;
1608
1609 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1610 if (!bus) {
1611 error_report("Invalid PCI device address %s for device %s",
1612 devaddr, pci_nic_names[i]);
1613 return NULL;
1614 }
1615
1616 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1617 dev = &pci_dev->qdev;
1618 qdev_set_nic_properties(dev, nd);
1619 if (qdev_init(dev) < 0)
1620 return NULL;
1621 return pci_dev;
1622 }
1623
1624 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1625 const char *default_model,
1626 const char *default_devaddr)
1627 {
1628 PCIDevice *res;
1629
1630 if (qemu_show_nic_models(nd->model, pci_nic_models))
1631 exit(0);
1632
1633 res = pci_nic_init(nd, rootbus, default_model, default_devaddr);
1634 if (!res)
1635 exit(1);
1636 return res;
1637 }
1638
1639 PCIDevice *pci_vga_init(PCIBus *bus)
1640 {
1641 switch (vga_interface_type) {
1642 case VGA_CIRRUS:
1643 return pci_create_simple(bus, -1, "cirrus-vga");
1644 case VGA_QXL:
1645 return pci_create_simple(bus, -1, "qxl-vga");
1646 case VGA_STD:
1647 return pci_create_simple(bus, -1, "VGA");
1648 case VGA_VMWARE:
1649 return pci_create_simple(bus, -1, "vmware-svga");
1650 case VGA_NONE:
1651 default: /* Other non-PCI types. Checking for unsupported types is already
1652 done in vl.c. */
1653 return NULL;
1654 }
1655 }
1656
1657 /* Whether a given bus number is in range of the secondary
1658 * bus of the given bridge device. */
1659 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1660 {
1661 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1662 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1663 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1664 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1665 }
1666
1667 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1668 {
1669 PCIBus *sec;
1670
1671 if (!bus) {
1672 return NULL;
1673 }
1674
1675 if (pci_bus_num(bus) == bus_num) {
1676 return bus;
1677 }
1678
1679 /* Consider all bus numbers in range for the host pci bridge. */
1680 if (!pci_bus_is_root(bus) &&
1681 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1682 return NULL;
1683 }
1684
1685 /* try child bus */
1686 for (; bus; bus = sec) {
1687 QLIST_FOREACH(sec, &bus->child, sibling) {
1688 assert(!pci_bus_is_root(sec));
1689 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1690 return sec;
1691 }
1692 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1693 break;
1694 }
1695 }
1696 }
1697
1698 return NULL;
1699 }
1700
1701 void pci_for_each_bus_depth_first(PCIBus *bus,
1702 void *(*begin)(PCIBus *bus, void *parent_state),
1703 void (*end)(PCIBus *bus, void *state),
1704 void *parent_state)
1705 {
1706 PCIBus *sec;
1707 void *state;
1708
1709 if (!bus) {
1710 return;
1711 }
1712
1713 if (begin) {
1714 state = begin(bus, parent_state);
1715 } else {
1716 state = parent_state;
1717 }
1718
1719 QLIST_FOREACH(sec, &bus->child, sibling) {
1720 pci_for_each_bus_depth_first(sec, begin, end, state);
1721 }
1722
1723 if (end) {
1724 end(bus, state);
1725 }
1726 }
1727
1728
1729 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1730 {
1731 bus = pci_find_bus_nr(bus, bus_num);
1732
1733 if (!bus)
1734 return NULL;
1735
1736 return bus->devices[devfn];
1737 }
1738
1739 static int pci_qdev_init(DeviceState *qdev)
1740 {
1741 PCIDevice *pci_dev = (PCIDevice *)qdev;
1742 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1743 PCIBus *bus;
1744 int rc;
1745 bool is_default_rom;
1746
1747 /* initialize cap_present for pci_is_express() and pci_config_size() */
1748 if (pc->is_express) {
1749 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1750 }
1751
1752 bus = PCI_BUS(qdev_get_parent_bus(qdev));
1753 pci_dev = do_pci_register_device(pci_dev, bus,
1754 object_get_typename(OBJECT(qdev)),
1755 pci_dev->devfn);
1756 if (pci_dev == NULL)
1757 return -1;
1758
1759 if (pc->init) {
1760 rc = pc->init(pci_dev);
1761 if (rc != 0) {
1762 do_pci_unregister_device(pci_dev);
1763 return rc;
1764 }
1765 }
1766
1767 /* rom loading */
1768 is_default_rom = false;
1769 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1770 pci_dev->romfile = g_strdup(pc->romfile);
1771 is_default_rom = true;
1772 }
1773 pci_add_option_rom(pci_dev, is_default_rom);
1774
1775 return 0;
1776 }
1777
1778 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1779 const char *name)
1780 {
1781 DeviceState *dev;
1782
1783 dev = qdev_create(&bus->qbus, name);
1784 qdev_prop_set_int32(dev, "addr", devfn);
1785 qdev_prop_set_bit(dev, "multifunction", multifunction);
1786 return PCI_DEVICE(dev);
1787 }
1788
1789 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1790 bool multifunction,
1791 const char *name)
1792 {
1793 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1794 qdev_init_nofail(&dev->qdev);
1795 return dev;
1796 }
1797
1798 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1799 {
1800 return pci_create_multifunction(bus, devfn, false, name);
1801 }
1802
1803 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1804 {
1805 return pci_create_simple_multifunction(bus, devfn, false, name);
1806 }
1807
1808 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
1809 {
1810 int offset = PCI_CONFIG_HEADER_SIZE;
1811 int i;
1812 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
1813 if (pdev->used[i])
1814 offset = i + 1;
1815 else if (i - offset + 1 == size)
1816 return offset;
1817 }
1818 return 0;
1819 }
1820
1821 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1822 uint8_t *prev_p)
1823 {
1824 uint8_t next, prev;
1825
1826 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1827 return 0;
1828
1829 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1830 prev = next + PCI_CAP_LIST_NEXT)
1831 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1832 break;
1833
1834 if (prev_p)
1835 *prev_p = prev;
1836 return next;
1837 }
1838
1839 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1840 {
1841 uint8_t next, prev, found = 0;
1842
1843 if (!(pdev->used[offset])) {
1844 return 0;
1845 }
1846
1847 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1848
1849 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1850 prev = next + PCI_CAP_LIST_NEXT) {
1851 if (next <= offset && next > found) {
1852 found = next;
1853 }
1854 }
1855 return found;
1856 }
1857
1858 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1859 This is needed for an option rom which is used for more than one device. */
1860 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1861 {
1862 uint16_t vendor_id;
1863 uint16_t device_id;
1864 uint16_t rom_vendor_id;
1865 uint16_t rom_device_id;
1866 uint16_t rom_magic;
1867 uint16_t pcir_offset;
1868 uint8_t checksum;
1869
1870 /* Words in rom data are little endian (like in PCI configuration),
1871 so they can be read / written with pci_get_word / pci_set_word. */
1872
1873 /* Only a valid rom will be patched. */
1874 rom_magic = pci_get_word(ptr);
1875 if (rom_magic != 0xaa55) {
1876 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1877 return;
1878 }
1879 pcir_offset = pci_get_word(ptr + 0x18);
1880 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1881 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1882 return;
1883 }
1884
1885 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1886 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1887 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1888 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1889
1890 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1891 vendor_id, device_id, rom_vendor_id, rom_device_id);
1892
1893 checksum = ptr[6];
1894
1895 if (vendor_id != rom_vendor_id) {
1896 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1897 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1898 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1899 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1900 ptr[6] = checksum;
1901 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1902 }
1903
1904 if (device_id != rom_device_id) {
1905 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1906 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1907 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1908 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1909 ptr[6] = checksum;
1910 pci_set_word(ptr + pcir_offset + 6, device_id);
1911 }
1912 }
1913
1914 /* Add an option rom for the device */
1915 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1916 {
1917 int size;
1918 char *path;
1919 void *ptr;
1920 char name[32];
1921 const VMStateDescription *vmsd;
1922
1923 if (!pdev->romfile)
1924 return 0;
1925 if (strlen(pdev->romfile) == 0)
1926 return 0;
1927
1928 if (!pdev->rom_bar) {
1929 /*
1930 * Load rom via fw_cfg instead of creating a rom bar,
1931 * for 0.11 compatibility.
1932 */
1933 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1934 if (class == 0x0300) {
1935 rom_add_vga(pdev->romfile);
1936 } else {
1937 rom_add_option(pdev->romfile, -1);
1938 }
1939 return 0;
1940 }
1941
1942 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1943 if (path == NULL) {
1944 path = g_strdup(pdev->romfile);
1945 }
1946
1947 size = get_image_size(path);
1948 if (size < 0) {
1949 error_report("%s: failed to find romfile \"%s\"",
1950 __func__, pdev->romfile);
1951 g_free(path);
1952 return -1;
1953 } else if (size == 0) {
1954 error_report("%s: ignoring empty romfile \"%s\"",
1955 __func__, pdev->romfile);
1956 g_free(path);
1957 return -1;
1958 }
1959 if (size & (size - 1)) {
1960 size = 1 << qemu_fls(size);
1961 }
1962
1963 vmsd = qdev_get_vmsd(DEVICE(pdev));
1964
1965 if (vmsd) {
1966 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
1967 } else {
1968 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
1969 }
1970 pdev->has_rom = true;
1971 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size);
1972 vmstate_register_ram(&pdev->rom, &pdev->qdev);
1973 ptr = memory_region_get_ram_ptr(&pdev->rom);
1974 load_image(path, ptr);
1975 g_free(path);
1976
1977 if (is_default_rom) {
1978 /* Only the default rom images will be patched (if needed). */
1979 pci_patch_ids(pdev, ptr, size);
1980 }
1981
1982 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1983
1984 return 0;
1985 }
1986
1987 static void pci_del_option_rom(PCIDevice *pdev)
1988 {
1989 if (!pdev->has_rom)
1990 return;
1991
1992 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
1993 memory_region_destroy(&pdev->rom);
1994 pdev->has_rom = false;
1995 }
1996
1997 /*
1998 * if !offset
1999 * Reserve space and add capability to the linked list in pci config space
2000 *
2001 * if offset = 0,
2002 * Find and reserve space and add capability to the linked list
2003 * in pci config space */
2004 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2005 uint8_t offset, uint8_t size)
2006 {
2007 uint8_t *config;
2008 int i, overlapping_cap;
2009
2010 if (!offset) {
2011 offset = pci_find_space(pdev, size);
2012 if (!offset) {
2013 return -ENOSPC;
2014 }
2015 } else {
2016 /* Verify that capabilities don't overlap. Note: device assignment
2017 * depends on this check to verify that the device is not broken.
2018 * Should never trigger for emulated devices, but it's helpful
2019 * for debugging these. */
2020 for (i = offset; i < offset + size; i++) {
2021 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2022 if (overlapping_cap) {
2023 fprintf(stderr, "ERROR: %s:%02x:%02x.%x "
2024 "Attempt to add PCI capability %x at offset "
2025 "%x overlaps existing capability %x at offset %x\n",
2026 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2027 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2028 cap_id, offset, overlapping_cap, i);
2029 return -EINVAL;
2030 }
2031 }
2032 }
2033
2034 config = pdev->config + offset;
2035 config[PCI_CAP_LIST_ID] = cap_id;
2036 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2037 pdev->config[PCI_CAPABILITY_LIST] = offset;
2038 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2039 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2040 /* Make capability read-only by default */
2041 memset(pdev->wmask + offset, 0, size);
2042 /* Check capability by default */
2043 memset(pdev->cmask + offset, 0xFF, size);
2044 return offset;
2045 }
2046
2047 /* Unlink capability from the pci config space. */
2048 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2049 {
2050 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2051 if (!offset)
2052 return;
2053 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2054 /* Make capability writable again */
2055 memset(pdev->wmask + offset, 0xff, size);
2056 memset(pdev->w1cmask + offset, 0, size);
2057 /* Clear cmask as device-specific registers can't be checked */
2058 memset(pdev->cmask + offset, 0, size);
2059 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2060
2061 if (!pdev->config[PCI_CAPABILITY_LIST])
2062 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2063 }
2064
2065 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2066 {
2067 return pci_find_capability_list(pdev, cap_id, NULL);
2068 }
2069
2070 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2071 {
2072 PCIDevice *d = (PCIDevice *)dev;
2073 const pci_class_desc *desc;
2074 char ctxt[64];
2075 PCIIORegion *r;
2076 int i, class;
2077
2078 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2079 desc = pci_class_descriptions;
2080 while (desc->desc && class != desc->class)
2081 desc++;
2082 if (desc->desc) {
2083 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2084 } else {
2085 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2086 }
2087
2088 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2089 "pci id %04x:%04x (sub %04x:%04x)\n",
2090 indent, "", ctxt, pci_bus_num(d->bus),
2091 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2092 pci_get_word(d->config + PCI_VENDOR_ID),
2093 pci_get_word(d->config + PCI_DEVICE_ID),
2094 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2095 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2096 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2097 r = &d->io_regions[i];
2098 if (!r->size)
2099 continue;
2100 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2101 " [0x%"FMT_PCIBUS"]\n",
2102 indent, "",
2103 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2104 r->addr, r->addr + r->size - 1);
2105 }
2106 }
2107
2108 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2109 {
2110 PCIDevice *d = (PCIDevice *)dev;
2111 const char *name = NULL;
2112 const pci_class_desc *desc = pci_class_descriptions;
2113 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2114
2115 while (desc->desc &&
2116 (class & ~desc->fw_ign_bits) !=
2117 (desc->class & ~desc->fw_ign_bits)) {
2118 desc++;
2119 }
2120
2121 if (desc->desc) {
2122 name = desc->fw_name;
2123 }
2124
2125 if (name) {
2126 pstrcpy(buf, len, name);
2127 } else {
2128 snprintf(buf, len, "pci%04x,%04x",
2129 pci_get_word(d->config + PCI_VENDOR_ID),
2130 pci_get_word(d->config + PCI_DEVICE_ID));
2131 }
2132
2133 return buf;
2134 }
2135
2136 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2137 {
2138 PCIDevice *d = (PCIDevice *)dev;
2139 char path[50], name[33];
2140 int off;
2141
2142 off = snprintf(path, sizeof(path), "%s@%x",
2143 pci_dev_fw_name(dev, name, sizeof name),
2144 PCI_SLOT(d->devfn));
2145 if (PCI_FUNC(d->devfn))
2146 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2147 return g_strdup(path);
2148 }
2149
2150 static char *pcibus_get_dev_path(DeviceState *dev)
2151 {
2152 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2153 PCIDevice *t;
2154 int slot_depth;
2155 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2156 * 00 is added here to make this format compatible with
2157 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2158 * Slot.Function list specifies the slot and function numbers for all
2159 * devices on the path from root to the specific device. */
2160 const char *root_bus_path;
2161 int root_bus_len;
2162 char slot[] = ":SS.F";
2163 int slot_len = sizeof slot - 1 /* For '\0' */;
2164 int path_len;
2165 char *path, *p;
2166 int s;
2167
2168 root_bus_path = pci_root_bus_path(d);
2169 root_bus_len = strlen(root_bus_path);
2170
2171 /* Calculate # of slots on path between device and root. */;
2172 slot_depth = 0;
2173 for (t = d; t; t = t->bus->parent_dev) {
2174 ++slot_depth;
2175 }
2176
2177 path_len = root_bus_len + slot_len * slot_depth;
2178
2179 /* Allocate memory, fill in the terminating null byte. */
2180 path = g_malloc(path_len + 1 /* For '\0' */);
2181 path[path_len] = '\0';
2182
2183 memcpy(path, root_bus_path, root_bus_len);
2184
2185 /* Fill in slot numbers. We walk up from device to root, so need to print
2186 * them in the reverse order, last to first. */
2187 p = path + path_len;
2188 for (t = d; t; t = t->bus->parent_dev) {
2189 p -= slot_len;
2190 s = snprintf(slot, sizeof slot, ":%02x.%x",
2191 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2192 assert(s == slot_len);
2193 memcpy(p, slot, slot_len);
2194 }
2195
2196 return path;
2197 }
2198
2199 static int pci_qdev_find_recursive(PCIBus *bus,
2200 const char *id, PCIDevice **pdev)
2201 {
2202 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2203 if (!qdev) {
2204 return -ENODEV;
2205 }
2206
2207 /* roughly check if given qdev is pci device */
2208 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2209 *pdev = PCI_DEVICE(qdev);
2210 return 0;
2211 }
2212 return -EINVAL;
2213 }
2214
2215 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2216 {
2217 PCIHostState *host_bridge;
2218 int rc = -ENODEV;
2219
2220 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2221 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2222 if (!tmp) {
2223 rc = 0;
2224 break;
2225 }
2226 if (tmp != -ENODEV) {
2227 rc = tmp;
2228 }
2229 }
2230
2231 return rc;
2232 }
2233
2234 MemoryRegion *pci_address_space(PCIDevice *dev)
2235 {
2236 return dev->bus->address_space_mem;
2237 }
2238
2239 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2240 {
2241 return dev->bus->address_space_io;
2242 }
2243
2244 static void pci_device_class_init(ObjectClass *klass, void *data)
2245 {
2246 DeviceClass *k = DEVICE_CLASS(klass);
2247 k->init = pci_qdev_init;
2248 k->exit = pci_unregister_device;
2249 k->bus_type = TYPE_PCI_BUS;
2250 k->props = pci_props;
2251 }
2252
2253 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2254 {
2255 PCIBus *bus = PCI_BUS(dev->bus);
2256
2257 if (bus->iommu_fn) {
2258 return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn);
2259 }
2260
2261 if (bus->parent_dev) {
2262 /** We are ignoring the bus master DMA bit of the bridge
2263 * as it would complicate things such as VFIO for no good reason */
2264 return pci_device_iommu_address_space(bus->parent_dev);
2265 }
2266
2267 return &address_space_memory;
2268 }
2269
2270 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2271 {
2272 bus->iommu_fn = fn;
2273 bus->iommu_opaque = opaque;
2274 }
2275
2276 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2277 {
2278 Range *range = opaque;
2279 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2280 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2281 int i;
2282
2283 if (!(cmd & PCI_COMMAND_MEMORY)) {
2284 return;
2285 }
2286
2287 if (pc->is_bridge) {
2288 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2289 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2290
2291 base = MAX(base, 0x1ULL << 32);
2292
2293 if (limit >= base) {
2294 Range pref_range;
2295 pref_range.begin = base;
2296 pref_range.end = limit + 1;
2297 range_extend(range, &pref_range);
2298 }
2299 }
2300 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2301 PCIIORegion *r = &dev->io_regions[i];
2302 Range region_range;
2303
2304 if (!r->size ||
2305 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2306 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2307 continue;
2308 }
2309 region_range.begin = pci_bar_address(dev, i, r->type, r->size);
2310 region_range.end = region_range.begin + r->size;
2311
2312 if (region_range.begin == PCI_BAR_UNMAPPED) {
2313 continue;
2314 }
2315
2316 region_range.begin = MAX(region_range.begin, 0x1ULL << 32);
2317
2318 if (region_range.end - 1 >= region_range.begin) {
2319 range_extend(range, &region_range);
2320 }
2321 }
2322 }
2323
2324 void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2325 {
2326 range->begin = range->end = 0;
2327 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2328 }
2329
2330 static const TypeInfo pci_device_type_info = {
2331 .name = TYPE_PCI_DEVICE,
2332 .parent = TYPE_DEVICE,
2333 .instance_size = sizeof(PCIDevice),
2334 .abstract = true,
2335 .class_size = sizeof(PCIDeviceClass),
2336 .class_init = pci_device_class_init,
2337 };
2338
2339 static void pci_register_types(void)
2340 {
2341 type_register_static(&pci_bus_info);
2342 type_register_static(&pcie_bus_info);
2343 type_register_static(&pci_device_type_info);
2344 }
2345
2346 type_init(pci_register_types)
QEmu