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hw/pci: removed irq field from PCIDevice
[qemu.git] / linux-user / main.c
blob01e3cd4cc1d503d05419102eda5ef6e8341b4aff
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "qemu/cache-utils.h"
32 #include "cpu.h"
33 #include "tcg.h"
34 #include "qemu/timer.h"
35 #include "qemu/envlist.h"
36 #include "elf.h"
37
38 char *exec_path;
39
40 int singlestep;
41 const char *filename;
42 const char *argv0;
43 int gdbstub_port;
44 envlist_t *envlist;
45 const char *cpu_model;
46 unsigned long mmap_min_addr;
47 #if defined(CONFIG_USE_GUEST_BASE)
48 unsigned long guest_base;
49 int have_guest_base;
50 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51 /*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
58 # ifdef TARGET_MIPS
59 /* MIPS only supports 31 bits of virtual address space for user space */
60 unsigned long reserved_va = 0x77000000;
61 # else
62 unsigned long reserved_va = 0xf7000000;
63 # endif
64 #else
65 unsigned long reserved_va;
66 #endif
67 #endif
68
69 static void usage(void);
70
71 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
72 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
73
74 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
77 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
78
79 void gemu_log(const char *fmt, ...)
80 {
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86 }
87
88 #if defined(TARGET_I386)
89 int cpu_get_pic_interrupt(CPUX86State *env)
90 {
91 return -1;
92 }
93 #endif
94
95 /***********************************************************/
96 /* Helper routines for implementing atomic operations. */
97
98 /* To implement exclusive operations we force all cpus to syncronise.
99 We don't require a full sync, only that no cpus are executing guest code.
100 The alternative is to map target atomic ops onto host equivalents,
101 which requires quite a lot of per host/target work. */
102 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
103 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
104 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
105 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
106 static int pending_cpus;
107
108 /* Make sure everything is in a consistent state for calling fork(). */
109 void fork_start(void)
110 {
111 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
112 pthread_mutex_lock(&exclusive_lock);
113 mmap_fork_start();
114 }
115
116 void fork_end(int child)
117 {
118 mmap_fork_end(child);
119 if (child) {
120 CPUState *cpu, *next_cpu;
121 /* Child processes created by fork() only have a single thread.
122 Discard information about the parent threads. */
123 CPU_FOREACH_SAFE(cpu, next_cpu) {
124 if (cpu != thread_cpu) {
125 QTAILQ_REMOVE(&cpus, thread_cpu, node);
126 }
127 }
128 pending_cpus = 0;
129 pthread_mutex_init(&exclusive_lock, NULL);
130 pthread_mutex_init(&cpu_list_mutex, NULL);
131 pthread_cond_init(&exclusive_cond, NULL);
132 pthread_cond_init(&exclusive_resume, NULL);
133 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
134 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
135 } else {
136 pthread_mutex_unlock(&exclusive_lock);
137 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
138 }
139 }
140
141 /* Wait for pending exclusive operations to complete. The exclusive lock
142 must be held. */
143 static inline void exclusive_idle(void)
144 {
145 while (pending_cpus) {
146 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
147 }
148 }
149
150 /* Start an exclusive operation.
151 Must only be called from outside cpu_arm_exec. */
152 static inline void start_exclusive(void)
153 {
154 CPUState *other_cpu;
155
156 pthread_mutex_lock(&exclusive_lock);
157 exclusive_idle();
158
159 pending_cpus = 1;
160 /* Make all other cpus stop executing. */
161 CPU_FOREACH(other_cpu) {
162 if (other_cpu->running) {
163 pending_cpus++;
164 cpu_exit(other_cpu);
165 }
166 }
167 if (pending_cpus > 1) {
168 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
169 }
170 }
171
172 /* Finish an exclusive operation. */
173 static inline void end_exclusive(void)
174 {
175 pending_cpus = 0;
176 pthread_cond_broadcast(&exclusive_resume);
177 pthread_mutex_unlock(&exclusive_lock);
178 }
179
180 /* Wait for exclusive ops to finish, and begin cpu execution. */
181 static inline void cpu_exec_start(CPUState *cpu)
182 {
183 pthread_mutex_lock(&exclusive_lock);
184 exclusive_idle();
185 cpu->running = true;
186 pthread_mutex_unlock(&exclusive_lock);
187 }
188
189 /* Mark cpu as not executing, and release pending exclusive ops. */
190 static inline void cpu_exec_end(CPUState *cpu)
191 {
192 pthread_mutex_lock(&exclusive_lock);
193 cpu->running = false;
194 if (pending_cpus > 1) {
195 pending_cpus--;
196 if (pending_cpus == 1) {
197 pthread_cond_signal(&exclusive_cond);
198 }
199 }
200 exclusive_idle();
201 pthread_mutex_unlock(&exclusive_lock);
202 }
203
204 void cpu_list_lock(void)
205 {
206 pthread_mutex_lock(&cpu_list_mutex);
207 }
208
209 void cpu_list_unlock(void)
210 {
211 pthread_mutex_unlock(&cpu_list_mutex);
212 }
213
214
215 #ifdef TARGET_I386
216 /***********************************************************/
217 /* CPUX86 core interface */
218
219 void cpu_smm_update(CPUX86State *env)
220 {
221 }
222
223 uint64_t cpu_get_tsc(CPUX86State *env)
224 {
225 return cpu_get_real_ticks();
226 }
227
228 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
229 int flags)
230 {
231 unsigned int e1, e2;
232 uint32_t *p;
233 e1 = (addr << 16) | (limit & 0xffff);
234 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
235 e2 |= flags;
236 p = ptr;
237 p[0] = tswap32(e1);
238 p[1] = tswap32(e2);
239 }
240
241 static uint64_t *idt_table;
242 #ifdef TARGET_X86_64
243 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
244 uint64_t addr, unsigned int sel)
245 {
246 uint32_t *p, e1, e2;
247 e1 = (addr & 0xffff) | (sel << 16);
248 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
249 p = ptr;
250 p[0] = tswap32(e1);
251 p[1] = tswap32(e2);
252 p[2] = tswap32(addr >> 32);
253 p[3] = 0;
254 }
255 /* only dpl matters as we do only user space emulation */
256 static void set_idt(int n, unsigned int dpl)
257 {
258 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
259 }
260 #else
261 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
262 uint32_t addr, unsigned int sel)
263 {
264 uint32_t *p, e1, e2;
265 e1 = (addr & 0xffff) | (sel << 16);
266 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
267 p = ptr;
268 p[0] = tswap32(e1);
269 p[1] = tswap32(e2);
270 }
271
272 /* only dpl matters as we do only user space emulation */
273 static void set_idt(int n, unsigned int dpl)
274 {
275 set_gate(idt_table + n, 0, dpl, 0, 0);
276 }
277 #endif
278
279 void cpu_loop(CPUX86State *env)
280 {
281 CPUState *cs = CPU(x86_env_get_cpu(env));
282 int trapnr;
283 abi_ulong pc;
284 target_siginfo_t info;
285
286 for(;;) {
287 trapnr = cpu_x86_exec(env);
288 switch(trapnr) {
289 case 0x80:
290 /* linux syscall from int $0x80 */
291 env->regs[R_EAX] = do_syscall(env,
292 env->regs[R_EAX],
293 env->regs[R_EBX],
294 env->regs[R_ECX],
295 env->regs[R_EDX],
296 env->regs[R_ESI],
297 env->regs[R_EDI],
298 env->regs[R_EBP],
299 0, 0);
300 break;
301 #ifndef TARGET_ABI32
302 case EXCP_SYSCALL:
303 /* linux syscall from syscall instruction */
304 env->regs[R_EAX] = do_syscall(env,
305 env->regs[R_EAX],
306 env->regs[R_EDI],
307 env->regs[R_ESI],
308 env->regs[R_EDX],
309 env->regs[10],
310 env->regs[8],
311 env->regs[9],
312 0, 0);
313 env->eip = env->exception_next_eip;
314 break;
315 #endif
316 case EXCP0B_NOSEG:
317 case EXCP0C_STACK:
318 info.si_signo = SIGBUS;
319 info.si_errno = 0;
320 info.si_code = TARGET_SI_KERNEL;
321 info._sifields._sigfault._addr = 0;
322 queue_signal(env, info.si_signo, &info);
323 break;
324 case EXCP0D_GPF:
325 /* XXX: potential problem if ABI32 */
326 #ifndef TARGET_X86_64
327 if (env->eflags & VM_MASK) {
328 handle_vm86_fault(env);
329 } else
330 #endif
331 {
332 info.si_signo = SIGSEGV;
333 info.si_errno = 0;
334 info.si_code = TARGET_SI_KERNEL;
335 info._sifields._sigfault._addr = 0;
336 queue_signal(env, info.si_signo, &info);
337 }
338 break;
339 case EXCP0E_PAGE:
340 info.si_signo = SIGSEGV;
341 info.si_errno = 0;
342 if (!(env->error_code & 1))
343 info.si_code = TARGET_SEGV_MAPERR;
344 else
345 info.si_code = TARGET_SEGV_ACCERR;
346 info._sifields._sigfault._addr = env->cr[2];
347 queue_signal(env, info.si_signo, &info);
348 break;
349 case EXCP00_DIVZ:
350 #ifndef TARGET_X86_64
351 if (env->eflags & VM_MASK) {
352 handle_vm86_trap(env, trapnr);
353 } else
354 #endif
355 {
356 /* division by zero */
357 info.si_signo = SIGFPE;
358 info.si_errno = 0;
359 info.si_code = TARGET_FPE_INTDIV;
360 info._sifields._sigfault._addr = env->eip;
361 queue_signal(env, info.si_signo, &info);
362 }
363 break;
364 case EXCP01_DB:
365 case EXCP03_INT3:
366 #ifndef TARGET_X86_64
367 if (env->eflags & VM_MASK) {
368 handle_vm86_trap(env, trapnr);
369 } else
370 #endif
371 {
372 info.si_signo = SIGTRAP;
373 info.si_errno = 0;
374 if (trapnr == EXCP01_DB) {
375 info.si_code = TARGET_TRAP_BRKPT;
376 info._sifields._sigfault._addr = env->eip;
377 } else {
378 info.si_code = TARGET_SI_KERNEL;
379 info._sifields._sigfault._addr = 0;
380 }
381 queue_signal(env, info.si_signo, &info);
382 }
383 break;
384 case EXCP04_INTO:
385 case EXCP05_BOUND:
386 #ifndef TARGET_X86_64
387 if (env->eflags & VM_MASK) {
388 handle_vm86_trap(env, trapnr);
389 } else
390 #endif
391 {
392 info.si_signo = SIGSEGV;
393 info.si_errno = 0;
394 info.si_code = TARGET_SI_KERNEL;
395 info._sifields._sigfault._addr = 0;
396 queue_signal(env, info.si_signo, &info);
397 }
398 break;
399 case EXCP06_ILLOP:
400 info.si_signo = SIGILL;
401 info.si_errno = 0;
402 info.si_code = TARGET_ILL_ILLOPN;
403 info._sifields._sigfault._addr = env->eip;
404 queue_signal(env, info.si_signo, &info);
405 break;
406 case EXCP_INTERRUPT:
407 /* just indicate that signals should be handled asap */
408 break;
409 case EXCP_DEBUG:
410 {
411 int sig;
412
413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
414 if (sig)
415 {
416 info.si_signo = sig;
417 info.si_errno = 0;
418 info.si_code = TARGET_TRAP_BRKPT;
419 queue_signal(env, info.si_signo, &info);
420 }
421 }
422 break;
423 default:
424 pc = env->segs[R_CS].base + env->eip;
425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
426 (long)pc, trapnr);
427 abort();
428 }
429 process_pending_signals(env);
430 }
431 }
432 #endif
433
434 #ifdef TARGET_ARM
435
436 #define get_user_code_u32(x, gaddr, doswap) \
437 ({ abi_long __r = get_user_u32((x), (gaddr)); \
438 if (!__r && (doswap)) { \
439 (x) = bswap32(x); \
440 } \
441 __r; \
442 })
443
444 #define get_user_code_u16(x, gaddr, doswap) \
445 ({ abi_long __r = get_user_u16((x), (gaddr)); \
446 if (!__r && (doswap)) { \
447 (x) = bswap16(x); \
448 } \
449 __r; \
450 })
451
452 #ifdef TARGET_ABI32
453 /* Commpage handling -- there is no commpage for AArch64 */
454
455 /*
456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
457 * Input:
458 * r0 = pointer to oldval
459 * r1 = pointer to newval
460 * r2 = pointer to target value
461 *
462 * Output:
463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
464 * C set if *ptr was changed, clear if no exchange happened
465 *
466 * Note segv's in kernel helpers are a bit tricky, we can set the
467 * data address sensibly but the PC address is just the entry point.
468 */
469 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
470 {
471 uint64_t oldval, newval, val;
472 uint32_t addr, cpsr;
473 target_siginfo_t info;
474
475 /* Based on the 32 bit code in do_kernel_trap */
476
477 /* XXX: This only works between threads, not between processes.
478 It's probably possible to implement this with native host
479 operations. However things like ldrex/strex are much harder so
480 there's not much point trying. */
481 start_exclusive();
482 cpsr = cpsr_read(env);
483 addr = env->regs[2];
484
485 if (get_user_u64(oldval, env->regs[0])) {
486 env->cp15.c6_data = env->regs[0];
487 goto segv;
488 };
489
490 if (get_user_u64(newval, env->regs[1])) {
491 env->cp15.c6_data = env->regs[1];
492 goto segv;
493 };
494
495 if (get_user_u64(val, addr)) {
496 env->cp15.c6_data = addr;
497 goto segv;
498 }
499
500 if (val == oldval) {
501 val = newval;
502
503 if (put_user_u64(val, addr)) {
504 env->cp15.c6_data = addr;
505 goto segv;
506 };
507
508 env->regs[0] = 0;
509 cpsr |= CPSR_C;
510 } else {
511 env->regs[0] = -1;
512 cpsr &= ~CPSR_C;
513 }
514 cpsr_write(env, cpsr, CPSR_C);
515 end_exclusive();
516 return;
517
518 segv:
519 end_exclusive();
520 /* We get the PC of the entry address - which is as good as anything,
521 on a real kernel what you get depends on which mode it uses. */
522 info.si_signo = SIGSEGV;
523 info.si_errno = 0;
524 /* XXX: check env->error_code */
525 info.si_code = TARGET_SEGV_MAPERR;
526 info._sifields._sigfault._addr = env->cp15.c6_data;
527 queue_signal(env, info.si_signo, &info);
528
529 end_exclusive();
530 }
531
532 /* Handle a jump to the kernel code page. */
533 static int
534 do_kernel_trap(CPUARMState *env)
535 {
536 uint32_t addr;
537 uint32_t cpsr;
538 uint32_t val;
539
540 switch (env->regs[15]) {
541 case 0xffff0fa0: /* __kernel_memory_barrier */
542 /* ??? No-op. Will need to do better for SMP. */
543 break;
544 case 0xffff0fc0: /* __kernel_cmpxchg */
545 /* XXX: This only works between threads, not between processes.
546 It's probably possible to implement this with native host
547 operations. However things like ldrex/strex are much harder so
548 there's not much point trying. */
549 start_exclusive();
550 cpsr = cpsr_read(env);
551 addr = env->regs[2];
552 /* FIXME: This should SEGV if the access fails. */
553 if (get_user_u32(val, addr))
554 val = ~env->regs[0];
555 if (val == env->regs[0]) {
556 val = env->regs[1];
557 /* FIXME: Check for segfaults. */
558 put_user_u32(val, addr);
559 env->regs[0] = 0;
560 cpsr |= CPSR_C;
561 } else {
562 env->regs[0] = -1;
563 cpsr &= ~CPSR_C;
564 }
565 cpsr_write(env, cpsr, CPSR_C);
566 end_exclusive();
567 break;
568 case 0xffff0fe0: /* __kernel_get_tls */
569 env->regs[0] = env->cp15.c13_tls2;
570 break;
571 case 0xffff0f60: /* __kernel_cmpxchg64 */
572 arm_kernel_cmpxchg64_helper(env);
573 break;
574
575 default:
576 return 1;
577 }
578 /* Jump back to the caller. */
579 addr = env->regs[14];
580 if (addr & 1) {
581 env->thumb = 1;
582 addr &= ~1;
583 }
584 env->regs[15] = addr;
585
586 return 0;
587 }
588 #endif
589
590 static int do_strex(CPUARMState *env)
591 {
592 uint32_t val;
593 int size;
594 int rc = 1;
595 int segv = 0;
596 uint32_t addr;
597 start_exclusive();
598 addr = env->exclusive_addr;
599 if (addr != env->exclusive_test) {
600 goto fail;
601 }
602 size = env->exclusive_info & 0xf;
603 switch (size) {
604 case 0:
605 segv = get_user_u8(val, addr);
606 break;
607 case 1:
608 segv = get_user_u16(val, addr);
609 break;
610 case 2:
611 case 3:
612 segv = get_user_u32(val, addr);
613 break;
614 default:
615 abort();
616 }
617 if (segv) {
618 env->cp15.c6_data = addr;
619 goto done;
620 }
621 if (val != env->exclusive_val) {
622 goto fail;
623 }
624 if (size == 3) {
625 segv = get_user_u32(val, addr + 4);
626 if (segv) {
627 env->cp15.c6_data = addr + 4;
628 goto done;
629 }
630 if (val != env->exclusive_high) {
631 goto fail;
632 }
633 }
634 val = env->regs[(env->exclusive_info >> 8) & 0xf];
635 switch (size) {
636 case 0:
637 segv = put_user_u8(val, addr);
638 break;
639 case 1:
640 segv = put_user_u16(val, addr);
641 break;
642 case 2:
643 case 3:
644 segv = put_user_u32(val, addr);
645 break;
646 }
647 if (segv) {
648 env->cp15.c6_data = addr;
649 goto done;
650 }
651 if (size == 3) {
652 val = env->regs[(env->exclusive_info >> 12) & 0xf];
653 segv = put_user_u32(val, addr + 4);
654 if (segv) {
655 env->cp15.c6_data = addr + 4;
656 goto done;
657 }
658 }
659 rc = 0;
660 fail:
661 env->regs[15] += 4;
662 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
663 done:
664 end_exclusive();
665 return segv;
666 }
667
668 #ifdef TARGET_ABI32
669 void cpu_loop(CPUARMState *env)
670 {
671 CPUState *cs = CPU(arm_env_get_cpu(env));
672 int trapnr;
673 unsigned int n, insn;
674 target_siginfo_t info;
675 uint32_t addr;
676
677 for(;;) {
678 cpu_exec_start(cs);
679 trapnr = cpu_arm_exec(env);
680 cpu_exec_end(cs);
681 switch(trapnr) {
682 case EXCP_UDEF:
683 {
684 TaskState *ts = env->opaque;
685 uint32_t opcode;
686 int rc;
687
688 /* we handle the FPU emulation here, as Linux */
689 /* we get the opcode */
690 /* FIXME - what to do if get_user() fails? */
691 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
692
693 rc = EmulateAll(opcode, &ts->fpa, env);
694 if (rc == 0) { /* illegal instruction */
695 info.si_signo = SIGILL;
696 info.si_errno = 0;
697 info.si_code = TARGET_ILL_ILLOPN;
698 info._sifields._sigfault._addr = env->regs[15];
699 queue_signal(env, info.si_signo, &info);
700 } else if (rc < 0) { /* FP exception */
701 int arm_fpe=0;
702
703 /* translate softfloat flags to FPSR flags */
704 if (-rc & float_flag_invalid)
705 arm_fpe |= BIT_IOC;
706 if (-rc & float_flag_divbyzero)
707 arm_fpe |= BIT_DZC;
708 if (-rc & float_flag_overflow)
709 arm_fpe |= BIT_OFC;
710 if (-rc & float_flag_underflow)
711 arm_fpe |= BIT_UFC;
712 if (-rc & float_flag_inexact)
713 arm_fpe |= BIT_IXC;
714
715 FPSR fpsr = ts->fpa.fpsr;
716 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
717
718 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
719 info.si_signo = SIGFPE;
720 info.si_errno = 0;
721
722 /* ordered by priority, least first */
723 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
724 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
725 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
726 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
727 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
728
729 info._sifields._sigfault._addr = env->regs[15];
730 queue_signal(env, info.si_signo, &info);
731 } else {
732 env->regs[15] += 4;
733 }
734
735 /* accumulate unenabled exceptions */
736 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
737 fpsr |= BIT_IXC;
738 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
739 fpsr |= BIT_UFC;
740 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
741 fpsr |= BIT_OFC;
742 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
743 fpsr |= BIT_DZC;
744 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
745 fpsr |= BIT_IOC;
746 ts->fpa.fpsr=fpsr;
747 } else { /* everything OK */
748 /* increment PC */
749 env->regs[15] += 4;
750 }
751 }
752 break;
753 case EXCP_SWI:
754 case EXCP_BKPT:
755 {
756 env->eabi = 1;
757 /* system call */
758 if (trapnr == EXCP_BKPT) {
759 if (env->thumb) {
760 /* FIXME - what to do if get_user() fails? */
761 get_user_code_u16(insn, env->regs[15], env->bswap_code);
762 n = insn & 0xff;
763 env->regs[15] += 2;
764 } else {
765 /* FIXME - what to do if get_user() fails? */
766 get_user_code_u32(insn, env->regs[15], env->bswap_code);
767 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
768 env->regs[15] += 4;
769 }
770 } else {
771 if (env->thumb) {
772 /* FIXME - what to do if get_user() fails? */
773 get_user_code_u16(insn, env->regs[15] - 2,
774 env->bswap_code);
775 n = insn & 0xff;
776 } else {
777 /* FIXME - what to do if get_user() fails? */
778 get_user_code_u32(insn, env->regs[15] - 4,
779 env->bswap_code);
780 n = insn & 0xffffff;
781 }
782 }
783
784 if (n == ARM_NR_cacheflush) {
785 /* nop */
786 } else if (n == ARM_NR_semihosting
787 || n == ARM_NR_thumb_semihosting) {
788 env->regs[0] = do_arm_semihosting (env);
789 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
790 /* linux syscall */
791 if (env->thumb || n == 0) {
792 n = env->regs[7];
793 } else {
794 n -= ARM_SYSCALL_BASE;
795 env->eabi = 0;
796 }
797 if ( n > ARM_NR_BASE) {
798 switch (n) {
799 case ARM_NR_cacheflush:
800 /* nop */
801 break;
802 case ARM_NR_set_tls:
803 cpu_set_tls(env, env->regs[0]);
804 env->regs[0] = 0;
805 break;
806 default:
807 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
808 n);
809 env->regs[0] = -TARGET_ENOSYS;
810 break;
811 }
812 } else {
813 env->regs[0] = do_syscall(env,
814 n,
815 env->regs[0],
816 env->regs[1],
817 env->regs[2],
818 env->regs[3],
819 env->regs[4],
820 env->regs[5],
821 0, 0);
822 }
823 } else {
824 goto error;
825 }
826 }
827 break;
828 case EXCP_INTERRUPT:
829 /* just indicate that signals should be handled asap */
830 break;
831 case EXCP_PREFETCH_ABORT:
832 addr = env->cp15.c6_insn;
833 goto do_segv;
834 case EXCP_DATA_ABORT:
835 addr = env->cp15.c6_data;
836 do_segv:
837 {
838 info.si_signo = SIGSEGV;
839 info.si_errno = 0;
840 /* XXX: check env->error_code */
841 info.si_code = TARGET_SEGV_MAPERR;
842 info._sifields._sigfault._addr = addr;
843 queue_signal(env, info.si_signo, &info);
844 }
845 break;
846 case EXCP_DEBUG:
847 {
848 int sig;
849
850 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
851 if (sig)
852 {
853 info.si_signo = sig;
854 info.si_errno = 0;
855 info.si_code = TARGET_TRAP_BRKPT;
856 queue_signal(env, info.si_signo, &info);
857 }
858 }
859 break;
860 case EXCP_KERNEL_TRAP:
861 if (do_kernel_trap(env))
862 goto error;
863 break;
864 case EXCP_STREX:
865 if (do_strex(env)) {
866 addr = env->cp15.c6_data;
867 goto do_segv;
868 }
869 break;
870 default:
871 error:
872 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
873 trapnr);
874 cpu_dump_state(cs, stderr, fprintf, 0);
875 abort();
876 }
877 process_pending_signals(env);
878 }
879 }
880
881 #else
882
883 /* AArch64 main loop */
884 void cpu_loop(CPUARMState *env)
885 {
886 CPUState *cs = CPU(arm_env_get_cpu(env));
887 int trapnr, sig;
888 target_siginfo_t info;
889 uint32_t addr;
890
891 for (;;) {
892 cpu_exec_start(cs);
893 trapnr = cpu_arm_exec(env);
894 cpu_exec_end(cs);
895
896 switch (trapnr) {
897 case EXCP_SWI:
898 env->xregs[0] = do_syscall(env,
899 env->xregs[8],
900 env->xregs[0],
901 env->xregs[1],
902 env->xregs[2],
903 env->xregs[3],
904 env->xregs[4],
905 env->xregs[5],
906 0, 0);
907 break;
908 case EXCP_INTERRUPT:
909 /* just indicate that signals should be handled asap */
910 break;
911 case EXCP_UDEF:
912 info.si_signo = SIGILL;
913 info.si_errno = 0;
914 info.si_code = TARGET_ILL_ILLOPN;
915 info._sifields._sigfault._addr = env->pc;
916 queue_signal(env, info.si_signo, &info);
917 break;
918 case EXCP_PREFETCH_ABORT:
919 addr = env->cp15.c6_insn;
920 goto do_segv;
921 case EXCP_DATA_ABORT:
922 addr = env->cp15.c6_data;
923 do_segv:
924 info.si_signo = SIGSEGV;
925 info.si_errno = 0;
926 /* XXX: check env->error_code */
927 info.si_code = TARGET_SEGV_MAPERR;
928 info._sifields._sigfault._addr = addr;
929 queue_signal(env, info.si_signo, &info);
930 break;
931 case EXCP_DEBUG:
932 case EXCP_BKPT:
933 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
934 if (sig) {
935 info.si_signo = sig;
936 info.si_errno = 0;
937 info.si_code = TARGET_TRAP_BRKPT;
938 queue_signal(env, info.si_signo, &info);
939 }
940 break;
941 case EXCP_STREX:
942 if (do_strex(env)) {
943 addr = env->cp15.c6_data;
944 goto do_segv;
945 }
946 break;
947 default:
948 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
949 trapnr);
950 cpu_dump_state(cs, stderr, fprintf, 0);
951 abort();
952 }
953 process_pending_signals(env);
954 }
955 }
956 #endif /* ndef TARGET_ABI32 */
957
958 #endif
959
960 #ifdef TARGET_UNICORE32
961
962 void cpu_loop(CPUUniCore32State *env)
963 {
964 CPUState *cs = CPU(uc32_env_get_cpu(env));
965 int trapnr;
966 unsigned int n, insn;
967 target_siginfo_t info;
968
969 for (;;) {
970 cpu_exec_start(cs);
971 trapnr = uc32_cpu_exec(env);
972 cpu_exec_end(cs);
973 switch (trapnr) {
974 case UC32_EXCP_PRIV:
975 {
976 /* system call */
977 get_user_u32(insn, env->regs[31] - 4);
978 n = insn & 0xffffff;
979
980 if (n >= UC32_SYSCALL_BASE) {
981 /* linux syscall */
982 n -= UC32_SYSCALL_BASE;
983 if (n == UC32_SYSCALL_NR_set_tls) {
984 cpu_set_tls(env, env->regs[0]);
985 env->regs[0] = 0;
986 } else {
987 env->regs[0] = do_syscall(env,
988 n,
989 env->regs[0],
990 env->regs[1],
991 env->regs[2],
992 env->regs[3],
993 env->regs[4],
994 env->regs[5],
995 0, 0);
996 }
997 } else {
998 goto error;
999 }
1000 }
1001 break;
1002 case UC32_EXCP_DTRAP:
1003 case UC32_EXCP_ITRAP:
1004 info.si_signo = SIGSEGV;
1005 info.si_errno = 0;
1006 /* XXX: check env->error_code */
1007 info.si_code = TARGET_SEGV_MAPERR;
1008 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1009 queue_signal(env, info.si_signo, &info);
1010 break;
1011 case EXCP_INTERRUPT:
1012 /* just indicate that signals should be handled asap */
1013 break;
1014 case EXCP_DEBUG:
1015 {
1016 int sig;
1017
1018 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1019 if (sig) {
1020 info.si_signo = sig;
1021 info.si_errno = 0;
1022 info.si_code = TARGET_TRAP_BRKPT;
1023 queue_signal(env, info.si_signo, &info);
1024 }
1025 }
1026 break;
1027 default:
1028 goto error;
1029 }
1030 process_pending_signals(env);
1031 }
1032
1033 error:
1034 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1035 cpu_dump_state(cs, stderr, fprintf, 0);
1036 abort();
1037 }
1038 #endif
1039
1040 #ifdef TARGET_SPARC
1041 #define SPARC64_STACK_BIAS 2047
1042
1043 //#define DEBUG_WIN
1044
1045 /* WARNING: dealing with register windows _is_ complicated. More info
1046 can be found at http://www.sics.se/~psm/sparcstack.html */
1047 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1048 {
1049 index = (index + cwp * 16) % (16 * env->nwindows);
1050 /* wrap handling : if cwp is on the last window, then we use the
1051 registers 'after' the end */
1052 if (index < 8 && env->cwp == env->nwindows - 1)
1053 index += 16 * env->nwindows;
1054 return index;
1055 }
1056
1057 /* save the register window 'cwp1' */
1058 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1059 {
1060 unsigned int i;
1061 abi_ulong sp_ptr;
1062
1063 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1064 #ifdef TARGET_SPARC64
1065 if (sp_ptr & 3)
1066 sp_ptr += SPARC64_STACK_BIAS;
1067 #endif
1068 #if defined(DEBUG_WIN)
1069 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1070 sp_ptr, cwp1);
1071 #endif
1072 for(i = 0; i < 16; i++) {
1073 /* FIXME - what to do if put_user() fails? */
1074 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1075 sp_ptr += sizeof(abi_ulong);
1076 }
1077 }
1078
1079 static void save_window(CPUSPARCState *env)
1080 {
1081 #ifndef TARGET_SPARC64
1082 unsigned int new_wim;
1083 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1084 ((1LL << env->nwindows) - 1);
1085 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1086 env->wim = new_wim;
1087 #else
1088 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1089 env->cansave++;
1090 env->canrestore--;
1091 #endif
1092 }
1093
1094 static void restore_window(CPUSPARCState *env)
1095 {
1096 #ifndef TARGET_SPARC64
1097 unsigned int new_wim;
1098 #endif
1099 unsigned int i, cwp1;
1100 abi_ulong sp_ptr;
1101
1102 #ifndef TARGET_SPARC64
1103 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1104 ((1LL << env->nwindows) - 1);
1105 #endif
1106
1107 /* restore the invalid window */
1108 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1109 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1110 #ifdef TARGET_SPARC64
1111 if (sp_ptr & 3)
1112 sp_ptr += SPARC64_STACK_BIAS;
1113 #endif
1114 #if defined(DEBUG_WIN)
1115 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1116 sp_ptr, cwp1);
1117 #endif
1118 for(i = 0; i < 16; i++) {
1119 /* FIXME - what to do if get_user() fails? */
1120 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1121 sp_ptr += sizeof(abi_ulong);
1122 }
1123 #ifdef TARGET_SPARC64
1124 env->canrestore++;
1125 if (env->cleanwin < env->nwindows - 1)
1126 env->cleanwin++;
1127 env->cansave--;
1128 #else
1129 env->wim = new_wim;
1130 #endif
1131 }
1132
1133 static void flush_windows(CPUSPARCState *env)
1134 {
1135 int offset, cwp1;
1136
1137 offset = 1;
1138 for(;;) {
1139 /* if restore would invoke restore_window(), then we can stop */
1140 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1141 #ifndef TARGET_SPARC64
1142 if (env->wim & (1 << cwp1))
1143 break;
1144 #else
1145 if (env->canrestore == 0)
1146 break;
1147 env->cansave++;
1148 env->canrestore--;
1149 #endif
1150 save_window_offset(env, cwp1);
1151 offset++;
1152 }
1153 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1154 #ifndef TARGET_SPARC64
1155 /* set wim so that restore will reload the registers */
1156 env->wim = 1 << cwp1;
1157 #endif
1158 #if defined(DEBUG_WIN)
1159 printf("flush_windows: nb=%d\n", offset - 1);
1160 #endif
1161 }
1162
1163 void cpu_loop (CPUSPARCState *env)
1164 {
1165 CPUState *cs = CPU(sparc_env_get_cpu(env));
1166 int trapnr;
1167 abi_long ret;
1168 target_siginfo_t info;
1169
1170 while (1) {
1171 trapnr = cpu_sparc_exec (env);
1172
1173 /* Compute PSR before exposing state. */
1174 if (env->cc_op != CC_OP_FLAGS) {
1175 cpu_get_psr(env);
1176 }
1177
1178 switch (trapnr) {
1179 #ifndef TARGET_SPARC64
1180 case 0x88:
1181 case 0x90:
1182 #else
1183 case 0x110:
1184 case 0x16d:
1185 #endif
1186 ret = do_syscall (env, env->gregs[1],
1187 env->regwptr[0], env->regwptr[1],
1188 env->regwptr[2], env->regwptr[3],
1189 env->regwptr[4], env->regwptr[5],
1190 0, 0);
1191 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1192 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1193 env->xcc |= PSR_CARRY;
1194 #else
1195 env->psr |= PSR_CARRY;
1196 #endif
1197 ret = -ret;
1198 } else {
1199 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1200 env->xcc &= ~PSR_CARRY;
1201 #else
1202 env->psr &= ~PSR_CARRY;
1203 #endif
1204 }
1205 env->regwptr[0] = ret;
1206 /* next instruction */
1207 env->pc = env->npc;
1208 env->npc = env->npc + 4;
1209 break;
1210 case 0x83: /* flush windows */
1211 #ifdef TARGET_ABI32
1212 case 0x103:
1213 #endif
1214 flush_windows(env);
1215 /* next instruction */
1216 env->pc = env->npc;
1217 env->npc = env->npc + 4;
1218 break;
1219 #ifndef TARGET_SPARC64
1220 case TT_WIN_OVF: /* window overflow */
1221 save_window(env);
1222 break;
1223 case TT_WIN_UNF: /* window underflow */
1224 restore_window(env);
1225 break;
1226 case TT_TFAULT:
1227 case TT_DFAULT:
1228 {
1229 info.si_signo = TARGET_SIGSEGV;
1230 info.si_errno = 0;
1231 /* XXX: check env->error_code */
1232 info.si_code = TARGET_SEGV_MAPERR;
1233 info._sifields._sigfault._addr = env->mmuregs[4];
1234 queue_signal(env, info.si_signo, &info);
1235 }
1236 break;
1237 #else
1238 case TT_SPILL: /* window overflow */
1239 save_window(env);
1240 break;
1241 case TT_FILL: /* window underflow */
1242 restore_window(env);
1243 break;
1244 case TT_TFAULT:
1245 case TT_DFAULT:
1246 {
1247 info.si_signo = TARGET_SIGSEGV;
1248 info.si_errno = 0;
1249 /* XXX: check env->error_code */
1250 info.si_code = TARGET_SEGV_MAPERR;
1251 if (trapnr == TT_DFAULT)
1252 info._sifields._sigfault._addr = env->dmmuregs[4];
1253 else
1254 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1255 queue_signal(env, info.si_signo, &info);
1256 }
1257 break;
1258 #ifndef TARGET_ABI32
1259 case 0x16e:
1260 flush_windows(env);
1261 sparc64_get_context(env);
1262 break;
1263 case 0x16f:
1264 flush_windows(env);
1265 sparc64_set_context(env);
1266 break;
1267 #endif
1268 #endif
1269 case EXCP_INTERRUPT:
1270 /* just indicate that signals should be handled asap */
1271 break;
1272 case TT_ILL_INSN:
1273 {
1274 info.si_signo = TARGET_SIGILL;
1275 info.si_errno = 0;
1276 info.si_code = TARGET_ILL_ILLOPC;
1277 info._sifields._sigfault._addr = env->pc;
1278 queue_signal(env, info.si_signo, &info);
1279 }
1280 break;
1281 case EXCP_DEBUG:
1282 {
1283 int sig;
1284
1285 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1286 if (sig)
1287 {
1288 info.si_signo = sig;
1289 info.si_errno = 0;
1290 info.si_code = TARGET_TRAP_BRKPT;
1291 queue_signal(env, info.si_signo, &info);
1292 }
1293 }
1294 break;
1295 default:
1296 printf ("Unhandled trap: 0x%x\n", trapnr);
1297 cpu_dump_state(cs, stderr, fprintf, 0);
1298 exit (1);
1299 }
1300 process_pending_signals (env);
1301 }
1302 }
1303
1304 #endif
1305
1306 #ifdef TARGET_PPC
1307 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1308 {
1309 /* TO FIX */
1310 return 0;
1311 }
1312
1313 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1314 {
1315 return cpu_ppc_get_tb(env);
1316 }
1317
1318 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1319 {
1320 return cpu_ppc_get_tb(env) >> 32;
1321 }
1322
1323 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1324 {
1325 return cpu_ppc_get_tb(env);
1326 }
1327
1328 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1329 {
1330 return cpu_ppc_get_tb(env) >> 32;
1331 }
1332
1333 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1334 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1335
1336 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1337 {
1338 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1339 }
1340
1341 /* XXX: to be fixed */
1342 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1343 {
1344 return -1;
1345 }
1346
1347 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1348 {
1349 return -1;
1350 }
1351
1352 #define EXCP_DUMP(env, fmt, ...) \
1353 do { \
1354 CPUState *cs = ENV_GET_CPU(env); \
1355 fprintf(stderr, fmt , ## __VA_ARGS__); \
1356 cpu_dump_state(cs, stderr, fprintf, 0); \
1357 qemu_log(fmt, ## __VA_ARGS__); \
1358 if (qemu_log_enabled()) { \
1359 log_cpu_state(cs, 0); \
1360 } \
1361 } while (0)
1362
1363 static int do_store_exclusive(CPUPPCState *env)
1364 {
1365 target_ulong addr;
1366 target_ulong page_addr;
1367 target_ulong val;
1368 int flags;
1369 int segv = 0;
1370
1371 addr = env->reserve_ea;
1372 page_addr = addr & TARGET_PAGE_MASK;
1373 start_exclusive();
1374 mmap_lock();
1375 flags = page_get_flags(page_addr);
1376 if ((flags & PAGE_READ) == 0) {
1377 segv = 1;
1378 } else {
1379 int reg = env->reserve_info & 0x1f;
1380 int size = (env->reserve_info >> 5) & 0xf;
1381 int stored = 0;
1382
1383 if (addr == env->reserve_addr) {
1384 switch (size) {
1385 case 1: segv = get_user_u8(val, addr); break;
1386 case 2: segv = get_user_u16(val, addr); break;
1387 case 4: segv = get_user_u32(val, addr); break;
1388 #if defined(TARGET_PPC64)
1389 case 8: segv = get_user_u64(val, addr); break;
1390 #endif
1391 default: abort();
1392 }
1393 if (!segv && val == env->reserve_val) {
1394 val = env->gpr[reg];
1395 switch (size) {
1396 case 1: segv = put_user_u8(val, addr); break;
1397 case 2: segv = put_user_u16(val, addr); break;
1398 case 4: segv = put_user_u32(val, addr); break;
1399 #if defined(TARGET_PPC64)
1400 case 8: segv = put_user_u64(val, addr); break;
1401 #endif
1402 default: abort();
1403 }
1404 if (!segv) {
1405 stored = 1;
1406 }
1407 }
1408 }
1409 env->crf[0] = (stored << 1) | xer_so;
1410 env->reserve_addr = (target_ulong)-1;
1411 }
1412 if (!segv) {
1413 env->nip += 4;
1414 }
1415 mmap_unlock();
1416 end_exclusive();
1417 return segv;
1418 }
1419
1420 void cpu_loop(CPUPPCState *env)
1421 {
1422 CPUState *cs = CPU(ppc_env_get_cpu(env));
1423 target_siginfo_t info;
1424 int trapnr;
1425 target_ulong ret;
1426
1427 for(;;) {
1428 cpu_exec_start(cs);
1429 trapnr = cpu_ppc_exec(env);
1430 cpu_exec_end(cs);
1431 switch(trapnr) {
1432 case POWERPC_EXCP_NONE:
1433 /* Just go on */
1434 break;
1435 case POWERPC_EXCP_CRITICAL: /* Critical input */
1436 cpu_abort(env, "Critical interrupt while in user mode. "
1437 "Aborting\n");
1438 break;
1439 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1440 cpu_abort(env, "Machine check exception while in user mode. "
1441 "Aborting\n");
1442 break;
1443 case POWERPC_EXCP_DSI: /* Data storage exception */
1444 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1445 env->spr[SPR_DAR]);
1446 /* XXX: check this. Seems bugged */
1447 switch (env->error_code & 0xFF000000) {
1448 case 0x40000000:
1449 info.si_signo = TARGET_SIGSEGV;
1450 info.si_errno = 0;
1451 info.si_code = TARGET_SEGV_MAPERR;
1452 break;
1453 case 0x04000000:
1454 info.si_signo = TARGET_SIGILL;
1455 info.si_errno = 0;
1456 info.si_code = TARGET_ILL_ILLADR;
1457 break;
1458 case 0x08000000:
1459 info.si_signo = TARGET_SIGSEGV;
1460 info.si_errno = 0;
1461 info.si_code = TARGET_SEGV_ACCERR;
1462 break;
1463 default:
1464 /* Let's send a regular segfault... */
1465 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1466 env->error_code);
1467 info.si_signo = TARGET_SIGSEGV;
1468 info.si_errno = 0;
1469 info.si_code = TARGET_SEGV_MAPERR;
1470 break;
1471 }
1472 info._sifields._sigfault._addr = env->nip;
1473 queue_signal(env, info.si_signo, &info);
1474 break;
1475 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1476 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1477 "\n", env->spr[SPR_SRR0]);
1478 /* XXX: check this */
1479 switch (env->error_code & 0xFF000000) {
1480 case 0x40000000:
1481 info.si_signo = TARGET_SIGSEGV;
1482 info.si_errno = 0;
1483 info.si_code = TARGET_SEGV_MAPERR;
1484 break;
1485 case 0x10000000:
1486 case 0x08000000:
1487 info.si_signo = TARGET_SIGSEGV;
1488 info.si_errno = 0;
1489 info.si_code = TARGET_SEGV_ACCERR;
1490 break;
1491 default:
1492 /* Let's send a regular segfault... */
1493 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1494 env->error_code);
1495 info.si_signo = TARGET_SIGSEGV;
1496 info.si_errno = 0;
1497 info.si_code = TARGET_SEGV_MAPERR;
1498 break;
1499 }
1500 info._sifields._sigfault._addr = env->nip - 4;
1501 queue_signal(env, info.si_signo, &info);
1502 break;
1503 case POWERPC_EXCP_EXTERNAL: /* External input */
1504 cpu_abort(env, "External interrupt while in user mode. "
1505 "Aborting\n");
1506 break;
1507 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1508 EXCP_DUMP(env, "Unaligned memory access\n");
1509 /* XXX: check this */
1510 info.si_signo = TARGET_SIGBUS;
1511 info.si_errno = 0;
1512 info.si_code = TARGET_BUS_ADRALN;
1513 info._sifields._sigfault._addr = env->nip - 4;
1514 queue_signal(env, info.si_signo, &info);
1515 break;
1516 case POWERPC_EXCP_PROGRAM: /* Program exception */
1517 /* XXX: check this */
1518 switch (env->error_code & ~0xF) {
1519 case POWERPC_EXCP_FP:
1520 EXCP_DUMP(env, "Floating point program exception\n");
1521 info.si_signo = TARGET_SIGFPE;
1522 info.si_errno = 0;
1523 switch (env->error_code & 0xF) {
1524 case POWERPC_EXCP_FP_OX:
1525 info.si_code = TARGET_FPE_FLTOVF;
1526 break;
1527 case POWERPC_EXCP_FP_UX:
1528 info.si_code = TARGET_FPE_FLTUND;
1529 break;
1530 case POWERPC_EXCP_FP_ZX:
1531 case POWERPC_EXCP_FP_VXZDZ:
1532 info.si_code = TARGET_FPE_FLTDIV;
1533 break;
1534 case POWERPC_EXCP_FP_XX:
1535 info.si_code = TARGET_FPE_FLTRES;
1536 break;
1537 case POWERPC_EXCP_FP_VXSOFT:
1538 info.si_code = TARGET_FPE_FLTINV;
1539 break;
1540 case POWERPC_EXCP_FP_VXSNAN:
1541 case POWERPC_EXCP_FP_VXISI:
1542 case POWERPC_EXCP_FP_VXIDI:
1543 case POWERPC_EXCP_FP_VXIMZ:
1544 case POWERPC_EXCP_FP_VXVC:
1545 case POWERPC_EXCP_FP_VXSQRT:
1546 case POWERPC_EXCP_FP_VXCVI:
1547 info.si_code = TARGET_FPE_FLTSUB;
1548 break;
1549 default:
1550 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1551 env->error_code);
1552 break;
1553 }
1554 break;
1555 case POWERPC_EXCP_INVAL:
1556 EXCP_DUMP(env, "Invalid instruction\n");
1557 info.si_signo = TARGET_SIGILL;
1558 info.si_errno = 0;
1559 switch (env->error_code & 0xF) {
1560 case POWERPC_EXCP_INVAL_INVAL:
1561 info.si_code = TARGET_ILL_ILLOPC;
1562 break;
1563 case POWERPC_EXCP_INVAL_LSWX:
1564 info.si_code = TARGET_ILL_ILLOPN;
1565 break;
1566 case POWERPC_EXCP_INVAL_SPR:
1567 info.si_code = TARGET_ILL_PRVREG;
1568 break;
1569 case POWERPC_EXCP_INVAL_FP:
1570 info.si_code = TARGET_ILL_COPROC;
1571 break;
1572 default:
1573 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1574 env->error_code & 0xF);
1575 info.si_code = TARGET_ILL_ILLADR;
1576 break;
1577 }
1578 break;
1579 case POWERPC_EXCP_PRIV:
1580 EXCP_DUMP(env, "Privilege violation\n");
1581 info.si_signo = TARGET_SIGILL;
1582 info.si_errno = 0;
1583 switch (env->error_code & 0xF) {
1584 case POWERPC_EXCP_PRIV_OPC:
1585 info.si_code = TARGET_ILL_PRVOPC;
1586 break;
1587 case POWERPC_EXCP_PRIV_REG:
1588 info.si_code = TARGET_ILL_PRVREG;
1589 break;
1590 default:
1591 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1592 env->error_code & 0xF);
1593 info.si_code = TARGET_ILL_PRVOPC;
1594 break;
1595 }
1596 break;
1597 case POWERPC_EXCP_TRAP:
1598 cpu_abort(env, "Tried to call a TRAP\n");
1599 break;
1600 default:
1601 /* Should not happen ! */
1602 cpu_abort(env, "Unknown program exception (%02x)\n",
1603 env->error_code);
1604 break;
1605 }
1606 info._sifields._sigfault._addr = env->nip - 4;
1607 queue_signal(env, info.si_signo, &info);
1608 break;
1609 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1610 EXCP_DUMP(env, "No floating point allowed\n");
1611 info.si_signo = TARGET_SIGILL;
1612 info.si_errno = 0;
1613 info.si_code = TARGET_ILL_COPROC;
1614 info._sifields._sigfault._addr = env->nip - 4;
1615 queue_signal(env, info.si_signo, &info);
1616 break;
1617 case POWERPC_EXCP_SYSCALL: /* System call exception */
1618 cpu_abort(env, "Syscall exception while in user mode. "
1619 "Aborting\n");
1620 break;
1621 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1622 EXCP_DUMP(env, "No APU instruction allowed\n");
1623 info.si_signo = TARGET_SIGILL;
1624 info.si_errno = 0;
1625 info.si_code = TARGET_ILL_COPROC;
1626 info._sifields._sigfault._addr = env->nip - 4;
1627 queue_signal(env, info.si_signo, &info);
1628 break;
1629 case POWERPC_EXCP_DECR: /* Decrementer exception */
1630 cpu_abort(env, "Decrementer interrupt while in user mode. "
1631 "Aborting\n");
1632 break;
1633 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1634 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1635 "Aborting\n");
1636 break;
1637 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1638 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1639 "Aborting\n");
1640 break;
1641 case POWERPC_EXCP_DTLB: /* Data TLB error */
1642 cpu_abort(env, "Data TLB exception while in user mode. "
1643 "Aborting\n");
1644 break;
1645 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1646 cpu_abort(env, "Instruction TLB exception while in user mode. "
1647 "Aborting\n");
1648 break;
1649 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1650 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1651 info.si_signo = TARGET_SIGILL;
1652 info.si_errno = 0;
1653 info.si_code = TARGET_ILL_COPROC;
1654 info._sifields._sigfault._addr = env->nip - 4;
1655 queue_signal(env, info.si_signo, &info);
1656 break;
1657 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1658 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1659 break;
1660 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1661 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1662 break;
1663 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1664 cpu_abort(env, "Performance monitor exception not handled\n");
1665 break;
1666 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1667 cpu_abort(env, "Doorbell interrupt while in user mode. "
1668 "Aborting\n");
1669 break;
1670 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1671 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1672 "Aborting\n");
1673 break;
1674 case POWERPC_EXCP_RESET: /* System reset exception */
1675 cpu_abort(env, "Reset interrupt while in user mode. "
1676 "Aborting\n");
1677 break;
1678 case POWERPC_EXCP_DSEG: /* Data segment exception */
1679 cpu_abort(env, "Data segment exception while in user mode. "
1680 "Aborting\n");
1681 break;
1682 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1683 cpu_abort(env, "Instruction segment exception "
1684 "while in user mode. Aborting\n");
1685 break;
1686 /* PowerPC 64 with hypervisor mode support */
1687 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1688 cpu_abort(env, "Hypervisor decrementer interrupt "
1689 "while in user mode. Aborting\n");
1690 break;
1691 case POWERPC_EXCP_TRACE: /* Trace exception */
1692 /* Nothing to do:
1693 * we use this exception to emulate step-by-step execution mode.
1694 */
1695 break;
1696 /* PowerPC 64 with hypervisor mode support */
1697 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1698 cpu_abort(env, "Hypervisor data storage exception "
1699 "while in user mode. Aborting\n");
1700 break;
1701 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1702 cpu_abort(env, "Hypervisor instruction storage exception "
1703 "while in user mode. Aborting\n");
1704 break;
1705 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1706 cpu_abort(env, "Hypervisor data segment exception "
1707 "while in user mode. Aborting\n");
1708 break;
1709 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1710 cpu_abort(env, "Hypervisor instruction segment exception "
1711 "while in user mode. Aborting\n");
1712 break;
1713 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1714 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1715 info.si_signo = TARGET_SIGILL;
1716 info.si_errno = 0;
1717 info.si_code = TARGET_ILL_COPROC;
1718 info._sifields._sigfault._addr = env->nip - 4;
1719 queue_signal(env, info.si_signo, &info);
1720 break;
1721 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1722 cpu_abort(env, "Programmable interval timer interrupt "
1723 "while in user mode. Aborting\n");
1724 break;
1725 case POWERPC_EXCP_IO: /* IO error exception */
1726 cpu_abort(env, "IO error exception while in user mode. "
1727 "Aborting\n");
1728 break;
1729 case POWERPC_EXCP_RUNM: /* Run mode exception */
1730 cpu_abort(env, "Run mode exception while in user mode. "
1731 "Aborting\n");
1732 break;
1733 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1734 cpu_abort(env, "Emulation trap exception not handled\n");
1735 break;
1736 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1737 cpu_abort(env, "Instruction fetch TLB exception "
1738 "while in user-mode. Aborting");
1739 break;
1740 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1741 cpu_abort(env, "Data load TLB exception while in user-mode. "
1742 "Aborting");
1743 break;
1744 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1745 cpu_abort(env, "Data store TLB exception while in user-mode. "
1746 "Aborting");
1747 break;
1748 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1749 cpu_abort(env, "Floating-point assist exception not handled\n");
1750 break;
1751 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1752 cpu_abort(env, "Instruction address breakpoint exception "
1753 "not handled\n");
1754 break;
1755 case POWERPC_EXCP_SMI: /* System management interrupt */
1756 cpu_abort(env, "System management interrupt while in user mode. "
1757 "Aborting\n");
1758 break;
1759 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1760 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1761 "Aborting\n");
1762 break;
1763 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1764 cpu_abort(env, "Performance monitor exception not handled\n");
1765 break;
1766 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1767 cpu_abort(env, "Vector assist exception not handled\n");
1768 break;
1769 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1770 cpu_abort(env, "Soft patch exception not handled\n");
1771 break;
1772 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1773 cpu_abort(env, "Maintenance exception while in user mode. "
1774 "Aborting\n");
1775 break;
1776 case POWERPC_EXCP_STOP: /* stop translation */
1777 /* We did invalidate the instruction cache. Go on */
1778 break;
1779 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1780 /* We just stopped because of a branch. Go on */
1781 break;
1782 case POWERPC_EXCP_SYSCALL_USER:
1783 /* system call in user-mode emulation */
1784 /* WARNING:
1785 * PPC ABI uses overflow flag in cr0 to signal an error
1786 * in syscalls.
1787 */
1788 env->crf[0] &= ~0x1;
1789 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1790 env->gpr[5], env->gpr[6], env->gpr[7],
1791 env->gpr[8], 0, 0);
1792 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1793 /* Returning from a successful sigreturn syscall.
1794 Avoid corrupting register state. */
1795 break;
1796 }
1797 if (ret > (target_ulong)(-515)) {
1798 env->crf[0] |= 0x1;
1799 ret = -ret;
1800 }
1801 env->gpr[3] = ret;
1802 break;
1803 case POWERPC_EXCP_STCX:
1804 if (do_store_exclusive(env)) {
1805 info.si_signo = TARGET_SIGSEGV;
1806 info.si_errno = 0;
1807 info.si_code = TARGET_SEGV_MAPERR;
1808 info._sifields._sigfault._addr = env->nip;
1809 queue_signal(env, info.si_signo, &info);
1810 }
1811 break;
1812 case EXCP_DEBUG:
1813 {
1814 int sig;
1815
1816 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1817 if (sig) {
1818 info.si_signo = sig;
1819 info.si_errno = 0;
1820 info.si_code = TARGET_TRAP_BRKPT;
1821 queue_signal(env, info.si_signo, &info);
1822 }
1823 }
1824 break;
1825 case EXCP_INTERRUPT:
1826 /* just indicate that signals should be handled asap */
1827 break;
1828 default:
1829 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1830 break;
1831 }
1832 process_pending_signals(env);
1833 }
1834 }
1835 #endif
1836
1837 #ifdef TARGET_MIPS
1838
1839 # ifdef TARGET_ABI_MIPSO32
1840 # define MIPS_SYS(name, args) args,
1841 static const uint8_t mips_syscall_args[] = {
1842 MIPS_SYS(sys_syscall , 8) /* 4000 */
1843 MIPS_SYS(sys_exit , 1)
1844 MIPS_SYS(sys_fork , 0)
1845 MIPS_SYS(sys_read , 3)
1846 MIPS_SYS(sys_write , 3)
1847 MIPS_SYS(sys_open , 3) /* 4005 */
1848 MIPS_SYS(sys_close , 1)
1849 MIPS_SYS(sys_waitpid , 3)
1850 MIPS_SYS(sys_creat , 2)
1851 MIPS_SYS(sys_link , 2)
1852 MIPS_SYS(sys_unlink , 1) /* 4010 */
1853 MIPS_SYS(sys_execve , 0)
1854 MIPS_SYS(sys_chdir , 1)
1855 MIPS_SYS(sys_time , 1)
1856 MIPS_SYS(sys_mknod , 3)
1857 MIPS_SYS(sys_chmod , 2) /* 4015 */
1858 MIPS_SYS(sys_lchown , 3)
1859 MIPS_SYS(sys_ni_syscall , 0)
1860 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1861 MIPS_SYS(sys_lseek , 3)
1862 MIPS_SYS(sys_getpid , 0) /* 4020 */
1863 MIPS_SYS(sys_mount , 5)
1864 MIPS_SYS(sys_oldumount , 1)
1865 MIPS_SYS(sys_setuid , 1)
1866 MIPS_SYS(sys_getuid , 0)
1867 MIPS_SYS(sys_stime , 1) /* 4025 */
1868 MIPS_SYS(sys_ptrace , 4)
1869 MIPS_SYS(sys_alarm , 1)
1870 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1871 MIPS_SYS(sys_pause , 0)
1872 MIPS_SYS(sys_utime , 2) /* 4030 */
1873 MIPS_SYS(sys_ni_syscall , 0)
1874 MIPS_SYS(sys_ni_syscall , 0)
1875 MIPS_SYS(sys_access , 2)
1876 MIPS_SYS(sys_nice , 1)
1877 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1878 MIPS_SYS(sys_sync , 0)
1879 MIPS_SYS(sys_kill , 2)
1880 MIPS_SYS(sys_rename , 2)
1881 MIPS_SYS(sys_mkdir , 2)
1882 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1883 MIPS_SYS(sys_dup , 1)
1884 MIPS_SYS(sys_pipe , 0)
1885 MIPS_SYS(sys_times , 1)
1886 MIPS_SYS(sys_ni_syscall , 0)
1887 MIPS_SYS(sys_brk , 1) /* 4045 */
1888 MIPS_SYS(sys_setgid , 1)
1889 MIPS_SYS(sys_getgid , 0)
1890 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1891 MIPS_SYS(sys_geteuid , 0)
1892 MIPS_SYS(sys_getegid , 0) /* 4050 */
1893 MIPS_SYS(sys_acct , 0)
1894 MIPS_SYS(sys_umount , 2)
1895 MIPS_SYS(sys_ni_syscall , 0)
1896 MIPS_SYS(sys_ioctl , 3)
1897 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1898 MIPS_SYS(sys_ni_syscall , 2)
1899 MIPS_SYS(sys_setpgid , 2)
1900 MIPS_SYS(sys_ni_syscall , 0)
1901 MIPS_SYS(sys_olduname , 1)
1902 MIPS_SYS(sys_umask , 1) /* 4060 */
1903 MIPS_SYS(sys_chroot , 1)
1904 MIPS_SYS(sys_ustat , 2)
1905 MIPS_SYS(sys_dup2 , 2)
1906 MIPS_SYS(sys_getppid , 0)
1907 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1908 MIPS_SYS(sys_setsid , 0)
1909 MIPS_SYS(sys_sigaction , 3)
1910 MIPS_SYS(sys_sgetmask , 0)
1911 MIPS_SYS(sys_ssetmask , 1)
1912 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1913 MIPS_SYS(sys_setregid , 2)
1914 MIPS_SYS(sys_sigsuspend , 0)
1915 MIPS_SYS(sys_sigpending , 1)
1916 MIPS_SYS(sys_sethostname , 2)
1917 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1918 MIPS_SYS(sys_getrlimit , 2)
1919 MIPS_SYS(sys_getrusage , 2)
1920 MIPS_SYS(sys_gettimeofday, 2)
1921 MIPS_SYS(sys_settimeofday, 2)
1922 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1923 MIPS_SYS(sys_setgroups , 2)
1924 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1925 MIPS_SYS(sys_symlink , 2)
1926 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1927 MIPS_SYS(sys_readlink , 3) /* 4085 */
1928 MIPS_SYS(sys_uselib , 1)
1929 MIPS_SYS(sys_swapon , 2)
1930 MIPS_SYS(sys_reboot , 3)
1931 MIPS_SYS(old_readdir , 3)
1932 MIPS_SYS(old_mmap , 6) /* 4090 */
1933 MIPS_SYS(sys_munmap , 2)
1934 MIPS_SYS(sys_truncate , 2)
1935 MIPS_SYS(sys_ftruncate , 2)
1936 MIPS_SYS(sys_fchmod , 2)
1937 MIPS_SYS(sys_fchown , 3) /* 4095 */
1938 MIPS_SYS(sys_getpriority , 2)
1939 MIPS_SYS(sys_setpriority , 3)
1940 MIPS_SYS(sys_ni_syscall , 0)
1941 MIPS_SYS(sys_statfs , 2)
1942 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1943 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1944 MIPS_SYS(sys_socketcall , 2)
1945 MIPS_SYS(sys_syslog , 3)
1946 MIPS_SYS(sys_setitimer , 3)
1947 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1948 MIPS_SYS(sys_newstat , 2)
1949 MIPS_SYS(sys_newlstat , 2)
1950 MIPS_SYS(sys_newfstat , 2)
1951 MIPS_SYS(sys_uname , 1)
1952 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1953 MIPS_SYS(sys_vhangup , 0)
1954 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1955 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1956 MIPS_SYS(sys_wait4 , 4)
1957 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1958 MIPS_SYS(sys_sysinfo , 1)
1959 MIPS_SYS(sys_ipc , 6)
1960 MIPS_SYS(sys_fsync , 1)
1961 MIPS_SYS(sys_sigreturn , 0)
1962 MIPS_SYS(sys_clone , 6) /* 4120 */
1963 MIPS_SYS(sys_setdomainname, 2)
1964 MIPS_SYS(sys_newuname , 1)
1965 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1966 MIPS_SYS(sys_adjtimex , 1)
1967 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1968 MIPS_SYS(sys_sigprocmask , 3)
1969 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1970 MIPS_SYS(sys_init_module , 5)
1971 MIPS_SYS(sys_delete_module, 1)
1972 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1973 MIPS_SYS(sys_quotactl , 0)
1974 MIPS_SYS(sys_getpgid , 1)
1975 MIPS_SYS(sys_fchdir , 1)
1976 MIPS_SYS(sys_bdflush , 2)
1977 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1978 MIPS_SYS(sys_personality , 1)
1979 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1980 MIPS_SYS(sys_setfsuid , 1)
1981 MIPS_SYS(sys_setfsgid , 1)
1982 MIPS_SYS(sys_llseek , 5) /* 4140 */
1983 MIPS_SYS(sys_getdents , 3)
1984 MIPS_SYS(sys_select , 5)
1985 MIPS_SYS(sys_flock , 2)
1986 MIPS_SYS(sys_msync , 3)
1987 MIPS_SYS(sys_readv , 3) /* 4145 */
1988 MIPS_SYS(sys_writev , 3)
1989 MIPS_SYS(sys_cacheflush , 3)
1990 MIPS_SYS(sys_cachectl , 3)
1991 MIPS_SYS(sys_sysmips , 4)
1992 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1993 MIPS_SYS(sys_getsid , 1)
1994 MIPS_SYS(sys_fdatasync , 0)
1995 MIPS_SYS(sys_sysctl , 1)
1996 MIPS_SYS(sys_mlock , 2)
1997 MIPS_SYS(sys_munlock , 2) /* 4155 */
1998 MIPS_SYS(sys_mlockall , 1)
1999 MIPS_SYS(sys_munlockall , 0)
2000 MIPS_SYS(sys_sched_setparam, 2)
2001 MIPS_SYS(sys_sched_getparam, 2)
2002 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2003 MIPS_SYS(sys_sched_getscheduler, 1)
2004 MIPS_SYS(sys_sched_yield , 0)
2005 MIPS_SYS(sys_sched_get_priority_max, 1)
2006 MIPS_SYS(sys_sched_get_priority_min, 1)
2007 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2008 MIPS_SYS(sys_nanosleep, 2)
2009 MIPS_SYS(sys_mremap , 5)
2010 MIPS_SYS(sys_accept , 3)
2011 MIPS_SYS(sys_bind , 3)
2012 MIPS_SYS(sys_connect , 3) /* 4170 */
2013 MIPS_SYS(sys_getpeername , 3)
2014 MIPS_SYS(sys_getsockname , 3)
2015 MIPS_SYS(sys_getsockopt , 5)
2016 MIPS_SYS(sys_listen , 2)
2017 MIPS_SYS(sys_recv , 4) /* 4175 */
2018 MIPS_SYS(sys_recvfrom , 6)
2019 MIPS_SYS(sys_recvmsg , 3)
2020 MIPS_SYS(sys_send , 4)
2021 MIPS_SYS(sys_sendmsg , 3)
2022 MIPS_SYS(sys_sendto , 6) /* 4180 */
2023 MIPS_SYS(sys_setsockopt , 5)
2024 MIPS_SYS(sys_shutdown , 2)
2025 MIPS_SYS(sys_socket , 3)
2026 MIPS_SYS(sys_socketpair , 4)
2027 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2028 MIPS_SYS(sys_getresuid , 3)
2029 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2030 MIPS_SYS(sys_poll , 3)
2031 MIPS_SYS(sys_nfsservctl , 3)
2032 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2033 MIPS_SYS(sys_getresgid , 3)
2034 MIPS_SYS(sys_prctl , 5)
2035 MIPS_SYS(sys_rt_sigreturn, 0)
2036 MIPS_SYS(sys_rt_sigaction, 4)
2037 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2038 MIPS_SYS(sys_rt_sigpending, 2)
2039 MIPS_SYS(sys_rt_sigtimedwait, 4)
2040 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2041 MIPS_SYS(sys_rt_sigsuspend, 0)
2042 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2043 MIPS_SYS(sys_pwrite64 , 6)
2044 MIPS_SYS(sys_chown , 3)
2045 MIPS_SYS(sys_getcwd , 2)
2046 MIPS_SYS(sys_capget , 2)
2047 MIPS_SYS(sys_capset , 2) /* 4205 */
2048 MIPS_SYS(sys_sigaltstack , 2)
2049 MIPS_SYS(sys_sendfile , 4)
2050 MIPS_SYS(sys_ni_syscall , 0)
2051 MIPS_SYS(sys_ni_syscall , 0)
2052 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2053 MIPS_SYS(sys_truncate64 , 4)
2054 MIPS_SYS(sys_ftruncate64 , 4)
2055 MIPS_SYS(sys_stat64 , 2)
2056 MIPS_SYS(sys_lstat64 , 2)
2057 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2058 MIPS_SYS(sys_pivot_root , 2)
2059 MIPS_SYS(sys_mincore , 3)
2060 MIPS_SYS(sys_madvise , 3)
2061 MIPS_SYS(sys_getdents64 , 3)
2062 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2063 MIPS_SYS(sys_ni_syscall , 0)
2064 MIPS_SYS(sys_gettid , 0)
2065 MIPS_SYS(sys_readahead , 5)
2066 MIPS_SYS(sys_setxattr , 5)
2067 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2068 MIPS_SYS(sys_fsetxattr , 5)
2069 MIPS_SYS(sys_getxattr , 4)
2070 MIPS_SYS(sys_lgetxattr , 4)
2071 MIPS_SYS(sys_fgetxattr , 4)
2072 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2073 MIPS_SYS(sys_llistxattr , 3)
2074 MIPS_SYS(sys_flistxattr , 3)
2075 MIPS_SYS(sys_removexattr , 2)
2076 MIPS_SYS(sys_lremovexattr, 2)
2077 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2078 MIPS_SYS(sys_tkill , 2)
2079 MIPS_SYS(sys_sendfile64 , 5)
2080 MIPS_SYS(sys_futex , 6)
2081 MIPS_SYS(sys_sched_setaffinity, 3)
2082 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2083 MIPS_SYS(sys_io_setup , 2)
2084 MIPS_SYS(sys_io_destroy , 1)
2085 MIPS_SYS(sys_io_getevents, 5)
2086 MIPS_SYS(sys_io_submit , 3)
2087 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2088 MIPS_SYS(sys_exit_group , 1)
2089 MIPS_SYS(sys_lookup_dcookie, 3)
2090 MIPS_SYS(sys_epoll_create, 1)
2091 MIPS_SYS(sys_epoll_ctl , 4)
2092 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2093 MIPS_SYS(sys_remap_file_pages, 5)
2094 MIPS_SYS(sys_set_tid_address, 1)
2095 MIPS_SYS(sys_restart_syscall, 0)
2096 MIPS_SYS(sys_fadvise64_64, 7)
2097 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2098 MIPS_SYS(sys_fstatfs64 , 2)
2099 MIPS_SYS(sys_timer_create, 3)
2100 MIPS_SYS(sys_timer_settime, 4)
2101 MIPS_SYS(sys_timer_gettime, 2)
2102 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2103 MIPS_SYS(sys_timer_delete, 1)
2104 MIPS_SYS(sys_clock_settime, 2)
2105 MIPS_SYS(sys_clock_gettime, 2)
2106 MIPS_SYS(sys_clock_getres, 2)
2107 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2108 MIPS_SYS(sys_tgkill , 3)
2109 MIPS_SYS(sys_utimes , 2)
2110 MIPS_SYS(sys_mbind , 4)
2111 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2112 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2113 MIPS_SYS(sys_mq_open , 4)
2114 MIPS_SYS(sys_mq_unlink , 1)
2115 MIPS_SYS(sys_mq_timedsend, 5)
2116 MIPS_SYS(sys_mq_timedreceive, 5)
2117 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2118 MIPS_SYS(sys_mq_getsetattr, 3)
2119 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2120 MIPS_SYS(sys_waitid , 4)
2121 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2122 MIPS_SYS(sys_add_key , 5)
2123 MIPS_SYS(sys_request_key, 4)
2124 MIPS_SYS(sys_keyctl , 5)
2125 MIPS_SYS(sys_set_thread_area, 1)
2126 MIPS_SYS(sys_inotify_init, 0)
2127 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2128 MIPS_SYS(sys_inotify_rm_watch, 2)
2129 MIPS_SYS(sys_migrate_pages, 4)
2130 MIPS_SYS(sys_openat, 4)
2131 MIPS_SYS(sys_mkdirat, 3)
2132 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2133 MIPS_SYS(sys_fchownat, 5)
2134 MIPS_SYS(sys_futimesat, 3)
2135 MIPS_SYS(sys_fstatat64, 4)
2136 MIPS_SYS(sys_unlinkat, 3)
2137 MIPS_SYS(sys_renameat, 4) /* 4295 */
2138 MIPS_SYS(sys_linkat, 5)
2139 MIPS_SYS(sys_symlinkat, 3)
2140 MIPS_SYS(sys_readlinkat, 4)
2141 MIPS_SYS(sys_fchmodat, 3)
2142 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2143 MIPS_SYS(sys_pselect6, 6)
2144 MIPS_SYS(sys_ppoll, 5)
2145 MIPS_SYS(sys_unshare, 1)
2146 MIPS_SYS(sys_splice, 6)
2147 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2148 MIPS_SYS(sys_tee, 4)
2149 MIPS_SYS(sys_vmsplice, 4)
2150 MIPS_SYS(sys_move_pages, 6)
2151 MIPS_SYS(sys_set_robust_list, 2)
2152 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2153 MIPS_SYS(sys_kexec_load, 4)
2154 MIPS_SYS(sys_getcpu, 3)
2155 MIPS_SYS(sys_epoll_pwait, 6)
2156 MIPS_SYS(sys_ioprio_set, 3)
2157 MIPS_SYS(sys_ioprio_get, 2)
2158 MIPS_SYS(sys_utimensat, 4)
2159 MIPS_SYS(sys_signalfd, 3)
2160 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2161 MIPS_SYS(sys_eventfd, 1)
2162 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2163 MIPS_SYS(sys_timerfd_create, 2)
2164 MIPS_SYS(sys_timerfd_gettime, 2)
2165 MIPS_SYS(sys_timerfd_settime, 4)
2166 MIPS_SYS(sys_signalfd4, 4)
2167 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2168 MIPS_SYS(sys_epoll_create1, 1)
2169 MIPS_SYS(sys_dup3, 3)
2170 MIPS_SYS(sys_pipe2, 2)
2171 MIPS_SYS(sys_inotify_init1, 1)
2172 MIPS_SYS(sys_preadv, 6) /* 4330 */
2173 MIPS_SYS(sys_pwritev, 6)
2174 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2175 MIPS_SYS(sys_perf_event_open, 5)
2176 MIPS_SYS(sys_accept4, 4)
2177 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2178 MIPS_SYS(sys_fanotify_init, 2)
2179 MIPS_SYS(sys_fanotify_mark, 6)
2180 MIPS_SYS(sys_prlimit64, 4)
2181 MIPS_SYS(sys_name_to_handle_at, 5)
2182 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2183 MIPS_SYS(sys_clock_adjtime, 2)
2184 MIPS_SYS(sys_syncfs, 1)
2185 };
2186 # undef MIPS_SYS
2187 # endif /* O32 */
2188
2189 static int do_store_exclusive(CPUMIPSState *env)
2190 {
2191 target_ulong addr;
2192 target_ulong page_addr;
2193 target_ulong val;
2194 int flags;
2195 int segv = 0;
2196 int reg;
2197 int d;
2198
2199 addr = env->lladdr;
2200 page_addr = addr & TARGET_PAGE_MASK;
2201 start_exclusive();
2202 mmap_lock();
2203 flags = page_get_flags(page_addr);
2204 if ((flags & PAGE_READ) == 0) {
2205 segv = 1;
2206 } else {
2207 reg = env->llreg & 0x1f;
2208 d = (env->llreg & 0x20) != 0;
2209 if (d) {
2210 segv = get_user_s64(val, addr);
2211 } else {
2212 segv = get_user_s32(val, addr);
2213 }
2214 if (!segv) {
2215 if (val != env->llval) {
2216 env->active_tc.gpr[reg] = 0;
2217 } else {
2218 if (d) {
2219 segv = put_user_u64(env->llnewval, addr);
2220 } else {
2221 segv = put_user_u32(env->llnewval, addr);
2222 }
2223 if (!segv) {
2224 env->active_tc.gpr[reg] = 1;
2225 }
2226 }
2227 }
2228 }
2229 env->lladdr = -1;
2230 if (!segv) {
2231 env->active_tc.PC += 4;
2232 }
2233 mmap_unlock();
2234 end_exclusive();
2235 return segv;
2236 }
2237
2238 /* Break codes */
2239 enum {
2240 BRK_OVERFLOW = 6,
2241 BRK_DIVZERO = 7
2242 };
2243
2244 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2245 unsigned int code)
2246 {
2247 int ret = -1;
2248
2249 switch (code) {
2250 case BRK_OVERFLOW:
2251 case BRK_DIVZERO:
2252 info->si_signo = TARGET_SIGFPE;
2253 info->si_errno = 0;
2254 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2255 queue_signal(env, info->si_signo, &*info);
2256 ret = 0;
2257 break;
2258 default:
2259 break;
2260 }
2261
2262 return ret;
2263 }
2264
2265 void cpu_loop(CPUMIPSState *env)
2266 {
2267 CPUState *cs = CPU(mips_env_get_cpu(env));
2268 target_siginfo_t info;
2269 int trapnr;
2270 abi_long ret;
2271 # ifdef TARGET_ABI_MIPSO32
2272 unsigned int syscall_num;
2273 # endif
2274
2275 for(;;) {
2276 cpu_exec_start(cs);
2277 trapnr = cpu_mips_exec(env);
2278 cpu_exec_end(cs);
2279 switch(trapnr) {
2280 case EXCP_SYSCALL:
2281 env->active_tc.PC += 4;
2282 # ifdef TARGET_ABI_MIPSO32
2283 syscall_num = env->active_tc.gpr[2] - 4000;
2284 if (syscall_num >= sizeof(mips_syscall_args)) {
2285 ret = -TARGET_ENOSYS;
2286 } else {
2287 int nb_args;
2288 abi_ulong sp_reg;
2289 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2290
2291 nb_args = mips_syscall_args[syscall_num];
2292 sp_reg = env->active_tc.gpr[29];
2293 switch (nb_args) {
2294 /* these arguments are taken from the stack */
2295 case 8:
2296 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2297 goto done_syscall;
2298 }
2299 case 7:
2300 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2301 goto done_syscall;
2302 }
2303 case 6:
2304 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2305 goto done_syscall;
2306 }
2307 case 5:
2308 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2309 goto done_syscall;
2310 }
2311 default:
2312 break;
2313 }
2314 ret = do_syscall(env, env->active_tc.gpr[2],
2315 env->active_tc.gpr[4],
2316 env->active_tc.gpr[5],
2317 env->active_tc.gpr[6],
2318 env->active_tc.gpr[7],
2319 arg5, arg6, arg7, arg8);
2320 }
2321 done_syscall:
2322 # else
2323 ret = do_syscall(env, env->active_tc.gpr[2],
2324 env->active_tc.gpr[4], env->active_tc.gpr[5],
2325 env->active_tc.gpr[6], env->active_tc.gpr[7],
2326 env->active_tc.gpr[8], env->active_tc.gpr[9],
2327 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2328 # endif /* O32 */
2329 if (ret == -TARGET_QEMU_ESIGRETURN) {
2330 /* Returning from a successful sigreturn syscall.
2331 Avoid clobbering register state. */
2332 break;
2333 }
2334 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2335 env->active_tc.gpr[7] = 1; /* error flag */
2336 ret = -ret;
2337 } else {
2338 env->active_tc.gpr[7] = 0; /* error flag */
2339 }
2340 env->active_tc.gpr[2] = ret;
2341 break;
2342 case EXCP_TLBL:
2343 case EXCP_TLBS:
2344 case EXCP_AdEL:
2345 case EXCP_AdES:
2346 info.si_signo = TARGET_SIGSEGV;
2347 info.si_errno = 0;
2348 /* XXX: check env->error_code */
2349 info.si_code = TARGET_SEGV_MAPERR;
2350 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2351 queue_signal(env, info.si_signo, &info);
2352 break;
2353 case EXCP_CpU:
2354 case EXCP_RI:
2355 info.si_signo = TARGET_SIGILL;
2356 info.si_errno = 0;
2357 info.si_code = 0;
2358 queue_signal(env, info.si_signo, &info);
2359 break;
2360 case EXCP_INTERRUPT:
2361 /* just indicate that signals should be handled asap */
2362 break;
2363 case EXCP_DEBUG:
2364 {
2365 int sig;
2366
2367 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2368 if (sig)
2369 {
2370 info.si_signo = sig;
2371 info.si_errno = 0;
2372 info.si_code = TARGET_TRAP_BRKPT;
2373 queue_signal(env, info.si_signo, &info);
2374 }
2375 }
2376 break;
2377 case EXCP_SC:
2378 if (do_store_exclusive(env)) {
2379 info.si_signo = TARGET_SIGSEGV;
2380 info.si_errno = 0;
2381 info.si_code = TARGET_SEGV_MAPERR;
2382 info._sifields._sigfault._addr = env->active_tc.PC;
2383 queue_signal(env, info.si_signo, &info);
2384 }
2385 break;
2386 case EXCP_DSPDIS:
2387 info.si_signo = TARGET_SIGILL;
2388 info.si_errno = 0;
2389 info.si_code = TARGET_ILL_ILLOPC;
2390 queue_signal(env, info.si_signo, &info);
2391 break;
2392 /* The code below was inspired by the MIPS Linux kernel trap
2393 * handling code in arch/mips/kernel/traps.c.
2394 */
2395 case EXCP_BREAK:
2396 {
2397 abi_ulong trap_instr;
2398 unsigned int code;
2399
2400 if (env->hflags & MIPS_HFLAG_M16) {
2401 if (env->insn_flags & ASE_MICROMIPS) {
2402 /* microMIPS mode */
2403 abi_ulong instr[2];
2404
2405 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2406 get_user_u16(instr[1], env->active_tc.PC + 2);
2407
2408 trap_instr = (instr[0] << 16) | instr[1];
2409 } else {
2410 /* MIPS16e mode */
2411 ret = get_user_u16(trap_instr, env->active_tc.PC);
2412 if (ret != 0) {
2413 goto error;
2414 }
2415 code = (trap_instr >> 6) & 0x3f;
2416 if (do_break(env, &info, code) != 0) {
2417 goto error;
2418 }
2419 break;
2420 }
2421 } else {
2422 ret = get_user_ual(trap_instr, env->active_tc.PC);
2423 }
2424
2425 if (ret != 0) {
2426 goto error;
2427 }
2428
2429 /* As described in the original Linux kernel code, the
2430 * below checks on 'code' are to work around an old
2431 * assembly bug.
2432 */
2433 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2434 if (code >= (1 << 10)) {
2435 code >>= 10;
2436 }
2437
2438 if (do_break(env, &info, code) != 0) {
2439 goto error;
2440 }
2441 }
2442 break;
2443 case EXCP_TRAP:
2444 {
2445 abi_ulong trap_instr;
2446 unsigned int code = 0;
2447
2448 if (env->hflags & MIPS_HFLAG_M16) {
2449 /* microMIPS mode */
2450 abi_ulong instr[2];
2451
2452 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2453 get_user_u16(instr[1], env->active_tc.PC + 2);
2454
2455 trap_instr = (instr[0] << 16) | instr[1];
2456 } else {
2457 ret = get_user_ual(trap_instr, env->active_tc.PC);
2458 }
2459
2460 if (ret != 0) {
2461 goto error;
2462 }
2463
2464 /* The immediate versions don't provide a code. */
2465 if (!(trap_instr & 0xFC000000)) {
2466 if (env->hflags & MIPS_HFLAG_M16) {
2467 /* microMIPS mode */
2468 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2469 } else {
2470 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2471 }
2472 }
2473
2474 if (do_break(env, &info, code) != 0) {
2475 goto error;
2476 }
2477 }
2478 break;
2479 default:
2480 error:
2481 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2482 trapnr);
2483 cpu_dump_state(cs, stderr, fprintf, 0);
2484 abort();
2485 }
2486 process_pending_signals(env);
2487 }
2488 }
2489 #endif
2490
2491 #ifdef TARGET_OPENRISC
2492
2493 void cpu_loop(CPUOpenRISCState *env)
2494 {
2495 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2496 int trapnr, gdbsig;
2497
2498 for (;;) {
2499 trapnr = cpu_exec(env);
2500 gdbsig = 0;
2501
2502 switch (trapnr) {
2503 case EXCP_RESET:
2504 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2505 exit(1);
2506 break;
2507 case EXCP_BUSERR:
2508 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2509 gdbsig = SIGBUS;
2510 break;
2511 case EXCP_DPF:
2512 case EXCP_IPF:
2513 cpu_dump_state(cs, stderr, fprintf, 0);
2514 gdbsig = TARGET_SIGSEGV;
2515 break;
2516 case EXCP_TICK:
2517 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2518 break;
2519 case EXCP_ALIGN:
2520 qemu_log("\nAlignment pc is %#x\n", env->pc);
2521 gdbsig = SIGBUS;
2522 break;
2523 case EXCP_ILLEGAL:
2524 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2525 gdbsig = SIGILL;
2526 break;
2527 case EXCP_INT:
2528 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2529 break;
2530 case EXCP_DTLBMISS:
2531 case EXCP_ITLBMISS:
2532 qemu_log("\nTLB miss\n");
2533 break;
2534 case EXCP_RANGE:
2535 qemu_log("\nRange\n");
2536 gdbsig = SIGSEGV;
2537 break;
2538 case EXCP_SYSCALL:
2539 env->pc += 4; /* 0xc00; */
2540 env->gpr[11] = do_syscall(env,
2541 env->gpr[11], /* return value */
2542 env->gpr[3], /* r3 - r7 are params */
2543 env->gpr[4],
2544 env->gpr[5],
2545 env->gpr[6],
2546 env->gpr[7],
2547 env->gpr[8], 0, 0);
2548 break;
2549 case EXCP_FPE:
2550 qemu_log("\nFloating point error\n");
2551 break;
2552 case EXCP_TRAP:
2553 qemu_log("\nTrap\n");
2554 gdbsig = SIGTRAP;
2555 break;
2556 case EXCP_NR:
2557 qemu_log("\nNR\n");
2558 break;
2559 default:
2560 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2561 trapnr);
2562 cpu_dump_state(cs, stderr, fprintf, 0);
2563 gdbsig = TARGET_SIGILL;
2564 break;
2565 }
2566 if (gdbsig) {
2567 gdb_handlesig(cs, gdbsig);
2568 if (gdbsig != TARGET_SIGTRAP) {
2569 exit(1);
2570 }
2571 }
2572
2573 process_pending_signals(env);
2574 }
2575 }
2576
2577 #endif /* TARGET_OPENRISC */
2578
2579 #ifdef TARGET_SH4
2580 void cpu_loop(CPUSH4State *env)
2581 {
2582 CPUState *cs = CPU(sh_env_get_cpu(env));
2583 int trapnr, ret;
2584 target_siginfo_t info;
2585
2586 while (1) {
2587 trapnr = cpu_sh4_exec (env);
2588
2589 switch (trapnr) {
2590 case 0x160:
2591 env->pc += 2;
2592 ret = do_syscall(env,
2593 env->gregs[3],
2594 env->gregs[4],
2595 env->gregs[5],
2596 env->gregs[6],
2597 env->gregs[7],
2598 env->gregs[0],
2599 env->gregs[1],
2600 0, 0);
2601 env->gregs[0] = ret;
2602 break;
2603 case EXCP_INTERRUPT:
2604 /* just indicate that signals should be handled asap */
2605 break;
2606 case EXCP_DEBUG:
2607 {
2608 int sig;
2609
2610 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2611 if (sig)
2612 {
2613 info.si_signo = sig;
2614 info.si_errno = 0;
2615 info.si_code = TARGET_TRAP_BRKPT;
2616 queue_signal(env, info.si_signo, &info);
2617 }
2618 }
2619 break;
2620 case 0xa0:
2621 case 0xc0:
2622 info.si_signo = SIGSEGV;
2623 info.si_errno = 0;
2624 info.si_code = TARGET_SEGV_MAPERR;
2625 info._sifields._sigfault._addr = env->tea;
2626 queue_signal(env, info.si_signo, &info);
2627 break;
2628
2629 default:
2630 printf ("Unhandled trap: 0x%x\n", trapnr);
2631 cpu_dump_state(cs, stderr, fprintf, 0);
2632 exit (1);
2633 }
2634 process_pending_signals (env);
2635 }
2636 }
2637 #endif
2638
2639 #ifdef TARGET_CRIS
2640 void cpu_loop(CPUCRISState *env)
2641 {
2642 CPUState *cs = CPU(cris_env_get_cpu(env));
2643 int trapnr, ret;
2644 target_siginfo_t info;
2645
2646 while (1) {
2647 trapnr = cpu_cris_exec (env);
2648 switch (trapnr) {
2649 case 0xaa:
2650 {
2651 info.si_signo = SIGSEGV;
2652 info.si_errno = 0;
2653 /* XXX: check env->error_code */
2654 info.si_code = TARGET_SEGV_MAPERR;
2655 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2656 queue_signal(env, info.si_signo, &info);
2657 }
2658 break;
2659 case EXCP_INTERRUPT:
2660 /* just indicate that signals should be handled asap */
2661 break;
2662 case EXCP_BREAK:
2663 ret = do_syscall(env,
2664 env->regs[9],
2665 env->regs[10],
2666 env->regs[11],
2667 env->regs[12],
2668 env->regs[13],
2669 env->pregs[7],
2670 env->pregs[11],
2671 0, 0);
2672 env->regs[10] = ret;
2673 break;
2674 case EXCP_DEBUG:
2675 {
2676 int sig;
2677
2678 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2679 if (sig)
2680 {
2681 info.si_signo = sig;
2682 info.si_errno = 0;
2683 info.si_code = TARGET_TRAP_BRKPT;
2684 queue_signal(env, info.si_signo, &info);
2685 }
2686 }
2687 break;
2688 default:
2689 printf ("Unhandled trap: 0x%x\n", trapnr);
2690 cpu_dump_state(cs, stderr, fprintf, 0);
2691 exit (1);
2692 }
2693 process_pending_signals (env);
2694 }
2695 }
2696 #endif
2697
2698 #ifdef TARGET_MICROBLAZE
2699 void cpu_loop(CPUMBState *env)
2700 {
2701 CPUState *cs = CPU(mb_env_get_cpu(env));
2702 int trapnr, ret;
2703 target_siginfo_t info;
2704
2705 while (1) {
2706 trapnr = cpu_mb_exec (env);
2707 switch (trapnr) {
2708 case 0xaa:
2709 {
2710 info.si_signo = SIGSEGV;
2711 info.si_errno = 0;
2712 /* XXX: check env->error_code */
2713 info.si_code = TARGET_SEGV_MAPERR;
2714 info._sifields._sigfault._addr = 0;
2715 queue_signal(env, info.si_signo, &info);
2716 }
2717 break;
2718 case EXCP_INTERRUPT:
2719 /* just indicate that signals should be handled asap */
2720 break;
2721 case EXCP_BREAK:
2722 /* Return address is 4 bytes after the call. */
2723 env->regs[14] += 4;
2724 env->sregs[SR_PC] = env->regs[14];
2725 ret = do_syscall(env,
2726 env->regs[12],
2727 env->regs[5],
2728 env->regs[6],
2729 env->regs[7],
2730 env->regs[8],
2731 env->regs[9],
2732 env->regs[10],
2733 0, 0);
2734 env->regs[3] = ret;
2735 break;
2736 case EXCP_HW_EXCP:
2737 env->regs[17] = env->sregs[SR_PC] + 4;
2738 if (env->iflags & D_FLAG) {
2739 env->sregs[SR_ESR] |= 1 << 12;
2740 env->sregs[SR_PC] -= 4;
2741 /* FIXME: if branch was immed, replay the imm as well. */
2742 }
2743
2744 env->iflags &= ~(IMM_FLAG | D_FLAG);
2745
2746 switch (env->sregs[SR_ESR] & 31) {
2747 case ESR_EC_DIVZERO:
2748 info.si_signo = SIGFPE;
2749 info.si_errno = 0;
2750 info.si_code = TARGET_FPE_FLTDIV;
2751 info._sifields._sigfault._addr = 0;
2752 queue_signal(env, info.si_signo, &info);
2753 break;
2754 case ESR_EC_FPU:
2755 info.si_signo = SIGFPE;
2756 info.si_errno = 0;
2757 if (env->sregs[SR_FSR] & FSR_IO) {
2758 info.si_code = TARGET_FPE_FLTINV;
2759 }
2760 if (env->sregs[SR_FSR] & FSR_DZ) {
2761 info.si_code = TARGET_FPE_FLTDIV;
2762 }
2763 info._sifields._sigfault._addr = 0;
2764 queue_signal(env, info.si_signo, &info);
2765 break;
2766 default:
2767 printf ("Unhandled hw-exception: 0x%x\n",
2768 env->sregs[SR_ESR] & ESR_EC_MASK);
2769 cpu_dump_state(cs, stderr, fprintf, 0);
2770 exit (1);
2771 break;
2772 }
2773 break;
2774 case EXCP_DEBUG:
2775 {
2776 int sig;
2777
2778 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2779 if (sig)
2780 {
2781 info.si_signo = sig;
2782 info.si_errno = 0;
2783 info.si_code = TARGET_TRAP_BRKPT;
2784 queue_signal(env, info.si_signo, &info);
2785 }
2786 }
2787 break;
2788 default:
2789 printf ("Unhandled trap: 0x%x\n", trapnr);
2790 cpu_dump_state(cs, stderr, fprintf, 0);
2791 exit (1);
2792 }
2793 process_pending_signals (env);
2794 }
2795 }
2796 #endif
2797
2798 #ifdef TARGET_M68K
2799
2800 void cpu_loop(CPUM68KState *env)
2801 {
2802 CPUState *cs = CPU(m68k_env_get_cpu(env));
2803 int trapnr;
2804 unsigned int n;
2805 target_siginfo_t info;
2806 TaskState *ts = env->opaque;
2807
2808 for(;;) {
2809 trapnr = cpu_m68k_exec(env);
2810 switch(trapnr) {
2811 case EXCP_ILLEGAL:
2812 {
2813 if (ts->sim_syscalls) {
2814 uint16_t nr;
2815 nr = lduw(env->pc + 2);
2816 env->pc += 4;
2817 do_m68k_simcall(env, nr);
2818 } else {
2819 goto do_sigill;
2820 }
2821 }
2822 break;
2823 case EXCP_HALT_INSN:
2824 /* Semihosing syscall. */
2825 env->pc += 4;
2826 do_m68k_semihosting(env, env->dregs[0]);
2827 break;
2828 case EXCP_LINEA:
2829 case EXCP_LINEF:
2830 case EXCP_UNSUPPORTED:
2831 do_sigill:
2832 info.si_signo = SIGILL;
2833 info.si_errno = 0;
2834 info.si_code = TARGET_ILL_ILLOPN;
2835 info._sifields._sigfault._addr = env->pc;
2836 queue_signal(env, info.si_signo, &info);
2837 break;
2838 case EXCP_TRAP0:
2839 {
2840 ts->sim_syscalls = 0;
2841 n = env->dregs[0];
2842 env->pc += 2;
2843 env->dregs[0] = do_syscall(env,
2844 n,
2845 env->dregs[1],
2846 env->dregs[2],
2847 env->dregs[3],
2848 env->dregs[4],
2849 env->dregs[5],
2850 env->aregs[0],
2851 0, 0);
2852 }
2853 break;
2854 case EXCP_INTERRUPT:
2855 /* just indicate that signals should be handled asap */
2856 break;
2857 case EXCP_ACCESS:
2858 {
2859 info.si_signo = SIGSEGV;
2860 info.si_errno = 0;
2861 /* XXX: check env->error_code */
2862 info.si_code = TARGET_SEGV_MAPERR;
2863 info._sifields._sigfault._addr = env->mmu.ar;
2864 queue_signal(env, info.si_signo, &info);
2865 }
2866 break;
2867 case EXCP_DEBUG:
2868 {
2869 int sig;
2870
2871 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2872 if (sig)
2873 {
2874 info.si_signo = sig;
2875 info.si_errno = 0;
2876 info.si_code = TARGET_TRAP_BRKPT;
2877 queue_signal(env, info.si_signo, &info);
2878 }
2879 }
2880 break;
2881 default:
2882 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2883 trapnr);
2884 cpu_dump_state(cs, stderr, fprintf, 0);
2885 abort();
2886 }
2887 process_pending_signals(env);
2888 }
2889 }
2890 #endif /* TARGET_M68K */
2891
2892 #ifdef TARGET_ALPHA
2893 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2894 {
2895 target_ulong addr, val, tmp;
2896 target_siginfo_t info;
2897 int ret = 0;
2898
2899 addr = env->lock_addr;
2900 tmp = env->lock_st_addr;
2901 env->lock_addr = -1;
2902 env->lock_st_addr = 0;
2903
2904 start_exclusive();
2905 mmap_lock();
2906
2907 if (addr == tmp) {
2908 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2909 goto do_sigsegv;
2910 }
2911
2912 if (val == env->lock_value) {
2913 tmp = env->ir[reg];
2914 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2915 goto do_sigsegv;
2916 }
2917 ret = 1;
2918 }
2919 }
2920 env->ir[reg] = ret;
2921 env->pc += 4;
2922
2923 mmap_unlock();
2924 end_exclusive();
2925 return;
2926
2927 do_sigsegv:
2928 mmap_unlock();
2929 end_exclusive();
2930
2931 info.si_signo = TARGET_SIGSEGV;
2932 info.si_errno = 0;
2933 info.si_code = TARGET_SEGV_MAPERR;
2934 info._sifields._sigfault._addr = addr;
2935 queue_signal(env, TARGET_SIGSEGV, &info);
2936 }
2937
2938 void cpu_loop(CPUAlphaState *env)
2939 {
2940 CPUState *cs = CPU(alpha_env_get_cpu(env));
2941 int trapnr;
2942 target_siginfo_t info;
2943 abi_long sysret;
2944
2945 while (1) {
2946 trapnr = cpu_alpha_exec (env);
2947
2948 /* All of the traps imply a transition through PALcode, which
2949 implies an REI instruction has been executed. Which means
2950 that the intr_flag should be cleared. */
2951 env->intr_flag = 0;
2952
2953 switch (trapnr) {
2954 case EXCP_RESET:
2955 fprintf(stderr, "Reset requested. Exit\n");
2956 exit(1);
2957 break;
2958 case EXCP_MCHK:
2959 fprintf(stderr, "Machine check exception. Exit\n");
2960 exit(1);
2961 break;
2962 case EXCP_SMP_INTERRUPT:
2963 case EXCP_CLK_INTERRUPT:
2964 case EXCP_DEV_INTERRUPT:
2965 fprintf(stderr, "External interrupt. Exit\n");
2966 exit(1);
2967 break;
2968 case EXCP_MMFAULT:
2969 env->lock_addr = -1;
2970 info.si_signo = TARGET_SIGSEGV;
2971 info.si_errno = 0;
2972 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
2973 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
2974 info._sifields._sigfault._addr = env->trap_arg0;
2975 queue_signal(env, info.si_signo, &info);
2976 break;
2977 case EXCP_UNALIGN:
2978 env->lock_addr = -1;
2979 info.si_signo = TARGET_SIGBUS;
2980 info.si_errno = 0;
2981 info.si_code = TARGET_BUS_ADRALN;
2982 info._sifields._sigfault._addr = env->trap_arg0;
2983 queue_signal(env, info.si_signo, &info);
2984 break;
2985 case EXCP_OPCDEC:
2986 do_sigill:
2987 env->lock_addr = -1;
2988 info.si_signo = TARGET_SIGILL;
2989 info.si_errno = 0;
2990 info.si_code = TARGET_ILL_ILLOPC;
2991 info._sifields._sigfault._addr = env->pc;
2992 queue_signal(env, info.si_signo, &info);
2993 break;
2994 case EXCP_ARITH:
2995 env->lock_addr = -1;
2996 info.si_signo = TARGET_SIGFPE;
2997 info.si_errno = 0;
2998 info.si_code = TARGET_FPE_FLTINV;
2999 info._sifields._sigfault._addr = env->pc;
3000 queue_signal(env, info.si_signo, &info);
3001 break;
3002 case EXCP_FEN:
3003 /* No-op. Linux simply re-enables the FPU. */
3004 break;
3005 case EXCP_CALL_PAL:
3006 env->lock_addr = -1;
3007 switch (env->error_code) {
3008 case 0x80:
3009 /* BPT */
3010 info.si_signo = TARGET_SIGTRAP;
3011 info.si_errno = 0;
3012 info.si_code = TARGET_TRAP_BRKPT;
3013 info._sifields._sigfault._addr = env->pc;
3014 queue_signal(env, info.si_signo, &info);
3015 break;
3016 case 0x81:
3017 /* BUGCHK */
3018 info.si_signo = TARGET_SIGTRAP;
3019 info.si_errno = 0;
3020 info.si_code = 0;
3021 info._sifields._sigfault._addr = env->pc;
3022 queue_signal(env, info.si_signo, &info);
3023 break;
3024 case 0x83:
3025 /* CALLSYS */
3026 trapnr = env->ir[IR_V0];
3027 sysret = do_syscall(env, trapnr,
3028 env->ir[IR_A0], env->ir[IR_A1],
3029 env->ir[IR_A2], env->ir[IR_A3],
3030 env->ir[IR_A4], env->ir[IR_A5],
3031 0, 0);
3032 if (trapnr == TARGET_NR_sigreturn
3033 || trapnr == TARGET_NR_rt_sigreturn) {
3034 break;
3035 }
3036 /* Syscall writes 0 to V0 to bypass error check, similar
3037 to how this is handled internal to Linux kernel.
3038 (Ab)use trapnr temporarily as boolean indicating error. */
3039 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3040 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3041 env->ir[IR_A3] = trapnr;
3042 break;
3043 case 0x86:
3044 /* IMB */
3045 /* ??? We can probably elide the code using page_unprotect
3046 that is checking for self-modifying code. Instead we
3047 could simply call tb_flush here. Until we work out the
3048 changes required to turn off the extra write protection,
3049 this can be a no-op. */
3050 break;
3051 case 0x9E:
3052 /* RDUNIQUE */
3053 /* Handled in the translator for usermode. */
3054 abort();
3055 case 0x9F:
3056 /* WRUNIQUE */
3057 /* Handled in the translator for usermode. */
3058 abort();
3059 case 0xAA:
3060 /* GENTRAP */
3061 info.si_signo = TARGET_SIGFPE;
3062 switch (env->ir[IR_A0]) {
3063 case TARGET_GEN_INTOVF:
3064 info.si_code = TARGET_FPE_INTOVF;
3065 break;
3066 case TARGET_GEN_INTDIV:
3067 info.si_code = TARGET_FPE_INTDIV;
3068 break;
3069 case TARGET_GEN_FLTOVF:
3070 info.si_code = TARGET_FPE_FLTOVF;
3071 break;
3072 case TARGET_GEN_FLTUND:
3073 info.si_code = TARGET_FPE_FLTUND;
3074 break;
3075 case TARGET_GEN_FLTINV:
3076 info.si_code = TARGET_FPE_FLTINV;
3077 break;
3078 case TARGET_GEN_FLTINE:
3079 info.si_code = TARGET_FPE_FLTRES;
3080 break;
3081 case TARGET_GEN_ROPRAND:
3082 info.si_code = 0;
3083 break;
3084 default:
3085 info.si_signo = TARGET_SIGTRAP;
3086 info.si_code = 0;
3087 break;
3088 }
3089 info.si_errno = 0;
3090 info._sifields._sigfault._addr = env->pc;
3091 queue_signal(env, info.si_signo, &info);
3092 break;
3093 default:
3094 goto do_sigill;
3095 }
3096 break;
3097 case EXCP_DEBUG:
3098 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3099 if (info.si_signo) {
3100 env->lock_addr = -1;
3101 info.si_errno = 0;
3102 info.si_code = TARGET_TRAP_BRKPT;
3103 queue_signal(env, info.si_signo, &info);
3104 }
3105 break;
3106 case EXCP_STL_C:
3107 case EXCP_STQ_C:
3108 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3109 break;
3110 case EXCP_INTERRUPT:
3111 /* Just indicate that signals should be handled asap. */
3112 break;
3113 default:
3114 printf ("Unhandled trap: 0x%x\n", trapnr);
3115 cpu_dump_state(cs, stderr, fprintf, 0);
3116 exit (1);
3117 }
3118 process_pending_signals (env);
3119 }
3120 }
3121 #endif /* TARGET_ALPHA */
3122
3123 #ifdef TARGET_S390X
3124 void cpu_loop(CPUS390XState *env)
3125 {
3126 CPUState *cs = CPU(s390_env_get_cpu(env));
3127 int trapnr, n, sig;
3128 target_siginfo_t info;
3129 target_ulong addr;
3130
3131 while (1) {
3132 trapnr = cpu_s390x_exec(env);
3133 switch (trapnr) {
3134 case EXCP_INTERRUPT:
3135 /* Just indicate that signals should be handled asap. */
3136 break;
3137
3138 case EXCP_SVC:
3139 n = env->int_svc_code;
3140 if (!n) {
3141 /* syscalls > 255 */
3142 n = env->regs[1];
3143 }
3144 env->psw.addr += env->int_svc_ilen;
3145 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3146 env->regs[4], env->regs[5],
3147 env->regs[6], env->regs[7], 0, 0);
3148 break;
3149
3150 case EXCP_DEBUG:
3151 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3152 if (sig) {
3153 n = TARGET_TRAP_BRKPT;
3154 goto do_signal_pc;
3155 }
3156 break;
3157 case EXCP_PGM:
3158 n = env->int_pgm_code;
3159 switch (n) {
3160 case PGM_OPERATION:
3161 case PGM_PRIVILEGED:
3162 sig = SIGILL;
3163 n = TARGET_ILL_ILLOPC;
3164 goto do_signal_pc;
3165 case PGM_PROTECTION:
3166 case PGM_ADDRESSING:
3167 sig = SIGSEGV;
3168 /* XXX: check env->error_code */
3169 n = TARGET_SEGV_MAPERR;
3170 addr = env->__excp_addr;
3171 goto do_signal;
3172 case PGM_EXECUTE:
3173 case PGM_SPECIFICATION:
3174 case PGM_SPECIAL_OP:
3175 case PGM_OPERAND:
3176 do_sigill_opn:
3177 sig = SIGILL;
3178 n = TARGET_ILL_ILLOPN;
3179 goto do_signal_pc;
3180
3181 case PGM_FIXPT_OVERFLOW:
3182 sig = SIGFPE;
3183 n = TARGET_FPE_INTOVF;
3184 goto do_signal_pc;
3185 case PGM_FIXPT_DIVIDE:
3186 sig = SIGFPE;
3187 n = TARGET_FPE_INTDIV;
3188 goto do_signal_pc;
3189
3190 case PGM_DATA:
3191 n = (env->fpc >> 8) & 0xff;
3192 if (n == 0xff) {
3193 /* compare-and-trap */
3194 goto do_sigill_opn;
3195 } else {
3196 /* An IEEE exception, simulated or otherwise. */
3197 if (n & 0x80) {
3198 n = TARGET_FPE_FLTINV;
3199 } else if (n & 0x40) {
3200 n = TARGET_FPE_FLTDIV;
3201 } else if (n & 0x20) {
3202 n = TARGET_FPE_FLTOVF;
3203 } else if (n & 0x10) {
3204 n = TARGET_FPE_FLTUND;
3205 } else if (n & 0x08) {
3206 n = TARGET_FPE_FLTRES;
3207 } else {
3208 /* ??? Quantum exception; BFP, DFP error. */
3209 goto do_sigill_opn;
3210 }
3211 sig = SIGFPE;
3212 goto do_signal_pc;
3213 }
3214
3215 default:
3216 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3217 cpu_dump_state(cs, stderr, fprintf, 0);
3218 exit(1);
3219 }
3220 break;
3221
3222 do_signal_pc:
3223 addr = env->psw.addr;
3224 do_signal:
3225 info.si_signo = sig;
3226 info.si_errno = 0;
3227 info.si_code = n;
3228 info._sifields._sigfault._addr = addr;
3229 queue_signal(env, info.si_signo, &info);
3230 break;
3231
3232 default:
3233 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3234 cpu_dump_state(cs, stderr, fprintf, 0);
3235 exit(1);
3236 }
3237 process_pending_signals (env);
3238 }
3239 }
3240
3241 #endif /* TARGET_S390X */
3242
3243 THREAD CPUState *thread_cpu;
3244
3245 void task_settid(TaskState *ts)
3246 {
3247 if (ts->ts_tid == 0) {
3248 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3249 }
3250 }
3251
3252 void stop_all_tasks(void)
3253 {
3254 /*
3255 * We trust that when using NPTL, start_exclusive()
3256 * handles thread stopping correctly.
3257 */
3258 start_exclusive();
3259 }
3260
3261 /* Assumes contents are already zeroed. */
3262 void init_task_state(TaskState *ts)
3263 {
3264 int i;
3265
3266 ts->used = 1;
3267 ts->first_free = ts->sigqueue_table;
3268 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3269 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3270 }
3271 ts->sigqueue_table[i].next = NULL;
3272 }
3273
3274 static void handle_arg_help(const char *arg)
3275 {
3276 usage();
3277 }
3278
3279 static void handle_arg_log(const char *arg)
3280 {
3281 int mask;
3282
3283 mask = qemu_str_to_log_mask(arg);
3284 if (!mask) {
3285 qemu_print_log_usage(stdout);
3286 exit(1);
3287 }
3288 qemu_set_log(mask);
3289 }
3290
3291 static void handle_arg_log_filename(const char *arg)
3292 {
3293 qemu_set_log_filename(arg);
3294 }
3295
3296 static void handle_arg_set_env(const char *arg)
3297 {
3298 char *r, *p, *token;
3299 r = p = strdup(arg);
3300 while ((token = strsep(&p, ",")) != NULL) {
3301 if (envlist_setenv(envlist, token) != 0) {
3302 usage();
3303 }
3304 }
3305 free(r);
3306 }
3307
3308 static void handle_arg_unset_env(const char *arg)
3309 {
3310 char *r, *p, *token;
3311 r = p = strdup(arg);
3312 while ((token = strsep(&p, ",")) != NULL) {
3313 if (envlist_unsetenv(envlist, token) != 0) {
3314 usage();
3315 }
3316 }
3317 free(r);
3318 }
3319
3320 static void handle_arg_argv0(const char *arg)
3321 {
3322 argv0 = strdup(arg);
3323 }
3324
3325 static void handle_arg_stack_size(const char *arg)
3326 {
3327 char *p;
3328 guest_stack_size = strtoul(arg, &p, 0);
3329 if (guest_stack_size == 0) {
3330 usage();
3331 }
3332
3333 if (*p == 'M') {
3334 guest_stack_size *= 1024 * 1024;
3335 } else if (*p == 'k' || *p == 'K') {
3336 guest_stack_size *= 1024;
3337 }
3338 }
3339
3340 static void handle_arg_ld_prefix(const char *arg)
3341 {
3342 interp_prefix = strdup(arg);
3343 }
3344
3345 static void handle_arg_pagesize(const char *arg)
3346 {
3347 qemu_host_page_size = atoi(arg);
3348 if (qemu_host_page_size == 0 ||
3349 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3350 fprintf(stderr, "page size must be a power of two\n");
3351 exit(1);
3352 }
3353 }
3354
3355 static void handle_arg_gdb(const char *arg)
3356 {
3357 gdbstub_port = atoi(arg);
3358 }
3359
3360 static void handle_arg_uname(const char *arg)
3361 {
3362 qemu_uname_release = strdup(arg);
3363 }
3364
3365 static void handle_arg_cpu(const char *arg)
3366 {
3367 cpu_model = strdup(arg);
3368 if (cpu_model == NULL || is_help_option(cpu_model)) {
3369 /* XXX: implement xxx_cpu_list for targets that still miss it */
3370 #if defined(cpu_list)
3371 cpu_list(stdout, &fprintf);
3372 #endif
3373 exit(1);
3374 }
3375 }
3376
3377 #if defined(CONFIG_USE_GUEST_BASE)
3378 static void handle_arg_guest_base(const char *arg)
3379 {
3380 guest_base = strtol(arg, NULL, 0);
3381 have_guest_base = 1;
3382 }
3383
3384 static void handle_arg_reserved_va(const char *arg)
3385 {
3386 char *p;
3387 int shift = 0;
3388 reserved_va = strtoul(arg, &p, 0);
3389 switch (*p) {
3390 case 'k':
3391 case 'K':
3392 shift = 10;
3393 break;
3394 case 'M':
3395 shift = 20;
3396 break;
3397 case 'G':
3398 shift = 30;
3399 break;
3400 }
3401 if (shift) {
3402 unsigned long unshifted = reserved_va;
3403 p++;
3404 reserved_va <<= shift;
3405 if (((reserved_va >> shift) != unshifted)
3406 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3407 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3408 #endif
3409 ) {
3410 fprintf(stderr, "Reserved virtual address too big\n");
3411 exit(1);
3412 }
3413 }
3414 if (*p) {
3415 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3416 exit(1);
3417 }
3418 }
3419 #endif
3420
3421 static void handle_arg_singlestep(const char *arg)
3422 {
3423 singlestep = 1;
3424 }
3425
3426 static void handle_arg_strace(const char *arg)
3427 {
3428 do_strace = 1;
3429 }
3430
3431 static void handle_arg_version(const char *arg)
3432 {
3433 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3434 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3435 exit(0);
3436 }
3437
3438 struct qemu_argument {
3439 const char *argv;
3440 const char *env;
3441 bool has_arg;
3442 void (*handle_opt)(const char *arg);
3443 const char *example;
3444 const char *help;
3445 };
3446
3447 static const struct qemu_argument arg_table[] = {
3448 {"h", "", false, handle_arg_help,
3449 "", "print this help"},
3450 {"g", "QEMU_GDB", true, handle_arg_gdb,
3451 "port", "wait gdb connection to 'port'"},
3452 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3453 "path", "set the elf interpreter prefix to 'path'"},
3454 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3455 "size", "set the stack size to 'size' bytes"},
3456 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3457 "model", "select CPU (-cpu help for list)"},
3458 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3459 "var=value", "sets targets environment variable (see below)"},
3460 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3461 "var", "unsets targets environment variable (see below)"},
3462 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3463 "argv0", "forces target process argv[0] to be 'argv0'"},
3464 {"r", "QEMU_UNAME", true, handle_arg_uname,
3465 "uname", "set qemu uname release string to 'uname'"},
3466 #if defined(CONFIG_USE_GUEST_BASE)
3467 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3468 "address", "set guest_base address to 'address'"},
3469 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3470 "size", "reserve 'size' bytes for guest virtual address space"},
3471 #endif
3472 {"d", "QEMU_LOG", true, handle_arg_log,
3473 "item[,...]", "enable logging of specified items "
3474 "(use '-d help' for a list of items)"},
3475 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3476 "logfile", "write logs to 'logfile' (default stderr)"},
3477 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3478 "pagesize", "set the host page size to 'pagesize'"},
3479 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3480 "", "run in singlestep mode"},
3481 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3482 "", "log system calls"},
3483 {"version", "QEMU_VERSION", false, handle_arg_version,
3484 "", "display version information and exit"},
3485 {NULL, NULL, false, NULL, NULL, NULL}
3486 };
3487
3488 static void usage(void)
3489 {
3490 const struct qemu_argument *arginfo;
3491 int maxarglen;
3492 int maxenvlen;
3493
3494 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3495 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3496 "\n"
3497 "Options and associated environment variables:\n"
3498 "\n");
3499
3500 /* Calculate column widths. We must always have at least enough space
3501 * for the column header.
3502 */
3503 maxarglen = strlen("Argument");
3504 maxenvlen = strlen("Env-variable");
3505
3506 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3507 int arglen = strlen(arginfo->argv);
3508 if (arginfo->has_arg) {
3509 arglen += strlen(arginfo->example) + 1;
3510 }
3511 if (strlen(arginfo->env) > maxenvlen) {
3512 maxenvlen = strlen(arginfo->env);
3513 }
3514 if (arglen > maxarglen) {
3515 maxarglen = arglen;
3516 }
3517 }
3518
3519 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3520 maxenvlen, "Env-variable");
3521
3522 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3523 if (arginfo->has_arg) {
3524 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3525 (int)(maxarglen - strlen(arginfo->argv) - 1),
3526 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3527 } else {
3528 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3529 maxenvlen, arginfo->env,
3530 arginfo->help);
3531 }
3532 }
3533
3534 printf("\n"
3535 "Defaults:\n"
3536 "QEMU_LD_PREFIX = %s\n"
3537 "QEMU_STACK_SIZE = %ld byte\n",
3538 interp_prefix,
3539 guest_stack_size);
3540
3541 printf("\n"
3542 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3543 "QEMU_UNSET_ENV environment variables to set and unset\n"
3544 "environment variables for the target process.\n"
3545 "It is possible to provide several variables by separating them\n"
3546 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3547 "provide the -E and -U options multiple times.\n"
3548 "The following lines are equivalent:\n"
3549 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3550 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3551 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3552 "Note that if you provide several changes to a single variable\n"
3553 "the last change will stay in effect.\n");
3554
3555 exit(1);
3556 }
3557
3558 static int parse_args(int argc, char **argv)
3559 {
3560 const char *r;
3561 int optind;
3562 const struct qemu_argument *arginfo;
3563
3564 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3565 if (arginfo->env == NULL) {
3566 continue;
3567 }
3568
3569 r = getenv(arginfo->env);
3570 if (r != NULL) {
3571 arginfo->handle_opt(r);
3572 }
3573 }
3574
3575 optind = 1;
3576 for (;;) {
3577 if (optind >= argc) {
3578 break;
3579 }
3580 r = argv[optind];
3581 if (r[0] != '-') {
3582 break;
3583 }
3584 optind++;
3585 r++;
3586 if (!strcmp(r, "-")) {
3587 break;
3588 }
3589
3590 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3591 if (!strcmp(r, arginfo->argv)) {
3592 if (arginfo->has_arg) {
3593 if (optind >= argc) {
3594 usage();
3595 }
3596 arginfo->handle_opt(argv[optind]);
3597 optind++;
3598 } else {
3599 arginfo->handle_opt(NULL);
3600 }
3601 break;
3602 }
3603 }
3604
3605 /* no option matched the current argv */
3606 if (arginfo->handle_opt == NULL) {
3607 usage();
3608 }
3609 }
3610
3611 if (optind >= argc) {
3612 usage();
3613 }
3614
3615 filename = argv[optind];
3616 exec_path = argv[optind];
3617
3618 return optind;
3619 }
3620
3621 int main(int argc, char **argv, char **envp)
3622 {
3623 struct target_pt_regs regs1, *regs = &regs1;
3624 struct image_info info1, *info = &info1;
3625 struct linux_binprm bprm;
3626 TaskState *ts;
3627 CPUArchState *env;
3628 CPUState *cpu;
3629 int optind;
3630 char **target_environ, **wrk;
3631 char **target_argv;
3632 int target_argc;
3633 int i;
3634 int ret;
3635
3636 module_call_init(MODULE_INIT_QOM);
3637
3638 qemu_cache_utils_init(envp);
3639
3640 if ((envlist = envlist_create()) == NULL) {
3641 (void) fprintf(stderr, "Unable to allocate envlist\n");
3642 exit(1);
3643 }
3644
3645 /* add current environment into the list */
3646 for (wrk = environ; *wrk != NULL; wrk++) {
3647 (void) envlist_setenv(envlist, *wrk);
3648 }
3649
3650 /* Read the stack limit from the kernel. If it's "unlimited",
3651 then we can do little else besides use the default. */
3652 {
3653 struct rlimit lim;
3654 if (getrlimit(RLIMIT_STACK, &lim) == 0
3655 && lim.rlim_cur != RLIM_INFINITY
3656 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3657 guest_stack_size = lim.rlim_cur;
3658 }
3659 }
3660
3661 cpu_model = NULL;
3662 #if defined(cpudef_setup)
3663 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3664 #endif
3665
3666 optind = parse_args(argc, argv);
3667
3668 /* Zero out regs */
3669 memset(regs, 0, sizeof(struct target_pt_regs));
3670
3671 /* Zero out image_info */
3672 memset(info, 0, sizeof(struct image_info));
3673
3674 memset(&bprm, 0, sizeof (bprm));
3675
3676 /* Scan interp_prefix dir for replacement files. */
3677 init_paths(interp_prefix);
3678
3679 init_qemu_uname_release();
3680
3681 if (cpu_model == NULL) {
3682 #if defined(TARGET_I386)
3683 #ifdef TARGET_X86_64
3684 cpu_model = "qemu64";
3685 #else
3686 cpu_model = "qemu32";
3687 #endif
3688 #elif defined(TARGET_ARM)
3689 cpu_model = "any";
3690 #elif defined(TARGET_UNICORE32)
3691 cpu_model = "any";
3692 #elif defined(TARGET_M68K)
3693 cpu_model = "any";
3694 #elif defined(TARGET_SPARC)
3695 #ifdef TARGET_SPARC64
3696 cpu_model = "TI UltraSparc II";
3697 #else
3698 cpu_model = "Fujitsu MB86904";
3699 #endif
3700 #elif defined(TARGET_MIPS)
3701 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3702 cpu_model = "20Kc";
3703 #else
3704 cpu_model = "24Kf";
3705 #endif
3706 #elif defined TARGET_OPENRISC
3707 cpu_model = "or1200";
3708 #elif defined(TARGET_PPC)
3709 #ifdef TARGET_PPC64
3710 cpu_model = "970fx";
3711 #else
3712 cpu_model = "750";
3713 #endif
3714 #else
3715 cpu_model = "any";
3716 #endif
3717 }
3718 tcg_exec_init(0);
3719 cpu_exec_init_all();
3720 /* NOTE: we need to init the CPU at this stage to get
3721 qemu_host_page_size */
3722 env = cpu_init(cpu_model);
3723 if (!env) {
3724 fprintf(stderr, "Unable to find CPU definition\n");
3725 exit(1);
3726 }
3727 cpu = ENV_GET_CPU(env);
3728 cpu_reset(cpu);
3729
3730 thread_cpu = cpu;
3731
3732 if (getenv("QEMU_STRACE")) {
3733 do_strace = 1;
3734 }
3735
3736 target_environ = envlist_to_environ(envlist, NULL);
3737 envlist_free(envlist);
3738
3739 #if defined(CONFIG_USE_GUEST_BASE)
3740 /*
3741 * Now that page sizes are configured in cpu_init() we can do
3742 * proper page alignment for guest_base.
3743 */
3744 guest_base = HOST_PAGE_ALIGN(guest_base);
3745
3746 if (reserved_va || have_guest_base) {
3747 guest_base = init_guest_space(guest_base, reserved_va, 0,
3748 have_guest_base);
3749 if (guest_base == (unsigned long)-1) {
3750 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3751 "space for use as guest address space (check your virtual "
3752 "memory ulimit setting or reserve less using -R option)\n",
3753 reserved_va);
3754 exit(1);
3755 }
3756
3757 if (reserved_va) {
3758 mmap_next_start = reserved_va;
3759 }
3760 }
3761 #endif /* CONFIG_USE_GUEST_BASE */
3762
3763 /*
3764 * Read in mmap_min_addr kernel parameter. This value is used
3765 * When loading the ELF image to determine whether guest_base
3766 * is needed. It is also used in mmap_find_vma.
3767 */
3768 {
3769 FILE *fp;
3770
3771 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3772 unsigned long tmp;
3773 if (fscanf(fp, "%lu", &tmp) == 1) {
3774 mmap_min_addr = tmp;
3775 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3776 }
3777 fclose(fp);
3778 }
3779 }
3780
3781 /*
3782 * Prepare copy of argv vector for target.
3783 */
3784 target_argc = argc - optind;
3785 target_argv = calloc(target_argc + 1, sizeof (char *));
3786 if (target_argv == NULL) {
3787 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3788 exit(1);
3789 }
3790
3791 /*
3792 * If argv0 is specified (using '-0' switch) we replace
3793 * argv[0] pointer with the given one.
3794 */
3795 i = 0;
3796 if (argv0 != NULL) {
3797 target_argv[i++] = strdup(argv0);
3798 }
3799 for (; i < target_argc; i++) {
3800 target_argv[i] = strdup(argv[optind + i]);
3801 }
3802 target_argv[target_argc] = NULL;
3803
3804 ts = g_malloc0 (sizeof(TaskState));
3805 init_task_state(ts);
3806 /* build Task State */
3807 ts->info = info;
3808 ts->bprm = &bprm;
3809 env->opaque = ts;
3810 task_settid(ts);
3811
3812 ret = loader_exec(filename, target_argv, target_environ, regs,
3813 info, &bprm);
3814 if (ret != 0) {
3815 printf("Error while loading %s: %s\n", filename, strerror(-ret));
3816 _exit(1);
3817 }
3818
3819 for (wrk = target_environ; *wrk; wrk++) {
3820 free(*wrk);
3821 }
3822
3823 free(target_environ);
3824
3825 if (qemu_log_enabled()) {
3826 #if defined(CONFIG_USE_GUEST_BASE)
3827 qemu_log("guest_base 0x%lx\n", guest_base);
3828 #endif
3829 log_page_dump();
3830
3831 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
3832 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
3833 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
3834 info->start_code);
3835 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
3836 info->start_data);
3837 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
3838 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
3839 info->start_stack);
3840 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
3841 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
3842 }
3843
3844 target_set_brk(info->brk);
3845 syscall_init();
3846 signal_init();
3847
3848 #if defined(CONFIG_USE_GUEST_BASE)
3849 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
3850 generating the prologue until now so that the prologue can take
3851 the real value of GUEST_BASE into account. */
3852 tcg_prologue_init(&tcg_ctx);
3853 #endif
3854
3855 #if defined(TARGET_I386)
3856 cpu_x86_set_cpl(env, 3);
3857
3858 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
3859 env->hflags |= HF_PE_MASK;
3860 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
3861 env->cr[4] |= CR4_OSFXSR_MASK;
3862 env->hflags |= HF_OSFXSR_MASK;
3863 }
3864 #ifndef TARGET_ABI32
3865 /* enable 64 bit mode if possible */
3866 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
3867 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3868 exit(1);
3869 }
3870 env->cr[4] |= CR4_PAE_MASK;
3871 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
3872 env->hflags |= HF_LMA_MASK;
3873 #endif
3874
3875 /* flags setup : we activate the IRQs by default as in user mode */
3876 env->eflags |= IF_MASK;
3877
3878 /* linux register setup */
3879 #ifndef TARGET_ABI32
3880 env->regs[R_EAX] = regs->rax;
3881 env->regs[R_EBX] = regs->rbx;
3882 env->regs[R_ECX] = regs->rcx;
3883 env->regs[R_EDX] = regs->rdx;
3884 env->regs[R_ESI] = regs->rsi;
3885 env->regs[R_EDI] = regs->rdi;
3886 env->regs[R_EBP] = regs->rbp;
3887 env->regs[R_ESP] = regs->rsp;
3888 env->eip = regs->rip;
3889 #else
3890 env->regs[R_EAX] = regs->eax;
3891 env->regs[R_EBX] = regs->ebx;
3892 env->regs[R_ECX] = regs->ecx;
3893 env->regs[R_EDX] = regs->edx;
3894 env->regs[R_ESI] = regs->esi;
3895 env->regs[R_EDI] = regs->edi;
3896 env->regs[R_EBP] = regs->ebp;
3897 env->regs[R_ESP] = regs->esp;
3898 env->eip = regs->eip;
3899 #endif
3900
3901 /* linux interrupt setup */
3902 #ifndef TARGET_ABI32
3903 env->idt.limit = 511;
3904 #else
3905 env->idt.limit = 255;
3906 #endif
3907 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3908 PROT_READ|PROT_WRITE,
3909 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3910 idt_table = g2h(env->idt.base);
3911 set_idt(0, 0);
3912 set_idt(1, 0);
3913 set_idt(2, 0);
3914 set_idt(3, 3);
3915 set_idt(4, 3);
3916 set_idt(5, 0);
3917 set_idt(6, 0);
3918 set_idt(7, 0);
3919 set_idt(8, 0);
3920 set_idt(9, 0);
3921 set_idt(10, 0);
3922 set_idt(11, 0);
3923 set_idt(12, 0);
3924 set_idt(13, 0);
3925 set_idt(14, 0);
3926 set_idt(15, 0);
3927 set_idt(16, 0);
3928 set_idt(17, 0);
3929 set_idt(18, 0);
3930 set_idt(19, 0);
3931 set_idt(0x80, 3);
3932
3933 /* linux segment setup */
3934 {
3935 uint64_t *gdt_table;
3936 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3937 PROT_READ|PROT_WRITE,
3938 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3939 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
3940 gdt_table = g2h(env->gdt.base);
3941 #ifdef TARGET_ABI32
3942 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3943 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3944 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3945 #else
3946 /* 64 bit code segment */
3947 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3948 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3949 DESC_L_MASK |
3950 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3951 #endif
3952 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3953 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3954 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3955 }
3956 cpu_x86_load_seg(env, R_CS, __USER_CS);
3957 cpu_x86_load_seg(env, R_SS, __USER_DS);
3958 #ifdef TARGET_ABI32
3959 cpu_x86_load_seg(env, R_DS, __USER_DS);
3960 cpu_x86_load_seg(env, R_ES, __USER_DS);
3961 cpu_x86_load_seg(env, R_FS, __USER_DS);
3962 cpu_x86_load_seg(env, R_GS, __USER_DS);
3963 /* This hack makes Wine work... */
3964 env->segs[R_FS].selector = 0;
3965 #else
3966 cpu_x86_load_seg(env, R_DS, 0);
3967 cpu_x86_load_seg(env, R_ES, 0);
3968 cpu_x86_load_seg(env, R_FS, 0);
3969 cpu_x86_load_seg(env, R_GS, 0);
3970 #endif
3971 #elif defined(TARGET_AARCH64)
3972 {
3973 int i;
3974
3975 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
3976 fprintf(stderr,
3977 "The selected ARM CPU does not support 64 bit mode\n");
3978 exit(1);
3979 }
3980
3981 for (i = 0; i < 31; i++) {
3982 env->xregs[i] = regs->regs[i];
3983 }
3984 env->pc = regs->pc;
3985 env->xregs[31] = regs->sp;
3986 }
3987 #elif defined(TARGET_ARM)
3988 {
3989 int i;
3990 cpsr_write(env, regs->uregs[16], 0xffffffff);
3991 for(i = 0; i < 16; i++) {
3992 env->regs[i] = regs->uregs[i];
3993 }
3994 /* Enable BE8. */
3995 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
3996 && (info->elf_flags & EF_ARM_BE8)) {
3997 env->bswap_code = 1;
3998 }
3999 }
4000 #elif defined(TARGET_UNICORE32)
4001 {
4002 int i;
4003 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4004 for (i = 0; i < 32; i++) {
4005 env->regs[i] = regs->uregs[i];
4006 }
4007 }
4008 #elif defined(TARGET_SPARC)
4009 {
4010 int i;
4011 env->pc = regs->pc;
4012 env->npc = regs->npc;
4013 env->y = regs->y;
4014 for(i = 0; i < 8; i++)
4015 env->gregs[i] = regs->u_regs[i];
4016 for(i = 0; i < 8; i++)
4017 env->regwptr[i] = regs->u_regs[i + 8];
4018 }
4019 #elif defined(TARGET_PPC)
4020 {
4021 int i;
4022
4023 #if defined(TARGET_PPC64)
4024 #if defined(TARGET_ABI32)
4025 env->msr &= ~((target_ulong)1 << MSR_SF);
4026 #else
4027 env->msr |= (target_ulong)1 << MSR_SF;
4028 #endif
4029 #endif
4030 env->nip = regs->nip;
4031 for(i = 0; i < 32; i++) {
4032 env->gpr[i] = regs->gpr[i];
4033 }
4034 }
4035 #elif defined(TARGET_M68K)
4036 {
4037 env->pc = regs->pc;
4038 env->dregs[0] = regs->d0;
4039 env->dregs[1] = regs->d1;
4040 env->dregs[2] = regs->d2;
4041 env->dregs[3] = regs->d3;
4042 env->dregs[4] = regs->d4;
4043 env->dregs[5] = regs->d5;
4044 env->dregs[6] = regs->d6;
4045 env->dregs[7] = regs->d7;
4046 env->aregs[0] = regs->a0;
4047 env->aregs[1] = regs->a1;
4048 env->aregs[2] = regs->a2;
4049 env->aregs[3] = regs->a3;
4050 env->aregs[4] = regs->a4;
4051 env->aregs[5] = regs->a5;
4052 env->aregs[6] = regs->a6;
4053 env->aregs[7] = regs->usp;
4054 env->sr = regs->sr;
4055 ts->sim_syscalls = 1;
4056 }
4057 #elif defined(TARGET_MICROBLAZE)
4058 {
4059 env->regs[0] = regs->r0;
4060 env->regs[1] = regs->r1;
4061 env->regs[2] = regs->r2;
4062 env->regs[3] = regs->r3;
4063 env->regs[4] = regs->r4;
4064 env->regs[5] = regs->r5;
4065 env->regs[6] = regs->r6;
4066 env->regs[7] = regs->r7;
4067 env->regs[8] = regs->r8;
4068 env->regs[9] = regs->r9;
4069 env->regs[10] = regs->r10;
4070 env->regs[11] = regs->r11;
4071 env->regs[12] = regs->r12;
4072 env->regs[13] = regs->r13;
4073 env->regs[14] = regs->r14;
4074 env->regs[15] = regs->r15;
4075 env->regs[16] = regs->r16;
4076 env->regs[17] = regs->r17;
4077 env->regs[18] = regs->r18;
4078 env->regs[19] = regs->r19;
4079 env->regs[20] = regs->r20;
4080 env->regs[21] = regs->r21;
4081 env->regs[22] = regs->r22;
4082 env->regs[23] = regs->r23;
4083 env->regs[24] = regs->r24;
4084 env->regs[25] = regs->r25;
4085 env->regs[26] = regs->r26;
4086 env->regs[27] = regs->r27;
4087 env->regs[28] = regs->r28;
4088 env->regs[29] = regs->r29;
4089 env->regs[30] = regs->r30;
4090 env->regs[31] = regs->r31;
4091 env->sregs[SR_PC] = regs->pc;
4092 }
4093 #elif defined(TARGET_MIPS)
4094 {
4095 int i;
4096
4097 for(i = 0; i < 32; i++) {
4098 env->active_tc.gpr[i] = regs->regs[i];
4099 }
4100 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4101 if (regs->cp0_epc & 1) {
4102 env->hflags |= MIPS_HFLAG_M16;
4103 }
4104 }
4105 #elif defined(TARGET_OPENRISC)
4106 {
4107 int i;
4108
4109 for (i = 0; i < 32; i++) {
4110 env->gpr[i] = regs->gpr[i];
4111 }
4112
4113 env->sr = regs->sr;
4114 env->pc = regs->pc;
4115 }
4116 #elif defined(TARGET_SH4)
4117 {
4118 int i;
4119
4120 for(i = 0; i < 16; i++) {
4121 env->gregs[i] = regs->regs[i];
4122 }
4123 env->pc = regs->pc;
4124 }
4125 #elif defined(TARGET_ALPHA)
4126 {
4127 int i;
4128
4129 for(i = 0; i < 28; i++) {
4130 env->ir[i] = ((abi_ulong *)regs)[i];
4131 }
4132 env->ir[IR_SP] = regs->usp;
4133 env->pc = regs->pc;
4134 }
4135 #elif defined(TARGET_CRIS)
4136 {
4137 env->regs[0] = regs->r0;
4138 env->regs[1] = regs->r1;
4139 env->regs[2] = regs->r2;
4140 env->regs[3] = regs->r3;
4141 env->regs[4] = regs->r4;
4142 env->regs[5] = regs->r5;
4143 env->regs[6] = regs->r6;
4144 env->regs[7] = regs->r7;
4145 env->regs[8] = regs->r8;
4146 env->regs[9] = regs->r9;
4147 env->regs[10] = regs->r10;
4148 env->regs[11] = regs->r11;
4149 env->regs[12] = regs->r12;
4150 env->regs[13] = regs->r13;
4151 env->regs[14] = info->start_stack;
4152 env->regs[15] = regs->acr;
4153 env->pc = regs->erp;
4154 }
4155 #elif defined(TARGET_S390X)
4156 {
4157 int i;
4158 for (i = 0; i < 16; i++) {
4159 env->regs[i] = regs->gprs[i];
4160 }
4161 env->psw.mask = regs->psw.mask;
4162 env->psw.addr = regs->psw.addr;
4163 }
4164 #else
4165 #error unsupported target CPU
4166 #endif
4167
4168 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4169 ts->stack_base = info->start_stack;
4170 ts->heap_base = info->brk;
4171 /* This will be filled in on the first SYS_HEAPINFO call. */
4172 ts->heap_limit = 0;
4173 #endif
4174
4175 if (gdbstub_port) {
4176 if (gdbserver_start(gdbstub_port) < 0) {
4177 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4178 gdbstub_port);
4179 exit(1);
4180 }
4181 gdb_handlesig(cpu, 0);
4182 }
4183 cpu_loop(env);
4184 /* never exits */
4185 return 0;
4186 }
QEmu