Support PCI based option rom loading
[qemu.git] / hw / tc6393xb.c
blobe0c5e5f08787f894c0513670942555363ddbe688
1 /*
2 * Toshiba TC6393XB I/O Controller.
3 * Found in Sharp Zaurus SL-6000 (tosa) or some
4 * Toshiba e-Series PDAs.
6 * Most features are currently unsupported!!!
8 * This code is licensed under the GNU GPL v2.
9 */
10 #include "hw.h"
11 #include "pxa.h"
12 #include "devices.h"
13 #include "flash.h"
14 #include "console.h"
15 #include "pixel_ops.h"
17 #define IRQ_TC6393_NAND 0
18 #define IRQ_TC6393_MMC 1
19 #define IRQ_TC6393_OHCI 2
20 #define IRQ_TC6393_SERIAL 3
21 #define IRQ_TC6393_FB 4
23 #define TC6393XB_NR_IRQS 8
25 #define TC6393XB_GPIOS 16
27 #define SCR_REVID 0x08 /* b Revision ID */
28 #define SCR_ISR 0x50 /* b Interrupt Status */
29 #define SCR_IMR 0x52 /* b Interrupt Mask */
30 #define SCR_IRR 0x54 /* b Interrupt Routing */
31 #define SCR_GPER 0x60 /* w GP Enable */
32 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
33 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
34 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
35 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
36 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
37 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
38 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
39 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
40 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
41 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
42 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
43 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
44 #define SCR_CCR 0x98 /* w Clock Control */
45 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
46 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
47 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
48 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
49 #define SCR_FER 0xe0 /* b Function Enable */
50 #define SCR_MCR 0xe4 /* w Mode Control */
51 #define SCR_CONFIG 0xfc /* b Configuration Control */
52 #define SCR_DEBUG 0xff /* b Debug */
54 #define NAND_CFG_COMMAND 0x04 /* w Command */
55 #define NAND_CFG_BASE 0x10 /* l Control Base Address */
56 #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */
57 #define NAND_CFG_INTE 0x48 /* b Int Enable */
58 #define NAND_CFG_EC 0x4a /* b Event Control */
59 #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */
60 #define NAND_CFG_ECCC 0x5b /* b ECC Control */
61 #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */
62 #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */
63 #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */
64 #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */
66 #define NAND_DATA 0x00 /* l Data */
67 #define NAND_MODE 0x04 /* b Mode */
68 #define NAND_STATUS 0x05 /* b Status */
69 #define NAND_ISR 0x06 /* b Interrupt Status */
70 #define NAND_IMR 0x07 /* b Interrupt Mask */
72 #define NAND_MODE_WP 0x80
73 #define NAND_MODE_CE 0x10
74 #define NAND_MODE_ALE 0x02
75 #define NAND_MODE_CLE 0x01
76 #define NAND_MODE_ECC_MASK 0x60
77 #define NAND_MODE_ECC_EN 0x20
78 #define NAND_MODE_ECC_READ 0x40
79 #define NAND_MODE_ECC_RST 0x60
81 struct TC6393xbState {
82 qemu_irq irq;
83 qemu_irq *sub_irqs;
84 struct {
85 uint8_t ISR;
86 uint8_t IMR;
87 uint8_t IRR;
88 uint16_t GPER;
89 uint8_t GPI_SR[3];
90 uint8_t GPI_IMR[3];
91 uint8_t GPI_EDER[3];
92 uint8_t GPI_LIR[3];
93 uint8_t GP_IARCR[3];
94 uint8_t GP_IARLCR[3];
95 uint8_t GPI_BCR[3];
96 uint16_t GPA_IARCR;
97 uint16_t GPA_IARLCR;
98 uint16_t CCR;
99 uint16_t PLL2CR;
100 uint32_t PLL1CR;
101 uint8_t DIARCR;
102 uint8_t DBOCR;
103 uint8_t FER;
104 uint16_t MCR;
105 uint8_t CONFIG;
106 uint8_t DEBUG;
107 } scr;
108 uint32_t gpio_dir;
109 uint32_t gpio_level;
110 uint32_t prev_level;
111 qemu_irq handler[TC6393XB_GPIOS];
112 qemu_irq *gpio_in;
114 struct {
115 uint8_t mode;
116 uint8_t isr;
117 uint8_t imr;
118 } nand;
119 int nand_enable;
120 uint32_t nand_phys;
121 NANDFlashState *flash;
122 ECCState ecc;
124 DisplayState *ds;
125 ram_addr_t vram_addr;
126 uint16_t *vram_ptr;
127 uint32_t scr_width, scr_height; /* in pixels */
128 qemu_irq l3v;
129 unsigned blank : 1,
130 blanked : 1;
133 qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
135 return s->gpio_in;
138 static void tc6393xb_gpio_set(void *opaque, int line, int level)
140 // TC6393xbState *s = opaque;
142 if (line > TC6393XB_GPIOS) {
143 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
144 return;
147 // FIXME: how does the chip reflect the GPIO input level change?
150 void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
151 qemu_irq handler)
153 if (line >= TC6393XB_GPIOS) {
154 fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
155 return;
158 s->handler[line] = handler;
161 static void tc6393xb_gpio_handler_update(TC6393xbState *s)
163 uint32_t level, diff;
164 int bit;
166 level = s->gpio_level & s->gpio_dir;
168 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
169 bit = ffs(diff) - 1;
170 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
173 s->prev_level = level;
176 qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
178 return s->l3v;
181 static void tc6393xb_l3v(void *opaque, int line, int level)
183 TC6393xbState *s = opaque;
184 s->blank = !level;
185 fprintf(stderr, "L3V: %d\n", level);
188 static void tc6393xb_sub_irq(void *opaque, int line, int level) {
189 TC6393xbState *s = opaque;
190 uint8_t isr = s->scr.ISR;
191 if (level)
192 isr |= 1 << line;
193 else
194 isr &= ~(1 << line);
195 s->scr.ISR = isr;
196 qemu_set_irq(s->irq, isr & s->scr.IMR);
199 #define SCR_REG_B(N) \
200 case SCR_ ##N: return s->scr.N
201 #define SCR_REG_W(N) \
202 case SCR_ ##N: return s->scr.N; \
203 case SCR_ ##N + 1: return s->scr.N >> 8;
204 #define SCR_REG_L(N) \
205 case SCR_ ##N: return s->scr.N; \
206 case SCR_ ##N + 1: return s->scr.N >> 8; \
207 case SCR_ ##N + 2: return s->scr.N >> 16; \
208 case SCR_ ##N + 3: return s->scr.N >> 24;
209 #define SCR_REG_A(N) \
210 case SCR_ ##N(0): return s->scr.N[0]; \
211 case SCR_ ##N(1): return s->scr.N[1]; \
212 case SCR_ ##N(2): return s->scr.N[2]
214 static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
216 switch (addr) {
217 case SCR_REVID:
218 return 3;
219 case SCR_REVID+1:
220 return 0;
221 SCR_REG_B(ISR);
222 SCR_REG_B(IMR);
223 SCR_REG_B(IRR);
224 SCR_REG_W(GPER);
225 SCR_REG_A(GPI_SR);
226 SCR_REG_A(GPI_IMR);
227 SCR_REG_A(GPI_EDER);
228 SCR_REG_A(GPI_LIR);
229 case SCR_GPO_DSR(0):
230 case SCR_GPO_DSR(1):
231 case SCR_GPO_DSR(2):
232 return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
233 case SCR_GPO_DOECR(0):
234 case SCR_GPO_DOECR(1):
235 case SCR_GPO_DOECR(2):
236 return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
237 SCR_REG_A(GP_IARCR);
238 SCR_REG_A(GP_IARLCR);
239 SCR_REG_A(GPI_BCR);
240 SCR_REG_W(GPA_IARCR);
241 SCR_REG_W(GPA_IARLCR);
242 SCR_REG_W(CCR);
243 SCR_REG_W(PLL2CR);
244 SCR_REG_L(PLL1CR);
245 SCR_REG_B(DIARCR);
246 SCR_REG_B(DBOCR);
247 SCR_REG_B(FER);
248 SCR_REG_W(MCR);
249 SCR_REG_B(CONFIG);
250 SCR_REG_B(DEBUG);
252 fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
253 return 0;
255 #undef SCR_REG_B
256 #undef SCR_REG_W
257 #undef SCR_REG_L
258 #undef SCR_REG_A
260 #define SCR_REG_B(N) \
261 case SCR_ ##N: s->scr.N = value; return;
262 #define SCR_REG_W(N) \
263 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
264 case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return
265 #define SCR_REG_L(N) \
266 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
267 case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \
268 case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \
269 case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return;
270 #define SCR_REG_A(N) \
271 case SCR_ ##N(0): s->scr.N[0] = value; return; \
272 case SCR_ ##N(1): s->scr.N[1] = value; return; \
273 case SCR_ ##N(2): s->scr.N[2] = value; return
275 static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value)
277 switch (addr) {
278 SCR_REG_B(ISR);
279 SCR_REG_B(IMR);
280 SCR_REG_B(IRR);
281 SCR_REG_W(GPER);
282 SCR_REG_A(GPI_SR);
283 SCR_REG_A(GPI_IMR);
284 SCR_REG_A(GPI_EDER);
285 SCR_REG_A(GPI_LIR);
286 case SCR_GPO_DSR(0):
287 case SCR_GPO_DSR(1):
288 case SCR_GPO_DSR(2):
289 s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
290 tc6393xb_gpio_handler_update(s);
291 return;
292 case SCR_GPO_DOECR(0):
293 case SCR_GPO_DOECR(1):
294 case SCR_GPO_DOECR(2):
295 s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
296 tc6393xb_gpio_handler_update(s);
297 return;
298 SCR_REG_A(GP_IARCR);
299 SCR_REG_A(GP_IARLCR);
300 SCR_REG_A(GPI_BCR);
301 SCR_REG_W(GPA_IARCR);
302 SCR_REG_W(GPA_IARLCR);
303 SCR_REG_W(CCR);
304 SCR_REG_W(PLL2CR);
305 SCR_REG_L(PLL1CR);
306 SCR_REG_B(DIARCR);
307 SCR_REG_B(DBOCR);
308 SCR_REG_B(FER);
309 SCR_REG_W(MCR);
310 SCR_REG_B(CONFIG);
311 SCR_REG_B(DEBUG);
313 fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
314 (uint32_t) addr, value & 0xff);
316 #undef SCR_REG_B
317 #undef SCR_REG_W
318 #undef SCR_REG_L
319 #undef SCR_REG_A
321 static void tc6393xb_nand_irq(TC6393xbState *s) {
322 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
323 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
326 static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) {
327 switch (addr) {
328 case NAND_CFG_COMMAND:
329 return s->nand_enable ? 2 : 0;
330 case NAND_CFG_BASE:
331 case NAND_CFG_BASE + 1:
332 case NAND_CFG_BASE + 2:
333 case NAND_CFG_BASE + 3:
334 return s->nand_phys >> (addr - NAND_CFG_BASE);
336 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
337 return 0;
339 static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
340 switch (addr) {
341 case NAND_CFG_COMMAND:
342 s->nand_enable = (value & 0x2);
343 return;
344 case NAND_CFG_BASE:
345 case NAND_CFG_BASE + 1:
346 case NAND_CFG_BASE + 2:
347 case NAND_CFG_BASE + 3:
348 s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
349 s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
350 return;
352 fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
353 (uint32_t) addr, value & 0xff);
356 static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
357 switch (addr) {
358 case NAND_DATA + 0:
359 case NAND_DATA + 1:
360 case NAND_DATA + 2:
361 case NAND_DATA + 3:
362 return nand_getio(s->flash);
363 case NAND_MODE:
364 return s->nand.mode;
365 case NAND_STATUS:
366 return 0x14;
367 case NAND_ISR:
368 return s->nand.isr;
369 case NAND_IMR:
370 return s->nand.imr;
372 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
373 return 0;
375 static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
376 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
377 // (uint32_t) addr, value & 0xff);
378 switch (addr) {
379 case NAND_DATA + 0:
380 case NAND_DATA + 1:
381 case NAND_DATA + 2:
382 case NAND_DATA + 3:
383 nand_setio(s->flash, value);
384 s->nand.isr &= 1;
385 tc6393xb_nand_irq(s);
386 return;
387 case NAND_MODE:
388 s->nand.mode = value;
389 nand_setpins(s->flash,
390 value & NAND_MODE_CLE,
391 value & NAND_MODE_ALE,
392 !(value & NAND_MODE_CE),
393 value & NAND_MODE_WP,
394 0); // FIXME: gnd
395 switch (value & NAND_MODE_ECC_MASK) {
396 case NAND_MODE_ECC_RST:
397 ecc_reset(&s->ecc);
398 break;
399 case NAND_MODE_ECC_READ:
400 // FIXME
401 break;
402 case NAND_MODE_ECC_EN:
403 ecc_reset(&s->ecc);
405 return;
406 case NAND_ISR:
407 s->nand.isr = value;
408 tc6393xb_nand_irq(s);
409 return;
410 case NAND_IMR:
411 s->nand.imr = value;
412 tc6393xb_nand_irq(s);
413 return;
415 fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
416 (uint32_t) addr, value & 0xff);
419 #define BITS 8
420 #include "tc6393xb_template.h"
421 #define BITS 15
422 #include "tc6393xb_template.h"
423 #define BITS 16
424 #include "tc6393xb_template.h"
425 #define BITS 24
426 #include "tc6393xb_template.h"
427 #define BITS 32
428 #include "tc6393xb_template.h"
430 static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
432 switch (ds_get_bits_per_pixel(s->ds)) {
433 case 8:
434 tc6393xb_draw_graphic8(s);
435 break;
436 case 15:
437 tc6393xb_draw_graphic15(s);
438 break;
439 case 16:
440 tc6393xb_draw_graphic16(s);
441 break;
442 case 24:
443 tc6393xb_draw_graphic24(s);
444 break;
445 case 32:
446 tc6393xb_draw_graphic32(s);
447 break;
448 default:
449 printf("tc6393xb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
450 return;
453 dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
456 static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
458 int i, w;
459 uint8_t *d;
461 if (!full_update)
462 return;
464 w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
465 d = ds_get_data(s->ds);
466 for(i = 0; i < s->scr_height; i++) {
467 memset(d, 0, w);
468 d += ds_get_linesize(s->ds);
471 dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
474 static void tc6393xb_update_display(void *opaque)
476 TC6393xbState *s = opaque;
477 int full_update;
479 if (s->scr_width == 0 || s->scr_height == 0)
480 return;
482 full_update = 0;
483 if (s->blanked != s->blank) {
484 s->blanked = s->blank;
485 full_update = 1;
487 if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
488 qemu_console_resize(s->ds, s->scr_width, s->scr_height);
489 full_update = 1;
491 if (s->blanked)
492 tc6393xb_draw_blank(s, full_update);
493 else
494 tc6393xb_draw_graphic(s, full_update);
498 static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) {
499 TC6393xbState *s = opaque;
501 switch (addr >> 8) {
502 case 0:
503 return tc6393xb_scr_readb(s, addr & 0xff);
504 case 1:
505 return tc6393xb_nand_cfg_readb(s, addr & 0xff);
508 if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
509 // return tc6393xb_nand_readb(s, addr & 0xff);
510 uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
511 // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
512 return d;
515 // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
516 return 0;
519 static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) {
520 TC6393xbState *s = opaque;
522 switch (addr >> 8) {
523 case 0:
524 tc6393xb_scr_writeb(s, addr & 0xff, value);
525 return;
526 case 1:
527 tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
528 return;
531 if ((addr &~0xff) == s->nand_phys && s->nand_enable)
532 tc6393xb_nand_writeb(s, addr & 0xff, value);
533 else
534 fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
535 (uint32_t) addr, value & 0xff);
538 static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr)
540 return (tc6393xb_readb(opaque, addr) & 0xff) |
541 (tc6393xb_readb(opaque, addr + 1) << 8);
544 static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr)
546 return (tc6393xb_readb(opaque, addr) & 0xff) |
547 ((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) |
548 ((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) |
549 ((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24);
552 static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
554 tc6393xb_writeb(opaque, addr, value);
555 tc6393xb_writeb(opaque, addr + 1, value >> 8);
558 static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
560 tc6393xb_writeb(opaque, addr, value);
561 tc6393xb_writeb(opaque, addr + 1, value >> 8);
562 tc6393xb_writeb(opaque, addr + 2, value >> 16);
563 tc6393xb_writeb(opaque, addr + 3, value >> 24);
566 TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq)
568 int iomemtype;
569 TC6393xbState *s;
570 CPUReadMemoryFunc * const tc6393xb_readfn[] = {
571 tc6393xb_readb,
572 tc6393xb_readw,
573 tc6393xb_readl,
575 CPUWriteMemoryFunc * const tc6393xb_writefn[] = {
576 tc6393xb_writeb,
577 tc6393xb_writew,
578 tc6393xb_writel,
581 s = (TC6393xbState *) qemu_mallocz(sizeof(TC6393xbState));
582 s->irq = irq;
583 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
585 s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
586 s->blanked = 1;
588 s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
590 s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76);
592 iomemtype = cpu_register_io_memory(tc6393xb_readfn,
593 tc6393xb_writefn, s);
594 cpu_register_physical_memory(base, 0x10000, iomemtype);
596 s->vram_addr = qemu_ram_alloc(0x100000);
597 s->vram_ptr = qemu_get_ram_ptr(s->vram_addr);
598 cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr);
599 s->scr_width = 480;
600 s->scr_height = 640;
601 s->ds = graphic_console_init(tc6393xb_update_display,
602 NULL, /* invalidate */
603 NULL, /* screen_dump */
604 NULL, /* text_update */
607 return s;