Support PCI based option rom loading
[qemu.git] / hw / ppc405_boards.c
blob735adc95e30719af7e773bc68fcf00ec9a6080eb
1 /*
2 * QEMU PowerPC 405 evaluation boards emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "nvram.h"
28 #include "flash.h"
29 #include "sysemu.h"
30 #include "block.h"
31 #include "boards.h"
32 #include "qemu-log.h"
33 #include "loader.h"
35 #define BIOS_FILENAME "ppc405_rom.bin"
36 #define BIOS_SIZE (2048 * 1024)
38 #define KERNEL_LOAD_ADDR 0x00000000
39 #define INITRD_LOAD_ADDR 0x01800000
41 #define USE_FLASH_BIOS
43 #define DEBUG_BOARD_INIT
45 /*****************************************************************************/
46 /* PPC405EP reference board (IBM) */
47 /* Standalone board with:
48 * - PowerPC 405EP CPU
49 * - SDRAM (0x00000000)
50 * - Flash (0xFFF80000)
51 * - SRAM (0xFFF00000)
52 * - NVRAM (0xF0000000)
53 * - FPGA (0xF0300000)
55 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
56 struct ref405ep_fpga_t {
57 uint8_t reg0;
58 uint8_t reg1;
61 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
63 ref405ep_fpga_t *fpga;
64 uint32_t ret;
66 fpga = opaque;
67 switch (addr) {
68 case 0x0:
69 ret = fpga->reg0;
70 break;
71 case 0x1:
72 ret = fpga->reg1;
73 break;
74 default:
75 ret = 0;
76 break;
79 return ret;
82 static void ref405ep_fpga_writeb (void *opaque,
83 target_phys_addr_t addr, uint32_t value)
85 ref405ep_fpga_t *fpga;
87 fpga = opaque;
88 switch (addr) {
89 case 0x0:
90 /* Read only */
91 break;
92 case 0x1:
93 fpga->reg1 = value;
94 break;
95 default:
96 break;
100 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
102 uint32_t ret;
104 ret = ref405ep_fpga_readb(opaque, addr) << 8;
105 ret |= ref405ep_fpga_readb(opaque, addr + 1);
107 return ret;
110 static void ref405ep_fpga_writew (void *opaque,
111 target_phys_addr_t addr, uint32_t value)
113 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
114 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
117 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
119 uint32_t ret;
121 ret = ref405ep_fpga_readb(opaque, addr) << 24;
122 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
123 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
124 ret |= ref405ep_fpga_readb(opaque, addr + 3);
126 return ret;
129 static void ref405ep_fpga_writel (void *opaque,
130 target_phys_addr_t addr, uint32_t value)
132 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
133 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
134 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
135 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
138 static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
139 &ref405ep_fpga_readb,
140 &ref405ep_fpga_readw,
141 &ref405ep_fpga_readl,
144 static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
145 &ref405ep_fpga_writeb,
146 &ref405ep_fpga_writew,
147 &ref405ep_fpga_writel,
150 static void ref405ep_fpga_reset (void *opaque)
152 ref405ep_fpga_t *fpga;
154 fpga = opaque;
155 fpga->reg0 = 0x00;
156 fpga->reg1 = 0x0F;
159 static void ref405ep_fpga_init (uint32_t base)
161 ref405ep_fpga_t *fpga;
162 int fpga_memory;
164 fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
165 fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
166 ref405ep_fpga_write, fpga);
167 cpu_register_physical_memory(base, 0x00000100, fpga_memory);
168 qemu_register_reset(&ref405ep_fpga_reset, fpga);
171 static void ref405ep_init (ram_addr_t ram_size,
172 const char *boot_device,
173 const char *kernel_filename,
174 const char *kernel_cmdline,
175 const char *initrd_filename,
176 const char *cpu_model)
178 char *filename;
179 ppc4xx_bd_info_t bd;
180 CPUPPCState *env;
181 qemu_irq *pic;
182 ram_addr_t sram_offset, bios_offset, bdloc;
183 target_phys_addr_t ram_bases[2], ram_sizes[2];
184 target_ulong sram_size, bios_size;
185 //int phy_addr = 0;
186 //static int phy_addr = 1;
187 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
188 int linux_boot;
189 int fl_idx, fl_sectors, len;
190 int ppc_boot_device = boot_device[0];
191 DriveInfo *dinfo;
193 /* XXX: fix this */
194 ram_bases[0] = qemu_ram_alloc(0x08000000);
195 ram_sizes[0] = 0x08000000;
196 ram_bases[1] = 0x00000000;
197 ram_sizes[1] = 0x00000000;
198 ram_size = 128 * 1024 * 1024;
199 #ifdef DEBUG_BOARD_INIT
200 printf("%s: register cpu\n", __func__);
201 #endif
202 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
203 kernel_filename == NULL ? 0 : 1);
204 /* allocate SRAM */
205 sram_size = 512 * 1024;
206 sram_offset = qemu_ram_alloc(sram_size);
207 #ifdef DEBUG_BOARD_INIT
208 printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
209 #endif
210 cpu_register_physical_memory(0xFFF00000, sram_size,
211 sram_offset | IO_MEM_RAM);
212 /* allocate and load BIOS */
213 #ifdef DEBUG_BOARD_INIT
214 printf("%s: register BIOS\n", __func__);
215 #endif
216 fl_idx = 0;
217 #ifdef USE_FLASH_BIOS
218 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
219 if (dinfo) {
220 bios_size = bdrv_getlength(dinfo->bdrv);
221 bios_offset = qemu_ram_alloc(bios_size);
222 fl_sectors = (bios_size + 65535) >> 16;
223 #ifdef DEBUG_BOARD_INIT
224 printf("Register parallel flash %d size " TARGET_FMT_lx
225 " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
226 fl_idx, bios_size, bios_offset, -bios_size,
227 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
228 #endif
229 pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
230 dinfo->bdrv, 65536, fl_sectors, 1,
231 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
232 fl_idx++;
233 } else
234 #endif
236 #ifdef DEBUG_BOARD_INIT
237 printf("Load BIOS from file\n");
238 #endif
239 bios_offset = qemu_ram_alloc(BIOS_SIZE);
240 if (bios_name == NULL)
241 bios_name = BIOS_FILENAME;
242 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
243 if (filename) {
244 bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
245 qemu_free(filename);
246 } else {
247 bios_size = -1;
249 if (bios_size < 0 || bios_size > BIOS_SIZE) {
250 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
251 bios_name);
252 exit(1);
254 bios_size = (bios_size + 0xfff) & ~0xfff;
255 cpu_register_physical_memory((uint32_t)(-bios_size),
256 bios_size, bios_offset | IO_MEM_ROM);
258 /* Register FPGA */
259 #ifdef DEBUG_BOARD_INIT
260 printf("%s: register FPGA\n", __func__);
261 #endif
262 ref405ep_fpga_init(0xF0300000);
263 /* Register NVRAM */
264 #ifdef DEBUG_BOARD_INIT
265 printf("%s: register NVRAM\n", __func__);
266 #endif
267 m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
268 /* Load kernel */
269 linux_boot = (kernel_filename != NULL);
270 if (linux_boot) {
271 #ifdef DEBUG_BOARD_INIT
272 printf("%s: load kernel\n", __func__);
273 #endif
274 memset(&bd, 0, sizeof(bd));
275 bd.bi_memstart = 0x00000000;
276 bd.bi_memsize = ram_size;
277 bd.bi_flashstart = -bios_size;
278 bd.bi_flashsize = -bios_size;
279 bd.bi_flashoffset = 0;
280 bd.bi_sramstart = 0xFFF00000;
281 bd.bi_sramsize = sram_size;
282 bd.bi_bootflags = 0;
283 bd.bi_intfreq = 133333333;
284 bd.bi_busfreq = 33333333;
285 bd.bi_baudrate = 115200;
286 bd.bi_s_version[0] = 'Q';
287 bd.bi_s_version[1] = 'M';
288 bd.bi_s_version[2] = 'U';
289 bd.bi_s_version[3] = '\0';
290 bd.bi_r_version[0] = 'Q';
291 bd.bi_r_version[1] = 'E';
292 bd.bi_r_version[2] = 'M';
293 bd.bi_r_version[3] = 'U';
294 bd.bi_r_version[4] = '\0';
295 bd.bi_procfreq = 133333333;
296 bd.bi_plb_busfreq = 33333333;
297 bd.bi_pci_busfreq = 33333333;
298 bd.bi_opbfreq = 33333333;
299 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
300 env->gpr[3] = bdloc;
301 kernel_base = KERNEL_LOAD_ADDR;
302 /* now we can load the kernel */
303 kernel_size = load_image_targphys(kernel_filename, kernel_base,
304 ram_size - kernel_base);
305 if (kernel_size < 0) {
306 fprintf(stderr, "qemu: could not load kernel '%s'\n",
307 kernel_filename);
308 exit(1);
310 printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
311 kernel_size, kernel_base);
312 /* load initrd */
313 if (initrd_filename) {
314 initrd_base = INITRD_LOAD_ADDR;
315 initrd_size = load_image_targphys(initrd_filename, initrd_base,
316 ram_size - initrd_base);
317 if (initrd_size < 0) {
318 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
319 initrd_filename);
320 exit(1);
322 } else {
323 initrd_base = 0;
324 initrd_size = 0;
326 env->gpr[4] = initrd_base;
327 env->gpr[5] = initrd_size;
328 ppc_boot_device = 'm';
329 if (kernel_cmdline != NULL) {
330 len = strlen(kernel_cmdline);
331 bdloc -= ((len + 255) & ~255);
332 cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
333 env->gpr[6] = bdloc;
334 env->gpr[7] = bdloc + len;
335 } else {
336 env->gpr[6] = 0;
337 env->gpr[7] = 0;
339 env->nip = KERNEL_LOAD_ADDR;
340 } else {
341 kernel_base = 0;
342 kernel_size = 0;
343 initrd_base = 0;
344 initrd_size = 0;
345 bdloc = 0;
347 #ifdef DEBUG_BOARD_INIT
348 printf("%s: Done\n", __func__);
349 #endif
350 printf("bdloc %016lx\n", (unsigned long)bdloc);
353 static QEMUMachine ref405ep_machine = {
354 .name = "ref405ep",
355 .desc = "ref405ep",
356 .init = ref405ep_init,
359 /*****************************************************************************/
360 /* AMCC Taihu evaluation board */
361 /* - PowerPC 405EP processor
362 * - SDRAM 128 MB at 0x00000000
363 * - Boot flash 2 MB at 0xFFE00000
364 * - Application flash 32 MB at 0xFC000000
365 * - 2 serial ports
366 * - 2 ethernet PHY
367 * - 1 USB 1.1 device 0x50000000
368 * - 1 LCD display 0x50100000
369 * - 1 CPLD 0x50100000
370 * - 1 I2C EEPROM
371 * - 1 I2C thermal sensor
372 * - a set of LEDs
373 * - bit-bang SPI port using GPIOs
374 * - 1 EBC interface connector 0 0x50200000
375 * - 1 cardbus controller + expansion slot.
376 * - 1 PCI expansion slot.
378 typedef struct taihu_cpld_t taihu_cpld_t;
379 struct taihu_cpld_t {
380 uint8_t reg0;
381 uint8_t reg1;
384 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
386 taihu_cpld_t *cpld;
387 uint32_t ret;
389 cpld = opaque;
390 switch (addr) {
391 case 0x0:
392 ret = cpld->reg0;
393 break;
394 case 0x1:
395 ret = cpld->reg1;
396 break;
397 default:
398 ret = 0;
399 break;
402 return ret;
405 static void taihu_cpld_writeb (void *opaque,
406 target_phys_addr_t addr, uint32_t value)
408 taihu_cpld_t *cpld;
410 cpld = opaque;
411 switch (addr) {
412 case 0x0:
413 /* Read only */
414 break;
415 case 0x1:
416 cpld->reg1 = value;
417 break;
418 default:
419 break;
423 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
425 uint32_t ret;
427 ret = taihu_cpld_readb(opaque, addr) << 8;
428 ret |= taihu_cpld_readb(opaque, addr + 1);
430 return ret;
433 static void taihu_cpld_writew (void *opaque,
434 target_phys_addr_t addr, uint32_t value)
436 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
437 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
440 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
442 uint32_t ret;
444 ret = taihu_cpld_readb(opaque, addr) << 24;
445 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
446 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
447 ret |= taihu_cpld_readb(opaque, addr + 3);
449 return ret;
452 static void taihu_cpld_writel (void *opaque,
453 target_phys_addr_t addr, uint32_t value)
455 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
456 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
457 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
458 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
461 static CPUReadMemoryFunc * const taihu_cpld_read[] = {
462 &taihu_cpld_readb,
463 &taihu_cpld_readw,
464 &taihu_cpld_readl,
467 static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
468 &taihu_cpld_writeb,
469 &taihu_cpld_writew,
470 &taihu_cpld_writel,
473 static void taihu_cpld_reset (void *opaque)
475 taihu_cpld_t *cpld;
477 cpld = opaque;
478 cpld->reg0 = 0x01;
479 cpld->reg1 = 0x80;
482 static void taihu_cpld_init (uint32_t base)
484 taihu_cpld_t *cpld;
485 int cpld_memory;
487 cpld = qemu_mallocz(sizeof(taihu_cpld_t));
488 cpld_memory = cpu_register_io_memory(taihu_cpld_read,
489 taihu_cpld_write, cpld);
490 cpu_register_physical_memory(base, 0x00000100, cpld_memory);
491 qemu_register_reset(&taihu_cpld_reset, cpld);
494 static void taihu_405ep_init(ram_addr_t ram_size,
495 const char *boot_device,
496 const char *kernel_filename,
497 const char *kernel_cmdline,
498 const char *initrd_filename,
499 const char *cpu_model)
501 char *filename;
502 CPUPPCState *env;
503 qemu_irq *pic;
504 ram_addr_t bios_offset;
505 target_phys_addr_t ram_bases[2], ram_sizes[2];
506 target_ulong bios_size;
507 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
508 int linux_boot;
509 int fl_idx, fl_sectors;
510 int ppc_boot_device = boot_device[0];
511 DriveInfo *dinfo;
513 /* RAM is soldered to the board so the size cannot be changed */
514 ram_bases[0] = qemu_ram_alloc(0x04000000);
515 ram_sizes[0] = 0x04000000;
516 ram_bases[1] = qemu_ram_alloc(0x04000000);
517 ram_sizes[1] = 0x04000000;
518 ram_size = 0x08000000;
519 #ifdef DEBUG_BOARD_INIT
520 printf("%s: register cpu\n", __func__);
521 #endif
522 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
523 kernel_filename == NULL ? 0 : 1);
524 /* allocate and load BIOS */
525 #ifdef DEBUG_BOARD_INIT
526 printf("%s: register BIOS\n", __func__);
527 #endif
528 fl_idx = 0;
529 #if defined(USE_FLASH_BIOS)
530 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
531 if (dinfo) {
532 bios_size = bdrv_getlength(dinfo->bdrv);
533 /* XXX: should check that size is 2MB */
534 // bios_size = 2 * 1024 * 1024;
535 fl_sectors = (bios_size + 65535) >> 16;
536 bios_offset = qemu_ram_alloc(bios_size);
537 #ifdef DEBUG_BOARD_INIT
538 printf("Register parallel flash %d size " TARGET_FMT_lx
539 " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
540 fl_idx, bios_size, bios_offset, -bios_size,
541 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
542 #endif
543 pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
544 dinfo->bdrv, 65536, fl_sectors, 1,
545 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
546 fl_idx++;
547 } else
548 #endif
550 #ifdef DEBUG_BOARD_INIT
551 printf("Load BIOS from file\n");
552 #endif
553 if (bios_name == NULL)
554 bios_name = BIOS_FILENAME;
555 bios_offset = qemu_ram_alloc(BIOS_SIZE);
556 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
557 if (filename) {
558 bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
559 } else {
560 bios_size = -1;
562 if (bios_size < 0 || bios_size > BIOS_SIZE) {
563 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
564 bios_name);
565 exit(1);
567 bios_size = (bios_size + 0xfff) & ~0xfff;
568 cpu_register_physical_memory((uint32_t)(-bios_size),
569 bios_size, bios_offset | IO_MEM_ROM);
571 /* Register Linux flash */
572 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
573 if (dinfo) {
574 bios_size = bdrv_getlength(dinfo->bdrv);
575 /* XXX: should check that size is 32MB */
576 bios_size = 32 * 1024 * 1024;
577 fl_sectors = (bios_size + 65535) >> 16;
578 #ifdef DEBUG_BOARD_INIT
579 printf("Register parallel flash %d size " TARGET_FMT_lx
580 " at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
581 fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
582 bdrv_get_device_name(dinfo->bdrv));
583 #endif
584 bios_offset = qemu_ram_alloc(bios_size);
585 pflash_cfi02_register(0xfc000000, bios_offset,
586 dinfo->bdrv, 65536, fl_sectors, 1,
587 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
588 fl_idx++;
590 /* Register CLPD & LCD display */
591 #ifdef DEBUG_BOARD_INIT
592 printf("%s: register CPLD\n", __func__);
593 #endif
594 taihu_cpld_init(0x50100000);
595 /* Load kernel */
596 linux_boot = (kernel_filename != NULL);
597 if (linux_boot) {
598 #ifdef DEBUG_BOARD_INIT
599 printf("%s: load kernel\n", __func__);
600 #endif
601 kernel_base = KERNEL_LOAD_ADDR;
602 /* now we can load the kernel */
603 kernel_size = load_image_targphys(kernel_filename, kernel_base,
604 ram_size - kernel_base);
605 if (kernel_size < 0) {
606 fprintf(stderr, "qemu: could not load kernel '%s'\n",
607 kernel_filename);
608 exit(1);
610 /* load initrd */
611 if (initrd_filename) {
612 initrd_base = INITRD_LOAD_ADDR;
613 initrd_size = load_image_targphys(initrd_filename, initrd_base,
614 ram_size - initrd_base);
615 if (initrd_size < 0) {
616 fprintf(stderr,
617 "qemu: could not load initial ram disk '%s'\n",
618 initrd_filename);
619 exit(1);
621 } else {
622 initrd_base = 0;
623 initrd_size = 0;
625 ppc_boot_device = 'm';
626 } else {
627 kernel_base = 0;
628 kernel_size = 0;
629 initrd_base = 0;
630 initrd_size = 0;
632 #ifdef DEBUG_BOARD_INIT
633 printf("%s: Done\n", __func__);
634 #endif
637 static QEMUMachine taihu_machine = {
638 .name = "taihu",
639 .desc = "taihu",
640 .init = taihu_405ep_init,
643 static void ppc405_machine_init(void)
645 qemu_register_machine(&ref405ep_machine);
646 qemu_register_machine(&taihu_machine);
649 machine_init(ppc405_machine_init);