2 * QEMU MIPS Jazz support
4 * Copyright (c) 2007-2008 Hervé Poussineau
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "mips_cpudevs.h"
32 #include "arch_init.h"
36 #include "mips-bios.h"
38 #include "mc146818rtc.h"
41 #include "exec-memory.h"
49 static void main_cpu_reset(void *opaque
)
51 CPUState
*env
= opaque
;
55 static uint64_t rtc_read(void *opaque
, target_phys_addr_t addr
, unsigned size
)
60 static void rtc_write(void *opaque
, target_phys_addr_t addr
,
61 uint64_t val
, unsigned size
)
63 cpu_outw(0x71, val
& 0xff);
66 static const MemoryRegionOps rtc_ops
= {
69 .endianness
= DEVICE_NATIVE_ENDIAN
,
72 static uint64_t dma_dummy_read(void *opaque
, target_phys_addr_t addr
,
75 /* Nothing to do. That is only to ensure that
76 * the current DMA acknowledge cycle is completed. */
80 static void dma_dummy_write(void *opaque
, target_phys_addr_t addr
,
81 uint64_t val
, unsigned size
)
83 /* Nothing to do. That is only to ensure that
84 * the current DMA acknowledge cycle is completed. */
87 static const MemoryRegionOps dma_dummy_ops
= {
88 .read
= dma_dummy_read
,
89 .write
= dma_dummy_write
,
90 .endianness
= DEVICE_NATIVE_ENDIAN
,
93 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
94 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
96 static void cpu_request_exit(void *opaque
, int irq
, int level
)
98 CPUState
*env
= cpu_single_env
;
106 void mips_jazz_init (MemoryRegion
*address_space
, ram_addr_t ram_size
,
107 const char *cpu_model
,
108 enum jazz_model_e jazz_model
)
113 qemu_irq
*rc4030
, *i8259
;
116 MemoryRegion
*rtc
= g_new(MemoryRegion
, 1);
117 MemoryRegion
*dma_dummy
= g_new(MemoryRegion
, 1);
120 SysBusDevice
*sysbus
;
122 DriveInfo
*fds
[MAX_FD
];
123 qemu_irq esp_reset
, dma_enable
;
124 qemu_irq
*cpu_exit_irq
;
125 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
126 MemoryRegion
*bios
= g_new(MemoryRegion
, 1);
127 MemoryRegion
*bios2
= g_new(MemoryRegion
, 1);
130 if (cpu_model
== NULL
) {
134 /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
138 env
= cpu_init(cpu_model
);
140 fprintf(stderr
, "Unable to find CPU definition\n");
143 qemu_register_reset(main_cpu_reset
, env
);
146 memory_region_init_ram(ram
, NULL
, "mips_jazz.ram", ram_size
);
147 memory_region_add_subregion(address_space
, 0, ram
);
149 memory_region_init_ram(bios
, NULL
, "mips_jazz.bios", MAGNUM_BIOS_SIZE
);
150 memory_region_set_readonly(bios
, true);
151 memory_region_init_alias(bios2
, "mips_jazz.bios", bios
,
152 0, MAGNUM_BIOS_SIZE
);
153 memory_region_add_subregion(address_space
, 0x1fc00000LL
, bios
);
154 memory_region_add_subregion(address_space
, 0xfff00000LL
, bios2
);
156 /* load the BIOS image. */
157 if (bios_name
== NULL
)
158 bios_name
= BIOS_FILENAME
;
159 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
161 bios_size
= load_image_targphys(filename
, 0xfff00000LL
,
167 if (bios_size
< 0 || bios_size
> MAGNUM_BIOS_SIZE
) {
168 fprintf(stderr
, "qemu: Could not load MIPS bios '%s'\n",
173 /* Init CPU internal devices */
174 cpu_mips_irq_init_cpu(env
);
175 cpu_mips_clock_init(env
);
178 rc4030_opaque
= rc4030_init(env
->irq
[6], env
->irq
[3], &rc4030
, &dmas
);
179 memory_region_init_io(dma_dummy
, &dma_dummy_ops
, NULL
, "dummy_dma", 0x1000);
180 memory_region_add_subregion(address_space
, 0x8000d000, dma_dummy
);
183 i8259
= i8259_init(env
->irq
[4]);
186 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
187 DMA_init(0, cpu_exit_irq
);
188 pit
= pit_init(0x40, 0);
191 /* ISA IO space at 0x90000000 */
192 isa_mmio_init(0x90000000, 0x01000000);
193 isa_mem_base
= 0x11000000;
196 switch (jazz_model
) {
198 dev
= qdev_create(NULL
, "sysbus-g364");
199 qdev_init_nofail(dev
);
200 sysbus
= sysbus_from_qdev(dev
);
201 sysbus_mmio_map(sysbus
, 0, 0x60080000);
202 sysbus_mmio_map(sysbus
, 1, 0x40000000);
203 sysbus_connect_irq(sysbus
, 0, rc4030
[3]);
205 /* Simple ROM, so user doesn't have to provide one */
206 MemoryRegion
*rom_mr
= g_new(MemoryRegion
, 1);
207 memory_region_init_ram(rom_mr
, NULL
, "g364fb.rom", 0x80000);
208 memory_region_set_readonly(rom_mr
, true);
209 uint8_t *rom
= memory_region_get_ram_ptr(rom_mr
);
210 memory_region_add_subregion(address_space
, 0x60000000, rom_mr
);
211 rom
[0] = 0x10; /* Mips G364 */
215 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
221 /* Network controller */
222 for (n
= 0; n
< nb_nics
; n
++) {
225 nd
->model
= g_strdup("dp83932");
226 if (strcmp(nd
->model
, "dp83932") == 0) {
227 dp83932_init(nd
, 0x80001000, 2, rc4030
[4],
228 rc4030_opaque
, rc4030_dma_memory_rw
);
230 } else if (strcmp(nd
->model
, "?") == 0) {
231 fprintf(stderr
, "qemu: Supported NICs: dp83932\n");
234 fprintf(stderr
, "qemu: Unsupported NIC: %s\n", nd
->model
);
240 esp_init(0x80002000, 0,
241 rc4030_dma_read
, rc4030_dma_write
, dmas
[0],
242 rc4030
[5], &esp_reset
, &dma_enable
);
245 if (drive_get_max_bus(IF_FLOPPY
) >= MAX_FD
) {
246 fprintf(stderr
, "qemu: too many floppy drives\n");
249 for (n
= 0; n
< MAX_FD
; n
++) {
250 fds
[n
] = drive_get(IF_FLOPPY
, 0, n
);
252 fdctrl_init_sysbus(rc4030
[1], 0, 0x80003000, fds
);
254 /* Real time clock */
255 rtc_init(1980, NULL
);
256 memory_region_init_io(rtc
, &rtc_ops
, NULL
, "rtc", 0x1000);
257 memory_region_add_subregion(address_space
, 0x80004000, rtc
);
259 /* Keyboard (i8042) */
260 i8042_mm_init(rc4030
[6], rc4030
[7], 0x80005000, 0x1000, 0x1);
264 #ifdef TARGET_WORDS_BIGENDIAN
265 serial_mm_init(0x80006000, 0, rc4030
[8], 8000000/16, serial_hds
[0], 1, 1);
267 serial_mm_init(0x80006000, 0, rc4030
[8], 8000000/16, serial_hds
[0], 1, 0);
271 #ifdef TARGET_WORDS_BIGENDIAN
272 serial_mm_init(0x80007000, 0, rc4030
[9], 8000000/16, serial_hds
[1], 1, 1);
274 serial_mm_init(0x80007000, 0, rc4030
[9], 8000000/16, serial_hds
[1], 1, 0);
280 parallel_mm_init(0x80008000, 0, rc4030
[0], parallel_hds
[0]);
283 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
284 audio_init(i8259
, NULL
);
287 dev
= qdev_create(NULL
, "ds1225y");
288 qdev_init_nofail(dev
);
289 sysbus
= sysbus_from_qdev(dev
);
290 sysbus_mmio_map(sysbus
, 0, 0x80009000);
293 jazz_led_init(0x8000f000);
297 void mips_magnum_init (ram_addr_t ram_size
,
298 const char *boot_device
,
299 const char *kernel_filename
, const char *kernel_cmdline
,
300 const char *initrd_filename
, const char *cpu_model
)
302 mips_jazz_init(get_system_memory(), ram_size
, cpu_model
, JAZZ_MAGNUM
);
306 void mips_pica61_init (ram_addr_t ram_size
,
307 const char *boot_device
,
308 const char *kernel_filename
, const char *kernel_cmdline
,
309 const char *initrd_filename
, const char *cpu_model
)
311 mips_jazz_init(get_system_memory(), ram_size
, cpu_model
, JAZZ_PICA61
);
314 static QEMUMachine mips_magnum_machine
= {
316 .desc
= "MIPS Magnum",
317 .init
= mips_magnum_init
,
321 static QEMUMachine mips_pica61_machine
= {
323 .desc
= "Acer Pica 61",
324 .init
= mips_pica61_init
,
328 static void mips_jazz_machine_init(void)
330 qemu_register_machine(&mips_magnum_machine
);
331 qemu_register_machine(&mips_pica61_machine
);
334 machine_init(mips_jazz_machine_init
);