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kvmvapic: Use QOM realize
[qemu.git] / disas / s390.c
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1 /* opcodes/s390-dis.c revision 1.12 */
2 /* s390-dis.c -- Disassemble S390 instructions
3 Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
4 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
5
6 This file is part of GDB, GAS and the GNU binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "qemu-common.h"
24 #include "disas/bfd.h"
25
26 /* include/opcode/s390.h revision 1.9 */
27 /* s390.h -- Header file for S390 opcode table
28 Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
29 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
30
31 This file is part of BFD, the Binary File Descriptor library.
32
33 This program is free software; you can redistribute it and/or modify
34 it under the terms of the GNU General Public License as published by
35 the Free Software Foundation; either version 2 of the License, or
36 (at your option) any later version.
37
38 This program is distributed in the hope that it will be useful,
39 but WITHOUT ANY WARRANTY; without even the implied warranty of
40 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41 GNU General Public License for more details.
42
43 You should have received a copy of the GNU General Public License
44 along with this program; if not, write to the Free Software
45 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
46 02110-1301, USA. */
47
48 #ifndef S390_H
49 #define S390_H
50
51 /* List of instruction sets variations. */
52
53 enum s390_opcode_mode_val
54 {
55 S390_OPCODE_ESA = 0,
56 S390_OPCODE_ZARCH
57 };
58
59 enum s390_opcode_cpu_val
60 {
61 S390_OPCODE_G5 = 0,
62 S390_OPCODE_G6,
63 S390_OPCODE_Z900,
64 S390_OPCODE_Z990,
65 S390_OPCODE_Z9_109,
66 S390_OPCODE_Z9_EC,
67 S390_OPCODE_Z10
68 };
69
70 /* The opcode table is an array of struct s390_opcode. */
71
72 struct s390_opcode
73 {
74 /* The opcode name. */
75 const char * name;
76
77 /* The opcode itself. Those bits which will be filled in with
78 operands are zeroes. */
79 unsigned char opcode[6];
80
81 /* The opcode mask. This is used by the disassembler. This is a
82 mask containing ones indicating those bits which must match the
83 opcode field, and zeroes indicating those bits which need not
84 match (and are presumably filled in by operands). */
85 unsigned char mask[6];
86
87 /* The opcode length in bytes. */
88 int oplen;
89
90 /* An array of operand codes. Each code is an index into the
91 operand table. They appear in the order which the operands must
92 appear in assembly code, and are terminated by a zero. */
93 unsigned char operands[6];
94
95 /* Bitmask of execution modes this opcode is available for. */
96 unsigned int modes;
97
98 /* First cpu this opcode is available for. */
99 enum s390_opcode_cpu_val min_cpu;
100 };
101
102 /* The table itself is sorted by major opcode number, and is otherwise
103 in the order in which the disassembler should consider
104 instructions. */
105 /* QEMU: Mark these static. */
106 static const struct s390_opcode s390_opcodes[];
107 static const int s390_num_opcodes;
108
109 /* A opcode format table for the .insn pseudo mnemonic. */
110 static const struct s390_opcode s390_opformats[];
111 static const int s390_num_opformats;
112
113 /* Values defined for the flags field of a struct powerpc_opcode. */
114
115 /* The operands table is an array of struct s390_operand. */
116
117 struct s390_operand
118 {
119 /* The number of bits in the operand. */
120 int bits;
121
122 /* How far the operand is left shifted in the instruction. */
123 int shift;
124
125 /* One bit syntax flags. */
126 unsigned long flags;
127 };
128
129 /* Elements in the table are retrieved by indexing with values from
130 the operands field of the powerpc_opcodes table. */
131
132 static const struct s390_operand s390_operands[];
133
134 /* Values defined for the flags field of a struct s390_operand. */
135
136 /* This operand names a register. The disassembler uses this to print
137 register names with a leading 'r'. */
138 #define S390_OPERAND_GPR 0x1
139
140 /* This operand names a floating point register. The disassembler
141 prints these with a leading 'f'. */
142 #define S390_OPERAND_FPR 0x2
143
144 /* This operand names an access register. The disassembler
145 prints these with a leading 'a'. */
146 #define S390_OPERAND_AR 0x4
147
148 /* This operand names a control register. The disassembler
149 prints these with a leading 'c'. */
150 #define S390_OPERAND_CR 0x8
151
152 /* This operand is a displacement. */
153 #define S390_OPERAND_DISP 0x10
154
155 /* This operand names a base register. */
156 #define S390_OPERAND_BASE 0x20
157
158 /* This operand names an index register, it can be skipped. */
159 #define S390_OPERAND_INDEX 0x40
160
161 /* This operand is a relative branch displacement. The disassembler
162 prints these symbolically if possible. */
163 #define S390_OPERAND_PCREL 0x80
164
165 /* This operand takes signed values. */
166 #define S390_OPERAND_SIGNED 0x100
167
168 /* This operand is a length. */
169 #define S390_OPERAND_LENGTH 0x200
170
171 /* This operand is optional. Only a single operand at the end of
172 the instruction may be optional. */
173 #define S390_OPERAND_OPTIONAL 0x400
174
175 /* QEMU-ADD */
176 /* ??? Not quite the format the assembler takes, but easy to implement
177 without recourse to the table generator. */
178 #define S390_OPERAND_CCODE 0x800
179
180 static const char s390_ccode_name[16][4] = {
181 "n", /* 0000 */
182 "o", /* 0001 */
183 "h", /* 0010 */
184 "nle", /* 0011 */
185 "l", /* 0100 */
186 "nhe", /* 0101 */
187 "lh", /* 0110 */
188 "ne", /* 0111 */
189 "e", /* 1000 */
190 "nlh", /* 1001 */
191 "he", /* 1010 */
192 "nl", /* 1011 */
193 "le", /* 1100 */
194 "nh", /* 1101 */
195 "no", /* 1110 */
196 "a" /* 1111 */
197 };
198 /* QEMU-END */
199
200 #endif /* S390_H */
201
202 static int init_flag = 0;
203 static int opc_index[256];
204
205 /* QEMU: We've disabled the architecture check below. */
206 /* static int current_arch_mask = 0; */
207
208 /* Set up index table for first opcode byte. */
209
210 static void
211 init_disasm (struct disassemble_info *info)
212 {
213 const struct s390_opcode *opcode;
214 const struct s390_opcode *opcode_end;
215
216 memset (opc_index, 0, sizeof (opc_index));
217 opcode_end = s390_opcodes + s390_num_opcodes;
218 for (opcode = s390_opcodes; opcode < opcode_end; opcode++)
219 {
220 opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes;
221 while ((opcode < opcode_end) &&
222 (opcode[1].opcode[0] == opcode->opcode[0]))
223 opcode++;
224 }
225
226 #ifdef QEMU_DISABLE
227 switch (info->mach)
228 {
229 case bfd_mach_s390_31:
230 current_arch_mask = 1 << S390_OPCODE_ESA;
231 break;
232 case bfd_mach_s390_64:
233 current_arch_mask = 1 << S390_OPCODE_ZARCH;
234 break;
235 default:
236 abort ();
237 }
238 #endif /* QEMU_DISABLE */
239
240 init_flag = 1;
241 }
242
243 /* Extracts an operand value from an instruction. */
244
245 static inline unsigned int
246 s390_extract_operand (unsigned char *insn, const struct s390_operand *operand)
247 {
248 unsigned int val;
249 int bits;
250
251 /* Extract fragments of the operand byte for byte. */
252 insn += operand->shift / 8;
253 bits = (operand->shift & 7) + operand->bits;
254 val = 0;
255 do
256 {
257 val <<= 8;
258 val |= (unsigned int) *insn++;
259 bits -= 8;
260 }
261 while (bits > 0);
262 val >>= -bits;
263 val &= ((1U << (operand->bits - 1)) << 1) - 1;
264
265 /* Check for special long displacement case. */
266 if (operand->bits == 20 && operand->shift == 20)
267 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8;
268
269 /* Sign extend value if the operand is signed or pc relative. */
270 if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL))
271 && (val & (1U << (operand->bits - 1))))
272 val |= (-1U << (operand->bits - 1)) << 1;
273
274 /* Double value if the operand is pc relative. */
275 if (operand->flags & S390_OPERAND_PCREL)
276 val <<= 1;
277
278 /* Length x in an instructions has real length x + 1. */
279 if (operand->flags & S390_OPERAND_LENGTH)
280 val++;
281 return val;
282 }
283
284 /* Print a S390 instruction. */
285
286 int
287 print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
288 {
289 bfd_byte buffer[6];
290 const struct s390_opcode *opcode;
291 const struct s390_opcode *opcode_end;
292 unsigned int value;
293 int status, opsize, bufsize;
294 char separator;
295
296 if (init_flag == 0)
297 init_disasm (info);
298
299 /* The output looks better if we put 6 bytes on a line. */
300 info->bytes_per_line = 6;
301
302 /* Every S390 instruction is max 6 bytes long. */
303 memset (buffer, 0, 6);
304 status = (*info->read_memory_func) (memaddr, buffer, 6, info);
305 if (status != 0)
306 {
307 for (bufsize = 0; bufsize < 6; bufsize++)
308 if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0)
309 break;
310 if (bufsize <= 0)
311 {
312 (*info->memory_error_func) (status, memaddr, info);
313 return -1;
314 }
315 /* Opsize calculation looks strange but it works
316 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes,
317 11xxxxxx -> 6 bytes. */
318 opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1;
319 status = opsize > bufsize;
320 }
321 else
322 {
323 bufsize = 6;
324 opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1;
325 }
326
327 if (status == 0)
328 {
329 /* Find the first match in the opcode table. */
330 opcode_end = s390_opcodes + s390_num_opcodes;
331 for (opcode = s390_opcodes + opc_index[(int) buffer[0]];
332 (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]);
333 opcode++)
334 {
335 const struct s390_operand *operand;
336 const unsigned char *opindex;
337
338 #ifdef QEMU_DISABLE
339 /* Check architecture. */
340 if (!(opcode->modes & current_arch_mask))
341 continue;
342 #endif /* QEMU_DISABLE */
343
344 /* Check signature of the opcode. */
345 if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1]
346 || (buffer[2] & opcode->mask[2]) != opcode->opcode[2]
347 || (buffer[3] & opcode->mask[3]) != opcode->opcode[3]
348 || (buffer[4] & opcode->mask[4]) != opcode->opcode[4]
349 || (buffer[5] & opcode->mask[5]) != opcode->opcode[5])
350 continue;
351
352 /* The instruction is valid. */
353 /* QEMU-MOD */
354 (*info->fprintf_func) (info->stream, "%s", opcode->name);
355
356 if (s390_operands[opcode->operands[0]].flags & S390_OPERAND_CCODE)
357 separator = 0;
358 else
359 separator = '\t';
360 /* QEMU-END */
361
362 /* Extract the operands. */
363 for (opindex = opcode->operands; *opindex != 0; opindex++)
364 {
365 unsigned int value;
366
367 operand = s390_operands + *opindex;
368 value = s390_extract_operand (buffer, operand);
369
370 if ((operand->flags & S390_OPERAND_INDEX) && value == 0)
371 continue;
372 if ((operand->flags & S390_OPERAND_BASE) &&
373 value == 0 && separator == '(')
374 {
375 separator = ',';
376 continue;
377 }
378
379 if (separator)
380 (*info->fprintf_func) (info->stream, "%c", separator);
381
382 if (operand->flags & S390_OPERAND_GPR)
383 (*info->fprintf_func) (info->stream, "%%r%i", value);
384 else if (operand->flags & S390_OPERAND_FPR)
385 (*info->fprintf_func) (info->stream, "%%f%i", value);
386 else if (operand->flags & S390_OPERAND_AR)
387 (*info->fprintf_func) (info->stream, "%%a%i", value);
388 else if (operand->flags & S390_OPERAND_CR)
389 (*info->fprintf_func) (info->stream, "%%c%i", value);
390 else if (operand->flags & S390_OPERAND_PCREL)
391 (*info->print_address_func) (memaddr + (int) value, info);
392 else if (operand->flags & S390_OPERAND_SIGNED)
393 (*info->fprintf_func) (info->stream, "%i", (int) value);
394 /* QEMU-ADD */
395 else if (operand->flags & S390_OPERAND_CCODE)
396 {
397 (*info->fprintf_func) (info->stream, "%s",
398 s390_ccode_name[(int) value]);
399 separator = '\t';
400 continue;
401 }
402 /* QEMU-END */
403 else
404 (*info->fprintf_func) (info->stream, "%u", value);
405
406 if (operand->flags & S390_OPERAND_DISP)
407 {
408 separator = '(';
409 }
410 else if (operand->flags & S390_OPERAND_BASE)
411 {
412 (*info->fprintf_func) (info->stream, ")");
413 separator = ',';
414 }
415 else
416 separator = ',';
417 }
418
419 /* Found instruction, printed it, return its size. */
420 return opsize;
421 }
422 /* No matching instruction found, fall through to hex print. */
423 }
424
425 if (bufsize >= 4)
426 {
427 value = (unsigned int) buffer[0];
428 value = (value << 8) + (unsigned int) buffer[1];
429 value = (value << 8) + (unsigned int) buffer[2];
430 value = (value << 8) + (unsigned int) buffer[3];
431 (*info->fprintf_func) (info->stream, ".long\t0x%08x", value);
432 return 4;
433 }
434 else if (bufsize >= 2)
435 {
436 value = (unsigned int) buffer[0];
437 value = (value << 8) + (unsigned int) buffer[1];
438 (*info->fprintf_func) (info->stream, ".short\t0x%04x", value);
439 return 2;
440 }
441 else
442 {
443 value = (unsigned int) buffer[0];
444 (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value);
445 return 1;
446 }
447 }
448
449 /* opcodes/s390-opc.c revision 1.16 */
450 /* s390-opc.c -- S390 opcode list
451 Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
452 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
453
454 This file is part of GDB, GAS, and the GNU binutils.
455
456 This program is free software; you can redistribute it and/or modify
457 it under the terms of the GNU General Public License as published by
458 the Free Software Foundation; either version 2 of the License, or
459 (at your option) any later version.
460
461 This program is distributed in the hope that it will be useful,
462 but WITHOUT ANY WARRANTY; without even the implied warranty of
463 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
464 GNU General Public License for more details.
465
466 You should have received a copy of the GNU General Public License
467 along with this program; if not, write to the Free Software
468 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
469 02110-1301, USA. */
470
471 /* This file holds the S390 opcode table. The opcode table
472 includes almost all of the extended instruction mnemonics. This
473 permits the disassembler to use them, and simplifies the assembler
474 logic, at the cost of increasing the table size. The table is
475 strictly constant data, so the compiler should be able to put it in
476 the .text section.
477
478 This file also holds the operand table. All knowledge about
479 inserting operands into instructions and vice-versa is kept in this
480 file. */
481
482 /* The operands table.
483 The fields are bits, shift, insert, extract, flags. */
484
485 static const struct s390_operand s390_operands[] =
486 {
487 #define UNUSED 0
488 { 0, 0, 0 }, /* Indicates the end of the operand list */
489
490 #define R_8 1 /* GPR starting at position 8 */
491 { 4, 8, S390_OPERAND_GPR },
492 #define R_12 2 /* GPR starting at position 12 */
493 { 4, 12, S390_OPERAND_GPR },
494 #define R_16 3 /* GPR starting at position 16 */
495 { 4, 16, S390_OPERAND_GPR },
496 #define R_20 4 /* GPR starting at position 20 */
497 { 4, 20, S390_OPERAND_GPR },
498 #define R_24 5 /* GPR starting at position 24 */
499 { 4, 24, S390_OPERAND_GPR },
500 #define R_28 6 /* GPR starting at position 28 */
501 { 4, 28, S390_OPERAND_GPR },
502 #define R_32 7 /* GPR starting at position 32 */
503 { 4, 32, S390_OPERAND_GPR },
504
505 #define F_8 8 /* FPR starting at position 8 */
506 { 4, 8, S390_OPERAND_FPR },
507 #define F_12 9 /* FPR starting at position 12 */
508 { 4, 12, S390_OPERAND_FPR },
509 #define F_16 10 /* FPR starting at position 16 */
510 { 4, 16, S390_OPERAND_FPR },
511 #define F_20 11 /* FPR starting at position 16 */
512 { 4, 16, S390_OPERAND_FPR },
513 #define F_24 12 /* FPR starting at position 24 */
514 { 4, 24, S390_OPERAND_FPR },
515 #define F_28 13 /* FPR starting at position 28 */
516 { 4, 28, S390_OPERAND_FPR },
517 #define F_32 14 /* FPR starting at position 32 */
518 { 4, 32, S390_OPERAND_FPR },
519
520 #define A_8 15 /* Access reg. starting at position 8 */
521 { 4, 8, S390_OPERAND_AR },
522 #define A_12 16 /* Access reg. starting at position 12 */
523 { 4, 12, S390_OPERAND_AR },
524 #define A_24 17 /* Access reg. starting at position 24 */
525 { 4, 24, S390_OPERAND_AR },
526 #define A_28 18 /* Access reg. starting at position 28 */
527 { 4, 28, S390_OPERAND_AR },
528
529 #define C_8 19 /* Control reg. starting at position 8 */
530 { 4, 8, S390_OPERAND_CR },
531 #define C_12 20 /* Control reg. starting at position 12 */
532 { 4, 12, S390_OPERAND_CR },
533
534 #define B_16 21 /* Base register starting at position 16 */
535 { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
536 #define B_32 22 /* Base register starting at position 32 */
537 { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
538
539 #define X_12 23 /* Index register starting at position 12 */
540 { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
541
542 #define D_20 24 /* Displacement starting at position 20 */
543 { 12, 20, S390_OPERAND_DISP },
544 #define D_36 25 /* Displacement starting at position 36 */
545 { 12, 36, S390_OPERAND_DISP },
546 #define D20_20 26 /* 20 bit displacement starting at 20 */
547 { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
548
549 #define L4_8 27 /* 4 bit length starting at position 8 */
550 { 4, 8, S390_OPERAND_LENGTH },
551 #define L4_12 28 /* 4 bit length starting at position 12 */
552 { 4, 12, S390_OPERAND_LENGTH },
553 #define L8_8 29 /* 8 bit length starting at position 8 */
554 { 8, 8, S390_OPERAND_LENGTH },
555
556 #define U4_8 30 /* 4 bit unsigned value starting at 8 */
557 { 4, 8, 0 },
558 #define U4_12 31 /* 4 bit unsigned value starting at 12 */
559 { 4, 12, 0 },
560 #define U4_16 32 /* 4 bit unsigned value starting at 16 */
561 { 4, 16, 0 },
562 #define U4_20 33 /* 4 bit unsigned value starting at 20 */
563 { 4, 20, 0 },
564 #define U8_8 34 /* 8 bit unsigned value starting at 8 */
565 { 8, 8, 0 },
566 #define U8_16 35 /* 8 bit unsigned value starting at 16 */
567 { 8, 16, 0 },
568 #define I16_16 36 /* 16 bit signed value starting at 16 */
569 { 16, 16, S390_OPERAND_SIGNED },
570 #define U16_16 37 /* 16 bit unsigned value starting at 16 */
571 { 16, 16, 0 },
572 #define J16_16 38 /* PC relative jump offset at 16 */
573 { 16, 16, S390_OPERAND_PCREL },
574 #define J32_16 39 /* PC relative long offset at 16 */
575 { 32, 16, S390_OPERAND_PCREL },
576 #define I32_16 40 /* 32 bit signed value starting at 16 */
577 { 32, 16, S390_OPERAND_SIGNED },
578 #define U32_16 41 /* 32 bit unsigned value starting at 16 */
579 { 32, 16, 0 },
580 #define M_16 42 /* 4 bit optional mask starting at 16 */
581 { 4, 16, S390_OPERAND_OPTIONAL },
582 #define RO_28 43 /* optional GPR starting at position 28 */
583 { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },
584
585 /* QEMU-ADD: */
586 #define M4_12 44 /* 4-bit condition-code starting at 12 */
587 { 4, 12, S390_OPERAND_CCODE },
588 #define M4_32 45 /* 4-bit condition-code starting at 32 */
589 { 4, 32, S390_OPERAND_CCODE },
590 #define I8_32 46 /* 8 bit signed value starting at 32 */
591 { 8, 32, S390_OPERAND_SIGNED },
592 #define U8_24 47 /* 8 bit unsigned value starting at 24 */
593 { 8, 24, 0 },
594 #define U8_32 48 /* 8 bit unsigned value starting at 32 */
595 { 8, 32, 0 },
596 #define I16_32 49
597 { 16, 32, S390_OPERAND_SIGNED },
598 #define M4_16 50 /* 4-bit condition-code starting at 12 */
599 { 4, 16, S390_OPERAND_CCODE },
600 #define I8_16 51
601 { 8, 16, S390_OPERAND_SIGNED },
602 /* QEMU-END */
603 };
604
605
606 /* Macros used to form opcodes. */
607
608 /* 8/16/48 bit opcodes. */
609 #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
610 #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
611 #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
612 (x >> 16) & 255, (x >> 8) & 255, x & 255}
613
614 /* The new format of the INSTR_x_y and MASK_x_y defines is based
615 on the following rules:
616 1) the middle part of the definition (x in INSTR_x_y) is the official
617 names of the instruction format that you can find in the principals
618 of operation.
619 2) the last part of the definition (y in INSTR_x_y) gives you an idea
620 which operands the binary represenation of the instruction has.
621 The meanings of the letters in y are:
622 a - access register
623 c - control register
624 d - displacement, 12 bit
625 f - floating pointer register
626 i - signed integer, 4, 8, 16 or 32 bit
627 l - length, 4 or 8 bit
628 p - pc relative
629 r - general purpose register
630 u - unsigned integer, 4, 8, 16 or 32 bit
631 m - mode field, 4 bit
632 0 - operand skipped.
633 The order of the letters reflects the layout of the format in
634 storage and not the order of the paramaters of the instructions.
635 The use of the letters is not a 100% match with the PoP but it is
636 quite close.
637
638 For example the instruction "mvo" is defined in the PoP as follows:
639
640 MVO D1(L1,B1),D2(L2,B2) [SS]
641
642 --------------------------------------
643 | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
644 --------------------------------------
645 0 8 12 16 20 32 36
646
647 The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
648
649 #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
650 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
651 #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
652 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
653 #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
654 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
655 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
656 #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */
657 #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
658 #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
659 #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
660 #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */
661 #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */
662 #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
663 #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
664 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
665 #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */
666 #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
667 #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */
668 #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
669 #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */
670 #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
671 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
672 /* Actually efpc and sfpc do not take an optional operand.
673 This is just a workaround for existing code e.g. glibc. */
674 #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */
675 #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
676 /* QEMU-MOD */
677 #define INSTR_RRF_F0FF2 4, { F_24,F_28,F_16,0,0,0 } /* e.g. cpsdr */
678 /* QEMU-END */
679 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
680 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
681 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
682 #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */
683 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
684 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
685 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
686 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */
687 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
688 #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */
689 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
690 #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
691 #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
692 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
693 #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
694 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
695 #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */
696 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
697 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */
698 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
699 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */
700 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
701 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
702 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */
703 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */
704 #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */
705 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
706 #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
707 #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
708 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
709 #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
710 #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
711 #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */
712 #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */
713 #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */
714 #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */
715 #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */
716 #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
717 #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
718 #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
719 #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
720 #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
721 #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */
722 #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
723 #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
724 #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */
725 #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
726 #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
727 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
728 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
729 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
730 #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
731 #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
732 #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
733
734 #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
735 #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
736 #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
737 #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
738 #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
739 #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
740 #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
741 #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
742 #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
743 #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
744 #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
745 #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
746 #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
747 #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
748 #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
749 #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
750 #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
751 #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
752 #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
753 #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
754 #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
755 #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
756 #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
757 #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
758 #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
759 #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
760 #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
761 #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
762 #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
763 #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
764 #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
765 #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
766 #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
767 #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
768 #define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
769 #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
770 #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
771 #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
772 #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
773 #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
774 #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
775 #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
776 #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
777 #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
778 #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
779 #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
780 #define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
781 #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
782 #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
783 #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
784 #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
785 #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
786 #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
787 #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
788 #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
789 #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
790 #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
791 #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
792 #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
793 #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
794 #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
795 #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
796 #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
797 #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
798 #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
799 #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
800 #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
801 #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
802 #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
803 #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
804 #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
805 #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
806 #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
807 #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
808 #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
809 #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
810 #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
811 #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
812 #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
813 #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
814
815 /* QEMU-ADD: */
816 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
817 #define MASK_RIE_MRRP { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
818
819 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
820 #define MASK_RIE_MRIP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
821
822 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
823 #define MASK_RIE_RRIII { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
824 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
825 #define MASK_RIE_MRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
826 #define INSTR_RIE_MRU 6, { M4_32, R_8, U16_16, 0, 0, 0 } /* e.g. clfit */
827 #define MASK_RIE_MRU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
828 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
829 #define MASK_RIE_RRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
830
831 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 }
832 #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
833
834 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 }
835 #define MASK_SIL_DRI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
836
837 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 }
838 #define MASK_SRY_MRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
839
840 #define INSTR_RRF_MRR 6, { M4_16, R_24, R_28, 0, 0, 0 }
841 #define MASK_RRF_MRR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
842
843 #define INSTR_SIY_DRI 6, { D20_20, B_16, I8_16, 0, 0, 0 }
844 #define MASK_SIY_DRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
845 /* QEMU-END */
846
847 /* The opcode formats table (blueprints for .insn pseudo mnemonic). */
848
849 static const struct s390_opcode s390_opformats[] =
850 {
851 { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 },
852 { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 },
853 { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 },
854 { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 },
855 { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 },
856 { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 },
857 { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 },
858 { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 },
859 { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 },
860 { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 },
861 { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 },
862 { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 },
863 { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 },
864 { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 },
865 { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 },
866 { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 },
867 { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 },
868 { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 },
869 { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 },
870 { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
871 { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 },
872 { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 },
873 };
874
875 static const int s390_num_opformats =
876 sizeof (s390_opformats) / sizeof (s390_opformats[0]);
877
878 /* include "s390-opc.tab" generated from opcodes/s390-opc.txt rev 1.17 */
879 /* The opcode table. This file was generated by s390-mkopc.
880
881 The format of the opcode table is:
882
883 NAME OPCODE MASK OPERANDS
884
885 Name is the name of the instruction.
886 OPCODE is the instruction opcode.
887 MASK is the opcode mask; this is used to tell the disassembler
888 which bits in the actual opcode must match OPCODE.
889 OPERANDS is the list of operands.
890
891 The disassembler reads the table in order and prints the first
892 instruction which matches. */
893
894 static const struct s390_opcode s390_opcodes[] =
895 {
896 { "dp", OP8(0xfdLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
897 { "mp", OP8(0xfcLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
898 { "sp", OP8(0xfbLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
899 { "ap", OP8(0xfaLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
900 { "cp", OP8(0xf9LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
901 { "zap", OP8(0xf8LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
902 { "unpk", OP8(0xf3LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
903 { "pack", OP8(0xf2LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
904 { "mvo", OP8(0xf1LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
905 { "srp", OP8(0xf0LL), MASK_SS_LIRDRD, INSTR_SS_LIRDRD, 3, 0},
906 { "lmd", OP8(0xefLL), MASK_SS_RRRDRD3, INSTR_SS_RRRDRD3, 2, 2},
907 { "plo", OP8(0xeeLL), MASK_SS_RRRDRD2, INSTR_SS_RRRDRD2, 3, 0},
908 { "stdy", OP48(0xed0000000067LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
909 { "stey", OP48(0xed0000000066LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
910 { "ldy", OP48(0xed0000000065LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
911 { "ley", OP48(0xed0000000064LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
912 { "tgxt", OP48(0xed0000000059LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
913 { "tcxt", OP48(0xed0000000058LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
914 { "tgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
915 { "tcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
916 { "tget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
917 { "tcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
918 { "srxt", OP48(0xed0000000049LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
919 { "slxt", OP48(0xed0000000048LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
920 { "srdt", OP48(0xed0000000041LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
921 { "sldt", OP48(0xed0000000040LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
922 { "msd", OP48(0xed000000003fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
923 { "mad", OP48(0xed000000003eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
924 { "myh", OP48(0xed000000003dLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
925 { "mayh", OP48(0xed000000003cLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
926 { "my", OP48(0xed000000003bLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
927 { "may", OP48(0xed000000003aLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
928 { "myl", OP48(0xed0000000039LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
929 { "mayl", OP48(0xed0000000038LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
930 { "mee", OP48(0xed0000000037LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
931 { "sqe", OP48(0xed0000000034LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
932 { "mse", OP48(0xed000000002fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
933 { "mae", OP48(0xed000000002eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
934 { "lxe", OP48(0xed0000000026LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
935 { "lxd", OP48(0xed0000000025LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
936 { "lde", OP48(0xed0000000024LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
937 { "msdb", OP48(0xed000000001fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
938 { "madb", OP48(0xed000000001eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
939 { "ddb", OP48(0xed000000001dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
940 { "mdb", OP48(0xed000000001cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
941 { "sdb", OP48(0xed000000001bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
942 { "adb", OP48(0xed000000001aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
943 { "cdb", OP48(0xed0000000019LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
944 { "kdb", OP48(0xed0000000018LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
945 { "meeb", OP48(0xed0000000017LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
946 { "sqdb", OP48(0xed0000000015LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
947 { "sqeb", OP48(0xed0000000014LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
948 { "tcxb", OP48(0xed0000000012LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
949 { "tcdb", OP48(0xed0000000011LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
950 { "tceb", OP48(0xed0000000010LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
951 { "mseb", OP48(0xed000000000fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
952 { "maeb", OP48(0xed000000000eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
953 { "deb", OP48(0xed000000000dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
954 { "mdeb", OP48(0xed000000000cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
955 { "seb", OP48(0xed000000000bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
956 { "aeb", OP48(0xed000000000aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
957 { "ceb", OP48(0xed0000000009LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
958 { "keb", OP48(0xed0000000008LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
959 { "mxdb", OP48(0xed0000000007LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
960 { "lxeb", OP48(0xed0000000006LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
961 { "lxdb", OP48(0xed0000000005LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
962 { "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
963 { "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
964 { "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
965 /* QEMU-ADD: */
966 { "crj", OP48(0xec0000000076LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
967 { "cgrj", OP48(0xec0000000064LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
968 { "clrj", OP48(0xec0000000077LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
969 { "clgrj", OP48(0xec0000000065LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
970 { "cij", OP48(0xec000000007eLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
971 { "cgij", OP48(0xec000000007cLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
972 { "clij", OP48(0xec000000007fLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
973 { "clgij", OP48(0xec000000007dLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
974 { "risbg", OP48(0xec0000000055LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
975 { "risbhg", OP48(0xec000000005dLL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
976 { "risblg", OP48(0xec0000000051LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
977 { "rnsbg", OP48(0xec0000000054LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
978 { "rosbg", OP48(0xec0000000056LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
979 { "rxsbg", OP48(0xec0000000057LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
980 { "cit", OP48(0xec0000000072LL), MASK_RIE_MRI, INSTR_RIE_MRI, 3, 6},
981 { "cgit", OP48(0xec0000000070LL), MASK_RIE_MRI, INSTR_RIE_MRI, 3, 6},
982 { "clfit", OP48(0xec0000000073LL), MASK_RIE_MRU, INSTR_RIE_MRU, 3, 6},
983 { "clgit", OP48(0xec0000000071LL), MASK_RIE_MRU, INSTR_RIE_MRU, 3, 6},
984 { "ahik", OP48(0xec00000000d8LL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
985 { "aghik", OP48(0xec00000000d9LL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
986 { "alhsik", OP48(0xec00000000daLL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
987 { "alghsik", OP48(0xec00000000dbLL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
988 /* QEMU-END */
989 { "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0},
990 { "stamy", OP48(0xeb000000009bLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
991 { "lamy", OP48(0xeb000000009aLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
992 { "lmy", OP48(0xeb0000000098LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
993 { "lmh", OP48(0xeb0000000096LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
994 { "lmh", OP48(0xeb0000000096LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
995 { "stmy", OP48(0xeb0000000090LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
996 { "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
997 { "mvclu", OP48(0xeb000000008eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3},
998 { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0},
999 { "icmy", OP48(0xeb0000000081LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
1000 { "icmh", OP48(0xeb0000000080LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
1001 { "icmh", OP48(0xeb0000000080LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
1002 { "xiy", OP48(0xeb0000000057LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
1003 { "oiy", OP48(0xeb0000000056LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
1004 { "cliy", OP48(0xeb0000000055LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
1005 { "niy", OP48(0xeb0000000054LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
1006 { "mviy", OP48(0xeb0000000052LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
1007 { "tmy", OP48(0xeb0000000051LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
1008 { "bxleg", OP48(0xeb0000000045LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1009 { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1010 { "bxhg", OP48(0xeb0000000044LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1011 { "bxhg", OP48(0xeb0000000044LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1012 { "cdsg", OP48(0xeb000000003eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1013 { "cdsg", OP48(0xeb000000003eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1014 { "cdsy", OP48(0xeb0000000031LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1015 { "csg", OP48(0xeb0000000030LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1016 { "csg", OP48(0xeb0000000030LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1017 { "lctlg", OP48(0xeb000000002fLL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3},
1018 { "lctlg", OP48(0xeb000000002fLL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2},
1019 { "stcmy", OP48(0xeb000000002dLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
1020 { "stcmh", OP48(0xeb000000002cLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
1021 { "stcmh", OP48(0xeb000000002cLL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
1022 { "stmh", OP48(0xeb0000000026LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1023 { "stmh", OP48(0xeb0000000026LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1024 { "stctg", OP48(0xeb0000000025LL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3},
1025 { "stctg", OP48(0xeb0000000025LL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2},
1026 { "stmg", OP48(0xeb0000000024LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1027 { "stmg", OP48(0xeb0000000024LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1028 { "clmy", OP48(0xeb0000000021LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
1029 { "clmh", OP48(0xeb0000000020LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
1030 { "clmh", OP48(0xeb0000000020LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
1031 { "rll", OP48(0xeb000000001dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3},
1032 { "rll", OP48(0xeb000000001dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 2},
1033 { "rllg", OP48(0xeb000000001cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1034 { "rllg", OP48(0xeb000000001cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1035 { "csy", OP48(0xeb0000000014LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1036 { "tracg", OP48(0xeb000000000fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1037 { "tracg", OP48(0xeb000000000fLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1038 { "sllg", OP48(0xeb000000000dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1039 { "sllg", OP48(0xeb000000000dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1040 { "srlg", OP48(0xeb000000000cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1041 { "srlg", OP48(0xeb000000000cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1042 { "slag", OP48(0xeb000000000bLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1043 { "slag", OP48(0xeb000000000bLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1044 { "srag", OP48(0xeb000000000aLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1045 { "srag", OP48(0xeb000000000aLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1046 { "lmg", OP48(0xeb0000000004LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1047 { "lmg", OP48(0xeb0000000004LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1048 /* QEMU-ADD: */
1049 { "loc", OP48(0xeb00000000f2LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1050 { "locg", OP48(0xeb00000000e2LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1051 { "stoc", OP48(0xeb00000000f3LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1052 { "stocg", OP48(0xeb00000000e3LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1053 { "srak", OP48(0xeb00000000dcLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1054 { "slak", OP48(0xeb00000000ddLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1055 { "srlk", OP48(0xeb00000000deLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1056 { "sllk", OP48(0xeb00000000dfLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1057 { "asi", OP48(0xeb000000006aLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1058 { "alsi", OP48(0xeb000000006eLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1059 { "agsi", OP48(0xeb000000007aLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1060 { "algsi", OP48(0xeb000000007eLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1061 /* QEMU-END */
1062 { "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1063 { "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0},
1064 { "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1065 { "mvcdk", OP16(0xe50fLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1066 { "mvcsk", OP16(0xe50eLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1067 { "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1068 { "strag", OP48(0xe50000000002LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 2},
1069 { "lasp", OP16(0xe500LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1070 /* QEMU-ADD: */
1071 { "mvhhi", OP16(0xe544LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1072 { "mvghi", OP16(0xe548LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1073 { "mvhi", OP16(0xe54cLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1074 { "chhsi", OP16(0xe554LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1075 { "clhhsi", OP16(0xe555LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1076 { "cghsi", OP16(0xe558LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1077 { "clghsi", OP16(0xe559LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1078 { "chsi", OP16(0xe55cLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1079 { "clfhsi", OP16(0xe55dLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1080 /* QEMU-END */
1081 { "slb", OP48(0xe30000000099LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1082 { "slb", OP48(0xe30000000099LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1083 { "alc", OP48(0xe30000000098LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1084 { "alc", OP48(0xe30000000098LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1085 { "dl", OP48(0xe30000000097LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1086 { "dl", OP48(0xe30000000097LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1087 { "ml", OP48(0xe30000000096LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1088 { "ml", OP48(0xe30000000096LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1089 { "llh", OP48(0xe30000000095LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1090 { "llc", OP48(0xe30000000094LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1091 { "llgh", OP48(0xe30000000091LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1092 { "llgh", OP48(0xe30000000091LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1093 { "llgc", OP48(0xe30000000090LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1094 { "llgc", OP48(0xe30000000090LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1095 { "lpq", OP48(0xe3000000008fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1096 { "lpq", OP48(0xe3000000008fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1097 { "stpq", OP48(0xe3000000008eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1098 { "stpq", OP48(0xe3000000008eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1099 { "slbg", OP48(0xe30000000089LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1100 { "slbg", OP48(0xe30000000089LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1101 { "alcg", OP48(0xe30000000088LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1102 { "alcg", OP48(0xe30000000088LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1103 { "dlg", OP48(0xe30000000087LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1104 { "dlg", OP48(0xe30000000087LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1105 { "mlg", OP48(0xe30000000086LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1106 { "mlg", OP48(0xe30000000086LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1107 { "xg", OP48(0xe30000000082LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1108 { "xg", OP48(0xe30000000082LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1109 { "og", OP48(0xe30000000081LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1110 { "og", OP48(0xe30000000081LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1111 { "ng", OP48(0xe30000000080LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1112 { "ng", OP48(0xe30000000080LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1113 { "shy", OP48(0xe3000000007bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1114 { "ahy", OP48(0xe3000000007aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1115 { "chy", OP48(0xe30000000079LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1116 { "lhy", OP48(0xe30000000078LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1117 { "lgb", OP48(0xe30000000077LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1118 { "lb", OP48(0xe30000000076LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1119 { "icy", OP48(0xe30000000073LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1120 { "stcy", OP48(0xe30000000072LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1121 { "lay", OP48(0xe30000000071LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1122 { "sthy", OP48(0xe30000000070LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1123 { "sly", OP48(0xe3000000005fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1124 { "aly", OP48(0xe3000000005eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1125 { "sy", OP48(0xe3000000005bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1126 { "ay", OP48(0xe3000000005aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1127 { "cy", OP48(0xe30000000059LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1128 { "ly", OP48(0xe30000000058LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1129 { "xy", OP48(0xe30000000057LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1130 { "oy", OP48(0xe30000000056LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1131 { "cly", OP48(0xe30000000055LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1132 { "ny", OP48(0xe30000000054LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1133 { "msy", OP48(0xe30000000051LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1134 { "sty", OP48(0xe30000000050LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1135 { "bctg", OP48(0xe30000000046LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1136 { "bctg", OP48(0xe30000000046LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1137 { "strvh", OP48(0xe3000000003fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1138 { "strvh", OP48(0xe3000000003fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1139 { "strv", OP48(0xe3000000003eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1140 { "strv", OP48(0xe3000000003eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1141 { "clgf", OP48(0xe30000000031LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1142 { "clgf", OP48(0xe30000000031LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1143 { "cgf", OP48(0xe30000000030LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1144 { "cgf", OP48(0xe30000000030LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1145 { "strvg", OP48(0xe3000000002fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1146 { "strvg", OP48(0xe3000000002fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1147 { "cvdg", OP48(0xe3000000002eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1148 { "cvdg", OP48(0xe3000000002eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1149 { "cvdy", OP48(0xe30000000026LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1150 { "stg", OP48(0xe30000000024LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1151 { "stg", OP48(0xe30000000024LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1152 { "clg", OP48(0xe30000000021LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1153 { "clg", OP48(0xe30000000021LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1154 { "cg", OP48(0xe30000000020LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1155 { "cg", OP48(0xe30000000020LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1156 { "lrvh", OP48(0xe3000000001fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1157 { "lrvh", OP48(0xe3000000001fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1158 { "lrv", OP48(0xe3000000001eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1159 { "lrv", OP48(0xe3000000001eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1160 { "dsgf", OP48(0xe3000000001dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1161 { "dsgf", OP48(0xe3000000001dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1162 { "msgf", OP48(0xe3000000001cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1163 { "msgf", OP48(0xe3000000001cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1164 { "slgf", OP48(0xe3000000001bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1165 { "slgf", OP48(0xe3000000001bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1166 { "algf", OP48(0xe3000000001aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1167 { "algf", OP48(0xe3000000001aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1168 { "sgf", OP48(0xe30000000019LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1169 { "sgf", OP48(0xe30000000019LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1170 { "agf", OP48(0xe30000000018LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1171 { "agf", OP48(0xe30000000018LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1172 { "llgt", OP48(0xe30000000017LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1173 { "llgt", OP48(0xe30000000017LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1174 { "llgf", OP48(0xe30000000016LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1175 { "llgf", OP48(0xe30000000016LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1176 { "lgh", OP48(0xe30000000015LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1177 { "lgh", OP48(0xe30000000015LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1178 { "lgf", OP48(0xe30000000014LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1179 { "lgf", OP48(0xe30000000014LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1180 { "lray", OP48(0xe30000000013LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1181 { "lt", OP48(0xe30000000012LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1182 { "lrvg", OP48(0xe3000000000fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1183 { "lrvg", OP48(0xe3000000000fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1184 { "cvbg", OP48(0xe3000000000eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1185 { "cvbg", OP48(0xe3000000000eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1186 { "dsg", OP48(0xe3000000000dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1187 { "dsg", OP48(0xe3000000000dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1188 { "msg", OP48(0xe3000000000cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1189 { "msg", OP48(0xe3000000000cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1190 { "slg", OP48(0xe3000000000bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1191 { "slg", OP48(0xe3000000000bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1192 { "alg", OP48(0xe3000000000aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1193 { "alg", OP48(0xe3000000000aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1194 { "sg", OP48(0xe30000000009LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1195 { "sg", OP48(0xe30000000009LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1196 { "ag", OP48(0xe30000000008LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1197 { "ag", OP48(0xe30000000008LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1198 { "cvby", OP48(0xe30000000006LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1199 { "lg", OP48(0xe30000000004LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1200 { "lg", OP48(0xe30000000004LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1201 { "lrag", OP48(0xe30000000003LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1202 { "lrag", OP48(0xe30000000003LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1203 { "ltg", OP48(0xe30000000002LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1204 /* QEMU-ADD: */
1205 { "pfd", OP48(0xe30000000036LL), MASK_RXY_URRD, INSTR_RXY_URRD, 3, 6},
1206 /* QEMU-END */
1207 { "unpku", OP8(0xe2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1208 { "pku", OP8(0xe1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1209 { "edmk", OP8(0xdfLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1210 { "ed", OP8(0xdeLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1211 { "trt", OP8(0xddLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1212 { "tr", OP8(0xdcLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1213 { "mvcs", OP8(0xdbLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
1214 { "mvcp", OP8(0xdaLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
1215 { "mvck", OP8(0xd9LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
1216 { "xc", OP8(0xd7LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1217 { "oc", OP8(0xd6LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1218 { "clc", OP8(0xd5LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1219 { "nc", OP8(0xd4LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1220 { "mvz", OP8(0xd3LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1221 { "mvc", OP8(0xd2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1222 { "mvn", OP8(0xd1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1223 { "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
1224 { "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
1225 { "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4},
1226 /* QEMU-ADD: */
1227 { "exrl", OP16(0xc600ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1228 { "pfdrl", OP16(0xc602ll), MASK_RIL_UP, INSTR_RIL_UP, 3, 6},
1229 { "cghrl", OP16(0xc604ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1230 { "chrl", OP16(0xc605ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1231 { "clghrl", OP16(0xc606ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1232 { "clhrl", OP16(0xc607ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1233 { "cgrl", OP16(0xc608ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1234 { "clgrl", OP16(0xc60all), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1235 { "cgfrl", OP16(0xc60cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1236 { "crl", OP16(0xc60dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1237 { "clgfrl", OP16(0xc60ell), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1238 { "clrl", OP16(0xc60fll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1239
1240 { "llhrl", OP16(0xc400ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1241 { "lghrl", OP16(0xc404ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1242 { "lhrl", OP16(0xc405ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1243 { "llghrl", OP16(0xc406ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1244 { "sthrl", OP16(0xc407ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1245 { "lgrl", OP16(0xc408ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1246 { "stgrl", OP16(0xc40bll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1247 { "lgfrl", OP16(0xc40cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1248 { "lrl", OP16(0xc40dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1249 { "llgfrl", OP16(0xc40ell), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1250 { "strl", OP16(0xc40fll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1251 /* QEMU-END */
1252 { "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1253 { "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1254 { "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1255 { "cgfi", OP16(0xc20cLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1256 { "alfi", OP16(0xc20bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1257 { "algfi", OP16(0xc20aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1258 { "afi", OP16(0xc209LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1259 { "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1260 { "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1261 { "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1262 /* QEMU-ADD: */
1263 { "msfi", OP16(0xc201ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
1264 { "msgfi", OP16(0xc200ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
1265 /* QEMU-END */
1266 { "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1267 { "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1268 { "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1269 { "jgnp", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1270 { "jgle", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1271 { "jgnl", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1272 { "jgnm", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1273 { "jghe", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1274 { "jgnlh", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1275 { "jge", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1276 { "jgz", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1277 { "jgne", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1278 { "jgnz", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1279 { "jglh", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1280 { "jgnhe", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1281 { "jgl", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1282 { "jgm", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1283 { "jgnle", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1284 { "jgh", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1285 { "jgp", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1286 { "jgo", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1287 { "llilf", OP16(0xc00fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1288 { "llihf", OP16(0xc00eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1289 { "oilf", OP16(0xc00dLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1290 { "oihf", OP16(0xc00cLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1291 { "nilf", OP16(0xc00bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1292 { "nihf", OP16(0xc00aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1293 { "iilf", OP16(0xc009LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1294 { "iihf", OP16(0xc008LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1295 { "xilf", OP16(0xc007LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1296 { "xihf", OP16(0xc006LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1297 { "brasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2},
1298 { "brcl", OP16(0xc004LL), MASK_RIL_UP, INSTR_RIL_UP, 3, 2},
1299 { "lgfi", OP16(0xc001LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1300 { "larl", OP16(0xc000LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2},
1301 { "icm", OP8(0xbfLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
1302 { "stcm", OP8(0xbeLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
1303 { "clm", OP8(0xbdLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
1304 { "cds", OP8(0xbbLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1305 { "cs", OP8(0xbaLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1306 { "cu42", OP16(0xb9b3LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1307 { "cu41", OP16(0xb9b2LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1308 { "cu24", OP16(0xb9b1LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1309 { "cu14", OP16(0xb9b0LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1310 { "lptea", OP16(0xb9aaLL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 4},
1311 { "esea", OP16(0xb99dLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 2},
1312 { "slbr", OP16(0xb999LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1313 { "alcr", OP16(0xb998LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1314 { "dlr", OP16(0xb997LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1315 { "mlr", OP16(0xb996LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1316 { "llhr", OP16(0xb995LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1317 { "llcr", OP16(0xb994LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1318 { "troo", OP16(0xb993LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1319 { "troo", OP16(0xb993LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1320 { "trot", OP16(0xb992LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1321 { "trot", OP16(0xb992LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1322 { "trto", OP16(0xb991LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1323 { "trto", OP16(0xb991LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1324 { "trtt", OP16(0xb990LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1325 { "trtt", OP16(0xb990LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1326 { "idte", OP16(0xb98eLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 3},
1327 { "epsw", OP16(0xb98dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1328 { "cspg", OP16(0xb98aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 3},
1329 { "slbgr", OP16(0xb989LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1330 { "alcgr", OP16(0xb988LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1331 { "dlgr", OP16(0xb987LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1332 { "mlgr", OP16(0xb986LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1333 { "llghr", OP16(0xb985LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1334 { "llgcr", OP16(0xb984LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1335 { "flogr", OP16(0xb983LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1336 { "xgr", OP16(0xb982LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1337 { "ogr", OP16(0xb981LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1338 { "ngr", OP16(0xb980LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1339 { "bctgr", OP16(0xb946LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1340 { "klmd", OP16(0xb93fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1341 { "kimd", OP16(0xb93eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1342 { "clgfr", OP16(0xb931LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1343 { "cgfr", OP16(0xb930LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1344 { "kmc", OP16(0xb92fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1345 { "km", OP16(0xb92eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1346 { "lhr", OP16(0xb927LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1347 { "lbr", OP16(0xb926LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1348 { "sturg", OP16(0xb925LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1349 { "clgr", OP16(0xb921LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1350 { "cgr", OP16(0xb920LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1351 { "lrvr", OP16(0xb91fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1352 { "kmac", OP16(0xb91eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1353 { "dsgfr", OP16(0xb91dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1354 { "msgfr", OP16(0xb91cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1355 { "slgfr", OP16(0xb91bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1356 { "algfr", OP16(0xb91aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1357 { "sgfr", OP16(0xb919LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1358 { "agfr", OP16(0xb918LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1359 { "llgtr", OP16(0xb917LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1360 { "llgfr", OP16(0xb916LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1361 { "lgfr", OP16(0xb914LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1362 { "lcgfr", OP16(0xb913LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1363 { "ltgfr", OP16(0xb912LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1364 { "lngfr", OP16(0xb911LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1365 { "lpgfr", OP16(0xb910LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1366 { "lrvgr", OP16(0xb90fLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1367 { "eregg", OP16(0xb90eLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1368 { "dsgr", OP16(0xb90dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1369 { "msgr", OP16(0xb90cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1370 { "slgr", OP16(0xb90bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1371 { "algr", OP16(0xb90aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1372 { "sgr", OP16(0xb909LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1373 { "agr", OP16(0xb908LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1374 { "lghr", OP16(0xb907LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1375 { "lgbr", OP16(0xb906LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1376 { "lurag", OP16(0xb905LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1377 { "lgr", OP16(0xb904LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1378 { "lcgr", OP16(0xb903LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1379 { "ltgr", OP16(0xb902LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1380 { "lngr", OP16(0xb901LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1381 { "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1382 /* QEMU-ADD: */
1383 { "crt", OP16(0xb972LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1384 { "cgrt", OP16(0xb960LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1385 { "clrt", OP16(0xb973LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1386 { "clgrt", OP16(0xb961LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1387 { "locr", OP16(0xb9f2LL), MASK_RRF_MRR, INSTR_RRF_MRR, 3, 6},
1388 { "locgr", OP16(0xb9e2LL), MASK_RRF_MRR, INSTR_RRF_MRR, 3, 6},
1389 { "popcnt", OP16(0xb9e1LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 6},
1390 { "ngrk", OP16(0xb9e4LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1391 { "ogrk", OP16(0xb9e6LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1392 { "xgrk", OP16(0xb9e7LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1393 { "agrk", OP16(0xb9e8LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1394 { "sgrk", OP16(0xb9e9LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1395 { "algrk", OP16(0xb9eaLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1396 { "slgrk", OP16(0xb9ebLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1397 { "nrk", OP16(0xb9f4LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1398 { "ork", OP16(0xb9f6LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1399 { "xrk", OP16(0xb9f7LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1400 { "ark", OP16(0xb9f8LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1401 { "srk", OP16(0xb9f9LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1402 { "alrk", OP16(0xb9faLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1403 { "slrk", OP16(0xb9fbLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1404 /* QEMU-END */
1405 { "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
1406 { "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
1407 { "rrxtr", OP16(0xb3ffLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1408 { "iextr", OP16(0xb3feLL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5},
1409 { "qaxtr", OP16(0xb3fdLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1410 { "cextr", OP16(0xb3fcLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1411 { "cxstr", OP16(0xb3fbLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1412 { "cxutr", OP16(0xb3faLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1413 { "cxgtr", OP16(0xb3f9LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1414 { "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1415 { "iedtr", OP16(0xb3f6LL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5},
1416 { "qadtr", OP16(0xb3f5LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1417 { "cedtr", OP16(0xb3f4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1418 { "cdstr", OP16(0xb3f3LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1419 { "cdutr", OP16(0xb3f2LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1420 { "cdgtr", OP16(0xb3f1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1421 { "esxtr", OP16(0xb3efLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1422 { "eextr", OP16(0xb3edLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1423 { "cxtr", OP16(0xb3ecLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1424 { "csxtr", OP16(0xb3ebLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1425 { "cuxtr", OP16(0xb3eaLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1426 { "cgxtr", OP16(0xb3e9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5},
1427 { "kxtr", OP16(0xb3e8LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1428 { "esdtr", OP16(0xb3e7LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1429 { "eedtr", OP16(0xb3e5LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1430 { "cdtr", OP16(0xb3e4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1431 { "csdtr", OP16(0xb3e3LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1432 { "cudtr", OP16(0xb3e2LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1433 { "cgdtr", OP16(0xb3e1LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5},
1434 { "kdtr", OP16(0xb3e0LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1435 { "fixtr", OP16(0xb3dfLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1436 { "ltxtr", OP16(0xb3deLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1437 { "ldxtr", OP16(0xb3ddLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1438 { "lxdtr", OP16(0xb3dcLL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5},
1439 { "sxtr", OP16(0xb3dbLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1440 { "axtr", OP16(0xb3daLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1441 { "dxtr", OP16(0xb3d9LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1442 { "mxtr", OP16(0xb3d8LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1443 { "fidtr", OP16(0xb3d7LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1444 { "ltdtr", OP16(0xb3d6LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1445 { "ledtr", OP16(0xb3d5LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1446 { "ldetr", OP16(0xb3d4LL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5},
1447 { "sdtr", OP16(0xb3d3LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1448 { "adtr", OP16(0xb3d2LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1449 { "ddtr", OP16(0xb3d1LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1450 { "mdtr", OP16(0xb3d0LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1451 { "lgdr", OP16(0xb3cdLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1452 { "cgxr", OP16(0xb3caLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1453 { "cgdr", OP16(0xb3c9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1454 { "cger", OP16(0xb3c8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1455 { "cxgr", OP16(0xb3c6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1456 { "cdgr", OP16(0xb3c5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1457 { "cegr", OP16(0xb3c4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1458 { "ldgr", OP16(0xb3c1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1459 { "cfxr", OP16(0xb3baLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1460 { "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1461 { "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1462 { "cxfr", OP16(0xb3b6LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1463 { "cdfr", OP16(0xb3b5LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1464 { "cefr", OP16(0xb3b4LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1465 { "cgxbr", OP16(0xb3aaLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1466 { "cgdbr", OP16(0xb3a9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1467 { "cgebr", OP16(0xb3a8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1468 { "cxgbr", OP16(0xb3a6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1469 { "cdgbr", OP16(0xb3a5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1470 { "cegbr", OP16(0xb3a4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1471 { "cfxbr", OP16(0xb39aLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
1472 { "cfdbr", OP16(0xb399LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
1473 { "cfebr", OP16(0xb398LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
1474 { "cxfbr", OP16(0xb396LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1475 { "cdfbr", OP16(0xb395LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1476 { "cefbr", OP16(0xb394LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1477 { "efpc", OP16(0xb38cLL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0},
1478 { "sfasr", OP16(0xb385LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 5},
1479 { "sfpc", OP16(0xb384LL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0},
1480 { "fidr", OP16(0xb37fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1481 { "fier", OP16(0xb377LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1482 { "lzxr", OP16(0xb376LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1483 { "lzdr", OP16(0xb375LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1484 { "lzer", OP16(0xb374LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1485 { "lcdfr", OP16(0xb373LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1486 { "cpsdr", OP16(0xb372LL), MASK_RRF_F0FF2, INSTR_RRF_F0FF2, 2, 5},
1487 { "lndfr", OP16(0xb371LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1488 { "lpdfr", OP16(0xb370LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1489 { "cxr", OP16(0xb369LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1490 { "fixr", OP16(0xb367LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1491 { "lexr", OP16(0xb366LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1492 { "lxr", OP16(0xb365LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1493 { "lcxr", OP16(0xb363LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1494 { "ltxr", OP16(0xb362LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1495 { "lnxr", OP16(0xb361LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1496 { "lpxr", OP16(0xb360LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1497 { "fidbr", OP16(0xb35fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1498 { "didbr", OP16(0xb35bLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0},
1499 { "thdr", OP16(0xb359LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1500 { "thder", OP16(0xb358LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1501 { "fiebr", OP16(0xb357LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1502 { "diebr", OP16(0xb353LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0},
1503 { "tbdr", OP16(0xb351LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1504 { "tbedr", OP16(0xb350LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1505 { "dxbr", OP16(0xb34dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1506 { "mxbr", OP16(0xb34cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1507 { "sxbr", OP16(0xb34bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1508 { "axbr", OP16(0xb34aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1509 { "cxbr", OP16(0xb349LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1510 { "kxbr", OP16(0xb348LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1511 { "fixbr", OP16(0xb347LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1512 { "lexbr", OP16(0xb346LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1513 { "ldxbr", OP16(0xb345LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1514 { "ledbr", OP16(0xb344LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1515 { "lcxbr", OP16(0xb343LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1516 { "ltxbr", OP16(0xb342LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1517 { "lnxbr", OP16(0xb341LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1518 { "lpxbr", OP16(0xb340LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1519 { "msdr", OP16(0xb33fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1520 { "madr", OP16(0xb33eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1521 { "myhr", OP16(0xb33dLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1522 { "mayhr", OP16(0xb33cLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1523 { "myr", OP16(0xb33bLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1524 { "mayr", OP16(0xb33aLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1525 { "mylr", OP16(0xb339LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1526 { "maylr", OP16(0xb338LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1527 { "meer", OP16(0xb337LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1528 { "sqxr", OP16(0xb336LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1529 { "mser", OP16(0xb32fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1530 { "maer", OP16(0xb32eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1531 { "lxer", OP16(0xb326LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1532 { "lxdr", OP16(0xb325LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1533 { "lder", OP16(0xb324LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1534 { "msdbr", OP16(0xb31fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1535 { "madbr", OP16(0xb31eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1536 { "ddbr", OP16(0xb31dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1537 { "mdbr", OP16(0xb31cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1538 { "sdbr", OP16(0xb31bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1539 { "adbr", OP16(0xb31aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1540 { "cdbr", OP16(0xb319LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1541 { "kdbr", OP16(0xb318LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1542 { "meebr", OP16(0xb317LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1543 { "sqxbr", OP16(0xb316LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1544 { "sqdbr", OP16(0xb315LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1545 { "sqebr", OP16(0xb314LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1546 { "lcdbr", OP16(0xb313LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1547 { "ltdbr", OP16(0xb312LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1548 { "lndbr", OP16(0xb311LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1549 { "lpdbr", OP16(0xb310LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1550 { "msebr", OP16(0xb30fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1551 { "maebr", OP16(0xb30eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1552 { "debr", OP16(0xb30dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1553 { "mdebr", OP16(0xb30cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1554 { "sebr", OP16(0xb30bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1555 { "aebr", OP16(0xb30aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1556 { "cebr", OP16(0xb309LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1557 { "kebr", OP16(0xb308LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1558 { "mxdbr", OP16(0xb307LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1559 { "lxebr", OP16(0xb306LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1560 { "lxdbr", OP16(0xb305LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1561 { "ldebr", OP16(0xb304LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1562 { "lcebr", OP16(0xb303LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1563 { "ltebr", OP16(0xb302LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1564 { "lnebr", OP16(0xb301LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1565 { "lpebr", OP16(0xb300LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1566 /* QEMU-ADD: */
1567 { "clfebr", OP16(0xb39cLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1568 { "clfdbr", OP16(0xb39dLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1569 { "clfxbr", OP16(0xb39eLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1570 { "clgebr", OP16(0xb3acLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1571 { "clgdbr", OP16(0xb3adLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1572 { "clgxbr", OP16(0xb3aeLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1573 { "celfbr", OP16(0xb390LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1574 { "cdlfbr", OP16(0xb391LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1575 { "cxlfbr", OP16(0xb392LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1576 { "celgbr", OP16(0xb3a0LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1577 { "cdlgbr", OP16(0xb3a1LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1578 { "cxlgbr", OP16(0xb3a2LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1579 /* QEMU-END */
1580 { "trap4", OP16(0xb2ffLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1581 { "lfas", OP16(0xb2bdLL), MASK_S_RD, INSTR_S_RD, 2, 5},
1582 { "srnmt", OP16(0xb2b9LL), MASK_S_RD, INSTR_S_RD, 2, 5},
1583 { "lpswe", OP16(0xb2b2LL), MASK_S_RD, INSTR_S_RD, 2, 2},
1584 { "stfl", OP16(0xb2b1LL), MASK_S_RD, INSTR_S_RD, 3, 2},
1585 { "stfle", OP16(0xb2b0LL), MASK_S_RD, INSTR_S_RD, 2, 4},
1586 { "cu12", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1587 { "cutfu", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1588 { "cutfu", OP16(0xb2a7LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1589 { "cu21", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1590 { "cuutf", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1591 { "cuutf", OP16(0xb2a6LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1592 { "tre", OP16(0xb2a5LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1593 { "lfpc", OP16(0xb29dLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1594 { "stfpc", OP16(0xb29cLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1595 { "srnm", OP16(0xb299LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1596 { "stsi", OP16(0xb27dLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1597 { "stckf", OP16(0xb27cLL), MASK_S_RD, INSTR_S_RD, 2, 4},
1598 { "sacf", OP16(0xb279LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1599 { "stcke", OP16(0xb278LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1600 { "rp", OP16(0xb277LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1601 { "xsch", OP16(0xb276LL), MASK_S_00, INSTR_S_00, 3, 0},
1602 { "siga", OP16(0xb274LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1603 { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1604 { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1605 { "srst", OP16(0xb25eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1606 { "clst", OP16(0xb25dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1607 { "bsa", OP16(0xb25aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1608 { "bsg", OP16(0xb258LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1609 { "cuse", OP16(0xb257LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1610 { "mvst", OP16(0xb255LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1611 { "mvpg", OP16(0xb254LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1612 { "msr", OP16(0xb252LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1613 { "csp", OP16(0xb250LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1614 { "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3, 0},
1615 { "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0},
1616 { "cpya", OP16(0xb24dLL), MASK_RRE_AA, INSTR_RRE_AA, 3, 0},
1617 { "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0},
1618 { "lura", OP16(0xb24bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1619 { "esta", OP16(0xb24aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1620 { "ereg", OP16(0xb249LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1621 { "palb", OP16(0xb248LL), MASK_RRE_00, INSTR_RRE_00, 3, 0},
1622 { "msta", OP16(0xb247LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1623 { "stura", OP16(0xb246LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1624 { "sqer", OP16(0xb245LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
1625 { "sqdr", OP16(0xb244LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
1626 { "cksm", OP16(0xb241LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1627 { "bakr", OP16(0xb240LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1628 { "schm", OP16(0xb23cLL), MASK_S_00, INSTR_S_00, 3, 0},
1629 { "rchp", OP16(0xb23bLL), MASK_S_00, INSTR_S_00, 3, 0},
1630 { "stcps", OP16(0xb23aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1631 { "stcrw", OP16(0xb239LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1632 { "rsch", OP16(0xb238LL), MASK_S_00, INSTR_S_00, 3, 0},
1633 { "sal", OP16(0xb237LL), MASK_S_00, INSTR_S_00, 3, 0},
1634 { "tpi", OP16(0xb236LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1635 { "tsch", OP16(0xb235LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1636 { "stsch", OP16(0xb234LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1637 { "ssch", OP16(0xb233LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1638 { "msch", OP16(0xb232LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1639 { "hsch", OP16(0xb231LL), MASK_S_00, INSTR_S_00, 3, 0},
1640 { "csch", OP16(0xb230LL), MASK_S_00, INSTR_S_00, 3, 0},
1641 { "pgout", OP16(0xb22fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1642 { "pgin", OP16(0xb22eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1643 { "dxr", OP16(0xb22dLL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
1644 { "tb", OP16(0xb22cLL), MASK_RRE_0R, INSTR_RRE_0R, 3, 0},
1645 { "sske", OP16(0xb22bLL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1646 { "sske", OP16(0xb22bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1647 { "rrbe", OP16(0xb22aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1648 { "iske", OP16(0xb229LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1649 { "pt", OP16(0xb228LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1650 { "esar", OP16(0xb227LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1651 { "epar", OP16(0xb226LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1652 { "ssar", OP16(0xb225LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1653 { "iac", OP16(0xb224LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1654 { "ivsk", OP16(0xb223LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1655 { "ipm", OP16(0xb222LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1656 { "ipte", OP16(0xb221LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1657 { "cfc", OP16(0xb21aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1658 { "sac", OP16(0xb219LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1659 { "pc", OP16(0xb218LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1660 { "sie", OP16(0xb214LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1661 { "stap", OP16(0xb212LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1662 { "stpx", OP16(0xb211LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1663 { "spx", OP16(0xb210LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1664 { "ptlb", OP16(0xb20dLL), MASK_S_00, INSTR_S_00, 3, 0},
1665 { "ipk", OP16(0xb20bLL), MASK_S_00, INSTR_S_00, 3, 0},
1666 { "spka", OP16(0xb20aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1667 { "stpt", OP16(0xb209LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1668 { "spt", OP16(0xb208LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1669 { "stckc", OP16(0xb207LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1670 { "sckc", OP16(0xb206LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1671 { "stck", OP16(0xb205LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1672 { "sck", OP16(0xb204LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1673 { "stidp", OP16(0xb202LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1674 { "lra", OP8(0xb1LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1675 { "mc", OP8(0xafLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1676 { "sigp", OP8(0xaeLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1677 { "stosm", OP8(0xadLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1678 { "stnsm", OP8(0xacLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1679 { "clcle", OP8(0xa9LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1680 { "mvcle", OP8(0xa8LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1681 { "j", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1682 { "jno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1683 { "jnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1684 { "jnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1685 { "jle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1686 { "jnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1687 { "jnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1688 { "jhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1689 { "jnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1690 { "je", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1691 { "jz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1692 { "jne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1693 { "jnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1694 { "jlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1695 { "jnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1696 { "jl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1697 { "jm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1698 { "jnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1699 { "jh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1700 { "jp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1701 { "jo", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1702 { "cghi", OP16(0xa70fLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1703 { "chi", OP16(0xa70eLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1704 { "mghi", OP16(0xa70dLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1705 { "mhi", OP16(0xa70cLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1706 { "aghi", OP16(0xa70bLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1707 { "ahi", OP16(0xa70aLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1708 { "lghi", OP16(0xa709LL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1709 { "lhi", OP16(0xa708LL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1710 { "brctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2},
1711 { "brct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0},
1712 { "bras", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0},
1713 { "brc", OP16(0xa704LL), MASK_RI_UP, INSTR_RI_UP, 3, 0},
1714 { "tmhl", OP16(0xa703LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1715 { "tmhh", OP16(0xa702LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1716 { "tml", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1717 { "tmll", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1718 { "tmh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1719 { "tmlh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1720 { "llill", OP16(0xa50fLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1721 { "llilh", OP16(0xa50eLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1722 { "llihl", OP16(0xa50dLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1723 { "llihh", OP16(0xa50cLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1724 { "oill", OP16(0xa50bLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1725 { "oilh", OP16(0xa50aLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1726 { "oihl", OP16(0xa509LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1727 { "oihh", OP16(0xa508LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1728 { "nill", OP16(0xa507LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1729 { "nilh", OP16(0xa506LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1730 { "nihl", OP16(0xa505LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1731 { "nihh", OP16(0xa504LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1732 { "iill", OP16(0xa503LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1733 { "iilh", OP16(0xa502LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1734 { "iihl", OP16(0xa501LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1735 { "iihh", OP16(0xa500LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1736 { "stam", OP8(0x9bLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0},
1737 { "lam", OP8(0x9aLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0},
1738 { "trace", OP8(0x99LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1739 { "lm", OP8(0x98LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1740 { "xi", OP8(0x97LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1741 { "oi", OP8(0x96LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1742 { "cli", OP8(0x95LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1743 { "ni", OP8(0x94LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1744 { "ts", OP8(0x93LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1745 { "mvi", OP8(0x92LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1746 { "tm", OP8(0x91LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1747 { "stm", OP8(0x90LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1748 { "slda", OP8(0x8fLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1749 { "srda", OP8(0x8eLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1750 { "sldl", OP8(0x8dLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1751 { "srdl", OP8(0x8cLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1752 { "sla", OP8(0x8bLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1753 { "sra", OP8(0x8aLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1754 { "sll", OP8(0x89LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1755 { "srl", OP8(0x88LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1756 { "bxle", OP8(0x87LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1757 { "bxh", OP8(0x86LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1758 { "brxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0},
1759 { "brxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0},
1760 { "diag", OP8(0x83LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1761 { "lpsw", OP8(0x82LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1762 { "ssm", OP8(0x80LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1763 { "su", OP8(0x7fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1764 { "au", OP8(0x7eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1765 { "de", OP8(0x7dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1766 { "me", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1767 { "mde", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1768 { "se", OP8(0x7bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1769 { "ae", OP8(0x7aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1770 { "ce", OP8(0x79LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1771 { "le", OP8(0x78LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1772 { "ms", OP8(0x71LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1773 { "ste", OP8(0x70LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1774 { "sw", OP8(0x6fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1775 { "aw", OP8(0x6eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1776 { "dd", OP8(0x6dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1777 { "md", OP8(0x6cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1778 { "sd", OP8(0x6bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1779 { "ad", OP8(0x6aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1780 { "cd", OP8(0x69LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1781 { "ld", OP8(0x68LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1782 { "mxd", OP8(0x67LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1783 { "std", OP8(0x60LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1784 { "sl", OP8(0x5fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1785 { "al", OP8(0x5eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1786 { "d", OP8(0x5dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1787 { "m", OP8(0x5cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1788 { "s", OP8(0x5bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1789 { "a", OP8(0x5aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1790 { "c", OP8(0x59LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1791 { "l", OP8(0x58LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1792 { "x", OP8(0x57LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1793 { "o", OP8(0x56LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1794 { "cl", OP8(0x55LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1795 { "n", OP8(0x54LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1796 { "lae", OP8(0x51LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1797 { "st", OP8(0x50LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1798 { "cvb", OP8(0x4fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1799 { "cvd", OP8(0x4eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1800 { "bas", OP8(0x4dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1801 { "mh", OP8(0x4cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1802 { "sh", OP8(0x4bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1803 { "ah", OP8(0x4aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1804 { "ch", OP8(0x49LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1805 { "lh", OP8(0x48LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1806 { "b", OP16(0x47f0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1807 { "bno", OP16(0x47e0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1808 { "bnh", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1809 { "bnp", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1810 { "ble", OP16(0x47c0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1811 { "bnl", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1812 { "bnm", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1813 { "bhe", OP16(0x47a0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1814 { "bnlh", OP16(0x4790LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1815 { "be", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1816 { "bz", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1817 { "bne", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1818 { "bnz", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1819 { "blh", OP16(0x4760LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1820 { "bnhe", OP16(0x4750LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1821 { "bl", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1822 { "bm", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1823 { "bnle", OP16(0x4730LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1824 { "bh", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1825 { "bp", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1826 { "bo", OP16(0x4710LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1827 { "bc", OP8(0x47LL), MASK_RX_URRD, INSTR_RX_URRD, 3, 0},
1828 { "nop", OP16(0x4700LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1829 { "bct", OP8(0x46LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1830 { "bal", OP8(0x45LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1831 { "ex", OP8(0x44LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1832 { "ic", OP8(0x43LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1833 { "stc", OP8(0x42LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1834 { "la", OP8(0x41LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1835 { "sth", OP8(0x40LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1836 { "sur", OP8(0x3fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1837 { "aur", OP8(0x3eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1838 { "der", OP8(0x3dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1839 { "mer", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1840 { "mder", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1841 { "ser", OP8(0x3bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1842 { "aer", OP8(0x3aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1843 { "cer", OP8(0x39LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1844 { "ler", OP8(0x38LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1845 { "sxr", OP8(0x37LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1846 { "axr", OP8(0x36LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1847 { "lrer", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1848 { "ledr", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1849 { "her", OP8(0x34LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1850 { "lcer", OP8(0x33LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1851 { "lter", OP8(0x32LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1852 { "lner", OP8(0x31LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1853 { "lper", OP8(0x30LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1854 { "swr", OP8(0x2fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1855 { "awr", OP8(0x2eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1856 { "ddr", OP8(0x2dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1857 { "mdr", OP8(0x2cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1858 { "sdr", OP8(0x2bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1859 { "adr", OP8(0x2aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1860 { "cdr", OP8(0x29LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1861 { "ldr", OP8(0x28LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1862 { "mxdr", OP8(0x27LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1863 { "mxr", OP8(0x26LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1864 { "lrdr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1865 { "ldxr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1866 { "hdr", OP8(0x24LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1867 { "lcdr", OP8(0x23LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1868 { "ltdr", OP8(0x22LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1869 { "lndr", OP8(0x21LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1870 { "lpdr", OP8(0x20LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1871 { "slr", OP8(0x1fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1872 { "alr", OP8(0x1eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1873 { "dr", OP8(0x1dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1874 { "mr", OP8(0x1cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1875 { "sr", OP8(0x1bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1876 { "ar", OP8(0x1aLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1877 { "cr", OP8(0x19LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1878 { "lr", OP8(0x18LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1879 { "xr", OP8(0x17LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1880 { "or", OP8(0x16LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1881 { "clr", OP8(0x15LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1882 { "nr", OP8(0x14LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1883 { "lcr", OP8(0x13LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1884 { "ltr", OP8(0x12LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1885 { "lnr", OP8(0x11LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1886 { "lpr", OP8(0x10LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1887 { "clcl", OP8(0x0fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1888 { "mvcl", OP8(0x0eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1889 { "basr", OP8(0x0dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1890 { "bassm", OP8(0x0cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1891 { "bsm", OP8(0x0bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1892 { "svc", OP8(0x0aLL), MASK_RR_U0, INSTR_RR_U0, 3, 0},
1893 { "br", OP16(0x07f0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1894 { "bnor", OP16(0x07e0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1895 { "bnhr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1896 { "bnpr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1897 { "bler", OP16(0x07c0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1898 { "bnlr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1899 { "bnmr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1900 { "bher", OP16(0x07a0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1901 { "bnlhr", OP16(0x0790LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1902 { "ber", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1903 { "bzr", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1904 { "bner", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1905 { "bnzr", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1906 { "blhr", OP16(0x0760LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1907 { "bnher", OP16(0x0750LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1908 { "blr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1909 { "bmr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1910 { "bnler", OP16(0x0730LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1911 { "bhr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1912 { "bpr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1913 { "bor", OP16(0x0710LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1914 { "bcr", OP8(0x07LL), MASK_RR_UR, INSTR_RR_UR, 3, 0},
1915 { "nopr", OP16(0x0700LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1916 { "bctr", OP8(0x06LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1917 { "balr", OP8(0x05LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1918 { "spm", OP8(0x04LL), MASK_RR_R0, INSTR_RR_R0, 3, 0},
1919 { "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3, 0},
1920 { "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2, 2},
1921 { "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 3, 2},
1922 { "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 3, 2},
1923 { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 3, 2},
1924 { "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5},
1925 { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0},
1926 { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0},
1927 { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0},
1928 };
1929
1930 static const int s390_num_opcodes =
1931 sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);
QEmu