target/nios2/cpu.h

   1 /*
   2  * Altera Nios II virtual CPU header
   3  *
   4  * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #ifndef NIOS2_CPU_H
  22 #define NIOS2_CPU_H
  23
  24 #include "exec/cpu-defs.h"
  25 #include "hw/core/cpu.h"
  26 #include "hw/registerfields.h"
  27 #include "qom/object.h"
  28
  29 typedef struct CPUArchState CPUNios2State;
  30 #if !defined(CONFIG_USER_ONLY)
  31 #include "mmu.h"
  32 #endif
  33
  34 #define TYPE_NIOS2_CPU "nios2-cpu"
  35
  36 OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
  37
  38 /**
  39  * Nios2CPUClass:
  40  * @parent_reset: The parent class' reset handler.
  41  *
  42  * A Nios2 CPU model.
  43  */
  44 struct Nios2CPUClass {
  45     /*< private >*/
  46     CPUClass parent_class;
  47     /*< public >*/
  48
  49     DeviceRealize parent_realize;
  50     DeviceReset parent_reset;
  51 };
  52
  53 #define TARGET_HAS_ICE 1
  54
  55 /* Configuration options for Nios II */
  56 #define RESET_ADDRESS         0x00000000
  57 #define EXCEPTION_ADDRESS     0x00000004
  58 #define FAST_TLB_MISS_ADDRESS 0x00000008
  59
  60 #define NUM_GP_REGS 32
  61 #define NUM_CR_REGS 32
  62
  63 /* General purpose register aliases */
  64 #define R_ZERO   0
  65 #define R_AT     1
  66 #define R_RET0   2
  67 #define R_RET1   3
  68 #define R_ARG0   4
  69 #define R_ARG1   5
  70 #define R_ARG2   6
  71 #define R_ARG3   7
  72 #define R_ET     24
  73 #define R_BT     25
  74 #define R_GP     26
  75 #define R_SP     27
  76 #define R_FP     28
  77 #define R_EA     29
  78 #define R_BA     30
  79 #define R_RA     31
  80
  81 /* Control register aliases */
  82 #define CR_STATUS        0
  83
  84 FIELD(CR_STATUS, PIE, 0, 1)
  85 FIELD(CR_STATUS, U, 1, 1)
  86 FIELD(CR_STATUS, EH, 2, 1)
  87 FIELD(CR_STATUS, IH, 3, 1)
  88 FIELD(CR_STATUS, IL, 4, 6)
  89 FIELD(CR_STATUS, CRS, 10, 6)
  90 FIELD(CR_STATUS, PRS, 16, 6)
  91 FIELD(CR_STATUS, NMI, 22, 1)
  92 FIELD(CR_STATUS, RSIE, 23, 1)
  93
  94 #define CR_STATUS_PIE    R_CR_STATUS_PIE_MASK
  95 #define CR_STATUS_U      R_CR_STATUS_U_MASK
  96 #define CR_STATUS_EH     R_CR_STATUS_EH_MASK
  97 #define CR_STATUS_IH     R_CR_STATUS_IH_MASK
  98 #define CR_STATUS_NMI    R_CR_STATUS_NMI_MASK
  99 #define CR_STATUS_RSIE   R_CR_STATUS_RSIE_MASK
 100
 101 #define CR_ESTATUS       1
 102 #define CR_BSTATUS       2
 103 #define CR_IENABLE       3
 104 #define CR_IPENDING      4
 105 #define CR_CPUID         5
 106 #define CR_CTL6          6
 107 #define CR_EXCEPTION     7
 108
 109 FIELD(CR_EXCEPTION, CAUSE, 2, 5)
 110 FIELD(CR_EXCEPTION, ECCFTL, 31, 1)
 111
 112 #define CR_PTEADDR       8
 113 #define   CR_PTEADDR_PTBASE_SHIFT 22
 114 #define   CR_PTEADDR_PTBASE_MASK  (0x3FF << CR_PTEADDR_PTBASE_SHIFT)
 115 #define   CR_PTEADDR_VPN_SHIFT    2
 116 #define   CR_PTEADDR_VPN_MASK     (0xFFFFF << CR_PTEADDR_VPN_SHIFT)
 117 #define CR_TLBACC        9
 118 #define   CR_TLBACC_IGN_SHIFT 25
 119 #define   CR_TLBACC_IGN_MASK  (0x7F << CR_TLBACC_IGN_SHIFT)
 120 #define   CR_TLBACC_C         (1 << 24)
 121 #define   CR_TLBACC_R         (1 << 23)
 122 #define   CR_TLBACC_W         (1 << 22)
 123 #define   CR_TLBACC_X         (1 << 21)
 124 #define   CR_TLBACC_G         (1 << 20)
 125 #define   CR_TLBACC_PFN_MASK  0x000FFFFF
 126 #define CR_TLBMISC       10
 127 #define   CR_TLBMISC_WAY_SHIFT 20
 128 #define   CR_TLBMISC_WAY_MASK  (0xF << CR_TLBMISC_WAY_SHIFT)
 129 #define   CR_TLBMISC_RD        (1 << 19)
 130 #define   CR_TLBMISC_WR        (1 << 18)
 131 #define   CR_TLBMISC_PID_SHIFT 4
 132 #define   CR_TLBMISC_PID_MASK  (0x3FFF << CR_TLBMISC_PID_SHIFT)
 133 #define   CR_TLBMISC_DBL       (1 << 3)
 134 #define   CR_TLBMISC_BAD       (1 << 2)
 135 #define   CR_TLBMISC_PERM      (1 << 1)
 136 #define   CR_TLBMISC_D         (1 << 0)
 137 #define CR_ENCINJ        11
 138 #define CR_BADADDR       12
 139 #define CR_CONFIG        13
 140 #define CR_MPUBASE       14
 141 #define CR_MPUACC        15
 142
 143 /* Exceptions */
 144 #define EXCP_BREAK    0x1000
 145 #define EXCP_RESET    0
 146 #define EXCP_PRESET   1
 147 #define EXCP_IRQ      2
 148 #define EXCP_TRAP     3
 149 #define EXCP_UNIMPL   4
 150 #define EXCP_ILLEGAL  5
 151 #define EXCP_UNALIGN  6
 152 #define EXCP_UNALIGND 7
 153 #define EXCP_DIV      8
 154 #define EXCP_SUPERA   9
 155 #define EXCP_SUPERI   10
 156 #define EXCP_SUPERD   11
 157 #define EXCP_TLBD     12
 158 #define EXCP_TLBX     13
 159 #define EXCP_TLBR     14
 160 #define EXCP_TLBW     15
 161 #define EXCP_MPUI     16
 162 #define EXCP_MPUD     17
 163
 164 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 165
 166 struct CPUArchState {
 167     uint32_t regs[NUM_GP_REGS];
 168     uint32_t ctrl[NUM_CR_REGS];
 169     uint32_t pc;
 170
 171 #if !defined(CONFIG_USER_ONLY)
 172     Nios2MMU mmu;
 173 #endif
 174     int error_code;
 175 };
 176
 177 /**
 178  * Nios2CPU:
 179  * @env: #CPUNios2State
 180  *
 181  * A Nios2 CPU.
 182  */
 183 struct ArchCPU {
 184     /*< private >*/
 185     CPUState parent_obj;
 186     /*< public >*/
 187
 188     CPUNegativeOffsetState neg;
 189     CPUNios2State env;
 190
 191     bool mmu_present;
 192     uint32_t pid_num_bits;
 193     uint32_t tlb_num_ways;
 194     uint32_t tlb_num_entries;
 195
 196     /* Addresses that are hard-coded in the FPGA build settings */
 197     uint32_t reset_addr;
 198     uint32_t exception_addr;
 199     uint32_t fast_tlb_miss_addr;
 200 };
 201
 202
 203 void nios2_tcg_init(void);
 204 void nios2_cpu_do_interrupt(CPUState *cs);
 205 void dump_mmu(CPUNios2State *env);
 206 void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 207 hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 208 G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 209                                               MMUAccessType access_type, int mmu_idx,
 210                                               uintptr_t retaddr);
 211
 212 void do_nios2_semihosting(CPUNios2State *env);
 213
 214 #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
 215
 216 #define cpu_gen_code cpu_nios2_gen_code
 217
 218 #define CPU_SAVE_VERSION 1
 219
 220 /* MMU modes definitions */
 221 #define MMU_SUPERVISOR_IDX  0
 222 #define MMU_USER_IDX        1
 223
 224 static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
 225 {
 226     return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
 227                                                   MMU_SUPERVISOR_IDX;
 228 }
 229
 230 #ifndef CONFIG_USER_ONLY
 231 bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 232                         MMUAccessType access_type, int mmu_idx,
 233                         bool probe, uintptr_t retaddr);
 234 #endif
 235
 236 typedef CPUNios2State CPUArchState;
 237 typedef Nios2CPU ArchCPU;
 238
 239 #include "exec/cpu-all.h"
 240
 241 static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
 242                                         target_ulong *cs_base, uint32_t *flags)
 243 {
 244     *pc = env->pc;
 245     *cs_base = 0;
 246     *flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U);
 247 }
 248
 249 #endif /* NIOS2_CPU_H */