hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31
  32 struct PCIBus {
  33     BusState qbus;
  34     int bus_num;
  35     int devfn_min;
  36     pci_set_irq_fn set_irq;
  37     pci_map_irq_fn map_irq;
  38     uint32_t config_reg; /* XXX: suppress */
  39     /* low level pic */
  40     SetIRQFunc *low_set_irq;
  41     qemu_irq *irq_opaque;
  42     PCIDevice *devices[256];
  43     PCIDevice *parent_dev;
  44     PCIBus *next;
  45     /* The bus IRQ state is the logical OR of the connected devices.
  46        Keep a count of the number of devices with raised IRQs.  */
  47     int nirq;
  48     int irq_count[];
  49 };
  50
  51 static void pci_update_mappings(PCIDevice *d);
  52 static void pci_set_irq(void *opaque, int irq_num, int level);
  53
  54 target_phys_addr_t pci_mem_base;
  55 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  56 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  57 static PCIBus *first_bus;
  58
  59 static void pcibus_save(QEMUFile *f, void *opaque)
  60 {
  61     PCIBus *bus = (PCIBus *)opaque;
  62     int i;
  63
  64     qemu_put_be32(f, bus->nirq);
  65     for (i = 0; i < bus->nirq; i++)
  66         qemu_put_be32(f, bus->irq_count[i]);
  67 }
  68
  69 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  70 {
  71     PCIBus *bus = (PCIBus *)opaque;
  72     int i, nirq;
  73
  74     if (version_id != 1)
  75         return -EINVAL;
  76
  77     nirq = qemu_get_be32(f);
  78     if (bus->nirq != nirq) {
  79         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  80                 nirq, bus->nirq);
  81         return -EINVAL;
  82     }
  83
  84     for (i = 0; i < nirq; i++)
  85         bus->irq_count[i] = qemu_get_be32(f);
  86
  87     return 0;
  88 }
  89
  90 static void pci_bus_reset(void *opaque)
  91 {
  92     PCIBus *bus = (PCIBus *)opaque;
  93     int i;
  94
  95     for (i = 0; i < bus->nirq; i++) {
  96         bus->irq_count[i] = 0;
  97     }
  98     for (i = 0; i < 256; i++) {
  99         if (bus->devices[i])
 100             memset(bus->devices[i]->irq_state, 0,
 101                    sizeof(bus->devices[i]->irq_state));
 102     }
 103 }
 104
 105 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 106                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 107                          qemu_irq *pic, int devfn_min, int nirq)
 108 {
 109     PCIBus *bus;
 110     static int nbus = 0;
 111
 112     bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI,
 113                                         sizeof(PCIBus) + (nirq * sizeof(int)),
 114                                         parent, name));
 115     bus->set_irq = set_irq;
 116     bus->map_irq = map_irq;
 117     bus->irq_opaque = pic;
 118     bus->devfn_min = devfn_min;
 119     bus->nirq = nirq;
 120     bus->next = first_bus;
 121     first_bus = bus;
 122     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 123     qemu_register_reset(pci_bus_reset, 0, bus);
 124     return bus;
 125 }
 126
 127 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 128 {
 129     PCIBus *bus;
 130     bus = qemu_mallocz(sizeof(PCIBus));
 131     bus->map_irq = map_irq;
 132     bus->parent_dev = dev;
 133     bus->next = dev->bus->next;
 134     dev->bus->next = bus;
 135     return bus;
 136 }
 137
 138 int pci_bus_num(PCIBus *s)
 139 {
 140     return s->bus_num;
 141 }
 142
 143 void pci_device_save(PCIDevice *s, QEMUFile *f)
 144 {
 145     int i;
 146
 147     qemu_put_be32(f, 2); /* PCI device version */
 148     qemu_put_buffer(f, s->config, 256);
 149     for (i = 0; i < 4; i++)
 150         qemu_put_be32(f, s->irq_state[i]);
 151 }
 152
 153 int pci_device_load(PCIDevice *s, QEMUFile *f)
 154 {
 155     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 156     uint32_t version_id;
 157     int i;
 158
 159     version_id = qemu_get_be32(f);
 160     if (version_id > 2)
 161         return -EINVAL;
 162     qemu_get_buffer(f, config, sizeof config);
 163     for (i = 0; i < sizeof config; ++i)
 164         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 165             return -EINVAL;
 166     memcpy(s->config, config, sizeof config);
 167
 168     pci_update_mappings(s);
 169
 170     if (version_id >= 2)
 171         for (i = 0; i < 4; i ++)
 172             s->irq_state[i] = qemu_get_be32(f);
 173     return 0;
 174 }
 175
 176 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 177 {
 178     uint16_t *id;
 179
 180     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 181     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 182     id[1] = cpu_to_le16(pci_default_sub_device_id);
 183     return 0;
 184 }
 185
 186 /*
 187  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 188  */
 189 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 190 {
 191     const char *p;
 192     char *e;
 193     unsigned long val;
 194     unsigned long dom = 0, bus = 0;
 195     unsigned slot = 0;
 196
 197     p = addr;
 198     val = strtoul(p, &e, 16);
 199     if (e == p)
 200         return -1;
 201     if (*e == ':') {
 202         bus = val;
 203         p = e + 1;
 204         val = strtoul(p, &e, 16);
 205         if (e == p)
 206             return -1;
 207         if (*e == ':') {
 208             dom = bus;
 209             bus = val;
 210             p = e + 1;
 211             val = strtoul(p, &e, 16);
 212             if (e == p)
 213                 return -1;
 214         }
 215     }
 216
 217     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 218         return -1;
 219
 220     slot = val;
 221
 222     if (*e)
 223         return -1;
 224
 225     /* Note: QEMU doesn't implement domains other than 0 */
 226     if (dom != 0 || pci_find_bus(bus) == NULL)
 227         return -1;
 228
 229     *domp = dom;
 230     *busp = bus;
 231     *slotp = slot;
 232     return 0;
 233 }
 234
 235 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 236 {
 237     char devaddr[32];
 238
 239     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 240         return -1;
 241
 242     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 243 }
 244
 245 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 246 {
 247     int dom, bus;
 248     unsigned slot;
 249
 250     if (!devaddr) {
 251         *devfnp = -1;
 252         return pci_find_bus(0);
 253     }
 254
 255     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 256         return NULL;
 257     }
 258
 259     *devfnp = slot << 3;
 260     return pci_find_bus(bus);
 261 }
 262
 263 static void pci_init_cmask(PCIDevice *dev)
 264 {
 265     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 266     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 267     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 268     dev->cmask[PCI_REVISION_ID] = 0xff;
 269     dev->cmask[PCI_CLASS_PROG] = 0xff;
 270     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 271     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 272     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 273 }
 274
 275 static void pci_init_wmask(PCIDevice *dev)
 276 {
 277     int i;
 278     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 279     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 280     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 281                               | PCI_COMMAND_MASTER;
 282     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 283         dev->wmask[i] = 0xff;
 284 }
 285
 286 /* -1 for devfn means auto assign */
 287 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 288                                          const char *name, int devfn,
 289                                          PCIConfigReadFunc *config_read,
 290                                          PCIConfigWriteFunc *config_write)
 291 {
 292     if (devfn < 0) {
 293         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 294             if (!bus->devices[devfn])
 295                 goto found;
 296         }
 297         return NULL;
 298     found: ;
 299     } else if (bus->devices[devfn]) {
 300         return NULL;
 301     }
 302     pci_dev->bus = bus;
 303     pci_dev->devfn = devfn;
 304     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 305     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 306     pci_set_default_subsystem_id(pci_dev);
 307     pci_init_cmask(pci_dev);
 308     pci_init_wmask(pci_dev);
 309
 310     if (!config_read)
 311         config_read = pci_default_read_config;
 312     if (!config_write)
 313         config_write = pci_default_write_config;
 314     pci_dev->config_read = config_read;
 315     pci_dev->config_write = config_write;
 316     bus->devices[devfn] = pci_dev;
 317     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 318     return pci_dev;
 319 }
 320
 321 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 322                                int instance_size, int devfn,
 323                                PCIConfigReadFunc *config_read,
 324                                PCIConfigWriteFunc *config_write)
 325 {
 326     PCIDevice *pci_dev;
 327
 328     pci_dev = qemu_mallocz(instance_size);
 329     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 330                                      config_read, config_write);
 331     return pci_dev;
 332 }
 333 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 334 {
 335     return addr + pci_mem_base;
 336 }
 337
 338 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 339 {
 340     PCIIORegion *r;
 341     int i;
 342
 343     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 344         r = &pci_dev->io_regions[i];
 345         if (!r->size || r->addr == -1)
 346             continue;
 347         if (r->type == PCI_ADDRESS_SPACE_IO) {
 348             isa_unassign_ioport(r->addr, r->size);
 349         } else {
 350             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 351                                                      r->size,
 352                                                      IO_MEM_UNASSIGNED);
 353         }
 354     }
 355 }
 356
 357 int pci_unregister_device(PCIDevice *pci_dev)
 358 {
 359     int ret = 0;
 360
 361     if (pci_dev->unregister)
 362         ret = pci_dev->unregister(pci_dev);
 363     if (ret)
 364         return ret;
 365
 366     pci_unregister_io_regions(pci_dev);
 367
 368     qemu_free_irqs(pci_dev->irq);
 369     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 370     qdev_free(&pci_dev->qdev);
 371     return 0;
 372 }
 373
 374 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 375                             uint32_t size, int type,
 376                             PCIMapIORegionFunc *map_func)
 377 {
 378     PCIIORegion *r;
 379     uint32_t addr;
 380     uint32_t wmask;
 381
 382     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 383         return;
 384
 385     if (size & (size-1)) {
 386         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 387                     "type=0x%x, size=0x%x\n", type, size);
 388         exit(1);
 389     }
 390
 391     r = &pci_dev->io_regions[region_num];
 392     r->addr = -1;
 393     r->size = size;
 394     r->type = type;
 395     r->map_func = map_func;
 396
 397     wmask = ~(size - 1);
 398     if (region_num == PCI_ROM_SLOT) {
 399         addr = 0x30;
 400         /* ROM enable bit is writeable */
 401         wmask |= 1;
 402     } else {
 403         addr = 0x10 + region_num * 4;
 404     }
 405     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 406     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 407     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 408 }
 409
 410 static void pci_update_mappings(PCIDevice *d)
 411 {
 412     PCIIORegion *r;
 413     int cmd, i;
 414     uint32_t last_addr, new_addr, config_ofs;
 415
 416     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 417     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 418         r = &d->io_regions[i];
 419         if (i == PCI_ROM_SLOT) {
 420             config_ofs = 0x30;
 421         } else {
 422             config_ofs = 0x10 + i * 4;
 423         }
 424         if (r->size != 0) {
 425             if (r->type & PCI_ADDRESS_SPACE_IO) {
 426                 if (cmd & PCI_COMMAND_IO) {
 427                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 428                                                          config_ofs));
 429                     new_addr = new_addr & ~(r->size - 1);
 430                     last_addr = new_addr + r->size - 1;
 431                     /* NOTE: we have only 64K ioports on PC */
 432                     if (last_addr <= new_addr || new_addr == 0 ||
 433                         last_addr >= 0x10000) {
 434                         new_addr = -1;
 435                     }
 436                 } else {
 437                     new_addr = -1;
 438                 }
 439             } else {
 440                 if (cmd & PCI_COMMAND_MEMORY) {
 441                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 442                                                          config_ofs));
 443                     /* the ROM slot has a specific enable bit */
 444                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 445                         goto no_mem_map;
 446                     new_addr = new_addr & ~(r->size - 1);
 447                     last_addr = new_addr + r->size - 1;
 448                     /* NOTE: we do not support wrapping */
 449                     /* XXX: as we cannot support really dynamic
 450                        mappings, we handle specific values as invalid
 451                        mappings. */
 452                     if (last_addr <= new_addr || new_addr == 0 ||
 453                         last_addr == -1) {
 454                         new_addr = -1;
 455                     }
 456                 } else {
 457                 no_mem_map:
 458                     new_addr = -1;
 459                 }
 460             }
 461             /* now do the real mapping */
 462             if (new_addr != r->addr) {
 463                 if (r->addr != -1) {
 464                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 465                         int class;
 466                         /* NOTE: specific hack for IDE in PC case:
 467                            only one byte must be mapped. */
 468                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 469                         if (class == 0x0101 && r->size == 4) {
 470                             isa_unassign_ioport(r->addr + 2, 1);
 471                         } else {
 472                             isa_unassign_ioport(r->addr, r->size);
 473                         }
 474                     } else {
 475                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 476                                                      r->size,
 477                                                      IO_MEM_UNASSIGNED);
 478                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 479                     }
 480                 }
 481                 r->addr = new_addr;
 482                 if (r->addr != -1) {
 483                     r->map_func(d, i, r->addr, r->size, r->type);
 484                 }
 485             }
 486         }
 487     }
 488 }
 489
 490 uint32_t pci_default_read_config(PCIDevice *d,
 491                                  uint32_t address, int len)
 492 {
 493     uint32_t val;
 494
 495     switch(len) {
 496     default:
 497     case 4:
 498         if (address <= 0xfc) {
 499             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 500             break;
 501         }
 502         /* fall through */
 503     case 2:
 504         if (address <= 0xfe) {
 505             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 506             break;
 507         }
 508         /* fall through */
 509     case 1:
 510         val = d->config[address];
 511         break;
 512     }
 513     return val;
 514 }
 515
 516 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 517 {
 518     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 519     int i;
 520
 521     /* not efficient, but simple */
 522     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 523     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 524         uint8_t wmask = d->wmask[addr];
 525         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 526     }
 527     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 528         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 529             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 530         pci_update_mappings(d);
 531 }
 532
 533 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 534 {
 535     PCIBus *s = opaque;
 536     PCIDevice *pci_dev;
 537     int config_addr, bus_num;
 538
 539 #if defined(DEBUG_PCI) && 0
 540     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 541            addr, val, len);
 542 #endif
 543     bus_num = (addr >> 16) & 0xff;
 544     while (s && s->bus_num != bus_num)
 545         s = s->next;
 546     if (!s)
 547         return;
 548     pci_dev = s->devices[(addr >> 8) & 0xff];
 549     if (!pci_dev)
 550         return;
 551     config_addr = addr & 0xff;
 552 #if defined(DEBUG_PCI)
 553     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 554            pci_dev->name, config_addr, val, len);
 555 #endif
 556     pci_dev->config_write(pci_dev, config_addr, val, len);
 557 }
 558
 559 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 560 {
 561     PCIBus *s = opaque;
 562     PCIDevice *pci_dev;
 563     int config_addr, bus_num;
 564     uint32_t val;
 565
 566     bus_num = (addr >> 16) & 0xff;
 567     while (s && s->bus_num != bus_num)
 568         s= s->next;
 569     if (!s)
 570         goto fail;
 571     pci_dev = s->devices[(addr >> 8) & 0xff];
 572     if (!pci_dev) {
 573     fail:
 574         switch(len) {
 575         case 1:
 576             val = 0xff;
 577             break;
 578         case 2:
 579             val = 0xffff;
 580             break;
 581         default:
 582         case 4:
 583             val = 0xffffffff;
 584             break;
 585         }
 586         goto the_end;
 587     }
 588     config_addr = addr & 0xff;
 589     val = pci_dev->config_read(pci_dev, config_addr, len);
 590 #if defined(DEBUG_PCI)
 591     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 592            pci_dev->name, config_addr, val, len);
 593 #endif
 594  the_end:
 595 #if defined(DEBUG_PCI) && 0
 596     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 597            addr, val, len);
 598 #endif
 599     return val;
 600 }
 601
 602 /***********************************************************/
 603 /* generic PCI irq support */
 604
 605 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 606 static void pci_set_irq(void *opaque, int irq_num, int level)
 607 {
 608     PCIDevice *pci_dev = (PCIDevice *)opaque;
 609     PCIBus *bus;
 610     int change;
 611
 612     change = level - pci_dev->irq_state[irq_num];
 613     if (!change)
 614         return;
 615
 616     pci_dev->irq_state[irq_num] = level;
 617     for (;;) {
 618         bus = pci_dev->bus;
 619         irq_num = bus->map_irq(pci_dev, irq_num);
 620         if (bus->set_irq)
 621             break;
 622         pci_dev = bus->parent_dev;
 623     }
 624     bus->irq_count[irq_num] += change;
 625     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 626 }
 627
 628 /***********************************************************/
 629 /* monitor info on PCI */
 630
 631 typedef struct {
 632     uint16_t class;
 633     const char *desc;
 634 } pci_class_desc;
 635
 636 static const pci_class_desc pci_class_descriptions[] =
 637 {
 638     { 0x0100, "SCSI controller"},
 639     { 0x0101, "IDE controller"},
 640     { 0x0102, "Floppy controller"},
 641     { 0x0103, "IPI controller"},
 642     { 0x0104, "RAID controller"},
 643     { 0x0106, "SATA controller"},
 644     { 0x0107, "SAS controller"},
 645     { 0x0180, "Storage controller"},
 646     { 0x0200, "Ethernet controller"},
 647     { 0x0201, "Token Ring controller"},
 648     { 0x0202, "FDDI controller"},
 649     { 0x0203, "ATM controller"},
 650     { 0x0280, "Network controller"},
 651     { 0x0300, "VGA controller"},
 652     { 0x0301, "XGA controller"},
 653     { 0x0302, "3D controller"},
 654     { 0x0380, "Display controller"},
 655     { 0x0400, "Video controller"},
 656     { 0x0401, "Audio controller"},
 657     { 0x0402, "Phone"},
 658     { 0x0480, "Multimedia controller"},
 659     { 0x0500, "RAM controller"},
 660     { 0x0501, "Flash controller"},
 661     { 0x0580, "Memory controller"},
 662     { 0x0600, "Host bridge"},
 663     { 0x0601, "ISA bridge"},
 664     { 0x0602, "EISA bridge"},
 665     { 0x0603, "MC bridge"},
 666     { 0x0604, "PCI bridge"},
 667     { 0x0605, "PCMCIA bridge"},
 668     { 0x0606, "NUBUS bridge"},
 669     { 0x0607, "CARDBUS bridge"},
 670     { 0x0608, "RACEWAY bridge"},
 671     { 0x0680, "Bridge"},
 672     { 0x0c03, "USB controller"},
 673     { 0, NULL}
 674 };
 675
 676 static void pci_info_device(PCIDevice *d)
 677 {
 678     Monitor *mon = cur_mon;
 679     int i, class;
 680     PCIIORegion *r;
 681     const pci_class_desc *desc;
 682
 683     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 684                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 685     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 686     monitor_printf(mon, "    ");
 687     desc = pci_class_descriptions;
 688     while (desc->desc && class != desc->class)
 689         desc++;
 690     if (desc->desc) {
 691         monitor_printf(mon, "%s", desc->desc);
 692     } else {
 693         monitor_printf(mon, "Class %04x", class);
 694     }
 695     monitor_printf(mon, ": PCI device %04x:%04x\n",
 696            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 697            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 698
 699     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 700         monitor_printf(mon, "      IRQ %d.\n",
 701                        d->config[PCI_INTERRUPT_LINE]);
 702     }
 703     if (class == 0x0604) {
 704         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 705     }
 706     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 707         r = &d->io_regions[i];
 708         if (r->size != 0) {
 709             monitor_printf(mon, "      BAR%d: ", i);
 710             if (r->type & PCI_ADDRESS_SPACE_IO) {
 711                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 712                                r->addr, r->addr + r->size - 1);
 713             } else {
 714                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 715                                r->addr, r->addr + r->size - 1);
 716             }
 717         }
 718     }
 719     if (class == 0x0604 && d->config[0x19] != 0) {
 720         pci_for_each_device(d->config[0x19], pci_info_device);
 721     }
 722 }
 723
 724 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 725 {
 726     PCIBus *bus = first_bus;
 727     PCIDevice *d;
 728     int devfn;
 729
 730     while (bus && bus->bus_num != bus_num)
 731         bus = bus->next;
 732     if (bus) {
 733         for(devfn = 0; devfn < 256; devfn++) {
 734             d = bus->devices[devfn];
 735             if (d)
 736                 fn(d);
 737         }
 738     }
 739 }
 740
 741 void pci_info(Monitor *mon)
 742 {
 743     pci_for_each_device(0, pci_info_device);
 744 }
 745
 746 PCIDevice *pci_create(const char *name, const char *devaddr)
 747 {
 748     PCIBus *bus;
 749     int devfn;
 750     DeviceState *dev;
 751
 752     bus = pci_get_bus_devfn(&devfn, devaddr);
 753     if (!bus) {
 754         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 755                 devaddr, name);
 756         exit(1);
 757     }
 758
 759     dev = qdev_create(&bus->qbus, name);
 760     qdev_set_prop_int(dev, "devfn", devfn);
 761     return (PCIDevice *)dev;
 762 }
 763
 764 static const char * const pci_nic_models[] = {
 765     "ne2k_pci",
 766     "i82551",
 767     "i82557b",
 768     "i82559er",
 769     "rtl8139",
 770     "e1000",
 771     "pcnet",
 772     "virtio",
 773     NULL
 774 };
 775
 776 static const char * const pci_nic_names[] = {
 777     "ne2k_pci",
 778     "i82551",
 779     "i82557b",
 780     "i82559er",
 781     "rtl8139",
 782     "e1000",
 783     "pcnet",
 784     "virtio-net-pci",
 785     NULL
 786 };
 787
 788 /* Initialize a PCI NIC.  */
 789 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 790                         const char *default_devaddr)
 791 {
 792     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 793     PCIDevice *pci_dev;
 794     DeviceState *dev;
 795     int i;
 796
 797     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 798
 799     for (i = 0; pci_nic_models[i]; i++) {
 800         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 801             pci_dev = pci_create(pci_nic_names[i], devaddr);
 802             dev = &pci_dev->qdev;
 803             qdev_set_netdev(dev, nd);
 804             qdev_init(dev);
 805             nd->private = dev;
 806             return pci_dev;
 807         }
 808     }
 809
 810     return NULL;
 811 }
 812
 813 typedef struct {
 814     PCIDevice dev;
 815     PCIBus *bus;
 816 } PCIBridge;
 817
 818 static void pci_bridge_write_config(PCIDevice *d,
 819                              uint32_t address, uint32_t val, int len)
 820 {
 821     PCIBridge *s = (PCIBridge *)d;
 822
 823     pci_default_write_config(d, address, val, len);
 824     s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
 825 }
 826
 827 PCIBus *pci_find_bus(int bus_num)
 828 {
 829     PCIBus *bus = first_bus;
 830
 831     while (bus && bus->bus_num != bus_num)
 832         bus = bus->next;
 833
 834     return bus;
 835 }
 836
 837 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 838 {
 839     PCIBus *bus = pci_find_bus(bus_num);
 840
 841     if (!bus)
 842         return NULL;
 843
 844     return bus->devices[PCI_DEVFN(slot, function)];
 845 }
 846
 847 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 848                         pci_map_irq_fn map_irq, const char *name)
 849 {
 850     PCIBridge *s;
 851     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 852                                          devfn, NULL, pci_bridge_write_config);
 853
 854     pci_config_set_vendor_id(s->dev.config, vid);
 855     pci_config_set_device_id(s->dev.config, did);
 856
 857     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 858     s->dev.config[0x05] = 0x00;
 859     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 860     s->dev.config[0x07] = 0x00; // status = fast devsel
 861     s->dev.config[0x08] = 0x00; // revision
 862     s->dev.config[0x09] = 0x00; // programming i/f
 863     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 864     s->dev.config[0x0D] = 0x10; // latency_timer
 865     s->dev.config[PCI_HEADER_TYPE] =
 866         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 867     s->dev.config[0x1E] = 0xa0; // secondary status
 868
 869     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 870     return s->bus;
 871 }
 872
 873 typedef struct {
 874     DeviceInfo qdev;
 875     pci_qdev_initfn init;
 876 } PCIDeviceInfo;
 877
 878 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 879 {
 880     PCIDevice *pci_dev = (PCIDevice *)qdev;
 881     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 882     PCIBus *bus;
 883     int devfn;
 884
 885     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 886     devfn = qdev_get_prop_int(qdev, "devfn", -1);
 887     pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
 888                                      NULL, NULL);//FIXME:config_read, config_write);
 889     assert(pci_dev);
 890     info->init(pci_dev);
 891 }
 892
 893 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
 894 {
 895     PCIDeviceInfo *info;
 896
 897     info = qemu_mallocz(sizeof(*info));
 898     info->qdev.name = qemu_strdup(name);
 899     info->qdev.size = size;
 900     info->init = init;
 901     info->qdev.init = pci_qdev_init;
 902     info->qdev.bus_type = BUS_TYPE_PCI;
 903
 904     qdev_register(&info->qdev);
 905 }
 906
 907 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 908 {
 909     DeviceState *dev;
 910
 911     dev = qdev_create(&bus->qbus, name);
 912     qdev_set_prop_int(dev, "devfn", devfn);
 913     qdev_init(dev);
 914
 915     return (PCIDevice *)dev;
 916 }
 917
 918 static int pci_find_space(PCIDevice *pdev, uint8_t size)
 919 {
 920     int offset = PCI_CONFIG_HEADER_SIZE;
 921     int i;
 922     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 923         if (pdev->used[i])
 924             offset = i + 1;
 925         else if (i - offset + 1 == size)
 926             return offset;
 927     return 0;
 928 }
 929
 930 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
 931                                         uint8_t *prev_p)
 932 {
 933     uint8_t next, prev;
 934
 935     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
 936         return 0;
 937
 938     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
 939          prev = next + PCI_CAP_LIST_NEXT)
 940         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
 941             break;
 942
 943     if (prev_p)
 944         *prev_p = prev;
 945     return next;
 946 }
 947
 948 /* Reserve space and add capability to the linked list in pci config space */
 949 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 950 {
 951     uint8_t offset = pci_find_space(pdev, size);
 952     uint8_t *config = pdev->config + offset;
 953     if (!offset)
 954         return -ENOSPC;
 955     config[PCI_CAP_LIST_ID] = cap_id;
 956     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
 957     pdev->config[PCI_CAPABILITY_LIST] = offset;
 958     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
 959     memset(pdev->used + offset, 0xFF, size);
 960     /* Make capability read-only by default */
 961     memset(pdev->wmask + offset, 0, size);
 962     /* Check capability by default */
 963     memset(pdev->cmask + offset, 0xFF, size);
 964     return offset;
 965 }
 966
 967 /* Unlink capability from the pci config space. */
 968 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 969 {
 970     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
 971     if (!offset)
 972         return;
 973     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
 974     /* Make capability writeable again */
 975     memset(pdev->wmask + offset, 0xff, size);
 976     /* Clear cmask as device-specific registers can't be checked */
 977     memset(pdev->cmask + offset, 0, size);
 978     memset(pdev->used + offset, 0, size);
 979
 980     if (!pdev->config[PCI_CAPABILITY_LIST])
 981         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
 982 }
 983
 984 /* Reserve space for capability at a known offset (to call after load). */
 985 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
 986 {
 987     memset(pdev->used + offset, 0xff, size);
 988 }
 989
 990 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
 991 {
 992     return pci_find_capability_list(pdev, cap_id, NULL);
 993 }