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valgrind/i386: avoid false positives on KVM_SET_XCRS ioctl
[qemu.git] / target-i386 / kvm.c
blob42f8def0fa2741a5e4e7ca174de42fef4bf10a2f
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
38 #include "migration/migration.h"
39 #include "qapi/qmp/qerror.h"
40
41 //#define DEBUG_KVM
42
43 #ifdef DEBUG_KVM
44 #define DPRINTF(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF(fmt, ...) \
48 do { } while (0)
49 #endif
50
51 #define MSR_KVM_WALL_CLOCK 0x11
52 #define MSR_KVM_SYSTEM_TIME 0x12
53
54 #ifndef BUS_MCEERR_AR
55 #define BUS_MCEERR_AR 4
56 #endif
57 #ifndef BUS_MCEERR_AO
58 #define BUS_MCEERR_AO 5
59 #endif
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
65 KVM_CAP_LAST_INFO
66 };
67
68 static bool has_msr_star;
69 static bool has_msr_hsave_pa;
70 static bool has_msr_tsc_adjust;
71 static bool has_msr_tsc_deadline;
72 static bool has_msr_feature_control;
73 static bool has_msr_async_pf_en;
74 static bool has_msr_pv_eoi_en;
75 static bool has_msr_misc_enable;
76 static bool has_msr_bndcfgs;
77 static bool has_msr_kvm_steal_time;
78 static int lm_capable_kernel;
79 static bool has_msr_hv_hypercall;
80 static bool has_msr_hv_vapic;
81 static bool has_msr_hv_tsc;
82 static bool has_msr_mtrr;
83
84 static bool has_msr_architectural_pmu;
85 static uint32_t num_architectural_pmu_counters;
86
87 bool kvm_allows_irq0_override(void)
88 {
89 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
90 }
91
92 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
93 {
94 struct kvm_cpuid2 *cpuid;
95 int r, size;
96
97 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
98 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
99 cpuid->nent = max;
100 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
101 if (r == 0 && cpuid->nent >= max) {
102 r = -E2BIG;
103 }
104 if (r < 0) {
105 if (r == -E2BIG) {
106 g_free(cpuid);
107 return NULL;
108 } else {
109 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
110 strerror(-r));
111 exit(1);
112 }
113 }
114 return cpuid;
115 }
116
117 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
118 * for all entries.
119 */
120 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
121 {
122 struct kvm_cpuid2 *cpuid;
123 int max = 1;
124 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
125 max *= 2;
126 }
127 return cpuid;
128 }
129
130 static const struct kvm_para_features {
131 int cap;
132 int feature;
133 } para_features[] = {
134 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
135 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
136 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
137 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
138 };
139
140 static int get_para_features(KVMState *s)
141 {
142 int i, features = 0;
143
144 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
145 if (kvm_check_extension(s, para_features[i].cap)) {
146 features |= (1 << para_features[i].feature);
147 }
148 }
149
150 return features;
151 }
152
153
154 /* Returns the value for a specific register on the cpuid entry
155 */
156 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
157 {
158 uint32_t ret = 0;
159 switch (reg) {
160 case R_EAX:
161 ret = entry->eax;
162 break;
163 case R_EBX:
164 ret = entry->ebx;
165 break;
166 case R_ECX:
167 ret = entry->ecx;
168 break;
169 case R_EDX:
170 ret = entry->edx;
171 break;
172 }
173 return ret;
174 }
175
176 /* Find matching entry for function/index on kvm_cpuid2 struct
177 */
178 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
179 uint32_t function,
180 uint32_t index)
181 {
182 int i;
183 for (i = 0; i < cpuid->nent; ++i) {
184 if (cpuid->entries[i].function == function &&
185 cpuid->entries[i].index == index) {
186 return &cpuid->entries[i];
187 }
188 }
189 /* not found: */
190 return NULL;
191 }
192
193 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
194 uint32_t index, int reg)
195 {
196 struct kvm_cpuid2 *cpuid;
197 uint32_t ret = 0;
198 uint32_t cpuid_1_edx;
199 bool found = false;
200
201 cpuid = get_supported_cpuid(s);
202
203 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
204 if (entry) {
205 found = true;
206 ret = cpuid_entry_get_reg(entry, reg);
207 }
208
209 /* Fixups for the data returned by KVM, below */
210
211 if (function == 1 && reg == R_EDX) {
212 /* KVM before 2.6.30 misreports the following features */
213 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
214 } else if (function == 1 && reg == R_ECX) {
215 /* We can set the hypervisor flag, even if KVM does not return it on
216 * GET_SUPPORTED_CPUID
217 */
218 ret |= CPUID_EXT_HYPERVISOR;
219 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
220 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
221 * and the irqchip is in the kernel.
222 */
223 if (kvm_irqchip_in_kernel() &&
224 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
225 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
226 }
227
228 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
229 * without the in-kernel irqchip
230 */
231 if (!kvm_irqchip_in_kernel()) {
232 ret &= ~CPUID_EXT_X2APIC;
233 }
234 } else if (function == 0x80000001 && reg == R_EDX) {
235 /* On Intel, kvm returns cpuid according to the Intel spec,
236 * so add missing bits according to the AMD spec:
237 */
238 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
239 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
240 }
241
242 g_free(cpuid);
243
244 /* fallback for older kernels */
245 if ((function == KVM_CPUID_FEATURES) && !found) {
246 ret = get_para_features(s);
247 }
248
249 return ret;
250 }
251
252 typedef struct HWPoisonPage {
253 ram_addr_t ram_addr;
254 QLIST_ENTRY(HWPoisonPage) list;
255 } HWPoisonPage;
256
257 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
258 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
259
260 static void kvm_unpoison_all(void *param)
261 {
262 HWPoisonPage *page, *next_page;
263
264 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
265 QLIST_REMOVE(page, list);
266 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
267 g_free(page);
268 }
269 }
270
271 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
272 {
273 HWPoisonPage *page;
274
275 QLIST_FOREACH(page, &hwpoison_page_list, list) {
276 if (page->ram_addr == ram_addr) {
277 return;
278 }
279 }
280 page = g_malloc(sizeof(HWPoisonPage));
281 page->ram_addr = ram_addr;
282 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
283 }
284
285 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
286 int *max_banks)
287 {
288 int r;
289
290 r = kvm_check_extension(s, KVM_CAP_MCE);
291 if (r > 0) {
292 *max_banks = r;
293 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
294 }
295 return -ENOSYS;
296 }
297
298 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
299 {
300 CPUX86State *env = &cpu->env;
301 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
302 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
303 uint64_t mcg_status = MCG_STATUS_MCIP;
304
305 if (code == BUS_MCEERR_AR) {
306 status |= MCI_STATUS_AR | 0x134;
307 mcg_status |= MCG_STATUS_EIPV;
308 } else {
309 status |= 0xc0;
310 mcg_status |= MCG_STATUS_RIPV;
311 }
312 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
313 (MCM_ADDR_PHYS << 6) | 0xc,
314 cpu_x86_support_mca_broadcast(env) ?
315 MCE_INJECT_BROADCAST : 0);
316 }
317
318 static void hardware_memory_error(void)
319 {
320 fprintf(stderr, "Hardware memory error!\n");
321 exit(1);
322 }
323
324 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
325 {
326 X86CPU *cpu = X86_CPU(c);
327 CPUX86State *env = &cpu->env;
328 ram_addr_t ram_addr;
329 hwaddr paddr;
330
331 if ((env->mcg_cap & MCG_SER_P) && addr
332 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
333 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
334 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
335 fprintf(stderr, "Hardware memory error for memory used by "
336 "QEMU itself instead of guest system!\n");
337 /* Hope we are lucky for AO MCE */
338 if (code == BUS_MCEERR_AO) {
339 return 0;
340 } else {
341 hardware_memory_error();
342 }
343 }
344 kvm_hwpoison_page_add(ram_addr);
345 kvm_mce_inject(cpu, paddr, code);
346 } else {
347 if (code == BUS_MCEERR_AO) {
348 return 0;
349 } else if (code == BUS_MCEERR_AR) {
350 hardware_memory_error();
351 } else {
352 return 1;
353 }
354 }
355 return 0;
356 }
357
358 int kvm_arch_on_sigbus(int code, void *addr)
359 {
360 X86CPU *cpu = X86_CPU(first_cpu);
361
362 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
363 ram_addr_t ram_addr;
364 hwaddr paddr;
365
366 /* Hope we are lucky for AO MCE */
367 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
368 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
369 addr, &paddr)) {
370 fprintf(stderr, "Hardware memory error for memory used by "
371 "QEMU itself instead of guest system!: %p\n", addr);
372 return 0;
373 }
374 kvm_hwpoison_page_add(ram_addr);
375 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
376 } else {
377 if (code == BUS_MCEERR_AO) {
378 return 0;
379 } else if (code == BUS_MCEERR_AR) {
380 hardware_memory_error();
381 } else {
382 return 1;
383 }
384 }
385 return 0;
386 }
387
388 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
389 {
390 CPUX86State *env = &cpu->env;
391
392 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
393 unsigned int bank, bank_num = env->mcg_cap & 0xff;
394 struct kvm_x86_mce mce;
395
396 env->exception_injected = -1;
397
398 /*
399 * There must be at least one bank in use if an MCE is pending.
400 * Find it and use its values for the event injection.
401 */
402 for (bank = 0; bank < bank_num; bank++) {
403 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
404 break;
405 }
406 }
407 assert(bank < bank_num);
408
409 mce.bank = bank;
410 mce.status = env->mce_banks[bank * 4 + 1];
411 mce.mcg_status = env->mcg_status;
412 mce.addr = env->mce_banks[bank * 4 + 2];
413 mce.misc = env->mce_banks[bank * 4 + 3];
414
415 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
416 }
417 return 0;
418 }
419
420 static void cpu_update_state(void *opaque, int running, RunState state)
421 {
422 CPUX86State *env = opaque;
423
424 if (running) {
425 env->tsc_valid = false;
426 }
427 }
428
429 unsigned long kvm_arch_vcpu_id(CPUState *cs)
430 {
431 X86CPU *cpu = X86_CPU(cs);
432 return cpu->env.cpuid_apic_id;
433 }
434
435 #ifndef KVM_CPUID_SIGNATURE_NEXT
436 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
437 #endif
438
439 static bool hyperv_hypercall_available(X86CPU *cpu)
440 {
441 return cpu->hyperv_vapic ||
442 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
443 }
444
445 static bool hyperv_enabled(X86CPU *cpu)
446 {
447 CPUState *cs = CPU(cpu);
448 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
449 (hyperv_hypercall_available(cpu) ||
450 cpu->hyperv_time ||
451 cpu->hyperv_relaxed_timing);
452 }
453
454 static Error *invtsc_mig_blocker;
455
456 #define KVM_MAX_CPUID_ENTRIES 100
457
458 int kvm_arch_init_vcpu(CPUState *cs)
459 {
460 struct {
461 struct kvm_cpuid2 cpuid;
462 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
463 } QEMU_PACKED cpuid_data;
464 X86CPU *cpu = X86_CPU(cs);
465 CPUX86State *env = &cpu->env;
466 uint32_t limit, i, j, cpuid_i;
467 uint32_t unused;
468 struct kvm_cpuid_entry2 *c;
469 uint32_t signature[3];
470 int kvm_base = KVM_CPUID_SIGNATURE;
471 int r;
472
473 memset(&cpuid_data, 0, sizeof(cpuid_data));
474
475 cpuid_i = 0;
476
477 /* Paravirtualization CPUIDs */
478 if (hyperv_enabled(cpu)) {
479 c = &cpuid_data.entries[cpuid_i++];
480 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
481 memcpy(signature, "Microsoft Hv", 12);
482 c->eax = HYPERV_CPUID_MIN;
483 c->ebx = signature[0];
484 c->ecx = signature[1];
485 c->edx = signature[2];
486
487 c = &cpuid_data.entries[cpuid_i++];
488 c->function = HYPERV_CPUID_INTERFACE;
489 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
490 c->eax = signature[0];
491 c->ebx = 0;
492 c->ecx = 0;
493 c->edx = 0;
494
495 c = &cpuid_data.entries[cpuid_i++];
496 c->function = HYPERV_CPUID_VERSION;
497 c->eax = 0x00001bbc;
498 c->ebx = 0x00060001;
499
500 c = &cpuid_data.entries[cpuid_i++];
501 c->function = HYPERV_CPUID_FEATURES;
502 if (cpu->hyperv_relaxed_timing) {
503 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
504 }
505 if (cpu->hyperv_vapic) {
506 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
507 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
508 has_msr_hv_vapic = true;
509 }
510 if (cpu->hyperv_time &&
511 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
512 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
513 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
514 c->eax |= 0x200;
515 has_msr_hv_tsc = true;
516 }
517 c = &cpuid_data.entries[cpuid_i++];
518 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
519 if (cpu->hyperv_relaxed_timing) {
520 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
521 }
522 if (has_msr_hv_vapic) {
523 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
524 }
525 c->ebx = cpu->hyperv_spinlock_attempts;
526
527 c = &cpuid_data.entries[cpuid_i++];
528 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
529 c->eax = 0x40;
530 c->ebx = 0x40;
531
532 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
533 has_msr_hv_hypercall = true;
534 }
535
536 if (cpu->expose_kvm) {
537 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
538 c = &cpuid_data.entries[cpuid_i++];
539 c->function = KVM_CPUID_SIGNATURE | kvm_base;
540 c->eax = KVM_CPUID_FEATURES | kvm_base;
541 c->ebx = signature[0];
542 c->ecx = signature[1];
543 c->edx = signature[2];
544
545 c = &cpuid_data.entries[cpuid_i++];
546 c->function = KVM_CPUID_FEATURES | kvm_base;
547 c->eax = env->features[FEAT_KVM];
548
549 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
550
551 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
552
553 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
554 }
555
556 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
557
558 for (i = 0; i <= limit; i++) {
559 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
560 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
561 abort();
562 }
563 c = &cpuid_data.entries[cpuid_i++];
564
565 switch (i) {
566 case 2: {
567 /* Keep reading function 2 till all the input is received */
568 int times;
569
570 c->function = i;
571 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
572 KVM_CPUID_FLAG_STATE_READ_NEXT;
573 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
574 times = c->eax & 0xff;
575
576 for (j = 1; j < times; ++j) {
577 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
578 fprintf(stderr, "cpuid_data is full, no space for "
579 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
580 abort();
581 }
582 c = &cpuid_data.entries[cpuid_i++];
583 c->function = i;
584 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
585 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
586 }
587 break;
588 }
589 case 4:
590 case 0xb:
591 case 0xd:
592 for (j = 0; ; j++) {
593 if (i == 0xd && j == 64) {
594 break;
595 }
596 c->function = i;
597 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
598 c->index = j;
599 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
600
601 if (i == 4 && c->eax == 0) {
602 break;
603 }
604 if (i == 0xb && !(c->ecx & 0xff00)) {
605 break;
606 }
607 if (i == 0xd && c->eax == 0) {
608 continue;
609 }
610 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
611 fprintf(stderr, "cpuid_data is full, no space for "
612 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
613 abort();
614 }
615 c = &cpuid_data.entries[cpuid_i++];
616 }
617 break;
618 default:
619 c->function = i;
620 c->flags = 0;
621 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
622 break;
623 }
624 }
625
626 if (limit >= 0x0a) {
627 uint32_t ver;
628
629 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
630 if ((ver & 0xff) > 0) {
631 has_msr_architectural_pmu = true;
632 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
633
634 /* Shouldn't be more than 32, since that's the number of bits
635 * available in EBX to tell us _which_ counters are available.
636 * Play it safe.
637 */
638 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
639 num_architectural_pmu_counters = MAX_GP_COUNTERS;
640 }
641 }
642 }
643
644 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
645
646 for (i = 0x80000000; i <= limit; i++) {
647 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
648 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
649 abort();
650 }
651 c = &cpuid_data.entries[cpuid_i++];
652
653 c->function = i;
654 c->flags = 0;
655 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
656 }
657
658 /* Call Centaur's CPUID instructions they are supported. */
659 if (env->cpuid_xlevel2 > 0) {
660 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
661
662 for (i = 0xC0000000; i <= limit; i++) {
663 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
664 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
665 abort();
666 }
667 c = &cpuid_data.entries[cpuid_i++];
668
669 c->function = i;
670 c->flags = 0;
671 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
672 }
673 }
674
675 cpuid_data.cpuid.nent = cpuid_i;
676
677 if (((env->cpuid_version >> 8)&0xF) >= 6
678 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
679 (CPUID_MCE | CPUID_MCA)
680 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
681 uint64_t mcg_cap;
682 int banks;
683 int ret;
684
685 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
686 if (ret < 0) {
687 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
688 return ret;
689 }
690
691 if (banks > MCE_BANKS_DEF) {
692 banks = MCE_BANKS_DEF;
693 }
694 mcg_cap &= MCE_CAP_DEF;
695 mcg_cap |= banks;
696 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
697 if (ret < 0) {
698 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
699 return ret;
700 }
701
702 env->mcg_cap = mcg_cap;
703 }
704
705 qemu_add_vm_change_state_handler(cpu_update_state, env);
706
707 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
708 if (c) {
709 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
710 !!(c->ecx & CPUID_EXT_SMX);
711 }
712
713 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
714 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
715 /* for migration */
716 error_setg(&invtsc_mig_blocker,
717 "State blocked by non-migratable CPU device"
718 " (invtsc flag)");
719 migrate_add_blocker(invtsc_mig_blocker);
720 /* for savevm */
721 vmstate_x86_cpu.unmigratable = 1;
722 }
723
724 cpuid_data.cpuid.padding = 0;
725 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
726 if (r) {
727 return r;
728 }
729
730 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
731 if (r && env->tsc_khz) {
732 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
733 if (r < 0) {
734 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
735 return r;
736 }
737 }
738
739 if (kvm_has_xsave()) {
740 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
741 }
742
743 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
744 has_msr_mtrr = true;
745 }
746
747 return 0;
748 }
749
750 void kvm_arch_reset_vcpu(X86CPU *cpu)
751 {
752 CPUX86State *env = &cpu->env;
753
754 env->exception_injected = -1;
755 env->interrupt_injected = -1;
756 env->xcr0 = 1;
757 if (kvm_irqchip_in_kernel()) {
758 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
759 KVM_MP_STATE_UNINITIALIZED;
760 } else {
761 env->mp_state = KVM_MP_STATE_RUNNABLE;
762 }
763 }
764
765 void kvm_arch_do_init_vcpu(X86CPU *cpu)
766 {
767 CPUX86State *env = &cpu->env;
768
769 /* APs get directly into wait-for-SIPI state. */
770 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
771 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
772 }
773 }
774
775 static int kvm_get_supported_msrs(KVMState *s)
776 {
777 static int kvm_supported_msrs;
778 int ret = 0;
779
780 /* first time */
781 if (kvm_supported_msrs == 0) {
782 struct kvm_msr_list msr_list, *kvm_msr_list;
783
784 kvm_supported_msrs = -1;
785
786 /* Obtain MSR list from KVM. These are the MSRs that we must
787 * save/restore */
788 msr_list.nmsrs = 0;
789 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
790 if (ret < 0 && ret != -E2BIG) {
791 return ret;
792 }
793 /* Old kernel modules had a bug and could write beyond the provided
794 memory. Allocate at least a safe amount of 1K. */
795 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
796 msr_list.nmsrs *
797 sizeof(msr_list.indices[0])));
798
799 kvm_msr_list->nmsrs = msr_list.nmsrs;
800 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
801 if (ret >= 0) {
802 int i;
803
804 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
805 if (kvm_msr_list->indices[i] == MSR_STAR) {
806 has_msr_star = true;
807 continue;
808 }
809 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
810 has_msr_hsave_pa = true;
811 continue;
812 }
813 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
814 has_msr_tsc_adjust = true;
815 continue;
816 }
817 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
818 has_msr_tsc_deadline = true;
819 continue;
820 }
821 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
822 has_msr_misc_enable = true;
823 continue;
824 }
825 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
826 has_msr_bndcfgs = true;
827 continue;
828 }
829 }
830 }
831
832 g_free(kvm_msr_list);
833 }
834
835 return ret;
836 }
837
838 int kvm_arch_init(KVMState *s)
839 {
840 uint64_t identity_base = 0xfffbc000;
841 uint64_t shadow_mem;
842 int ret;
843 struct utsname utsname;
844
845 ret = kvm_get_supported_msrs(s);
846 if (ret < 0) {
847 return ret;
848 }
849
850 uname(&utsname);
851 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
852
853 /*
854 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
855 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
856 * Since these must be part of guest physical memory, we need to allocate
857 * them, both by setting their start addresses in the kernel and by
858 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
859 *
860 * Older KVM versions may not support setting the identity map base. In
861 * that case we need to stick with the default, i.e. a 256K maximum BIOS
862 * size.
863 */
864 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
865 /* Allows up to 16M BIOSes. */
866 identity_base = 0xfeffc000;
867
868 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
869 if (ret < 0) {
870 return ret;
871 }
872 }
873
874 /* Set TSS base one page after EPT identity map. */
875 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
876 if (ret < 0) {
877 return ret;
878 }
879
880 /* Tell fw_cfg to notify the BIOS to reserve the range. */
881 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
882 if (ret < 0) {
883 fprintf(stderr, "e820_add_entry() table is full\n");
884 return ret;
885 }
886 qemu_register_reset(kvm_unpoison_all, NULL);
887
888 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
889 "kvm_shadow_mem", -1);
890 if (shadow_mem != -1) {
891 shadow_mem /= 4096;
892 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
893 if (ret < 0) {
894 return ret;
895 }
896 }
897 return 0;
898 }
899
900 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
901 {
902 lhs->selector = rhs->selector;
903 lhs->base = rhs->base;
904 lhs->limit = rhs->limit;
905 lhs->type = 3;
906 lhs->present = 1;
907 lhs->dpl = 3;
908 lhs->db = 0;
909 lhs->s = 1;
910 lhs->l = 0;
911 lhs->g = 0;
912 lhs->avl = 0;
913 lhs->unusable = 0;
914 }
915
916 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
917 {
918 unsigned flags = rhs->flags;
919 lhs->selector = rhs->selector;
920 lhs->base = rhs->base;
921 lhs->limit = rhs->limit;
922 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
923 lhs->present = (flags & DESC_P_MASK) != 0;
924 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
925 lhs->db = (flags >> DESC_B_SHIFT) & 1;
926 lhs->s = (flags & DESC_S_MASK) != 0;
927 lhs->l = (flags >> DESC_L_SHIFT) & 1;
928 lhs->g = (flags & DESC_G_MASK) != 0;
929 lhs->avl = (flags & DESC_AVL_MASK) != 0;
930 lhs->unusable = 0;
931 lhs->padding = 0;
932 }
933
934 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
935 {
936 lhs->selector = rhs->selector;
937 lhs->base = rhs->base;
938 lhs->limit = rhs->limit;
939 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
940 (rhs->present * DESC_P_MASK) |
941 (rhs->dpl << DESC_DPL_SHIFT) |
942 (rhs->db << DESC_B_SHIFT) |
943 (rhs->s * DESC_S_MASK) |
944 (rhs->l << DESC_L_SHIFT) |
945 (rhs->g * DESC_G_MASK) |
946 (rhs->avl * DESC_AVL_MASK);
947 }
948
949 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
950 {
951 if (set) {
952 *kvm_reg = *qemu_reg;
953 } else {
954 *qemu_reg = *kvm_reg;
955 }
956 }
957
958 static int kvm_getput_regs(X86CPU *cpu, int set)
959 {
960 CPUX86State *env = &cpu->env;
961 struct kvm_regs regs;
962 int ret = 0;
963
964 if (!set) {
965 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
966 if (ret < 0) {
967 return ret;
968 }
969 }
970
971 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
972 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
973 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
974 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
975 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
976 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
977 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
978 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
979 #ifdef TARGET_X86_64
980 kvm_getput_reg(&regs.r8, &env->regs[8], set);
981 kvm_getput_reg(&regs.r9, &env->regs[9], set);
982 kvm_getput_reg(&regs.r10, &env->regs[10], set);
983 kvm_getput_reg(&regs.r11, &env->regs[11], set);
984 kvm_getput_reg(&regs.r12, &env->regs[12], set);
985 kvm_getput_reg(&regs.r13, &env->regs[13], set);
986 kvm_getput_reg(&regs.r14, &env->regs[14], set);
987 kvm_getput_reg(&regs.r15, &env->regs[15], set);
988 #endif
989
990 kvm_getput_reg(&regs.rflags, &env->eflags, set);
991 kvm_getput_reg(&regs.rip, &env->eip, set);
992
993 if (set) {
994 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
995 }
996
997 return ret;
998 }
999
1000 static int kvm_put_fpu(X86CPU *cpu)
1001 {
1002 CPUX86State *env = &cpu->env;
1003 struct kvm_fpu fpu;
1004 int i;
1005
1006 memset(&fpu, 0, sizeof fpu);
1007 fpu.fsw = env->fpus & ~(7 << 11);
1008 fpu.fsw |= (env->fpstt & 7) << 11;
1009 fpu.fcw = env->fpuc;
1010 fpu.last_opcode = env->fpop;
1011 fpu.last_ip = env->fpip;
1012 fpu.last_dp = env->fpdp;
1013 for (i = 0; i < 8; ++i) {
1014 fpu.ftwx |= (!env->fptags[i]) << i;
1015 }
1016 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1017 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
1018 fpu.mxcsr = env->mxcsr;
1019
1020 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1021 }
1022
1023 #define XSAVE_FCW_FSW 0
1024 #define XSAVE_FTW_FOP 1
1025 #define XSAVE_CWD_RIP 2
1026 #define XSAVE_CWD_RDP 4
1027 #define XSAVE_MXCSR 6
1028 #define XSAVE_ST_SPACE 8
1029 #define XSAVE_XMM_SPACE 40
1030 #define XSAVE_XSTATE_BV 128
1031 #define XSAVE_YMMH_SPACE 144
1032 #define XSAVE_BNDREGS 240
1033 #define XSAVE_BNDCSR 256
1034 #define XSAVE_OPMASK 272
1035 #define XSAVE_ZMM_Hi256 288
1036 #define XSAVE_Hi16_ZMM 416
1037
1038 static int kvm_put_xsave(X86CPU *cpu)
1039 {
1040 CPUX86State *env = &cpu->env;
1041 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1042 uint16_t cwd, swd, twd;
1043 int i, r;
1044
1045 if (!kvm_has_xsave()) {
1046 return kvm_put_fpu(cpu);
1047 }
1048
1049 memset(xsave, 0, sizeof(struct kvm_xsave));
1050 twd = 0;
1051 swd = env->fpus & ~(7 << 11);
1052 swd |= (env->fpstt & 7) << 11;
1053 cwd = env->fpuc;
1054 for (i = 0; i < 8; ++i) {
1055 twd |= (!env->fptags[i]) << i;
1056 }
1057 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1058 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1059 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1060 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1061 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1062 sizeof env->fpregs);
1063 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
1064 sizeof env->xmm_regs);
1065 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1066 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1067 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
1068 sizeof env->ymmh_regs);
1069 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1070 sizeof env->bnd_regs);
1071 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1072 sizeof(env->bndcs_regs));
1073 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1074 sizeof env->opmask_regs);
1075 memcpy(&xsave->region[XSAVE_ZMM_Hi256], env->zmmh_regs,
1076 sizeof env->zmmh_regs);
1077 #ifdef TARGET_X86_64
1078 memcpy(&xsave->region[XSAVE_Hi16_ZMM], env->hi16_zmm_regs,
1079 sizeof env->hi16_zmm_regs);
1080 #endif
1081 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1082 return r;
1083 }
1084
1085 static int kvm_put_xcrs(X86CPU *cpu)
1086 {
1087 CPUX86State *env = &cpu->env;
1088 struct kvm_xcrs xcrs = {};
1089
1090 if (!kvm_has_xcrs()) {
1091 return 0;
1092 }
1093
1094 xcrs.nr_xcrs = 1;
1095 xcrs.flags = 0;
1096 xcrs.xcrs[0].xcr = 0;
1097 xcrs.xcrs[0].value = env->xcr0;
1098 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1099 }
1100
1101 static int kvm_put_sregs(X86CPU *cpu)
1102 {
1103 CPUX86State *env = &cpu->env;
1104 struct kvm_sregs sregs;
1105
1106 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1107 if (env->interrupt_injected >= 0) {
1108 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1109 (uint64_t)1 << (env->interrupt_injected % 64);
1110 }
1111
1112 if ((env->eflags & VM_MASK)) {
1113 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1114 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1115 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1116 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1117 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1118 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1119 } else {
1120 set_seg(&sregs.cs, &env->segs[R_CS]);
1121 set_seg(&sregs.ds, &env->segs[R_DS]);
1122 set_seg(&sregs.es, &env->segs[R_ES]);
1123 set_seg(&sregs.fs, &env->segs[R_FS]);
1124 set_seg(&sregs.gs, &env->segs[R_GS]);
1125 set_seg(&sregs.ss, &env->segs[R_SS]);
1126 }
1127
1128 set_seg(&sregs.tr, &env->tr);
1129 set_seg(&sregs.ldt, &env->ldt);
1130
1131 sregs.idt.limit = env->idt.limit;
1132 sregs.idt.base = env->idt.base;
1133 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1134 sregs.gdt.limit = env->gdt.limit;
1135 sregs.gdt.base = env->gdt.base;
1136 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1137
1138 sregs.cr0 = env->cr[0];
1139 sregs.cr2 = env->cr[2];
1140 sregs.cr3 = env->cr[3];
1141 sregs.cr4 = env->cr[4];
1142
1143 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1144 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1145
1146 sregs.efer = env->efer;
1147
1148 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1149 }
1150
1151 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1152 uint32_t index, uint64_t value)
1153 {
1154 entry->index = index;
1155 entry->data = value;
1156 }
1157
1158 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1159 {
1160 CPUX86State *env = &cpu->env;
1161 struct {
1162 struct kvm_msrs info;
1163 struct kvm_msr_entry entries[1];
1164 } msr_data;
1165 struct kvm_msr_entry *msrs = msr_data.entries;
1166
1167 if (!has_msr_tsc_deadline) {
1168 return 0;
1169 }
1170
1171 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1172
1173 msr_data.info.nmsrs = 1;
1174
1175 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1176 }
1177
1178 /*
1179 * Provide a separate write service for the feature control MSR in order to
1180 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1181 * before writing any other state because forcibly leaving nested mode
1182 * invalidates the VCPU state.
1183 */
1184 static int kvm_put_msr_feature_control(X86CPU *cpu)
1185 {
1186 struct {
1187 struct kvm_msrs info;
1188 struct kvm_msr_entry entry;
1189 } msr_data;
1190
1191 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1192 cpu->env.msr_ia32_feature_control);
1193 msr_data.info.nmsrs = 1;
1194 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1195 }
1196
1197 static int kvm_put_msrs(X86CPU *cpu, int level)
1198 {
1199 CPUX86State *env = &cpu->env;
1200 struct {
1201 struct kvm_msrs info;
1202 struct kvm_msr_entry entries[150];
1203 } msr_data;
1204 struct kvm_msr_entry *msrs = msr_data.entries;
1205 int n = 0, i;
1206
1207 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1208 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1209 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1210 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1211 if (has_msr_star) {
1212 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1213 }
1214 if (has_msr_hsave_pa) {
1215 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1216 }
1217 if (has_msr_tsc_adjust) {
1218 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1219 }
1220 if (has_msr_misc_enable) {
1221 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1222 env->msr_ia32_misc_enable);
1223 }
1224 if (has_msr_bndcfgs) {
1225 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1226 }
1227 #ifdef TARGET_X86_64
1228 if (lm_capable_kernel) {
1229 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1230 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1231 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1232 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1233 }
1234 #endif
1235 /*
1236 * The following MSRs have side effects on the guest or are too heavy
1237 * for normal writeback. Limit them to reset or full state updates.
1238 */
1239 if (level >= KVM_PUT_RESET_STATE) {
1240 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1241 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1242 env->system_time_msr);
1243 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1244 if (has_msr_async_pf_en) {
1245 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1246 env->async_pf_en_msr);
1247 }
1248 if (has_msr_pv_eoi_en) {
1249 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1250 env->pv_eoi_en_msr);
1251 }
1252 if (has_msr_kvm_steal_time) {
1253 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1254 env->steal_time_msr);
1255 }
1256 if (has_msr_architectural_pmu) {
1257 /* Stop the counter. */
1258 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1259 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1260
1261 /* Set the counter values. */
1262 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1263 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1264 env->msr_fixed_counters[i]);
1265 }
1266 for (i = 0; i < num_architectural_pmu_counters; i++) {
1267 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1268 env->msr_gp_counters[i]);
1269 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1270 env->msr_gp_evtsel[i]);
1271 }
1272 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1273 env->msr_global_status);
1274 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1275 env->msr_global_ovf_ctrl);
1276
1277 /* Now start the PMU. */
1278 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1279 env->msr_fixed_ctr_ctrl);
1280 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1281 env->msr_global_ctrl);
1282 }
1283 if (has_msr_hv_hypercall) {
1284 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1285 env->msr_hv_guest_os_id);
1286 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1287 env->msr_hv_hypercall);
1288 }
1289 if (has_msr_hv_vapic) {
1290 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1291 env->msr_hv_vapic);
1292 }
1293 if (has_msr_hv_tsc) {
1294 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1295 env->msr_hv_tsc);
1296 }
1297 if (has_msr_mtrr) {
1298 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1299 kvm_msr_entry_set(&msrs[n++],
1300 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1301 kvm_msr_entry_set(&msrs[n++],
1302 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1303 kvm_msr_entry_set(&msrs[n++],
1304 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1305 kvm_msr_entry_set(&msrs[n++],
1306 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1307 kvm_msr_entry_set(&msrs[n++],
1308 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1309 kvm_msr_entry_set(&msrs[n++],
1310 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1311 kvm_msr_entry_set(&msrs[n++],
1312 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1313 kvm_msr_entry_set(&msrs[n++],
1314 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1315 kvm_msr_entry_set(&msrs[n++],
1316 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1317 kvm_msr_entry_set(&msrs[n++],
1318 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1319 kvm_msr_entry_set(&msrs[n++],
1320 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1321 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1322 kvm_msr_entry_set(&msrs[n++],
1323 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1324 kvm_msr_entry_set(&msrs[n++],
1325 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1326 }
1327 }
1328
1329 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1330 * kvm_put_msr_feature_control. */
1331 }
1332 if (env->mcg_cap) {
1333 int i;
1334
1335 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1336 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1337 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1338 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1339 }
1340 }
1341
1342 msr_data.info.nmsrs = n;
1343
1344 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1345
1346 }
1347
1348
1349 static int kvm_get_fpu(X86CPU *cpu)
1350 {
1351 CPUX86State *env = &cpu->env;
1352 struct kvm_fpu fpu;
1353 int i, ret;
1354
1355 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1356 if (ret < 0) {
1357 return ret;
1358 }
1359
1360 env->fpstt = (fpu.fsw >> 11) & 7;
1361 env->fpus = fpu.fsw;
1362 env->fpuc = fpu.fcw;
1363 env->fpop = fpu.last_opcode;
1364 env->fpip = fpu.last_ip;
1365 env->fpdp = fpu.last_dp;
1366 for (i = 0; i < 8; ++i) {
1367 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1368 }
1369 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1370 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1371 env->mxcsr = fpu.mxcsr;
1372
1373 return 0;
1374 }
1375
1376 static int kvm_get_xsave(X86CPU *cpu)
1377 {
1378 CPUX86State *env = &cpu->env;
1379 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1380 int ret, i;
1381 uint16_t cwd, swd, twd;
1382
1383 if (!kvm_has_xsave()) {
1384 return kvm_get_fpu(cpu);
1385 }
1386
1387 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1388 if (ret < 0) {
1389 return ret;
1390 }
1391
1392 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1393 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1394 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1395 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1396 env->fpstt = (swd >> 11) & 7;
1397 env->fpus = swd;
1398 env->fpuc = cwd;
1399 for (i = 0; i < 8; ++i) {
1400 env->fptags[i] = !((twd >> i) & 1);
1401 }
1402 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1403 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1404 env->mxcsr = xsave->region[XSAVE_MXCSR];
1405 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1406 sizeof env->fpregs);
1407 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1408 sizeof env->xmm_regs);
1409 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1410 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1411 sizeof env->ymmh_regs);
1412 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1413 sizeof env->bnd_regs);
1414 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1415 sizeof(env->bndcs_regs));
1416 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1417 sizeof env->opmask_regs);
1418 memcpy(env->zmmh_regs, &xsave->region[XSAVE_ZMM_Hi256],
1419 sizeof env->zmmh_regs);
1420 #ifdef TARGET_X86_64
1421 memcpy(env->hi16_zmm_regs, &xsave->region[XSAVE_Hi16_ZMM],
1422 sizeof env->hi16_zmm_regs);
1423 #endif
1424 return 0;
1425 }
1426
1427 static int kvm_get_xcrs(X86CPU *cpu)
1428 {
1429 CPUX86State *env = &cpu->env;
1430 int i, ret;
1431 struct kvm_xcrs xcrs;
1432
1433 if (!kvm_has_xcrs()) {
1434 return 0;
1435 }
1436
1437 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1438 if (ret < 0) {
1439 return ret;
1440 }
1441
1442 for (i = 0; i < xcrs.nr_xcrs; i++) {
1443 /* Only support xcr0 now */
1444 if (xcrs.xcrs[i].xcr == 0) {
1445 env->xcr0 = xcrs.xcrs[i].value;
1446 break;
1447 }
1448 }
1449 return 0;
1450 }
1451
1452 static int kvm_get_sregs(X86CPU *cpu)
1453 {
1454 CPUX86State *env = &cpu->env;
1455 struct kvm_sregs sregs;
1456 uint32_t hflags;
1457 int bit, i, ret;
1458
1459 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1460 if (ret < 0) {
1461 return ret;
1462 }
1463
1464 /* There can only be one pending IRQ set in the bitmap at a time, so try
1465 to find it and save its number instead (-1 for none). */
1466 env->interrupt_injected = -1;
1467 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1468 if (sregs.interrupt_bitmap[i]) {
1469 bit = ctz64(sregs.interrupt_bitmap[i]);
1470 env->interrupt_injected = i * 64 + bit;
1471 break;
1472 }
1473 }
1474
1475 get_seg(&env->segs[R_CS], &sregs.cs);
1476 get_seg(&env->segs[R_DS], &sregs.ds);
1477 get_seg(&env->segs[R_ES], &sregs.es);
1478 get_seg(&env->segs[R_FS], &sregs.fs);
1479 get_seg(&env->segs[R_GS], &sregs.gs);
1480 get_seg(&env->segs[R_SS], &sregs.ss);
1481
1482 get_seg(&env->tr, &sregs.tr);
1483 get_seg(&env->ldt, &sregs.ldt);
1484
1485 env->idt.limit = sregs.idt.limit;
1486 env->idt.base = sregs.idt.base;
1487 env->gdt.limit = sregs.gdt.limit;
1488 env->gdt.base = sregs.gdt.base;
1489
1490 env->cr[0] = sregs.cr0;
1491 env->cr[2] = sregs.cr2;
1492 env->cr[3] = sregs.cr3;
1493 env->cr[4] = sregs.cr4;
1494
1495 env->efer = sregs.efer;
1496
1497 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1498
1499 #define HFLAG_COPY_MASK \
1500 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1501 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1502 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1503 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1504
1505 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1506 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1507 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1508 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1509 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1510 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1511 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1512
1513 if (env->efer & MSR_EFER_LMA) {
1514 hflags |= HF_LMA_MASK;
1515 }
1516
1517 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1518 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1519 } else {
1520 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1521 (DESC_B_SHIFT - HF_CS32_SHIFT);
1522 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1523 (DESC_B_SHIFT - HF_SS32_SHIFT);
1524 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1525 !(hflags & HF_CS32_MASK)) {
1526 hflags |= HF_ADDSEG_MASK;
1527 } else {
1528 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1529 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1530 }
1531 }
1532 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1533
1534 return 0;
1535 }
1536
1537 static int kvm_get_msrs(X86CPU *cpu)
1538 {
1539 CPUX86State *env = &cpu->env;
1540 struct {
1541 struct kvm_msrs info;
1542 struct kvm_msr_entry entries[150];
1543 } msr_data;
1544 struct kvm_msr_entry *msrs = msr_data.entries;
1545 int ret, i, n;
1546
1547 n = 0;
1548 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1549 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1550 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1551 msrs[n++].index = MSR_PAT;
1552 if (has_msr_star) {
1553 msrs[n++].index = MSR_STAR;
1554 }
1555 if (has_msr_hsave_pa) {
1556 msrs[n++].index = MSR_VM_HSAVE_PA;
1557 }
1558 if (has_msr_tsc_adjust) {
1559 msrs[n++].index = MSR_TSC_ADJUST;
1560 }
1561 if (has_msr_tsc_deadline) {
1562 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1563 }
1564 if (has_msr_misc_enable) {
1565 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1566 }
1567 if (has_msr_feature_control) {
1568 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1569 }
1570 if (has_msr_bndcfgs) {
1571 msrs[n++].index = MSR_IA32_BNDCFGS;
1572 }
1573
1574 if (!env->tsc_valid) {
1575 msrs[n++].index = MSR_IA32_TSC;
1576 env->tsc_valid = !runstate_is_running();
1577 }
1578
1579 #ifdef TARGET_X86_64
1580 if (lm_capable_kernel) {
1581 msrs[n++].index = MSR_CSTAR;
1582 msrs[n++].index = MSR_KERNELGSBASE;
1583 msrs[n++].index = MSR_FMASK;
1584 msrs[n++].index = MSR_LSTAR;
1585 }
1586 #endif
1587 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1588 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1589 if (has_msr_async_pf_en) {
1590 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1591 }
1592 if (has_msr_pv_eoi_en) {
1593 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1594 }
1595 if (has_msr_kvm_steal_time) {
1596 msrs[n++].index = MSR_KVM_STEAL_TIME;
1597 }
1598 if (has_msr_architectural_pmu) {
1599 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1600 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1601 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1602 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1603 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1604 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1605 }
1606 for (i = 0; i < num_architectural_pmu_counters; i++) {
1607 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1608 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1609 }
1610 }
1611
1612 if (env->mcg_cap) {
1613 msrs[n++].index = MSR_MCG_STATUS;
1614 msrs[n++].index = MSR_MCG_CTL;
1615 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1616 msrs[n++].index = MSR_MC0_CTL + i;
1617 }
1618 }
1619
1620 if (has_msr_hv_hypercall) {
1621 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1622 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1623 }
1624 if (has_msr_hv_vapic) {
1625 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1626 }
1627 if (has_msr_hv_tsc) {
1628 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1629 }
1630 if (has_msr_mtrr) {
1631 msrs[n++].index = MSR_MTRRdefType;
1632 msrs[n++].index = MSR_MTRRfix64K_00000;
1633 msrs[n++].index = MSR_MTRRfix16K_80000;
1634 msrs[n++].index = MSR_MTRRfix16K_A0000;
1635 msrs[n++].index = MSR_MTRRfix4K_C0000;
1636 msrs[n++].index = MSR_MTRRfix4K_C8000;
1637 msrs[n++].index = MSR_MTRRfix4K_D0000;
1638 msrs[n++].index = MSR_MTRRfix4K_D8000;
1639 msrs[n++].index = MSR_MTRRfix4K_E0000;
1640 msrs[n++].index = MSR_MTRRfix4K_E8000;
1641 msrs[n++].index = MSR_MTRRfix4K_F0000;
1642 msrs[n++].index = MSR_MTRRfix4K_F8000;
1643 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1644 msrs[n++].index = MSR_MTRRphysBase(i);
1645 msrs[n++].index = MSR_MTRRphysMask(i);
1646 }
1647 }
1648
1649 msr_data.info.nmsrs = n;
1650 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1651 if (ret < 0) {
1652 return ret;
1653 }
1654
1655 for (i = 0; i < ret; i++) {
1656 uint32_t index = msrs[i].index;
1657 switch (index) {
1658 case MSR_IA32_SYSENTER_CS:
1659 env->sysenter_cs = msrs[i].data;
1660 break;
1661 case MSR_IA32_SYSENTER_ESP:
1662 env->sysenter_esp = msrs[i].data;
1663 break;
1664 case MSR_IA32_SYSENTER_EIP:
1665 env->sysenter_eip = msrs[i].data;
1666 break;
1667 case MSR_PAT:
1668 env->pat = msrs[i].data;
1669 break;
1670 case MSR_STAR:
1671 env->star = msrs[i].data;
1672 break;
1673 #ifdef TARGET_X86_64
1674 case MSR_CSTAR:
1675 env->cstar = msrs[i].data;
1676 break;
1677 case MSR_KERNELGSBASE:
1678 env->kernelgsbase = msrs[i].data;
1679 break;
1680 case MSR_FMASK:
1681 env->fmask = msrs[i].data;
1682 break;
1683 case MSR_LSTAR:
1684 env->lstar = msrs[i].data;
1685 break;
1686 #endif
1687 case MSR_IA32_TSC:
1688 env->tsc = msrs[i].data;
1689 break;
1690 case MSR_TSC_ADJUST:
1691 env->tsc_adjust = msrs[i].data;
1692 break;
1693 case MSR_IA32_TSCDEADLINE:
1694 env->tsc_deadline = msrs[i].data;
1695 break;
1696 case MSR_VM_HSAVE_PA:
1697 env->vm_hsave = msrs[i].data;
1698 break;
1699 case MSR_KVM_SYSTEM_TIME:
1700 env->system_time_msr = msrs[i].data;
1701 break;
1702 case MSR_KVM_WALL_CLOCK:
1703 env->wall_clock_msr = msrs[i].data;
1704 break;
1705 case MSR_MCG_STATUS:
1706 env->mcg_status = msrs[i].data;
1707 break;
1708 case MSR_MCG_CTL:
1709 env->mcg_ctl = msrs[i].data;
1710 break;
1711 case MSR_IA32_MISC_ENABLE:
1712 env->msr_ia32_misc_enable = msrs[i].data;
1713 break;
1714 case MSR_IA32_FEATURE_CONTROL:
1715 env->msr_ia32_feature_control = msrs[i].data;
1716 break;
1717 case MSR_IA32_BNDCFGS:
1718 env->msr_bndcfgs = msrs[i].data;
1719 break;
1720 default:
1721 if (msrs[i].index >= MSR_MC0_CTL &&
1722 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1723 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1724 }
1725 break;
1726 case MSR_KVM_ASYNC_PF_EN:
1727 env->async_pf_en_msr = msrs[i].data;
1728 break;
1729 case MSR_KVM_PV_EOI_EN:
1730 env->pv_eoi_en_msr = msrs[i].data;
1731 break;
1732 case MSR_KVM_STEAL_TIME:
1733 env->steal_time_msr = msrs[i].data;
1734 break;
1735 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1736 env->msr_fixed_ctr_ctrl = msrs[i].data;
1737 break;
1738 case MSR_CORE_PERF_GLOBAL_CTRL:
1739 env->msr_global_ctrl = msrs[i].data;
1740 break;
1741 case MSR_CORE_PERF_GLOBAL_STATUS:
1742 env->msr_global_status = msrs[i].data;
1743 break;
1744 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1745 env->msr_global_ovf_ctrl = msrs[i].data;
1746 break;
1747 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1748 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1749 break;
1750 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1751 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1752 break;
1753 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1754 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1755 break;
1756 case HV_X64_MSR_HYPERCALL:
1757 env->msr_hv_hypercall = msrs[i].data;
1758 break;
1759 case HV_X64_MSR_GUEST_OS_ID:
1760 env->msr_hv_guest_os_id = msrs[i].data;
1761 break;
1762 case HV_X64_MSR_APIC_ASSIST_PAGE:
1763 env->msr_hv_vapic = msrs[i].data;
1764 break;
1765 case HV_X64_MSR_REFERENCE_TSC:
1766 env->msr_hv_tsc = msrs[i].data;
1767 break;
1768 case MSR_MTRRdefType:
1769 env->mtrr_deftype = msrs[i].data;
1770 break;
1771 case MSR_MTRRfix64K_00000:
1772 env->mtrr_fixed[0] = msrs[i].data;
1773 break;
1774 case MSR_MTRRfix16K_80000:
1775 env->mtrr_fixed[1] = msrs[i].data;
1776 break;
1777 case MSR_MTRRfix16K_A0000:
1778 env->mtrr_fixed[2] = msrs[i].data;
1779 break;
1780 case MSR_MTRRfix4K_C0000:
1781 env->mtrr_fixed[3] = msrs[i].data;
1782 break;
1783 case MSR_MTRRfix4K_C8000:
1784 env->mtrr_fixed[4] = msrs[i].data;
1785 break;
1786 case MSR_MTRRfix4K_D0000:
1787 env->mtrr_fixed[5] = msrs[i].data;
1788 break;
1789 case MSR_MTRRfix4K_D8000:
1790 env->mtrr_fixed[6] = msrs[i].data;
1791 break;
1792 case MSR_MTRRfix4K_E0000:
1793 env->mtrr_fixed[7] = msrs[i].data;
1794 break;
1795 case MSR_MTRRfix4K_E8000:
1796 env->mtrr_fixed[8] = msrs[i].data;
1797 break;
1798 case MSR_MTRRfix4K_F0000:
1799 env->mtrr_fixed[9] = msrs[i].data;
1800 break;
1801 case MSR_MTRRfix4K_F8000:
1802 env->mtrr_fixed[10] = msrs[i].data;
1803 break;
1804 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1805 if (index & 1) {
1806 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1807 } else {
1808 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1809 }
1810 break;
1811 }
1812 }
1813
1814 return 0;
1815 }
1816
1817 static int kvm_put_mp_state(X86CPU *cpu)
1818 {
1819 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1820
1821 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1822 }
1823
1824 static int kvm_get_mp_state(X86CPU *cpu)
1825 {
1826 CPUState *cs = CPU(cpu);
1827 CPUX86State *env = &cpu->env;
1828 struct kvm_mp_state mp_state;
1829 int ret;
1830
1831 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1832 if (ret < 0) {
1833 return ret;
1834 }
1835 env->mp_state = mp_state.mp_state;
1836 if (kvm_irqchip_in_kernel()) {
1837 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1838 }
1839 return 0;
1840 }
1841
1842 static int kvm_get_apic(X86CPU *cpu)
1843 {
1844 DeviceState *apic = cpu->apic_state;
1845 struct kvm_lapic_state kapic;
1846 int ret;
1847
1848 if (apic && kvm_irqchip_in_kernel()) {
1849 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1850 if (ret < 0) {
1851 return ret;
1852 }
1853
1854 kvm_get_apic_state(apic, &kapic);
1855 }
1856 return 0;
1857 }
1858
1859 static int kvm_put_apic(X86CPU *cpu)
1860 {
1861 DeviceState *apic = cpu->apic_state;
1862 struct kvm_lapic_state kapic;
1863
1864 if (apic && kvm_irqchip_in_kernel()) {
1865 kvm_put_apic_state(apic, &kapic);
1866
1867 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1868 }
1869 return 0;
1870 }
1871
1872 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1873 {
1874 CPUX86State *env = &cpu->env;
1875 struct kvm_vcpu_events events;
1876
1877 if (!kvm_has_vcpu_events()) {
1878 return 0;
1879 }
1880
1881 events.exception.injected = (env->exception_injected >= 0);
1882 events.exception.nr = env->exception_injected;
1883 events.exception.has_error_code = env->has_error_code;
1884 events.exception.error_code = env->error_code;
1885 events.exception.pad = 0;
1886
1887 events.interrupt.injected = (env->interrupt_injected >= 0);
1888 events.interrupt.nr = env->interrupt_injected;
1889 events.interrupt.soft = env->soft_interrupt;
1890
1891 events.nmi.injected = env->nmi_injected;
1892 events.nmi.pending = env->nmi_pending;
1893 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1894 events.nmi.pad = 0;
1895
1896 events.sipi_vector = env->sipi_vector;
1897
1898 events.flags = 0;
1899 if (level >= KVM_PUT_RESET_STATE) {
1900 events.flags |=
1901 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1902 }
1903
1904 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1905 }
1906
1907 static int kvm_get_vcpu_events(X86CPU *cpu)
1908 {
1909 CPUX86State *env = &cpu->env;
1910 struct kvm_vcpu_events events;
1911 int ret;
1912
1913 if (!kvm_has_vcpu_events()) {
1914 return 0;
1915 }
1916
1917 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1918 if (ret < 0) {
1919 return ret;
1920 }
1921 env->exception_injected =
1922 events.exception.injected ? events.exception.nr : -1;
1923 env->has_error_code = events.exception.has_error_code;
1924 env->error_code = events.exception.error_code;
1925
1926 env->interrupt_injected =
1927 events.interrupt.injected ? events.interrupt.nr : -1;
1928 env->soft_interrupt = events.interrupt.soft;
1929
1930 env->nmi_injected = events.nmi.injected;
1931 env->nmi_pending = events.nmi.pending;
1932 if (events.nmi.masked) {
1933 env->hflags2 |= HF2_NMI_MASK;
1934 } else {
1935 env->hflags2 &= ~HF2_NMI_MASK;
1936 }
1937
1938 env->sipi_vector = events.sipi_vector;
1939
1940 return 0;
1941 }
1942
1943 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1944 {
1945 CPUState *cs = CPU(cpu);
1946 CPUX86State *env = &cpu->env;
1947 int ret = 0;
1948 unsigned long reinject_trap = 0;
1949
1950 if (!kvm_has_vcpu_events()) {
1951 if (env->exception_injected == 1) {
1952 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1953 } else if (env->exception_injected == 3) {
1954 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1955 }
1956 env->exception_injected = -1;
1957 }
1958
1959 /*
1960 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1961 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1962 * by updating the debug state once again if single-stepping is on.
1963 * Another reason to call kvm_update_guest_debug here is a pending debug
1964 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1965 * reinject them via SET_GUEST_DEBUG.
1966 */
1967 if (reinject_trap ||
1968 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1969 ret = kvm_update_guest_debug(cs, reinject_trap);
1970 }
1971 return ret;
1972 }
1973
1974 static int kvm_put_debugregs(X86CPU *cpu)
1975 {
1976 CPUX86State *env = &cpu->env;
1977 struct kvm_debugregs dbgregs;
1978 int i;
1979
1980 if (!kvm_has_debugregs()) {
1981 return 0;
1982 }
1983
1984 for (i = 0; i < 4; i++) {
1985 dbgregs.db[i] = env->dr[i];
1986 }
1987 dbgregs.dr6 = env->dr[6];
1988 dbgregs.dr7 = env->dr[7];
1989 dbgregs.flags = 0;
1990
1991 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1992 }
1993
1994 static int kvm_get_debugregs(X86CPU *cpu)
1995 {
1996 CPUX86State *env = &cpu->env;
1997 struct kvm_debugregs dbgregs;
1998 int i, ret;
1999
2000 if (!kvm_has_debugregs()) {
2001 return 0;
2002 }
2003
2004 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2005 if (ret < 0) {
2006 return ret;
2007 }
2008 for (i = 0; i < 4; i++) {
2009 env->dr[i] = dbgregs.db[i];
2010 }
2011 env->dr[4] = env->dr[6] = dbgregs.dr6;
2012 env->dr[5] = env->dr[7] = dbgregs.dr7;
2013
2014 return 0;
2015 }
2016
2017 int kvm_arch_put_registers(CPUState *cpu, int level)
2018 {
2019 X86CPU *x86_cpu = X86_CPU(cpu);
2020 int ret;
2021
2022 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2023
2024 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2025 ret = kvm_put_msr_feature_control(x86_cpu);
2026 if (ret < 0) {
2027 return ret;
2028 }
2029 }
2030
2031 ret = kvm_getput_regs(x86_cpu, 1);
2032 if (ret < 0) {
2033 return ret;
2034 }
2035 ret = kvm_put_xsave(x86_cpu);
2036 if (ret < 0) {
2037 return ret;
2038 }
2039 ret = kvm_put_xcrs(x86_cpu);
2040 if (ret < 0) {
2041 return ret;
2042 }
2043 ret = kvm_put_sregs(x86_cpu);
2044 if (ret < 0) {
2045 return ret;
2046 }
2047 /* must be before kvm_put_msrs */
2048 ret = kvm_inject_mce_oldstyle(x86_cpu);
2049 if (ret < 0) {
2050 return ret;
2051 }
2052 ret = kvm_put_msrs(x86_cpu, level);
2053 if (ret < 0) {
2054 return ret;
2055 }
2056 if (level >= KVM_PUT_RESET_STATE) {
2057 ret = kvm_put_mp_state(x86_cpu);
2058 if (ret < 0) {
2059 return ret;
2060 }
2061 ret = kvm_put_apic(x86_cpu);
2062 if (ret < 0) {
2063 return ret;
2064 }
2065 }
2066
2067 ret = kvm_put_tscdeadline_msr(x86_cpu);
2068 if (ret < 0) {
2069 return ret;
2070 }
2071
2072 ret = kvm_put_vcpu_events(x86_cpu, level);
2073 if (ret < 0) {
2074 return ret;
2075 }
2076 ret = kvm_put_debugregs(x86_cpu);
2077 if (ret < 0) {
2078 return ret;
2079 }
2080 /* must be last */
2081 ret = kvm_guest_debug_workarounds(x86_cpu);
2082 if (ret < 0) {
2083 return ret;
2084 }
2085 return 0;
2086 }
2087
2088 int kvm_arch_get_registers(CPUState *cs)
2089 {
2090 X86CPU *cpu = X86_CPU(cs);
2091 int ret;
2092
2093 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2094
2095 ret = kvm_getput_regs(cpu, 0);
2096 if (ret < 0) {
2097 return ret;
2098 }
2099 ret = kvm_get_xsave(cpu);
2100 if (ret < 0) {
2101 return ret;
2102 }
2103 ret = kvm_get_xcrs(cpu);
2104 if (ret < 0) {
2105 return ret;
2106 }
2107 ret = kvm_get_sregs(cpu);
2108 if (ret < 0) {
2109 return ret;
2110 }
2111 ret = kvm_get_msrs(cpu);
2112 if (ret < 0) {
2113 return ret;
2114 }
2115 ret = kvm_get_mp_state(cpu);
2116 if (ret < 0) {
2117 return ret;
2118 }
2119 ret = kvm_get_apic(cpu);
2120 if (ret < 0) {
2121 return ret;
2122 }
2123 ret = kvm_get_vcpu_events(cpu);
2124 if (ret < 0) {
2125 return ret;
2126 }
2127 ret = kvm_get_debugregs(cpu);
2128 if (ret < 0) {
2129 return ret;
2130 }
2131 return 0;
2132 }
2133
2134 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2135 {
2136 X86CPU *x86_cpu = X86_CPU(cpu);
2137 CPUX86State *env = &x86_cpu->env;
2138 int ret;
2139
2140 /* Inject NMI */
2141 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2142 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2143 DPRINTF("injected NMI\n");
2144 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2145 if (ret < 0) {
2146 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2147 strerror(-ret));
2148 }
2149 }
2150
2151 /* Force the VCPU out of its inner loop to process any INIT requests
2152 * or (for userspace APIC, but it is cheap to combine the checks here)
2153 * pending TPR access reports.
2154 */
2155 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2156 cpu->exit_request = 1;
2157 }
2158
2159 if (!kvm_irqchip_in_kernel()) {
2160 /* Try to inject an interrupt if the guest can accept it */
2161 if (run->ready_for_interrupt_injection &&
2162 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2163 (env->eflags & IF_MASK)) {
2164 int irq;
2165
2166 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2167 irq = cpu_get_pic_interrupt(env);
2168 if (irq >= 0) {
2169 struct kvm_interrupt intr;
2170
2171 intr.irq = irq;
2172 DPRINTF("injected interrupt %d\n", irq);
2173 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2174 if (ret < 0) {
2175 fprintf(stderr,
2176 "KVM: injection failed, interrupt lost (%s)\n",
2177 strerror(-ret));
2178 }
2179 }
2180 }
2181
2182 /* If we have an interrupt but the guest is not ready to receive an
2183 * interrupt, request an interrupt window exit. This will
2184 * cause a return to userspace as soon as the guest is ready to
2185 * receive interrupts. */
2186 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2187 run->request_interrupt_window = 1;
2188 } else {
2189 run->request_interrupt_window = 0;
2190 }
2191
2192 DPRINTF("setting tpr\n");
2193 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2194 }
2195 }
2196
2197 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2198 {
2199 X86CPU *x86_cpu = X86_CPU(cpu);
2200 CPUX86State *env = &x86_cpu->env;
2201
2202 if (run->if_flag) {
2203 env->eflags |= IF_MASK;
2204 } else {
2205 env->eflags &= ~IF_MASK;
2206 }
2207 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2208 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2209 }
2210
2211 int kvm_arch_process_async_events(CPUState *cs)
2212 {
2213 X86CPU *cpu = X86_CPU(cs);
2214 CPUX86State *env = &cpu->env;
2215
2216 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2217 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2218 assert(env->mcg_cap);
2219
2220 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2221
2222 kvm_cpu_synchronize_state(cs);
2223
2224 if (env->exception_injected == EXCP08_DBLE) {
2225 /* this means triple fault */
2226 qemu_system_reset_request();
2227 cs->exit_request = 1;
2228 return 0;
2229 }
2230 env->exception_injected = EXCP12_MCHK;
2231 env->has_error_code = 0;
2232
2233 cs->halted = 0;
2234 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2235 env->mp_state = KVM_MP_STATE_RUNNABLE;
2236 }
2237 }
2238
2239 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2240 kvm_cpu_synchronize_state(cs);
2241 do_cpu_init(cpu);
2242 }
2243
2244 if (kvm_irqchip_in_kernel()) {
2245 return 0;
2246 }
2247
2248 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2249 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2250 apic_poll_irq(cpu->apic_state);
2251 }
2252 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2253 (env->eflags & IF_MASK)) ||
2254 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2255 cs->halted = 0;
2256 }
2257 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2258 kvm_cpu_synchronize_state(cs);
2259 do_cpu_sipi(cpu);
2260 }
2261 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2262 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2263 kvm_cpu_synchronize_state(cs);
2264 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2265 env->tpr_access_type);
2266 }
2267
2268 return cs->halted;
2269 }
2270
2271 static int kvm_handle_halt(X86CPU *cpu)
2272 {
2273 CPUState *cs = CPU(cpu);
2274 CPUX86State *env = &cpu->env;
2275
2276 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2277 (env->eflags & IF_MASK)) &&
2278 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2279 cs->halted = 1;
2280 return EXCP_HLT;
2281 }
2282
2283 return 0;
2284 }
2285
2286 static int kvm_handle_tpr_access(X86CPU *cpu)
2287 {
2288 CPUState *cs = CPU(cpu);
2289 struct kvm_run *run = cs->kvm_run;
2290
2291 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2292 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2293 : TPR_ACCESS_READ);
2294 return 1;
2295 }
2296
2297 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2298 {
2299 static const uint8_t int3 = 0xcc;
2300
2301 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2302 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2303 return -EINVAL;
2304 }
2305 return 0;
2306 }
2307
2308 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2309 {
2310 uint8_t int3;
2311
2312 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2313 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2314 return -EINVAL;
2315 }
2316 return 0;
2317 }
2318
2319 static struct {
2320 target_ulong addr;
2321 int len;
2322 int type;
2323 } hw_breakpoint[4];
2324
2325 static int nb_hw_breakpoint;
2326
2327 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2328 {
2329 int n;
2330
2331 for (n = 0; n < nb_hw_breakpoint; n++) {
2332 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2333 (hw_breakpoint[n].len == len || len == -1)) {
2334 return n;
2335 }
2336 }
2337 return -1;
2338 }
2339
2340 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2341 target_ulong len, int type)
2342 {
2343 switch (type) {
2344 case GDB_BREAKPOINT_HW:
2345 len = 1;
2346 break;
2347 case GDB_WATCHPOINT_WRITE:
2348 case GDB_WATCHPOINT_ACCESS:
2349 switch (len) {
2350 case 1:
2351 break;
2352 case 2:
2353 case 4:
2354 case 8:
2355 if (addr & (len - 1)) {
2356 return -EINVAL;
2357 }
2358 break;
2359 default:
2360 return -EINVAL;
2361 }
2362 break;
2363 default:
2364 return -ENOSYS;
2365 }
2366
2367 if (nb_hw_breakpoint == 4) {
2368 return -ENOBUFS;
2369 }
2370 if (find_hw_breakpoint(addr, len, type) >= 0) {
2371 return -EEXIST;
2372 }
2373 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2374 hw_breakpoint[nb_hw_breakpoint].len = len;
2375 hw_breakpoint[nb_hw_breakpoint].type = type;
2376 nb_hw_breakpoint++;
2377
2378 return 0;
2379 }
2380
2381 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2382 target_ulong len, int type)
2383 {
2384 int n;
2385
2386 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2387 if (n < 0) {
2388 return -ENOENT;
2389 }
2390 nb_hw_breakpoint--;
2391 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2392
2393 return 0;
2394 }
2395
2396 void kvm_arch_remove_all_hw_breakpoints(void)
2397 {
2398 nb_hw_breakpoint = 0;
2399 }
2400
2401 static CPUWatchpoint hw_watchpoint;
2402
2403 static int kvm_handle_debug(X86CPU *cpu,
2404 struct kvm_debug_exit_arch *arch_info)
2405 {
2406 CPUState *cs = CPU(cpu);
2407 CPUX86State *env = &cpu->env;
2408 int ret = 0;
2409 int n;
2410
2411 if (arch_info->exception == 1) {
2412 if (arch_info->dr6 & (1 << 14)) {
2413 if (cs->singlestep_enabled) {
2414 ret = EXCP_DEBUG;
2415 }
2416 } else {
2417 for (n = 0; n < 4; n++) {
2418 if (arch_info->dr6 & (1 << n)) {
2419 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2420 case 0x0:
2421 ret = EXCP_DEBUG;
2422 break;
2423 case 0x1:
2424 ret = EXCP_DEBUG;
2425 cs->watchpoint_hit = &hw_watchpoint;
2426 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2427 hw_watchpoint.flags = BP_MEM_WRITE;
2428 break;
2429 case 0x3:
2430 ret = EXCP_DEBUG;
2431 cs->watchpoint_hit = &hw_watchpoint;
2432 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2433 hw_watchpoint.flags = BP_MEM_ACCESS;
2434 break;
2435 }
2436 }
2437 }
2438 }
2439 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2440 ret = EXCP_DEBUG;
2441 }
2442 if (ret == 0) {
2443 cpu_synchronize_state(cs);
2444 assert(env->exception_injected == -1);
2445
2446 /* pass to guest */
2447 env->exception_injected = arch_info->exception;
2448 env->has_error_code = 0;
2449 }
2450
2451 return ret;
2452 }
2453
2454 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2455 {
2456 const uint8_t type_code[] = {
2457 [GDB_BREAKPOINT_HW] = 0x0,
2458 [GDB_WATCHPOINT_WRITE] = 0x1,
2459 [GDB_WATCHPOINT_ACCESS] = 0x3
2460 };
2461 const uint8_t len_code[] = {
2462 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2463 };
2464 int n;
2465
2466 if (kvm_sw_breakpoints_active(cpu)) {
2467 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2468 }
2469 if (nb_hw_breakpoint > 0) {
2470 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2471 dbg->arch.debugreg[7] = 0x0600;
2472 for (n = 0; n < nb_hw_breakpoint; n++) {
2473 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2474 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2475 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2476 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2477 }
2478 }
2479 }
2480
2481 static bool host_supports_vmx(void)
2482 {
2483 uint32_t ecx, unused;
2484
2485 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2486 return ecx & CPUID_EXT_VMX;
2487 }
2488
2489 #define VMX_INVALID_GUEST_STATE 0x80000021
2490
2491 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2492 {
2493 X86CPU *cpu = X86_CPU(cs);
2494 uint64_t code;
2495 int ret;
2496
2497 switch (run->exit_reason) {
2498 case KVM_EXIT_HLT:
2499 DPRINTF("handle_hlt\n");
2500 ret = kvm_handle_halt(cpu);
2501 break;
2502 case KVM_EXIT_SET_TPR:
2503 ret = 0;
2504 break;
2505 case KVM_EXIT_TPR_ACCESS:
2506 ret = kvm_handle_tpr_access(cpu);
2507 break;
2508 case KVM_EXIT_FAIL_ENTRY:
2509 code = run->fail_entry.hardware_entry_failure_reason;
2510 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2511 code);
2512 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2513 fprintf(stderr,
2514 "\nIf you're running a guest on an Intel machine without "
2515 "unrestricted mode\n"
2516 "support, the failure can be most likely due to the guest "
2517 "entering an invalid\n"
2518 "state for Intel VT. For example, the guest maybe running "
2519 "in big real mode\n"
2520 "which is not supported on less recent Intel processors."
2521 "\n\n");
2522 }
2523 ret = -1;
2524 break;
2525 case KVM_EXIT_EXCEPTION:
2526 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2527 run->ex.exception, run->ex.error_code);
2528 ret = -1;
2529 break;
2530 case KVM_EXIT_DEBUG:
2531 DPRINTF("kvm_exit_debug\n");
2532 ret = kvm_handle_debug(cpu, &run->debug.arch);
2533 break;
2534 default:
2535 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2536 ret = -1;
2537 break;
2538 }
2539
2540 return ret;
2541 }
2542
2543 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2544 {
2545 X86CPU *cpu = X86_CPU(cs);
2546 CPUX86State *env = &cpu->env;
2547
2548 kvm_cpu_synchronize_state(cs);
2549 return !(env->cr[0] & CR0_PE_MASK) ||
2550 ((env->segs[R_CS].selector & 3) != 3);
2551 }
2552
2553 void kvm_arch_init_irq_routing(KVMState *s)
2554 {
2555 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2556 /* If kernel can't do irq routing, interrupt source
2557 * override 0->2 cannot be set up as required by HPET.
2558 * So we have to disable it.
2559 */
2560 no_hpet = 1;
2561 }
2562 /* We know at this point that we're using the in-kernel
2563 * irqchip, so we can use irqfds, and on x86 we know
2564 * we can use msi via irqfd and GSI routing.
2565 */
2566 kvm_msi_via_irqfd_allowed = true;
2567 kvm_gsi_routing_allowed = true;
2568 }
2569
2570 /* Classic KVM device assignment interface. Will remain x86 only. */
2571 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2572 uint32_t flags, uint32_t *dev_id)
2573 {
2574 struct kvm_assigned_pci_dev dev_data = {
2575 .segnr = dev_addr->domain,
2576 .busnr = dev_addr->bus,
2577 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2578 .flags = flags,
2579 };
2580 int ret;
2581
2582 dev_data.assigned_dev_id =
2583 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2584
2585 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2586 if (ret < 0) {
2587 return ret;
2588 }
2589
2590 *dev_id = dev_data.assigned_dev_id;
2591
2592 return 0;
2593 }
2594
2595 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2596 {
2597 struct kvm_assigned_pci_dev dev_data = {
2598 .assigned_dev_id = dev_id,
2599 };
2600
2601 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2602 }
2603
2604 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2605 uint32_t irq_type, uint32_t guest_irq)
2606 {
2607 struct kvm_assigned_irq assigned_irq = {
2608 .assigned_dev_id = dev_id,
2609 .guest_irq = guest_irq,
2610 .flags = irq_type,
2611 };
2612
2613 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2614 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2615 } else {
2616 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2617 }
2618 }
2619
2620 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2621 uint32_t guest_irq)
2622 {
2623 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2624 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2625
2626 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2627 }
2628
2629 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2630 {
2631 struct kvm_assigned_pci_dev dev_data = {
2632 .assigned_dev_id = dev_id,
2633 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2634 };
2635
2636 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2637 }
2638
2639 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2640 uint32_t type)
2641 {
2642 struct kvm_assigned_irq assigned_irq = {
2643 .assigned_dev_id = dev_id,
2644 .flags = type,
2645 };
2646
2647 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2648 }
2649
2650 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2651 {
2652 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2653 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2654 }
2655
2656 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2657 {
2658 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2659 KVM_DEV_IRQ_GUEST_MSI, virq);
2660 }
2661
2662 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2663 {
2664 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2665 KVM_DEV_IRQ_HOST_MSI);
2666 }
2667
2668 bool kvm_device_msix_supported(KVMState *s)
2669 {
2670 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2671 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2672 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2673 }
2674
2675 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2676 uint32_t nr_vectors)
2677 {
2678 struct kvm_assigned_msix_nr msix_nr = {
2679 .assigned_dev_id = dev_id,
2680 .entry_nr = nr_vectors,
2681 };
2682
2683 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2684 }
2685
2686 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2687 int virq)
2688 {
2689 struct kvm_assigned_msix_entry msix_entry = {
2690 .assigned_dev_id = dev_id,
2691 .gsi = virq,
2692 .entry = vector,
2693 };
2694
2695 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2696 }
2697
2698 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2699 {
2700 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2701 KVM_DEV_IRQ_GUEST_MSIX, 0);
2702 }
2703
2704 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2705 {
2706 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2707 KVM_DEV_IRQ_HOST_MSIX);
2708 }
QEmu