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target/arm: make psci-conduit settable after realize
[qemu.git] / hw / block / m25p80.c
blobc6bf3c6bfa833b65526bf0bb61a6b50a214e31e5
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/qdev-properties-system.h"
29 #include "hw/ssi/ssi.h"
30 #include "migration/vmstate.h"
31 #include "qemu/bitops.h"
32 #include "qemu/log.h"
33 #include "qemu/module.h"
34 #include "qemu/error-report.h"
35 #include "qapi/error.h"
36 #include "trace.h"
37 #include "qom/object.h"
38
39 /* Fields for FlashPartInfo->flags */
40
41 /* erase capabilities */
42 #define ER_4K 1
43 #define ER_32K 2
44 /* set to allow the page program command to write 0s back to 1. Useful for
45 * modelling EEPROM with SPI flash command set
46 */
47 #define EEPROM 0x100
48
49 /* 16 MiB max in 3 byte address mode */
50 #define MAX_3BYTES_SIZE 0x1000000
51
52 #define SPI_NOR_MAX_ID_LEN 6
53
54 typedef struct FlashPartInfo {
55 const char *part_name;
56 /*
57 * This array stores the ID bytes.
58 * The first three bytes are the JEDIC ID.
59 * JEDEC ID zero means "no ID" (mostly older chips).
60 */
61 uint8_t id[SPI_NOR_MAX_ID_LEN];
62 uint8_t id_len;
63 /* there is confusion between manufacturers as to what a sector is. In this
64 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
65 * command (opcode 0xd8).
66 */
67 uint32_t sector_size;
68 uint32_t n_sectors;
69 uint32_t page_size;
70 uint16_t flags;
71 /*
72 * Big sized spi nor are often stacked devices, thus sometime
73 * replace chip erase with die erase.
74 * This field inform how many die is in the chip.
75 */
76 uint8_t die_cnt;
77 } FlashPartInfo;
78
79 /* adapted from linux */
80 /* Used when the "_ext_id" is two bytes at most */
81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
82 .part_name = _part_name,\
83 .id = {\
84 ((_jedec_id) >> 16) & 0xff,\
85 ((_jedec_id) >> 8) & 0xff,\
86 (_jedec_id) & 0xff,\
87 ((_ext_id) >> 8) & 0xff,\
88 (_ext_id) & 0xff,\
89 },\
90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
91 .sector_size = (_sector_size),\
92 .n_sectors = (_n_sectors),\
93 .page_size = 256,\
94 .flags = (_flags),\
95 .die_cnt = 0
96
97 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
98 .part_name = _part_name,\
99 .id = {\
100 ((_jedec_id) >> 16) & 0xff,\
101 ((_jedec_id) >> 8) & 0xff,\
102 (_jedec_id) & 0xff,\
103 ((_ext_id) >> 16) & 0xff,\
104 ((_ext_id) >> 8) & 0xff,\
105 (_ext_id) & 0xff,\
106 },\
107 .id_len = 6,\
108 .sector_size = (_sector_size),\
109 .n_sectors = (_n_sectors),\
110 .page_size = 256,\
111 .flags = (_flags),\
112 .die_cnt = 0
113
114 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
115 _flags, _die_cnt)\
116 .part_name = _part_name,\
117 .id = {\
118 ((_jedec_id) >> 16) & 0xff,\
119 ((_jedec_id) >> 8) & 0xff,\
120 (_jedec_id) & 0xff,\
121 ((_ext_id) >> 8) & 0xff,\
122 (_ext_id) & 0xff,\
123 },\
124 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
125 .sector_size = (_sector_size),\
126 .n_sectors = (_n_sectors),\
127 .page_size = 256,\
128 .flags = (_flags),\
129 .die_cnt = _die_cnt
130
131 #define JEDEC_NUMONYX 0x20
132 #define JEDEC_WINBOND 0xEF
133 #define JEDEC_SPANSION 0x01
134
135 /* Numonyx (Micron) Configuration register macros */
136 #define VCFG_DUMMY 0x1
137 #define VCFG_WRAP_SEQUENTIAL 0x2
138 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
139 #define NVCFG_XIP_MODE_MASK (7 << 9)
140 #define VCFG_XIP_MODE_DISABLED (1 << 3)
141 #define CFG_DUMMY_CLK_LEN 4
142 #define NVCFG_DUMMY_CLK_POS 12
143 #define VCFG_DUMMY_CLK_POS 4
144 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
145 #define EVCFG_VPP_ACCELERATOR (1 << 3)
146 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
147 #define NVCFG_DUAL_IO_MASK (1 << 2)
148 #define EVCFG_DUAL_IO_DISABLED (1 << 6)
149 #define NVCFG_QUAD_IO_MASK (1 << 3)
150 #define EVCFG_QUAD_IO_DISABLED (1 << 7)
151 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
152 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
153
154 /* Numonyx (Micron) Flag Status Register macros */
155 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
156 #define FSR_FLASH_READY (1 << 7)
157
158 /* Spansion configuration registers macros. */
159 #define SPANSION_QUAD_CFG_POS 0
160 #define SPANSION_QUAD_CFG_LEN 1
161 #define SPANSION_DUMMY_CLK_POS 0
162 #define SPANSION_DUMMY_CLK_LEN 4
163 #define SPANSION_ADDR_LEN_POS 7
164 #define SPANSION_ADDR_LEN_LEN 1
165
166 /*
167 * Spansion read mode command length in bytes,
168 * the mode is currently not supported.
169 */
170
171 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
172 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
173
174 static const FlashPartInfo known_devices[] = {
175 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
176 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
177 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
178
179 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
180 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
181 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
182
183 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
184 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
185 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
186 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
187
188 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
189
190 /* Atmel EEPROMS - it is assumed, that don't care bit in command
191 * is set to 0. Block protection is not supported.
192 */
193 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
194 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
195
196 /* EON -- en25xxx */
197 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
198 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
199 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
200 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
201 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
202
203 /* GigaDevice */
204 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
205 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
206
207 /* Intel/Numonyx -- xxxs33b */
208 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
209 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
210 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
211 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
212
213 /* ISSI */
214 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) },
215 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) },
216 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) },
217 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) },
218 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) },
219 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) },
220 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) },
221 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
222 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
223 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
224 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) },
225
226 /* Macronix */
227 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
228 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
229 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
230 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
231 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
232 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
233 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
234 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
235 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) },
236 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
237 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
238 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
239 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
240 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
241
242 /* Micron */
243 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
244 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
245 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
246 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
247 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
248 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
249 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
250 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
251 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) },
252 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
253 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
254 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
255 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
256 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },
257 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
258 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024,
259 ER_4K | ER_32K, 2) },
260 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
261 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
262 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
263 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
264 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) },
265 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) },
266
267 /* Spansion -- single (large) sector size only, at least
268 * for the chips listed here (without boot sectors).
269 */
270 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
271 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
272 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
273 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
274 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
275 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
276 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
277 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
278 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
279 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
280 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
281 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
282 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
283 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
284 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
285 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
286 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
287
288 /* Spansion -- boot sectors support */
289 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
290 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
291
292 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
293 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
294 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
295 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
296 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
297 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
298 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
299 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
300 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
301 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
302
303 /* ST Microelectronics -- newer production may have feature updates */
304 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
305 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
306 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
307 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
308 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
309 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
310 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
311 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
312 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
313 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
314
315 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
316 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
317 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
318
319 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
320 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
321 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
322
323 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
324 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
325 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
326 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
327
328 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
329 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
330 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
331 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
332 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
333 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
334 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
335 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
336 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
337 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
338 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
339 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
340 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
341 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
342 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) },
343 };
344
345 typedef enum {
346 NOP = 0,
347 WRSR = 0x1,
348 WRDI = 0x4,
349 RDSR = 0x5,
350 WREN = 0x6,
351 BRRD = 0x16,
352 BRWR = 0x17,
353 JEDEC_READ = 0x9f,
354 BULK_ERASE_60 = 0x60,
355 BULK_ERASE = 0xc7,
356 READ_FSR = 0x70,
357 RDCR = 0x15,
358
359 READ = 0x03,
360 READ4 = 0x13,
361 FAST_READ = 0x0b,
362 FAST_READ4 = 0x0c,
363 DOR = 0x3b,
364 DOR4 = 0x3c,
365 QOR = 0x6b,
366 QOR4 = 0x6c,
367 DIOR = 0xbb,
368 DIOR4 = 0xbc,
369 QIOR = 0xeb,
370 QIOR4 = 0xec,
371
372 PP = 0x02,
373 PP4 = 0x12,
374 PP4_4 = 0x3e,
375 DPP = 0xa2,
376 QPP = 0x32,
377 QPP_4 = 0x34,
378 RDID_90 = 0x90,
379 RDID_AB = 0xab,
380 AAI_WP = 0xad,
381
382 ERASE_4K = 0x20,
383 ERASE4_4K = 0x21,
384 ERASE_32K = 0x52,
385 ERASE4_32K = 0x5c,
386 ERASE_SECTOR = 0xd8,
387 ERASE4_SECTOR = 0xdc,
388
389 EN_4BYTE_ADDR = 0xB7,
390 EX_4BYTE_ADDR = 0xE9,
391
392 EXTEND_ADDR_READ = 0xC8,
393 EXTEND_ADDR_WRITE = 0xC5,
394
395 RESET_ENABLE = 0x66,
396 RESET_MEMORY = 0x99,
397
398 /*
399 * Micron: 0x35 - enable QPI
400 * Spansion: 0x35 - read control register
401 */
402 RDCR_EQIO = 0x35,
403 RSTQIO = 0xf5,
404
405 RNVCR = 0xB5,
406 WNVCR = 0xB1,
407
408 RVCR = 0x85,
409 WVCR = 0x81,
410
411 REVCR = 0x65,
412 WEVCR = 0x61,
413
414 DIE_ERASE = 0xC4,
415 } FlashCMD;
416
417 typedef enum {
418 STATE_IDLE,
419 STATE_PAGE_PROGRAM,
420 STATE_READ,
421 STATE_COLLECTING_DATA,
422 STATE_COLLECTING_VAR_LEN_DATA,
423 STATE_READING_DATA,
424 } CMDState;
425
426 typedef enum {
427 MAN_SPANSION,
428 MAN_MACRONIX,
429 MAN_NUMONYX,
430 MAN_WINBOND,
431 MAN_SST,
432 MAN_ISSI,
433 MAN_GENERIC,
434 } Manufacturer;
435
436 typedef enum {
437 MODE_STD = 0,
438 MODE_DIO = 1,
439 MODE_QIO = 2
440 } SPIMode;
441
442 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
443
444 struct Flash {
445 SSIPeripheral parent_obj;
446
447 BlockBackend *blk;
448
449 uint8_t *storage;
450 uint32_t size;
451 int page_size;
452
453 uint8_t state;
454 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
455 uint32_t len;
456 uint32_t pos;
457 bool data_read_loop;
458 uint8_t needed_bytes;
459 uint8_t cmd_in_progress;
460 uint32_t cur_addr;
461 uint32_t nonvolatile_cfg;
462 /* Configuration register for Macronix */
463 uint32_t volatile_cfg;
464 uint32_t enh_volatile_cfg;
465 /* Spansion cfg registers. */
466 uint8_t spansion_cr1nv;
467 uint8_t spansion_cr2nv;
468 uint8_t spansion_cr3nv;
469 uint8_t spansion_cr4nv;
470 uint8_t spansion_cr1v;
471 uint8_t spansion_cr2v;
472 uint8_t spansion_cr3v;
473 uint8_t spansion_cr4v;
474 bool write_enable;
475 bool four_bytes_address_mode;
476 bool reset_enable;
477 bool quad_enable;
478 bool aai_enable;
479 uint8_t ear;
480
481 int64_t dirty_page;
482
483 const FlashPartInfo *pi;
484
485 };
486
487 struct M25P80Class {
488 SSIPeripheralClass parent_class;
489 FlashPartInfo *pi;
490 };
491
492 #define TYPE_M25P80 "m25p80-generic"
493 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80)
494
495 static inline Manufacturer get_man(Flash *s)
496 {
497 switch (s->pi->id[0]) {
498 case 0x20:
499 return MAN_NUMONYX;
500 case 0xEF:
501 return MAN_WINBOND;
502 case 0x01:
503 return MAN_SPANSION;
504 case 0xC2:
505 return MAN_MACRONIX;
506 case 0xBF:
507 return MAN_SST;
508 case 0x9D:
509 return MAN_ISSI;
510 default:
511 return MAN_GENERIC;
512 }
513 }
514
515 static void blk_sync_complete(void *opaque, int ret)
516 {
517 QEMUIOVector *iov = opaque;
518
519 qemu_iovec_destroy(iov);
520 g_free(iov);
521
522 /* do nothing. Masters do not directly interact with the backing store,
523 * only the working copy so no mutexing required.
524 */
525 }
526
527 static void flash_sync_page(Flash *s, int page)
528 {
529 QEMUIOVector *iov;
530
531 if (!s->blk || !blk_is_writable(s->blk)) {
532 return;
533 }
534
535 iov = g_new(QEMUIOVector, 1);
536 qemu_iovec_init(iov, 1);
537 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
538 s->pi->page_size);
539 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
540 blk_sync_complete, iov);
541 }
542
543 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
544 {
545 QEMUIOVector *iov;
546
547 if (!s->blk || !blk_is_writable(s->blk)) {
548 return;
549 }
550
551 assert(!(len % BDRV_SECTOR_SIZE));
552 iov = g_new(QEMUIOVector, 1);
553 qemu_iovec_init(iov, 1);
554 qemu_iovec_add(iov, s->storage + off, len);
555 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
556 }
557
558 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
559 {
560 uint32_t len;
561 uint8_t capa_to_assert = 0;
562
563 switch (cmd) {
564 case ERASE_4K:
565 case ERASE4_4K:
566 len = 4 * KiB;
567 capa_to_assert = ER_4K;
568 break;
569 case ERASE_32K:
570 case ERASE4_32K:
571 len = 32 * KiB;
572 capa_to_assert = ER_32K;
573 break;
574 case ERASE_SECTOR:
575 case ERASE4_SECTOR:
576 len = s->pi->sector_size;
577 break;
578 case BULK_ERASE:
579 len = s->size;
580 break;
581 case DIE_ERASE:
582 if (s->pi->die_cnt) {
583 len = s->size / s->pi->die_cnt;
584 offset = offset & (~(len - 1));
585 } else {
586 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
587 " by device\n");
588 return;
589 }
590 break;
591 default:
592 abort();
593 }
594
595 trace_m25p80_flash_erase(s, offset, len);
596
597 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
598 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
599 " device\n", len);
600 }
601
602 if (!s->write_enable) {
603 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
604 return;
605 }
606 memset(s->storage + offset, 0xff, len);
607 flash_sync_area(s, offset, len);
608 }
609
610 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
611 {
612 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
613 flash_sync_page(s, s->dirty_page);
614 s->dirty_page = newpage;
615 }
616 }
617
618 static inline
619 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
620 {
621 uint32_t page = addr / s->pi->page_size;
622 uint8_t prev = s->storage[s->cur_addr];
623
624 if (!s->write_enable) {
625 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
626 return;
627 }
628
629 if ((prev ^ data) & data) {
630 trace_m25p80_programming_zero_to_one(s, addr, prev, data);
631 }
632
633 if (s->pi->flags & EEPROM) {
634 s->storage[s->cur_addr] = data;
635 } else {
636 s->storage[s->cur_addr] &= data;
637 }
638
639 flash_sync_dirty(s, page);
640 s->dirty_page = page;
641 }
642
643 static inline int get_addr_length(Flash *s)
644 {
645 /* check if eeprom is in use */
646 if (s->pi->flags == EEPROM) {
647 return 2;
648 }
649
650 switch (s->cmd_in_progress) {
651 case PP4:
652 case PP4_4:
653 case QPP_4:
654 case READ4:
655 case QIOR4:
656 case ERASE4_4K:
657 case ERASE4_32K:
658 case ERASE4_SECTOR:
659 case FAST_READ4:
660 case DOR4:
661 case QOR4:
662 case DIOR4:
663 return 4;
664 default:
665 return s->four_bytes_address_mode ? 4 : 3;
666 }
667 }
668
669 static void complete_collecting_data(Flash *s)
670 {
671 int i, n;
672
673 n = get_addr_length(s);
674 s->cur_addr = (n == 3 ? s->ear : 0);
675 for (i = 0; i < n; ++i) {
676 s->cur_addr <<= 8;
677 s->cur_addr |= s->data[i];
678 }
679
680 s->cur_addr &= s->size - 1;
681
682 s->state = STATE_IDLE;
683
684 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
685 s->cur_addr);
686
687 switch (s->cmd_in_progress) {
688 case DPP:
689 case QPP:
690 case QPP_4:
691 case PP:
692 case PP4:
693 case PP4_4:
694 s->state = STATE_PAGE_PROGRAM;
695 break;
696 case AAI_WP:
697 /* AAI programming starts from the even address */
698 s->cur_addr &= ~BIT(0);
699 s->state = STATE_PAGE_PROGRAM;
700 break;
701 case READ:
702 case READ4:
703 case FAST_READ:
704 case FAST_READ4:
705 case DOR:
706 case DOR4:
707 case QOR:
708 case QOR4:
709 case DIOR:
710 case DIOR4:
711 case QIOR:
712 case QIOR4:
713 s->state = STATE_READ;
714 break;
715 case ERASE_4K:
716 case ERASE4_4K:
717 case ERASE_32K:
718 case ERASE4_32K:
719 case ERASE_SECTOR:
720 case ERASE4_SECTOR:
721 case DIE_ERASE:
722 flash_erase(s, s->cur_addr, s->cmd_in_progress);
723 break;
724 case WRSR:
725 switch (get_man(s)) {
726 case MAN_SPANSION:
727 s->quad_enable = !!(s->data[1] & 0x02);
728 break;
729 case MAN_ISSI:
730 s->quad_enable = extract32(s->data[0], 6, 1);
731 break;
732 case MAN_MACRONIX:
733 s->quad_enable = extract32(s->data[0], 6, 1);
734 if (s->len > 1) {
735 s->volatile_cfg = s->data[1];
736 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
737 }
738 break;
739 default:
740 break;
741 }
742 if (s->write_enable) {
743 s->write_enable = false;
744 }
745 break;
746 case BRWR:
747 case EXTEND_ADDR_WRITE:
748 s->ear = s->data[0];
749 break;
750 case WNVCR:
751 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
752 break;
753 case WVCR:
754 s->volatile_cfg = s->data[0];
755 break;
756 case WEVCR:
757 s->enh_volatile_cfg = s->data[0];
758 break;
759 case RDID_90:
760 case RDID_AB:
761 if (get_man(s) == MAN_SST) {
762 if (s->cur_addr <= 1) {
763 if (s->cur_addr) {
764 s->data[0] = s->pi->id[2];
765 s->data[1] = s->pi->id[0];
766 } else {
767 s->data[0] = s->pi->id[0];
768 s->data[1] = s->pi->id[2];
769 }
770 s->pos = 0;
771 s->len = 2;
772 s->data_read_loop = true;
773 s->state = STATE_READING_DATA;
774 } else {
775 qemu_log_mask(LOG_GUEST_ERROR,
776 "M25P80: Invalid read id address\n");
777 }
778 } else {
779 qemu_log_mask(LOG_GUEST_ERROR,
780 "M25P80: Read id (command 0x90/0xAB) is not supported"
781 " by device\n");
782 }
783 break;
784 default:
785 break;
786 }
787 }
788
789 static void reset_memory(Flash *s)
790 {
791 s->cmd_in_progress = NOP;
792 s->cur_addr = 0;
793 s->ear = 0;
794 s->four_bytes_address_mode = false;
795 s->len = 0;
796 s->needed_bytes = 0;
797 s->pos = 0;
798 s->state = STATE_IDLE;
799 s->write_enable = false;
800 s->reset_enable = false;
801 s->quad_enable = false;
802 s->aai_enable = false;
803
804 switch (get_man(s)) {
805 case MAN_NUMONYX:
806 s->volatile_cfg = 0;
807 s->volatile_cfg |= VCFG_DUMMY;
808 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
809 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
810 == NVCFG_XIP_MODE_DISABLED) {
811 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED;
812 }
813 s->volatile_cfg |= deposit32(s->volatile_cfg,
814 VCFG_DUMMY_CLK_POS,
815 CFG_DUMMY_CLK_LEN,
816 extract32(s->nonvolatile_cfg,
817 NVCFG_DUMMY_CLK_POS,
818 CFG_DUMMY_CLK_LEN)
819 );
820
821 s->enh_volatile_cfg = 0;
822 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
823 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
824 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
825 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
826 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED;
827 }
828 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
829 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED;
830 }
831 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
832 s->four_bytes_address_mode = true;
833 }
834 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
835 s->ear = s->size / MAX_3BYTES_SIZE - 1;
836 }
837 break;
838 case MAN_MACRONIX:
839 s->volatile_cfg = 0x7;
840 break;
841 case MAN_SPANSION:
842 s->spansion_cr1v = s->spansion_cr1nv;
843 s->spansion_cr2v = s->spansion_cr2nv;
844 s->spansion_cr3v = s->spansion_cr3nv;
845 s->spansion_cr4v = s->spansion_cr4nv;
846 s->quad_enable = extract32(s->spansion_cr1v,
847 SPANSION_QUAD_CFG_POS,
848 SPANSION_QUAD_CFG_LEN
849 );
850 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
851 SPANSION_ADDR_LEN_POS,
852 SPANSION_ADDR_LEN_LEN
853 );
854 break;
855 default:
856 break;
857 }
858
859 trace_m25p80_reset_done(s);
860 }
861
862 static uint8_t numonyx_mode(Flash *s)
863 {
864 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) {
865 return MODE_QIO;
866 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) {
867 return MODE_DIO;
868 } else {
869 return MODE_STD;
870 }
871 }
872
873 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s)
874 {
875 uint8_t num_dummies;
876 uint8_t mode;
877 assert(get_man(s) == MAN_NUMONYX);
878
879 mode = numonyx_mode(s);
880 num_dummies = extract32(s->volatile_cfg, 4, 4);
881
882 if (num_dummies == 0x0 || num_dummies == 0xf) {
883 switch (s->cmd_in_progress) {
884 case QIOR:
885 case QIOR4:
886 num_dummies = 10;
887 break;
888 default:
889 num_dummies = (mode == MODE_QIO) ? 10 : 8;
890 break;
891 }
892 }
893
894 return num_dummies;
895 }
896
897 static void decode_fast_read_cmd(Flash *s)
898 {
899 s->needed_bytes = get_addr_length(s);
900 switch (get_man(s)) {
901 /* Dummy cycles - modeled with bytes writes instead of bits */
902 case MAN_SST:
903 s->needed_bytes += 1;
904 break;
905 case MAN_WINBOND:
906 s->needed_bytes += 8;
907 break;
908 case MAN_NUMONYX:
909 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
910 break;
911 case MAN_MACRONIX:
912 if (extract32(s->volatile_cfg, 6, 2) == 1) {
913 s->needed_bytes += 6;
914 } else {
915 s->needed_bytes += 8;
916 }
917 break;
918 case MAN_SPANSION:
919 s->needed_bytes += extract32(s->spansion_cr2v,
920 SPANSION_DUMMY_CLK_POS,
921 SPANSION_DUMMY_CLK_LEN
922 );
923 break;
924 case MAN_ISSI:
925 /*
926 * The Fast Read instruction code is followed by address bytes and
927 * dummy cycles, transmitted via the SI line.
928 *
929 * The number of dummy cycles is configurable but this is currently
930 * unmodeled, hence the default value 8 is used.
931 *
932 * QPI (Quad Peripheral Interface) mode has different default value
933 * of dummy cycles, but this is unsupported at the time being.
934 */
935 s->needed_bytes += 1;
936 break;
937 default:
938 break;
939 }
940 s->pos = 0;
941 s->len = 0;
942 s->state = STATE_COLLECTING_DATA;
943 }
944
945 static void decode_dio_read_cmd(Flash *s)
946 {
947 s->needed_bytes = get_addr_length(s);
948 /* Dummy cycles modeled with bytes writes instead of bits */
949 switch (get_man(s)) {
950 case MAN_WINBOND:
951 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
952 break;
953 case MAN_SPANSION:
954 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
955 s->needed_bytes += extract32(s->spansion_cr2v,
956 SPANSION_DUMMY_CLK_POS,
957 SPANSION_DUMMY_CLK_LEN
958 );
959 break;
960 case MAN_NUMONYX:
961 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
962 break;
963 case MAN_MACRONIX:
964 switch (extract32(s->volatile_cfg, 6, 2)) {
965 case 1:
966 s->needed_bytes += 6;
967 break;
968 case 2:
969 s->needed_bytes += 8;
970 break;
971 default:
972 s->needed_bytes += 4;
973 break;
974 }
975 break;
976 case MAN_ISSI:
977 /*
978 * The Fast Read Dual I/O instruction code is followed by address bytes
979 * and dummy cycles, transmitted via the IO1 and IO0 line.
980 *
981 * The number of dummy cycles is configurable but this is currently
982 * unmodeled, hence the default value 4 is used.
983 */
984 s->needed_bytes += 1;
985 break;
986 default:
987 break;
988 }
989 s->pos = 0;
990 s->len = 0;
991 s->state = STATE_COLLECTING_DATA;
992 }
993
994 static void decode_qio_read_cmd(Flash *s)
995 {
996 s->needed_bytes = get_addr_length(s);
997 /* Dummy cycles modeled with bytes writes instead of bits */
998 switch (get_man(s)) {
999 case MAN_WINBOND:
1000 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
1001 s->needed_bytes += 4;
1002 break;
1003 case MAN_SPANSION:
1004 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
1005 s->needed_bytes += extract32(s->spansion_cr2v,
1006 SPANSION_DUMMY_CLK_POS,
1007 SPANSION_DUMMY_CLK_LEN
1008 );
1009 break;
1010 case MAN_NUMONYX:
1011 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
1012 break;
1013 case MAN_MACRONIX:
1014 switch (extract32(s->volatile_cfg, 6, 2)) {
1015 case 1:
1016 s->needed_bytes += 4;
1017 break;
1018 case 2:
1019 s->needed_bytes += 8;
1020 break;
1021 default:
1022 s->needed_bytes += 6;
1023 break;
1024 }
1025 break;
1026 case MAN_ISSI:
1027 /*
1028 * The Fast Read Quad I/O instruction code is followed by address bytes
1029 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line.
1030 *
1031 * The number of dummy cycles is configurable but this is currently
1032 * unmodeled, hence the default value 6 is used.
1033 *
1034 * QPI (Quad Peripheral Interface) mode has different default value
1035 * of dummy cycles, but this is unsupported at the time being.
1036 */
1037 s->needed_bytes += 3;
1038 break;
1039 default:
1040 break;
1041 }
1042 s->pos = 0;
1043 s->len = 0;
1044 s->state = STATE_COLLECTING_DATA;
1045 }
1046
1047 static bool is_valid_aai_cmd(uint32_t cmd)
1048 {
1049 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
1050 }
1051
1052 static void decode_new_cmd(Flash *s, uint32_t value)
1053 {
1054 int i;
1055
1056 s->cmd_in_progress = value;
1057 trace_m25p80_command_decoded(s, value);
1058
1059 if (value != RESET_MEMORY) {
1060 s->reset_enable = false;
1061 }
1062
1063 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
1064 qemu_log_mask(LOG_GUEST_ERROR,
1065 "M25P80: Invalid cmd within AAI programming sequence");
1066 }
1067
1068 switch (value) {
1069
1070 case ERASE_4K:
1071 case ERASE4_4K:
1072 case ERASE_32K:
1073 case ERASE4_32K:
1074 case ERASE_SECTOR:
1075 case ERASE4_SECTOR:
1076 case PP:
1077 case PP4:
1078 case DIE_ERASE:
1079 case RDID_90:
1080 case RDID_AB:
1081 s->needed_bytes = get_addr_length(s);
1082 s->pos = 0;
1083 s->len = 0;
1084 s->state = STATE_COLLECTING_DATA;
1085 break;
1086 case READ:
1087 case READ4:
1088 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1089 s->needed_bytes = get_addr_length(s);
1090 s->pos = 0;
1091 s->len = 0;
1092 s->state = STATE_COLLECTING_DATA;
1093 } else {
1094 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1095 "DIO or QIO mode\n", s->cmd_in_progress);
1096 }
1097 break;
1098 case DPP:
1099 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1100 s->needed_bytes = get_addr_length(s);
1101 s->pos = 0;
1102 s->len = 0;
1103 s->state = STATE_COLLECTING_DATA;
1104 } else {
1105 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1106 "QIO mode\n", s->cmd_in_progress);
1107 }
1108 break;
1109 case QPP:
1110 case QPP_4:
1111 case PP4_4:
1112 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1113 s->needed_bytes = get_addr_length(s);
1114 s->pos = 0;
1115 s->len = 0;
1116 s->state = STATE_COLLECTING_DATA;
1117 } else {
1118 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1119 "DIO mode\n", s->cmd_in_progress);
1120 }
1121 break;
1122
1123 case FAST_READ:
1124 case FAST_READ4:
1125 decode_fast_read_cmd(s);
1126 break;
1127 case DOR:
1128 case DOR4:
1129 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1130 decode_fast_read_cmd(s);
1131 } else {
1132 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1133 "QIO mode\n", s->cmd_in_progress);
1134 }
1135 break;
1136 case QOR:
1137 case QOR4:
1138 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1139 decode_fast_read_cmd(s);
1140 } else {
1141 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1142 "DIO mode\n", s->cmd_in_progress);
1143 }
1144 break;
1145
1146 case DIOR:
1147 case DIOR4:
1148 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1149 decode_dio_read_cmd(s);
1150 } else {
1151 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1152 "QIO mode\n", s->cmd_in_progress);
1153 }
1154 break;
1155
1156 case QIOR:
1157 case QIOR4:
1158 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1159 decode_qio_read_cmd(s);
1160 } else {
1161 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1162 "DIO mode\n", s->cmd_in_progress);
1163 }
1164 break;
1165
1166 case WRSR:
1167 if (s->write_enable) {
1168 switch (get_man(s)) {
1169 case MAN_SPANSION:
1170 s->needed_bytes = 2;
1171 s->state = STATE_COLLECTING_DATA;
1172 break;
1173 case MAN_MACRONIX:
1174 s->needed_bytes = 2;
1175 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1176 break;
1177 default:
1178 s->needed_bytes = 1;
1179 s->state = STATE_COLLECTING_DATA;
1180 }
1181 s->pos = 0;
1182 }
1183 break;
1184
1185 case WRDI:
1186 s->write_enable = false;
1187 if (get_man(s) == MAN_SST) {
1188 s->aai_enable = false;
1189 }
1190 break;
1191 case WREN:
1192 s->write_enable = true;
1193 break;
1194
1195 case RDSR:
1196 s->data[0] = (!!s->write_enable) << 1;
1197 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
1198 s->data[0] |= (!!s->quad_enable) << 6;
1199 }
1200 if (get_man(s) == MAN_SST) {
1201 s->data[0] |= (!!s->aai_enable) << 6;
1202 }
1203
1204 s->pos = 0;
1205 s->len = 1;
1206 s->data_read_loop = true;
1207 s->state = STATE_READING_DATA;
1208 break;
1209
1210 case READ_FSR:
1211 s->data[0] = FSR_FLASH_READY;
1212 if (s->four_bytes_address_mode) {
1213 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
1214 }
1215 s->pos = 0;
1216 s->len = 1;
1217 s->data_read_loop = true;
1218 s->state = STATE_READING_DATA;
1219 break;
1220
1221 case JEDEC_READ:
1222 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1223 trace_m25p80_populated_jedec(s);
1224 for (i = 0; i < s->pi->id_len; i++) {
1225 s->data[i] = s->pi->id[i];
1226 }
1227 for (; i < SPI_NOR_MAX_ID_LEN; i++) {
1228 s->data[i] = 0;
1229 }
1230
1231 s->len = SPI_NOR_MAX_ID_LEN;
1232 s->pos = 0;
1233 s->state = STATE_READING_DATA;
1234 } else {
1235 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read "
1236 "in DIO or QIO mode\n");
1237 }
1238 break;
1239
1240 case RDCR:
1241 s->data[0] = s->volatile_cfg & 0xFF;
1242 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1243 s->pos = 0;
1244 s->len = 1;
1245 s->state = STATE_READING_DATA;
1246 break;
1247
1248 case BULK_ERASE_60:
1249 case BULK_ERASE:
1250 if (s->write_enable) {
1251 trace_m25p80_chip_erase(s);
1252 flash_erase(s, 0, BULK_ERASE);
1253 } else {
1254 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1255 "protect!\n");
1256 }
1257 break;
1258 case NOP:
1259 break;
1260 case EN_4BYTE_ADDR:
1261 s->four_bytes_address_mode = true;
1262 break;
1263 case EX_4BYTE_ADDR:
1264 s->four_bytes_address_mode = false;
1265 break;
1266 case BRRD:
1267 case EXTEND_ADDR_READ:
1268 s->data[0] = s->ear;
1269 s->pos = 0;
1270 s->len = 1;
1271 s->state = STATE_READING_DATA;
1272 break;
1273 case BRWR:
1274 case EXTEND_ADDR_WRITE:
1275 if (s->write_enable) {
1276 s->needed_bytes = 1;
1277 s->pos = 0;
1278 s->len = 0;
1279 s->state = STATE_COLLECTING_DATA;
1280 }
1281 break;
1282 case RNVCR:
1283 s->data[0] = s->nonvolatile_cfg & 0xFF;
1284 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1285 s->pos = 0;
1286 s->len = 2;
1287 s->state = STATE_READING_DATA;
1288 break;
1289 case WNVCR:
1290 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1291 s->needed_bytes = 2;
1292 s->pos = 0;
1293 s->len = 0;
1294 s->state = STATE_COLLECTING_DATA;
1295 }
1296 break;
1297 case RVCR:
1298 s->data[0] = s->volatile_cfg & 0xFF;
1299 s->pos = 0;
1300 s->len = 1;
1301 s->state = STATE_READING_DATA;
1302 break;
1303 case WVCR:
1304 if (s->write_enable) {
1305 s->needed_bytes = 1;
1306 s->pos = 0;
1307 s->len = 0;
1308 s->state = STATE_COLLECTING_DATA;
1309 }
1310 break;
1311 case REVCR:
1312 s->data[0] = s->enh_volatile_cfg & 0xFF;
1313 s->pos = 0;
1314 s->len = 1;
1315 s->state = STATE_READING_DATA;
1316 break;
1317 case WEVCR:
1318 if (s->write_enable) {
1319 s->needed_bytes = 1;
1320 s->pos = 0;
1321 s->len = 0;
1322 s->state = STATE_COLLECTING_DATA;
1323 }
1324 break;
1325 case RESET_ENABLE:
1326 s->reset_enable = true;
1327 break;
1328 case RESET_MEMORY:
1329 if (s->reset_enable) {
1330 reset_memory(s);
1331 }
1332 break;
1333 case RDCR_EQIO:
1334 switch (get_man(s)) {
1335 case MAN_SPANSION:
1336 s->data[0] = (!!s->quad_enable) << 1;
1337 s->pos = 0;
1338 s->len = 1;
1339 s->state = STATE_READING_DATA;
1340 break;
1341 case MAN_MACRONIX:
1342 s->quad_enable = true;
1343 break;
1344 default:
1345 break;
1346 }
1347 break;
1348 case RSTQIO:
1349 s->quad_enable = false;
1350 break;
1351 case AAI_WP:
1352 if (get_man(s) == MAN_SST) {
1353 if (s->write_enable) {
1354 if (s->aai_enable) {
1355 s->state = STATE_PAGE_PROGRAM;
1356 } else {
1357 s->aai_enable = true;
1358 s->needed_bytes = get_addr_length(s);
1359 s->state = STATE_COLLECTING_DATA;
1360 }
1361 } else {
1362 qemu_log_mask(LOG_GUEST_ERROR,
1363 "M25P80: AAI_WP with write protect\n");
1364 }
1365 } else {
1366 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1367 }
1368 break;
1369 default:
1370 s->pos = 0;
1371 s->len = 1;
1372 s->state = STATE_READING_DATA;
1373 s->data_read_loop = true;
1374 s->data[0] = 0;
1375 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1376 break;
1377 }
1378 }
1379
1380 static int m25p80_cs(SSIPeripheral *ss, bool select)
1381 {
1382 Flash *s = M25P80(ss);
1383
1384 if (select) {
1385 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1386 complete_collecting_data(s);
1387 }
1388 s->len = 0;
1389 s->pos = 0;
1390 s->state = STATE_IDLE;
1391 flash_sync_dirty(s, -1);
1392 s->data_read_loop = false;
1393 }
1394
1395 trace_m25p80_select(s, select ? "de" : "");
1396
1397 return 0;
1398 }
1399
1400 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
1401 {
1402 Flash *s = M25P80(ss);
1403 uint32_t r = 0;
1404
1405 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
1406 s->cur_addr, (uint8_t)tx);
1407
1408 switch (s->state) {
1409
1410 case STATE_PAGE_PROGRAM:
1411 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
1412 flash_write8(s, s->cur_addr, (uint8_t)tx);
1413 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1414
1415 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
1416 /*
1417 * There is no wrap mode during AAI programming once the highest
1418 * unprotected memory address is reached. The Write-Enable-Latch
1419 * bit is automatically reset, and AAI programming mode aborts.
1420 */
1421 s->write_enable = false;
1422 s->aai_enable = false;
1423 }
1424
1425 break;
1426
1427 case STATE_READ:
1428 r = s->storage[s->cur_addr];
1429 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
1430 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1431 break;
1432
1433 case STATE_COLLECTING_DATA:
1434 case STATE_COLLECTING_VAR_LEN_DATA:
1435
1436 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1437 qemu_log_mask(LOG_GUEST_ERROR,
1438 "M25P80: Write overrun internal data buffer. "
1439 "SPI controller (QEMU emulator or guest driver) "
1440 "is misbehaving\n");
1441 s->len = s->pos = 0;
1442 s->state = STATE_IDLE;
1443 break;
1444 }
1445
1446 s->data[s->len] = (uint8_t)tx;
1447 s->len++;
1448
1449 if (s->len == s->needed_bytes) {
1450 complete_collecting_data(s);
1451 }
1452 break;
1453
1454 case STATE_READING_DATA:
1455
1456 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1457 qemu_log_mask(LOG_GUEST_ERROR,
1458 "M25P80: Read overrun internal data buffer. "
1459 "SPI controller (QEMU emulator or guest driver) "
1460 "is misbehaving\n");
1461 s->len = s->pos = 0;
1462 s->state = STATE_IDLE;
1463 break;
1464 }
1465
1466 r = s->data[s->pos];
1467 trace_m25p80_read_data(s, s->pos, (uint8_t)r);
1468 s->pos++;
1469 if (s->pos == s->len) {
1470 s->pos = 0;
1471 if (!s->data_read_loop) {
1472 s->state = STATE_IDLE;
1473 }
1474 }
1475 break;
1476
1477 default:
1478 case STATE_IDLE:
1479 decode_new_cmd(s, (uint8_t)tx);
1480 break;
1481 }
1482
1483 return r;
1484 }
1485
1486 static void m25p80_realize(SSIPeripheral *ss, Error **errp)
1487 {
1488 Flash *s = M25P80(ss);
1489 M25P80Class *mc = M25P80_GET_CLASS(s);
1490 int ret;
1491
1492 s->pi = mc->pi;
1493
1494 s->size = s->pi->sector_size * s->pi->n_sectors;
1495 s->dirty_page = -1;
1496
1497 if (s->blk) {
1498 uint64_t perm = BLK_PERM_CONSISTENT_READ |
1499 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
1500 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
1501 if (ret < 0) {
1502 return;
1503 }
1504
1505 trace_m25p80_binding(s);
1506 s->storage = blk_blockalign(s->blk, s->size);
1507
1508 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1509 error_setg(errp, "failed to read the initial flash content");
1510 return;
1511 }
1512 } else {
1513 trace_m25p80_binding_no_bdrv(s);
1514 s->storage = blk_blockalign(NULL, s->size);
1515 memset(s->storage, 0xFF, s->size);
1516 }
1517 }
1518
1519 static void m25p80_reset(DeviceState *d)
1520 {
1521 Flash *s = M25P80(d);
1522
1523 reset_memory(s);
1524 }
1525
1526 static int m25p80_pre_save(void *opaque)
1527 {
1528 flash_sync_dirty((Flash *)opaque, -1);
1529
1530 return 0;
1531 }
1532
1533 static Property m25p80_properties[] = {
1534 /* This is default value for Micron flash */
1535 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1536 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1537 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1538 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1539 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1540 DEFINE_PROP_DRIVE("drive", Flash, blk),
1541 DEFINE_PROP_END_OF_LIST(),
1542 };
1543
1544 static int m25p80_pre_load(void *opaque)
1545 {
1546 Flash *s = (Flash *)opaque;
1547
1548 s->data_read_loop = false;
1549 return 0;
1550 }
1551
1552 static bool m25p80_data_read_loop_needed(void *opaque)
1553 {
1554 Flash *s = (Flash *)opaque;
1555
1556 return s->data_read_loop;
1557 }
1558
1559 static const VMStateDescription vmstate_m25p80_data_read_loop = {
1560 .name = "m25p80/data_read_loop",
1561 .version_id = 1,
1562 .minimum_version_id = 1,
1563 .needed = m25p80_data_read_loop_needed,
1564 .fields = (VMStateField[]) {
1565 VMSTATE_BOOL(data_read_loop, Flash),
1566 VMSTATE_END_OF_LIST()
1567 }
1568 };
1569
1570 static bool m25p80_aai_enable_needed(void *opaque)
1571 {
1572 Flash *s = (Flash *)opaque;
1573
1574 return s->aai_enable;
1575 }
1576
1577 static const VMStateDescription vmstate_m25p80_aai_enable = {
1578 .name = "m25p80/aai_enable",
1579 .version_id = 1,
1580 .minimum_version_id = 1,
1581 .needed = m25p80_aai_enable_needed,
1582 .fields = (VMStateField[]) {
1583 VMSTATE_BOOL(aai_enable, Flash),
1584 VMSTATE_END_OF_LIST()
1585 }
1586 };
1587
1588 static const VMStateDescription vmstate_m25p80 = {
1589 .name = "m25p80",
1590 .version_id = 0,
1591 .minimum_version_id = 0,
1592 .pre_save = m25p80_pre_save,
1593 .pre_load = m25p80_pre_load,
1594 .fields = (VMStateField[]) {
1595 VMSTATE_UINT8(state, Flash),
1596 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1597 VMSTATE_UINT32(len, Flash),
1598 VMSTATE_UINT32(pos, Flash),
1599 VMSTATE_UINT8(needed_bytes, Flash),
1600 VMSTATE_UINT8(cmd_in_progress, Flash),
1601 VMSTATE_UINT32(cur_addr, Flash),
1602 VMSTATE_BOOL(write_enable, Flash),
1603 VMSTATE_BOOL(reset_enable, Flash),
1604 VMSTATE_UINT8(ear, Flash),
1605 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1606 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1607 VMSTATE_UINT32(volatile_cfg, Flash),
1608 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1609 VMSTATE_BOOL(quad_enable, Flash),
1610 VMSTATE_UINT8(spansion_cr1nv, Flash),
1611 VMSTATE_UINT8(spansion_cr2nv, Flash),
1612 VMSTATE_UINT8(spansion_cr3nv, Flash),
1613 VMSTATE_UINT8(spansion_cr4nv, Flash),
1614 VMSTATE_END_OF_LIST()
1615 },
1616 .subsections = (const VMStateDescription * []) {
1617 &vmstate_m25p80_data_read_loop,
1618 &vmstate_m25p80_aai_enable,
1619 NULL
1620 }
1621 };
1622
1623 static void m25p80_class_init(ObjectClass *klass, void *data)
1624 {
1625 DeviceClass *dc = DEVICE_CLASS(klass);
1626 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
1627 M25P80Class *mc = M25P80_CLASS(klass);
1628
1629 k->realize = m25p80_realize;
1630 k->transfer = m25p80_transfer8;
1631 k->set_cs = m25p80_cs;
1632 k->cs_polarity = SSI_CS_LOW;
1633 dc->vmsd = &vmstate_m25p80;
1634 device_class_set_props(dc, m25p80_properties);
1635 dc->reset = m25p80_reset;
1636 mc->pi = data;
1637 }
1638
1639 static const TypeInfo m25p80_info = {
1640 .name = TYPE_M25P80,
1641 .parent = TYPE_SSI_PERIPHERAL,
1642 .instance_size = sizeof(Flash),
1643 .class_size = sizeof(M25P80Class),
1644 .abstract = true,
1645 };
1646
1647 static void m25p80_register_types(void)
1648 {
1649 int i;
1650
1651 type_register_static(&m25p80_info);
1652 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1653 TypeInfo ti = {
1654 .name = known_devices[i].part_name,
1655 .parent = TYPE_M25P80,
1656 .class_init = m25p80_class_init,
1657 .class_data = (void *)&known_devices[i],
1658 };
1659 type_register(&ti);
1660 }
1661 }
1662
1663 type_init(m25p80_register_types)
QEmu