?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
vmware-vga: use vmsvga_verify_rect in vmsvga_fill_rect
[qemu.git] / target-i386 / translate.c
blob418173e0eab8a2b1176ead89d2331fc686feafe5
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "qemu/host-utils.h"
27 #include "cpu.h"
28 #include "disas/disas.h"
29 #include "tcg-op.h"
30 #include "exec/cpu_ldst.h"
31
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34
35 #include "trace-tcg.h"
36
37
38 #define PREFIX_REPZ 0x01
39 #define PREFIX_REPNZ 0x02
40 #define PREFIX_LOCK 0x04
41 #define PREFIX_DATA 0x08
42 #define PREFIX_ADR 0x10
43 #define PREFIX_VEX 0x20
44
45 #ifdef TARGET_X86_64
46 #define CODE64(s) ((s)->code64)
47 #define REX_X(s) ((s)->rex_x)
48 #define REX_B(s) ((s)->rex_b)
49 #else
50 #define CODE64(s) 0
51 #define REX_X(s) 0
52 #define REX_B(s) 0
53 #endif
54
55 #ifdef TARGET_X86_64
56 # define ctztl ctz64
57 # define clztl clz64
58 #else
59 # define ctztl ctz32
60 # define clztl clz32
61 #endif
62
63 //#define MACRO_TEST 1
64
65 /* global register indexes */
66 static TCGv_ptr cpu_env;
67 static TCGv cpu_A0;
68 static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT;
69 static TCGv_i32 cpu_cc_op;
70 static TCGv cpu_regs[CPU_NB_REGS];
71 /* local temps */
72 static TCGv cpu_T[2];
73 /* local register indexes (only used inside old micro ops) */
74 static TCGv cpu_tmp0, cpu_tmp4;
75 static TCGv_ptr cpu_ptr0, cpu_ptr1;
76 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
77 static TCGv_i64 cpu_tmp1_i64;
78
79 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
80
81 #include "exec/gen-icount.h"
82
83 #ifdef TARGET_X86_64
84 static int x86_64_hregs;
85 #endif
86
87 typedef struct DisasContext {
88 /* current insn context */
89 int override; /* -1 if no override */
90 int prefix;
91 TCGMemOp aflag;
92 TCGMemOp dflag;
93 target_ulong pc; /* pc = eip + cs_base */
94 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
95 static state change (stop translation) */
96 /* current block context */
97 target_ulong cs_base; /* base of CS segment */
98 int pe; /* protected mode */
99 int code32; /* 32 bit code segment */
100 #ifdef TARGET_X86_64
101 int lma; /* long mode active */
102 int code64; /* 64 bit code segment */
103 int rex_x, rex_b;
104 #endif
105 int vex_l; /* vex vector length */
106 int vex_v; /* vex vvvv register, without 1's compliment. */
107 int ss32; /* 32 bit stack segment */
108 CCOp cc_op; /* current CC operation */
109 bool cc_op_dirty;
110 int addseg; /* non zero if either DS/ES/SS have a non zero base */
111 int f_st; /* currently unused */
112 int vm86; /* vm86 mode */
113 int cpl;
114 int iopl;
115 int tf; /* TF cpu flag */
116 int singlestep_enabled; /* "hardware" single step enabled */
117 int jmp_opt; /* use direct block chaining for direct jumps */
118 int mem_index; /* select memory access functions */
119 uint64_t flags; /* all execution flags */
120 struct TranslationBlock *tb;
121 int popl_esp_hack; /* for correct popl with esp base handling */
122 int rip_offset; /* only used in x86_64, but left for simplicity */
123 int cpuid_features;
124 int cpuid_ext_features;
125 int cpuid_ext2_features;
126 int cpuid_ext3_features;
127 int cpuid_7_0_ebx_features;
128 } DisasContext;
129
130 static void gen_eob(DisasContext *s);
131 static void gen_jmp(DisasContext *s, target_ulong eip);
132 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
133 static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d);
134
135 /* i386 arith/logic operations */
136 enum {
137 OP_ADDL,
138 OP_ORL,
139 OP_ADCL,
140 OP_SBBL,
141 OP_ANDL,
142 OP_SUBL,
143 OP_XORL,
144 OP_CMPL,
145 };
146
147 /* i386 shift ops */
148 enum {
149 OP_ROL,
150 OP_ROR,
151 OP_RCL,
152 OP_RCR,
153 OP_SHL,
154 OP_SHR,
155 OP_SHL1, /* undocumented */
156 OP_SAR = 7,
157 };
158
159 enum {
160 JCC_O,
161 JCC_B,
162 JCC_Z,
163 JCC_BE,
164 JCC_S,
165 JCC_P,
166 JCC_L,
167 JCC_LE,
168 };
169
170 enum {
171 /* I386 int registers */
172 OR_EAX, /* MUST be even numbered */
173 OR_ECX,
174 OR_EDX,
175 OR_EBX,
176 OR_ESP,
177 OR_EBP,
178 OR_ESI,
179 OR_EDI,
180
181 OR_TMP0 = 16, /* temporary operand register */
182 OR_TMP1,
183 OR_A0, /* temporary register used when doing address evaluation */
184 };
185
186 enum {
187 USES_CC_DST = 1,
188 USES_CC_SRC = 2,
189 USES_CC_SRC2 = 4,
190 USES_CC_SRCT = 8,
191 };
192
193 /* Bit set if the global variable is live after setting CC_OP to X. */
194 static const uint8_t cc_op_live[CC_OP_NB] = {
195 [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2,
196 [CC_OP_EFLAGS] = USES_CC_SRC,
197 [CC_OP_MULB ... CC_OP_MULQ] = USES_CC_DST | USES_CC_SRC,
198 [CC_OP_ADDB ... CC_OP_ADDQ] = USES_CC_DST | USES_CC_SRC,
199 [CC_OP_ADCB ... CC_OP_ADCQ] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2,
200 [CC_OP_SUBB ... CC_OP_SUBQ] = USES_CC_DST | USES_CC_SRC | USES_CC_SRCT,
201 [CC_OP_SBBB ... CC_OP_SBBQ] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2,
202 [CC_OP_LOGICB ... CC_OP_LOGICQ] = USES_CC_DST,
203 [CC_OP_INCB ... CC_OP_INCQ] = USES_CC_DST | USES_CC_SRC,
204 [CC_OP_DECB ... CC_OP_DECQ] = USES_CC_DST | USES_CC_SRC,
205 [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC,
206 [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC,
207 [CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC,
208 [CC_OP_ADCX] = USES_CC_DST | USES_CC_SRC,
209 [CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2,
210 [CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2,
211 [CC_OP_CLR] = 0,
212 };
213
214 static void set_cc_op(DisasContext *s, CCOp op)
215 {
216 int dead;
217
218 if (s->cc_op == op) {
219 return;
220 }
221
222 /* Discard CC computation that will no longer be used. */
223 dead = cc_op_live[s->cc_op] & ~cc_op_live[op];
224 if (dead & USES_CC_DST) {
225 tcg_gen_discard_tl(cpu_cc_dst);
226 }
227 if (dead & USES_CC_SRC) {
228 tcg_gen_discard_tl(cpu_cc_src);
229 }
230 if (dead & USES_CC_SRC2) {
231 tcg_gen_discard_tl(cpu_cc_src2);
232 }
233 if (dead & USES_CC_SRCT) {
234 tcg_gen_discard_tl(cpu_cc_srcT);
235 }
236
237 if (op == CC_OP_DYNAMIC) {
238 /* The DYNAMIC setting is translator only, and should never be
239 stored. Thus we always consider it clean. */
240 s->cc_op_dirty = false;
241 } else {
242 /* Discard any computed CC_OP value (see shifts). */
243 if (s->cc_op == CC_OP_DYNAMIC) {
244 tcg_gen_discard_i32(cpu_cc_op);
245 }
246 s->cc_op_dirty = true;
247 }
248 s->cc_op = op;
249 }
250
251 static void gen_update_cc_op(DisasContext *s)
252 {
253 if (s->cc_op_dirty) {
254 tcg_gen_movi_i32(cpu_cc_op, s->cc_op);
255 s->cc_op_dirty = false;
256 }
257 }
258
259 #ifdef TARGET_X86_64
260
261 #define NB_OP_SIZES 4
262
263 #else /* !TARGET_X86_64 */
264
265 #define NB_OP_SIZES 3
266
267 #endif /* !TARGET_X86_64 */
268
269 #if defined(HOST_WORDS_BIGENDIAN)
270 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
271 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
272 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
273 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
274 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
275 #else
276 #define REG_B_OFFSET 0
277 #define REG_H_OFFSET 1
278 #define REG_W_OFFSET 0
279 #define REG_L_OFFSET 0
280 #define REG_LH_OFFSET 4
281 #endif
282
283 /* In instruction encodings for byte register accesses the
284 * register number usually indicates "low 8 bits of register N";
285 * however there are some special cases where N 4..7 indicates
286 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
287 * true for this special case, false otherwise.
288 */
289 static inline bool byte_reg_is_xH(int reg)
290 {
291 if (reg < 4) {
292 return false;
293 }
294 #ifdef TARGET_X86_64
295 if (reg >= 8 || x86_64_hregs) {
296 return false;
297 }
298 #endif
299 return true;
300 }
301
302 /* Select the size of a push/pop operation. */
303 static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)
304 {
305 if (CODE64(s)) {
306 return ot == MO_16 ? MO_16 : MO_64;
307 } else {
308 return ot;
309 }
310 }
311
312 /* Select only size 64 else 32. Used for SSE operand sizes. */
313 static inline TCGMemOp mo_64_32(TCGMemOp ot)
314 {
315 #ifdef TARGET_X86_64
316 return ot == MO_64 ? MO_64 : MO_32;
317 #else
318 return MO_32;
319 #endif
320 }
321
322 /* Select size 8 if lsb of B is clear, else OT. Used for decoding
323 byte vs word opcodes. */
324 static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)
325 {
326 return b & 1 ? ot : MO_8;
327 }
328
329 /* Select size 8 if lsb of B is clear, else OT capped at 32.
330 Used for decoding operand size of port opcodes. */
331 static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)
332 {
333 return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;
334 }
335
336 static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
337 {
338 switch(ot) {
339 case MO_8:
340 if (!byte_reg_is_xH(reg)) {
341 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
342 } else {
343 tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
344 }
345 break;
346 case MO_16:
347 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
348 break;
349 case MO_32:
350 /* For x86_64, this sets the higher half of register to zero.
351 For i386, this is equivalent to a mov. */
352 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
353 break;
354 #ifdef TARGET_X86_64
355 case MO_64:
356 tcg_gen_mov_tl(cpu_regs[reg], t0);
357 break;
358 #endif
359 default:
360 tcg_abort();
361 }
362 }
363
364 static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
365 {
366 if (ot == MO_8 && byte_reg_is_xH(reg)) {
367 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
368 tcg_gen_ext8u_tl(t0, t0);
369 } else {
370 tcg_gen_mov_tl(t0, cpu_regs[reg]);
371 }
372 }
373
374 static inline void gen_op_movl_A0_reg(int reg)
375 {
376 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
377 }
378
379 static inline void gen_op_addl_A0_im(int32_t val)
380 {
381 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
382 #ifdef TARGET_X86_64
383 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
384 #endif
385 }
386
387 #ifdef TARGET_X86_64
388 static inline void gen_op_addq_A0_im(int64_t val)
389 {
390 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
391 }
392 #endif
393
394 static void gen_add_A0_im(DisasContext *s, int val)
395 {
396 #ifdef TARGET_X86_64
397 if (CODE64(s))
398 gen_op_addq_A0_im(val);
399 else
400 #endif
401 gen_op_addl_A0_im(val);
402 }
403
404 static inline void gen_op_jmp_v(TCGv dest)
405 {
406 tcg_gen_st_tl(dest, cpu_env, offsetof(CPUX86State, eip));
407 }
408
409 static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val)
410 {
411 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
412 gen_op_mov_reg_v(size, reg, cpu_tmp0);
413 }
414
415 static inline void gen_op_add_reg_T0(TCGMemOp size, int reg)
416 {
417 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
418 gen_op_mov_reg_v(size, reg, cpu_tmp0);
419 }
420
421 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
422 {
423 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
424 if (shift != 0)
425 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
426 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
427 /* For x86_64, this sets the higher half of register to zero.
428 For i386, this is equivalent to a nop. */
429 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
430 }
431
432 static inline void gen_op_movl_A0_seg(int reg)
433 {
434 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET);
435 }
436
437 static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
438 {
439 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
440 #ifdef TARGET_X86_64
441 if (CODE64(s)) {
442 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
443 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
444 } else {
445 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
446 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
447 }
448 #else
449 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
450 #endif
451 }
452
453 #ifdef TARGET_X86_64
454 static inline void gen_op_movq_A0_seg(int reg)
455 {
456 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base));
457 }
458
459 static inline void gen_op_addq_A0_seg(int reg)
460 {
461 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
462 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
463 }
464
465 static inline void gen_op_movq_A0_reg(int reg)
466 {
467 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
468 }
469
470 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
471 {
472 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
473 if (shift != 0)
474 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
475 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
476 }
477 #endif
478
479 static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
480 {
481 tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
482 }
483
484 static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
485 {
486 tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE);
487 }
488
489 static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
490 {
491 if (d == OR_TMP0) {
492 gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
493 } else {
494 gen_op_mov_reg_v(idx, d, cpu_T[0]);
495 }
496 }
497
498 static inline void gen_jmp_im(target_ulong pc)
499 {
500 tcg_gen_movi_tl(cpu_tmp0, pc);
501 gen_op_jmp_v(cpu_tmp0);
502 }
503
504 static inline void gen_string_movl_A0_ESI(DisasContext *s)
505 {
506 int override;
507
508 override = s->override;
509 switch (s->aflag) {
510 #ifdef TARGET_X86_64
511 case MO_64:
512 if (override >= 0) {
513 gen_op_movq_A0_seg(override);
514 gen_op_addq_A0_reg_sN(0, R_ESI);
515 } else {
516 gen_op_movq_A0_reg(R_ESI);
517 }
518 break;
519 #endif
520 case MO_32:
521 /* 32 bit address */
522 if (s->addseg && override < 0)
523 override = R_DS;
524 if (override >= 0) {
525 gen_op_movl_A0_seg(override);
526 gen_op_addl_A0_reg_sN(0, R_ESI);
527 } else {
528 gen_op_movl_A0_reg(R_ESI);
529 }
530 break;
531 case MO_16:
532 /* 16 address, always override */
533 if (override < 0)
534 override = R_DS;
535 tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]);
536 gen_op_addl_A0_seg(s, override);
537 break;
538 default:
539 tcg_abort();
540 }
541 }
542
543 static inline void gen_string_movl_A0_EDI(DisasContext *s)
544 {
545 switch (s->aflag) {
546 #ifdef TARGET_X86_64
547 case MO_64:
548 gen_op_movq_A0_reg(R_EDI);
549 break;
550 #endif
551 case MO_32:
552 if (s->addseg) {
553 gen_op_movl_A0_seg(R_ES);
554 gen_op_addl_A0_reg_sN(0, R_EDI);
555 } else {
556 gen_op_movl_A0_reg(R_EDI);
557 }
558 break;
559 case MO_16:
560 tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_EDI]);
561 gen_op_addl_A0_seg(s, R_ES);
562 break;
563 default:
564 tcg_abort();
565 }
566 }
567
568 static inline void gen_op_movl_T0_Dshift(TCGMemOp ot)
569 {
570 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
571 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
572 };
573
574 static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)
575 {
576 switch (size) {
577 case MO_8:
578 if (sign) {
579 tcg_gen_ext8s_tl(dst, src);
580 } else {
581 tcg_gen_ext8u_tl(dst, src);
582 }
583 return dst;
584 case MO_16:
585 if (sign) {
586 tcg_gen_ext16s_tl(dst, src);
587 } else {
588 tcg_gen_ext16u_tl(dst, src);
589 }
590 return dst;
591 #ifdef TARGET_X86_64
592 case MO_32:
593 if (sign) {
594 tcg_gen_ext32s_tl(dst, src);
595 } else {
596 tcg_gen_ext32u_tl(dst, src);
597 }
598 return dst;
599 #endif
600 default:
601 return src;
602 }
603 }
604
605 static void gen_extu(TCGMemOp ot, TCGv reg)
606 {
607 gen_ext_tl(reg, reg, ot, false);
608 }
609
610 static void gen_exts(TCGMemOp ot, TCGv reg)
611 {
612 gen_ext_tl(reg, reg, ot, true);
613 }
614
615 static inline void gen_op_jnz_ecx(TCGMemOp size, int label1)
616 {
617 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
618 gen_extu(size, cpu_tmp0);
619 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
620 }
621
622 static inline void gen_op_jz_ecx(TCGMemOp size, int label1)
623 {
624 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
625 gen_extu(size, cpu_tmp0);
626 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
627 }
628
629 static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)
630 {
631 switch (ot) {
632 case MO_8:
633 gen_helper_inb(v, n);
634 break;
635 case MO_16:
636 gen_helper_inw(v, n);
637 break;
638 case MO_32:
639 gen_helper_inl(v, n);
640 break;
641 default:
642 tcg_abort();
643 }
644 }
645
646 static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)
647 {
648 switch (ot) {
649 case MO_8:
650 gen_helper_outb(v, n);
651 break;
652 case MO_16:
653 gen_helper_outw(v, n);
654 break;
655 case MO_32:
656 gen_helper_outl(v, n);
657 break;
658 default:
659 tcg_abort();
660 }
661 }
662
663 static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
664 uint32_t svm_flags)
665 {
666 int state_saved;
667 target_ulong next_eip;
668
669 state_saved = 0;
670 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
671 gen_update_cc_op(s);
672 gen_jmp_im(cur_eip);
673 state_saved = 1;
674 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
675 switch (ot) {
676 case MO_8:
677 gen_helper_check_iob(cpu_env, cpu_tmp2_i32);
678 break;
679 case MO_16:
680 gen_helper_check_iow(cpu_env, cpu_tmp2_i32);
681 break;
682 case MO_32:
683 gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
684 break;
685 default:
686 tcg_abort();
687 }
688 }
689 if(s->flags & HF_SVMI_MASK) {
690 if (!state_saved) {
691 gen_update_cc_op(s);
692 gen_jmp_im(cur_eip);
693 }
694 svm_flags |= (1 << (4 + ot));
695 next_eip = s->pc - s->cs_base;
696 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
697 gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32,
698 tcg_const_i32(svm_flags),
699 tcg_const_i32(next_eip - cur_eip));
700 }
701 }
702
703 static inline void gen_movs(DisasContext *s, TCGMemOp ot)
704 {
705 gen_string_movl_A0_ESI(s);
706 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
707 gen_string_movl_A0_EDI(s);
708 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
709 gen_op_movl_T0_Dshift(ot);
710 gen_op_add_reg_T0(s->aflag, R_ESI);
711 gen_op_add_reg_T0(s->aflag, R_EDI);
712 }
713
714 static void gen_op_update1_cc(void)
715 {
716 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
717 }
718
719 static void gen_op_update2_cc(void)
720 {
721 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
722 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
723 }
724
725 static void gen_op_update3_cc(TCGv reg)
726 {
727 tcg_gen_mov_tl(cpu_cc_src2, reg);
728 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
729 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
730 }
731
732 static inline void gen_op_testl_T0_T1_cc(void)
733 {
734 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
735 }
736
737 static void gen_op_update_neg_cc(void)
738 {
739 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
740 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
741 tcg_gen_movi_tl(cpu_cc_srcT, 0);
742 }
743
744 /* compute all eflags to cc_src */
745 static void gen_compute_eflags(DisasContext *s)
746 {
747 TCGv zero, dst, src1, src2;
748 int live, dead;
749
750 if (s->cc_op == CC_OP_EFLAGS) {
751 return;
752 }
753 if (s->cc_op == CC_OP_CLR) {
754 tcg_gen_movi_tl(cpu_cc_src, CC_Z | CC_P);
755 set_cc_op(s, CC_OP_EFLAGS);
756 return;
757 }
758
759 TCGV_UNUSED(zero);
760 dst = cpu_cc_dst;
761 src1 = cpu_cc_src;
762 src2 = cpu_cc_src2;
763
764 /* Take care to not read values that are not live. */
765 live = cc_op_live[s->cc_op] & ~USES_CC_SRCT;
766 dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2);
767 if (dead) {
768 zero = tcg_const_tl(0);
769 if (dead & USES_CC_DST) {
770 dst = zero;
771 }
772 if (dead & USES_CC_SRC) {
773 src1 = zero;
774 }
775 if (dead & USES_CC_SRC2) {
776 src2 = zero;
777 }
778 }
779
780 gen_update_cc_op(s);
781 gen_helper_cc_compute_all(cpu_cc_src, dst, src1, src2, cpu_cc_op);
782 set_cc_op(s, CC_OP_EFLAGS);
783
784 if (dead) {
785 tcg_temp_free(zero);
786 }
787 }
788
789 typedef struct CCPrepare {
790 TCGCond cond;
791 TCGv reg;
792 TCGv reg2;
793 target_ulong imm;
794 target_ulong mask;
795 bool use_reg2;
796 bool no_setcond;
797 } CCPrepare;
798
799 /* compute eflags.C to reg */
800 static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
801 {
802 TCGv t0, t1;
803 int size, shift;
804
805 switch (s->cc_op) {
806 case CC_OP_SUBB ... CC_OP_SUBQ:
807 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
808 size = s->cc_op - CC_OP_SUBB;
809 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
810 /* If no temporary was used, be careful not to alias t1 and t0. */
811 t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg;
812 tcg_gen_mov_tl(t0, cpu_cc_srcT);
813 gen_extu(size, t0);
814 goto add_sub;
815
816 case CC_OP_ADDB ... CC_OP_ADDQ:
817 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
818 size = s->cc_op - CC_OP_ADDB;
819 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
820 t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
821 add_sub:
822 return (CCPrepare) { .cond = TCG_COND_LTU, .reg = t0,
823 .reg2 = t1, .mask = -1, .use_reg2 = true };
824
825 case CC_OP_LOGICB ... CC_OP_LOGICQ:
826 case CC_OP_CLR:
827 return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
828
829 case CC_OP_INCB ... CC_OP_INCQ:
830 case CC_OP_DECB ... CC_OP_DECQ:
831 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
832 .mask = -1, .no_setcond = true };
833
834 case CC_OP_SHLB ... CC_OP_SHLQ:
835 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
836 size = s->cc_op - CC_OP_SHLB;
837 shift = (8 << size) - 1;
838 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
839 .mask = (target_ulong)1 << shift };
840
841 case CC_OP_MULB ... CC_OP_MULQ:
842 return (CCPrepare) { .cond = TCG_COND_NE,
843 .reg = cpu_cc_src, .mask = -1 };
844
845 case CC_OP_BMILGB ... CC_OP_BMILGQ:
846 size = s->cc_op - CC_OP_BMILGB;
847 t0 = gen_ext_tl(reg, cpu_cc_src, size, false);
848 return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };
849
850 case CC_OP_ADCX:
851 case CC_OP_ADCOX:
852 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_dst,
853 .mask = -1, .no_setcond = true };
854
855 case CC_OP_EFLAGS:
856 case CC_OP_SARB ... CC_OP_SARQ:
857 /* CC_SRC & 1 */
858 return (CCPrepare) { .cond = TCG_COND_NE,
859 .reg = cpu_cc_src, .mask = CC_C };
860
861 default:
862 /* The need to compute only C from CC_OP_DYNAMIC is important
863 in efficiently implementing e.g. INC at the start of a TB. */
864 gen_update_cc_op(s);
865 gen_helper_cc_compute_c(reg, cpu_cc_dst, cpu_cc_src,
866 cpu_cc_src2, cpu_cc_op);
867 return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
868 .mask = -1, .no_setcond = true };
869 }
870 }
871
872 /* compute eflags.P to reg */
873 static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg)
874 {
875 gen_compute_eflags(s);
876 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
877 .mask = CC_P };
878 }
879
880 /* compute eflags.S to reg */
881 static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
882 {
883 switch (s->cc_op) {
884 case CC_OP_DYNAMIC:
885 gen_compute_eflags(s);
886 /* FALLTHRU */
887 case CC_OP_EFLAGS:
888 case CC_OP_ADCX:
889 case CC_OP_ADOX:
890 case CC_OP_ADCOX:
891 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
892 .mask = CC_S };
893 case CC_OP_CLR:
894 return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
895 default:
896 {
897 TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
898 TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);
899 return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 };
900 }
901 }
902 }
903
904 /* compute eflags.O to reg */
905 static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
906 {
907 switch (s->cc_op) {
908 case CC_OP_ADOX:
909 case CC_OP_ADCOX:
910 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src2,
911 .mask = -1, .no_setcond = true };
912 case CC_OP_CLR:
913 return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
914 default:
915 gen_compute_eflags(s);
916 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
917 .mask = CC_O };
918 }
919 }
920
921 /* compute eflags.Z to reg */
922 static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
923 {
924 switch (s->cc_op) {
925 case CC_OP_DYNAMIC:
926 gen_compute_eflags(s);
927 /* FALLTHRU */
928 case CC_OP_EFLAGS:
929 case CC_OP_ADCX:
930 case CC_OP_ADOX:
931 case CC_OP_ADCOX:
932 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
933 .mask = CC_Z };
934 case CC_OP_CLR:
935 return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 };
936 default:
937 {
938 TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
939 TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
940 return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };
941 }
942 }
943 }
944
945 /* perform a conditional store into register 'reg' according to jump opcode
946 value 'b'. In the fast case, T0 is guaranted not to be used. */
947 static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
948 {
949 int inv, jcc_op, cond;
950 TCGMemOp size;
951 CCPrepare cc;
952 TCGv t0;
953
954 inv = b & 1;
955 jcc_op = (b >> 1) & 7;
956
957 switch (s->cc_op) {
958 case CC_OP_SUBB ... CC_OP_SUBQ:
959 /* We optimize relational operators for the cmp/jcc case. */
960 size = s->cc_op - CC_OP_SUBB;
961 switch (jcc_op) {
962 case JCC_BE:
963 tcg_gen_mov_tl(cpu_tmp4, cpu_cc_srcT);
964 gen_extu(size, cpu_tmp4);
965 t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
966 cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4,
967 .reg2 = t0, .mask = -1, .use_reg2 = true };
968 break;
969
970 case JCC_L:
971 cond = TCG_COND_LT;
972 goto fast_jcc_l;
973 case JCC_LE:
974 cond = TCG_COND_LE;
975 fast_jcc_l:
976 tcg_gen_mov_tl(cpu_tmp4, cpu_cc_srcT);
977 gen_exts(size, cpu_tmp4);
978 t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true);
979 cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4,
980 .reg2 = t0, .mask = -1, .use_reg2 = true };
981 break;
982
983 default:
984 goto slow_jcc;
985 }
986 break;
987
988 default:
989 slow_jcc:
990 /* This actually generates good code for JC, JZ and JS. */
991 switch (jcc_op) {
992 case JCC_O:
993 cc = gen_prepare_eflags_o(s, reg);
994 break;
995 case JCC_B:
996 cc = gen_prepare_eflags_c(s, reg);
997 break;
998 case JCC_Z:
999 cc = gen_prepare_eflags_z(s, reg);
1000 break;
1001 case JCC_BE:
1002 gen_compute_eflags(s);
1003 cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
1004 .mask = CC_Z | CC_C };
1005 break;
1006 case JCC_S:
1007 cc = gen_prepare_eflags_s(s, reg);
1008 break;
1009 case JCC_P:
1010 cc = gen_prepare_eflags_p(s, reg);
1011 break;
1012 case JCC_L:
1013 gen_compute_eflags(s);
1014 if (TCGV_EQUAL(reg, cpu_cc_src)) {
1015 reg = cpu_tmp0;
1016 }
1017 tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
1018 tcg_gen_xor_tl(reg, reg, cpu_cc_src);
1019 cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
1020 .mask = CC_S };
1021 break;
1022 default:
1023 case JCC_LE:
1024 gen_compute_eflags(s);
1025 if (TCGV_EQUAL(reg, cpu_cc_src)) {
1026 reg = cpu_tmp0;
1027 }
1028 tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
1029 tcg_gen_xor_tl(reg, reg, cpu_cc_src);
1030 cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
1031 .mask = CC_S | CC_Z };
1032 break;
1033 }
1034 break;
1035 }
1036
1037 if (inv) {
1038 cc.cond = tcg_invert_cond(cc.cond);
1039 }
1040 return cc;
1041 }
1042
1043 static void gen_setcc1(DisasContext *s, int b, TCGv reg)
1044 {
1045 CCPrepare cc = gen_prepare_cc(s, b, reg);
1046
1047 if (cc.no_setcond) {
1048 if (cc.cond == TCG_COND_EQ) {
1049 tcg_gen_xori_tl(reg, cc.reg, 1);
1050 } else {
1051 tcg_gen_mov_tl(reg, cc.reg);
1052 }
1053 return;
1054 }
1055
1056 if (cc.cond == TCG_COND_NE && !cc.use_reg2 && cc.imm == 0 &&
1057 cc.mask != 0 && (cc.mask & (cc.mask - 1)) == 0) {
1058 tcg_gen_shri_tl(reg, cc.reg, ctztl(cc.mask));
1059 tcg_gen_andi_tl(reg, reg, 1);
1060 return;
1061 }
1062 if (cc.mask != -1) {
1063 tcg_gen_andi_tl(reg, cc.reg, cc.mask);
1064 cc.reg = reg;
1065 }
1066 if (cc.use_reg2) {
1067 tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2);
1068 } else {
1069 tcg_gen_setcondi_tl(cc.cond, reg, cc.reg, cc.imm);
1070 }
1071 }
1072
1073 static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg)
1074 {
1075 gen_setcc1(s, JCC_B << 1, reg);
1076 }
1077
1078 /* generate a conditional jump to label 'l1' according to jump opcode
1079 value 'b'. In the fast case, T0 is guaranted not to be used. */
1080 static inline void gen_jcc1_noeob(DisasContext *s, int b, int l1)
1081 {
1082 CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]);
1083
1084 if (cc.mask != -1) {
1085 tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask);
1086 cc.reg = cpu_T[0];
1087 }
1088 if (cc.use_reg2) {
1089 tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1);
1090 } else {
1091 tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1);
1092 }
1093 }
1094
1095 /* Generate a conditional jump to label 'l1' according to jump opcode
1096 value 'b'. In the fast case, T0 is guaranted not to be used.
1097 A translation block must end soon. */
1098 static inline void gen_jcc1(DisasContext *s, int b, int l1)
1099 {
1100 CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]);
1101
1102 gen_update_cc_op(s);
1103 if (cc.mask != -1) {
1104 tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask);
1105 cc.reg = cpu_T[0];
1106 }
1107 set_cc_op(s, CC_OP_DYNAMIC);
1108 if (cc.use_reg2) {
1109 tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1);
1110 } else {
1111 tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1);
1112 }
1113 }
1114
1115 /* XXX: does not work with gdbstub "ice" single step - not a
1116 serious problem */
1117 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1118 {
1119 int l1, l2;
1120
1121 l1 = gen_new_label();
1122 l2 = gen_new_label();
1123 gen_op_jnz_ecx(s->aflag, l1);
1124 gen_set_label(l2);
1125 gen_jmp_tb(s, next_eip, 1);
1126 gen_set_label(l1);
1127 return l2;
1128 }
1129
1130 static inline void gen_stos(DisasContext *s, TCGMemOp ot)
1131 {
1132 gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
1133 gen_string_movl_A0_EDI(s);
1134 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
1135 gen_op_movl_T0_Dshift(ot);
1136 gen_op_add_reg_T0(s->aflag, R_EDI);
1137 }
1138
1139 static inline void gen_lods(DisasContext *s, TCGMemOp ot)
1140 {
1141 gen_string_movl_A0_ESI(s);
1142 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
1143 gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
1144 gen_op_movl_T0_Dshift(ot);
1145 gen_op_add_reg_T0(s->aflag, R_ESI);
1146 }
1147
1148 static inline void gen_scas(DisasContext *s, TCGMemOp ot)
1149 {
1150 gen_string_movl_A0_EDI(s);
1151 gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
1152 gen_op(s, OP_CMPL, ot, R_EAX);
1153 gen_op_movl_T0_Dshift(ot);
1154 gen_op_add_reg_T0(s->aflag, R_EDI);
1155 }
1156
1157 static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
1158 {
1159 gen_string_movl_A0_EDI(s);
1160 gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
1161 gen_string_movl_A0_ESI(s);
1162 gen_op(s, OP_CMPL, ot, OR_TMP0);
1163 gen_op_movl_T0_Dshift(ot);
1164 gen_op_add_reg_T0(s->aflag, R_ESI);
1165 gen_op_add_reg_T0(s->aflag, R_EDI);
1166 }
1167
1168 static inline void gen_ins(DisasContext *s, TCGMemOp ot)
1169 {
1170 if (use_icount)
1171 gen_io_start();
1172 gen_string_movl_A0_EDI(s);
1173 /* Note: we must do this dummy write first to be restartable in
1174 case of page fault. */
1175 tcg_gen_movi_tl(cpu_T[0], 0);
1176 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
1177 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
1178 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1179 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1180 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
1181 gen_op_movl_T0_Dshift(ot);
1182 gen_op_add_reg_T0(s->aflag, R_EDI);
1183 if (use_icount)
1184 gen_io_end();
1185 }
1186
1187 static inline void gen_outs(DisasContext *s, TCGMemOp ot)
1188 {
1189 if (use_icount)
1190 gen_io_start();
1191 gen_string_movl_A0_ESI(s);
1192 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
1193
1194 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
1195 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1196 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1197 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1198
1199 gen_op_movl_T0_Dshift(ot);
1200 gen_op_add_reg_T0(s->aflag, R_ESI);
1201 if (use_icount)
1202 gen_io_end();
1203 }
1204
1205 /* same method as Valgrind : we generate jumps to current or next
1206 instruction */
1207 #define GEN_REPZ(op) \
1208 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1209 target_ulong cur_eip, target_ulong next_eip) \
1210 { \
1211 int l2;\
1212 gen_update_cc_op(s); \
1213 l2 = gen_jz_ecx_string(s, next_eip); \
1214 gen_ ## op(s, ot); \
1215 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1216 /* a loop would cause two single step exceptions if ECX = 1 \
1217 before rep string_insn */ \
1218 if (!s->jmp_opt) \
1219 gen_op_jz_ecx(s->aflag, l2); \
1220 gen_jmp(s, cur_eip); \
1221 }
1222
1223 #define GEN_REPZ2(op) \
1224 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1225 target_ulong cur_eip, \
1226 target_ulong next_eip, \
1227 int nz) \
1228 { \
1229 int l2;\
1230 gen_update_cc_op(s); \
1231 l2 = gen_jz_ecx_string(s, next_eip); \
1232 gen_ ## op(s, ot); \
1233 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1234 gen_update_cc_op(s); \
1235 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1236 if (!s->jmp_opt) \
1237 gen_op_jz_ecx(s->aflag, l2); \
1238 gen_jmp(s, cur_eip); \
1239 }
1240
1241 GEN_REPZ(movs)
1242 GEN_REPZ(stos)
1243 GEN_REPZ(lods)
1244 GEN_REPZ(ins)
1245 GEN_REPZ(outs)
1246 GEN_REPZ2(scas)
1247 GEN_REPZ2(cmps)
1248
1249 static void gen_helper_fp_arith_ST0_FT0(int op)
1250 {
1251 switch (op) {
1252 case 0:
1253 gen_helper_fadd_ST0_FT0(cpu_env);
1254 break;
1255 case 1:
1256 gen_helper_fmul_ST0_FT0(cpu_env);
1257 break;
1258 case 2:
1259 gen_helper_fcom_ST0_FT0(cpu_env);
1260 break;
1261 case 3:
1262 gen_helper_fcom_ST0_FT0(cpu_env);
1263 break;
1264 case 4:
1265 gen_helper_fsub_ST0_FT0(cpu_env);
1266 break;
1267 case 5:
1268 gen_helper_fsubr_ST0_FT0(cpu_env);
1269 break;
1270 case 6:
1271 gen_helper_fdiv_ST0_FT0(cpu_env);
1272 break;
1273 case 7:
1274 gen_helper_fdivr_ST0_FT0(cpu_env);
1275 break;
1276 }
1277 }
1278
1279 /* NOTE the exception in "r" op ordering */
1280 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1281 {
1282 TCGv_i32 tmp = tcg_const_i32(opreg);
1283 switch (op) {
1284 case 0:
1285 gen_helper_fadd_STN_ST0(cpu_env, tmp);
1286 break;
1287 case 1:
1288 gen_helper_fmul_STN_ST0(cpu_env, tmp);
1289 break;
1290 case 4:
1291 gen_helper_fsubr_STN_ST0(cpu_env, tmp);
1292 break;
1293 case 5:
1294 gen_helper_fsub_STN_ST0(cpu_env, tmp);
1295 break;
1296 case 6:
1297 gen_helper_fdivr_STN_ST0(cpu_env, tmp);
1298 break;
1299 case 7:
1300 gen_helper_fdiv_STN_ST0(cpu_env, tmp);
1301 break;
1302 }
1303 }
1304
1305 /* if d == OR_TMP0, it means memory operand (address in A0) */
1306 static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
1307 {
1308 if (d != OR_TMP0) {
1309 gen_op_mov_v_reg(ot, cpu_T[0], d);
1310 } else {
1311 gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
1312 }
1313 switch(op) {
1314 case OP_ADCL:
1315 gen_compute_eflags_c(s1, cpu_tmp4);
1316 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1317 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1318 gen_op_st_rm_T0_A0(s1, ot, d);
1319 gen_op_update3_cc(cpu_tmp4);
1320 set_cc_op(s1, CC_OP_ADCB + ot);
1321 break;
1322 case OP_SBBL:
1323 gen_compute_eflags_c(s1, cpu_tmp4);
1324 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1325 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1326 gen_op_st_rm_T0_A0(s1, ot, d);
1327 gen_op_update3_cc(cpu_tmp4);
1328 set_cc_op(s1, CC_OP_SBBB + ot);
1329 break;
1330 case OP_ADDL:
1331 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1332 gen_op_st_rm_T0_A0(s1, ot, d);
1333 gen_op_update2_cc();
1334 set_cc_op(s1, CC_OP_ADDB + ot);
1335 break;
1336 case OP_SUBL:
1337 tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]);
1338 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1339 gen_op_st_rm_T0_A0(s1, ot, d);
1340 gen_op_update2_cc();
1341 set_cc_op(s1, CC_OP_SUBB + ot);
1342 break;
1343 default:
1344 case OP_ANDL:
1345 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1346 gen_op_st_rm_T0_A0(s1, ot, d);
1347 gen_op_update1_cc();
1348 set_cc_op(s1, CC_OP_LOGICB + ot);
1349 break;
1350 case OP_ORL:
1351 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1352 gen_op_st_rm_T0_A0(s1, ot, d);
1353 gen_op_update1_cc();
1354 set_cc_op(s1, CC_OP_LOGICB + ot);
1355 break;
1356 case OP_XORL:
1357 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1358 gen_op_st_rm_T0_A0(s1, ot, d);
1359 gen_op_update1_cc();
1360 set_cc_op(s1, CC_OP_LOGICB + ot);
1361 break;
1362 case OP_CMPL:
1363 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1364 tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]);
1365 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
1366 set_cc_op(s1, CC_OP_SUBB + ot);
1367 break;
1368 }
1369 }
1370
1371 /* if d == OR_TMP0, it means memory operand (address in A0) */
1372 static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
1373 {
1374 if (d != OR_TMP0) {
1375 gen_op_mov_v_reg(ot, cpu_T[0], d);
1376 } else {
1377 gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
1378 }
1379 gen_compute_eflags_c(s1, cpu_cc_src);
1380 if (c > 0) {
1381 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1382 set_cc_op(s1, CC_OP_INCB + ot);
1383 } else {
1384 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1385 set_cc_op(s1, CC_OP_DECB + ot);
1386 }
1387 gen_op_st_rm_T0_A0(s1, ot, d);
1388 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1389 }
1390
1391 static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,
1392 TCGv shm1, TCGv count, bool is_right)
1393 {
1394 TCGv_i32 z32, s32, oldop;
1395 TCGv z_tl;
1396
1397 /* Store the results into the CC variables. If we know that the
1398 variable must be dead, store unconditionally. Otherwise we'll
1399 need to not disrupt the current contents. */
1400 z_tl = tcg_const_tl(0);
1401 if (cc_op_live[s->cc_op] & USES_CC_DST) {
1402 tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl,
1403 result, cpu_cc_dst);
1404 } else {
1405 tcg_gen_mov_tl(cpu_cc_dst, result);
1406 }
1407 if (cc_op_live[s->cc_op] & USES_CC_SRC) {
1408 tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_src, count, z_tl,
1409 shm1, cpu_cc_src);
1410 } else {
1411 tcg_gen_mov_tl(cpu_cc_src, shm1);
1412 }
1413 tcg_temp_free(z_tl);
1414
1415 /* Get the two potential CC_OP values into temporaries. */
1416 tcg_gen_movi_i32(cpu_tmp2_i32, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot);
1417 if (s->cc_op == CC_OP_DYNAMIC) {
1418 oldop = cpu_cc_op;
1419 } else {
1420 tcg_gen_movi_i32(cpu_tmp3_i32, s->cc_op);
1421 oldop = cpu_tmp3_i32;
1422 }
1423
1424 /* Conditionally store the CC_OP value. */
1425 z32 = tcg_const_i32(0);
1426 s32 = tcg_temp_new_i32();
1427 tcg_gen_trunc_tl_i32(s32, count);
1428 tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, cpu_tmp2_i32, oldop);
1429 tcg_temp_free_i32(z32);
1430 tcg_temp_free_i32(s32);
1431
1432 /* The CC_OP value is no longer predictable. */
1433 set_cc_op(s, CC_OP_DYNAMIC);
1434 }
1435
1436 static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
1437 int is_right, int is_arith)
1438 {
1439 target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
1440
1441 /* load */
1442 if (op1 == OR_TMP0) {
1443 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
1444 } else {
1445 gen_op_mov_v_reg(ot, cpu_T[0], op1);
1446 }
1447
1448 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1449 tcg_gen_subi_tl(cpu_tmp0, cpu_T[1], 1);
1450
1451 if (is_right) {
1452 if (is_arith) {
1453 gen_exts(ot, cpu_T[0]);
1454 tcg_gen_sar_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
1455 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1456 } else {
1457 gen_extu(ot, cpu_T[0]);
1458 tcg_gen_shr_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
1459 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1460 }
1461 } else {
1462 tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
1463 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1464 }
1465
1466 /* store */
1467 gen_op_st_rm_T0_A0(s, ot, op1);
1468
1469 gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, cpu_T[1], is_right);
1470 }
1471
1472 static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
1473 int is_right, int is_arith)
1474 {
1475 int mask = (ot == MO_64 ? 0x3f : 0x1f);
1476
1477 /* load */
1478 if (op1 == OR_TMP0)
1479 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
1480 else
1481 gen_op_mov_v_reg(ot, cpu_T[0], op1);
1482
1483 op2 &= mask;
1484 if (op2 != 0) {
1485 if (is_right) {
1486 if (is_arith) {
1487 gen_exts(ot, cpu_T[0]);
1488 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1489 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1490 } else {
1491 gen_extu(ot, cpu_T[0]);
1492 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1493 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1494 }
1495 } else {
1496 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1497 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1498 }
1499 }
1500
1501 /* store */
1502 gen_op_st_rm_T0_A0(s, ot, op1);
1503
1504 /* update eflags if non zero shift */
1505 if (op2 != 0) {
1506 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1507 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1508 set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot);
1509 }
1510 }
1511
1512 static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
1513 {
1514 target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
1515 TCGv_i32 t0, t1;
1516
1517 /* load */
1518 if (op1 == OR_TMP0) {
1519 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
1520 } else {
1521 gen_op_mov_v_reg(ot, cpu_T[0], op1);
1522 }
1523
1524 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1525
1526 switch (ot) {
1527 case MO_8:
1528 /* Replicate the 8-bit input so that a 32-bit rotate works. */
1529 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
1530 tcg_gen_muli_tl(cpu_T[0], cpu_T[0], 0x01010101);
1531 goto do_long;
1532 case MO_16:
1533 /* Replicate the 16-bit input so that a 32-bit rotate works. */
1534 tcg_gen_deposit_tl(cpu_T[0], cpu_T[0], cpu_T[0], 16, 16);
1535 goto do_long;
1536 do_long:
1537 #ifdef TARGET_X86_64
1538 case MO_32:
1539 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
1540 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
1541 if (is_right) {
1542 tcg_gen_rotr_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
1543 } else {
1544 tcg_gen_rotl_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
1545 }
1546 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
1547 break;
1548 #endif
1549 default:
1550 if (is_right) {
1551 tcg_gen_rotr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1552 } else {
1553 tcg_gen_rotl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1554 }
1555 break;
1556 }
1557
1558 /* store */
1559 gen_op_st_rm_T0_A0(s, ot, op1);
1560
1561 /* We'll need the flags computed into CC_SRC. */
1562 gen_compute_eflags(s);
1563
1564 /* The value that was "rotated out" is now present at the other end
1565 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1566 since we've computed the flags into CC_SRC, these variables are
1567 currently dead. */
1568 if (is_right) {
1569 tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
1570 tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
1571 tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
1572 } else {
1573 tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
1574 tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);
1575 }
1576 tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1);
1577 tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst);
1578
1579 /* Now conditionally store the new CC_OP value. If the shift count
1580 is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
1581 Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
1582 exactly as we computed above. */
1583 t0 = tcg_const_i32(0);
1584 t1 = tcg_temp_new_i32();
1585 tcg_gen_trunc_tl_i32(t1, cpu_T[1]);
1586 tcg_gen_movi_i32(cpu_tmp2_i32, CC_OP_ADCOX);
1587 tcg_gen_movi_i32(cpu_tmp3_i32, CC_OP_EFLAGS);
1588 tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, t1, t0,
1589 cpu_tmp2_i32, cpu_tmp3_i32);
1590 tcg_temp_free_i32(t0);
1591 tcg_temp_free_i32(t1);
1592
1593 /* The CC_OP value is no longer predictable. */
1594 set_cc_op(s, CC_OP_DYNAMIC);
1595 }
1596
1597 static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
1598 int is_right)
1599 {
1600 int mask = (ot == MO_64 ? 0x3f : 0x1f);
1601 int shift;
1602
1603 /* load */
1604 if (op1 == OR_TMP0) {
1605 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
1606 } else {
1607 gen_op_mov_v_reg(ot, cpu_T[0], op1);
1608 }
1609
1610 op2 &= mask;
1611 if (op2 != 0) {
1612 switch (ot) {
1613 #ifdef TARGET_X86_64
1614 case MO_32:
1615 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
1616 if (is_right) {
1617 tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2);
1618 } else {
1619 tcg_gen_rotli_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2);
1620 }
1621 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
1622 break;
1623 #endif
1624 default:
1625 if (is_right) {
1626 tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], op2);
1627 } else {
1628 tcg_gen_rotli_tl(cpu_T[0], cpu_T[0], op2);
1629 }
1630 break;
1631 case MO_8:
1632 mask = 7;
1633 goto do_shifts;
1634 case MO_16:
1635 mask = 15;
1636 do_shifts:
1637 shift = op2 & mask;
1638 if (is_right) {
1639 shift = mask + 1 - shift;
1640 }
1641 gen_extu(ot, cpu_T[0]);
1642 tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], shift);
1643 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], mask + 1 - shift);
1644 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1645 break;
1646 }
1647 }
1648
1649 /* store */
1650 gen_op_st_rm_T0_A0(s, ot, op1);
1651
1652 if (op2 != 0) {
1653 /* Compute the flags into CC_SRC. */
1654 gen_compute_eflags(s);
1655
1656 /* The value that was "rotated out" is now present at the other end
1657 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1658 since we've computed the flags into CC_SRC, these variables are
1659 currently dead. */
1660 if (is_right) {
1661 tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
1662 tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
1663 tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
1664 } else {
1665 tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
1666 tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);
1667 }
1668 tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1);
1669 tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst);
1670 set_cc_op(s, CC_OP_ADCOX);
1671 }
1672 }
1673
1674 /* XXX: add faster immediate = 1 case */
1675 static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
1676 int is_right)
1677 {
1678 gen_compute_eflags(s);
1679 assert(s->cc_op == CC_OP_EFLAGS);
1680
1681 /* load */
1682 if (op1 == OR_TMP0)
1683 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
1684 else
1685 gen_op_mov_v_reg(ot, cpu_T[0], op1);
1686
1687 if (is_right) {
1688 switch (ot) {
1689 case MO_8:
1690 gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1691 break;
1692 case MO_16:
1693 gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1694 break;
1695 case MO_32:
1696 gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1697 break;
1698 #ifdef TARGET_X86_64
1699 case MO_64:
1700 gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1701 break;
1702 #endif
1703 default:
1704 tcg_abort();
1705 }
1706 } else {
1707 switch (ot) {
1708 case MO_8:
1709 gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1710 break;
1711 case MO_16:
1712 gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1713 break;
1714 case MO_32:
1715 gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1716 break;
1717 #ifdef TARGET_X86_64
1718 case MO_64:
1719 gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1720 break;
1721 #endif
1722 default:
1723 tcg_abort();
1724 }
1725 }
1726 /* store */
1727 gen_op_st_rm_T0_A0(s, ot, op1);
1728 }
1729
1730 /* XXX: add faster immediate case */
1731 static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
1732 bool is_right, TCGv count_in)
1733 {
1734 target_ulong mask = (ot == MO_64 ? 63 : 31);
1735 TCGv count;
1736
1737 /* load */
1738 if (op1 == OR_TMP0) {
1739 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
1740 } else {
1741 gen_op_mov_v_reg(ot, cpu_T[0], op1);
1742 }
1743
1744 count = tcg_temp_new();
1745 tcg_gen_andi_tl(count, count_in, mask);
1746
1747 switch (ot) {
1748 case MO_16:
1749 /* Note: we implement the Intel behaviour for shift count > 16.
1750 This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
1751 portion by constructing it as a 32-bit value. */
1752 if (is_right) {
1753 tcg_gen_deposit_tl(cpu_tmp0, cpu_T[0], cpu_T[1], 16, 16);
1754 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1755 tcg_gen_mov_tl(cpu_T[0], cpu_tmp0);
1756 } else {
1757 tcg_gen_deposit_tl(cpu_T[1], cpu_T[0], cpu_T[1], 16, 16);
1758 }
1759 /* FALLTHRU */
1760 #ifdef TARGET_X86_64
1761 case MO_32:
1762 /* Concatenate the two 32-bit values and use a 64-bit shift. */
1763 tcg_gen_subi_tl(cpu_tmp0, count, 1);
1764 if (is_right) {
1765 tcg_gen_concat_tl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
1766 tcg_gen_shr_i64(cpu_tmp0, cpu_T[0], cpu_tmp0);
1767 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], count);
1768 } else {
1769 tcg_gen_concat_tl_i64(cpu_T[0], cpu_T[1], cpu_T[0]);
1770 tcg_gen_shl_i64(cpu_tmp0, cpu_T[0], cpu_tmp0);
1771 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], count);
1772 tcg_gen_shri_i64(cpu_tmp0, cpu_tmp0, 32);
1773 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], 32);
1774 }
1775 break;
1776 #endif
1777 default:
1778 tcg_gen_subi_tl(cpu_tmp0, count, 1);
1779 if (is_right) {
1780 tcg_gen_shr_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
1781
1782 tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count);
1783 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], count);
1784 tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp4);
1785 } else {
1786 tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
1787 if (ot == MO_16) {
1788 /* Only needed if count > 16, for Intel behaviour. */
1789 tcg_gen_subfi_tl(cpu_tmp4, 33, count);
1790 tcg_gen_shr_tl(cpu_tmp4, cpu_T[1], cpu_tmp4);
1791 tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, cpu_tmp4);
1792 }
1793
1794 tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count);
1795 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], count);
1796 tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp4);
1797 }
1798 tcg_gen_movi_tl(cpu_tmp4, 0);
1799 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[1], count, cpu_tmp4,
1800 cpu_tmp4, cpu_T[1]);
1801 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1802 break;
1803 }
1804
1805 /* store */
1806 gen_op_st_rm_T0_A0(s, ot, op1);
1807
1808 gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, count, is_right);
1809 tcg_temp_free(count);
1810 }
1811
1812 static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
1813 {
1814 if (s != OR_TMP1)
1815 gen_op_mov_v_reg(ot, cpu_T[1], s);
1816 switch(op) {
1817 case OP_ROL:
1818 gen_rot_rm_T1(s1, ot, d, 0);
1819 break;
1820 case OP_ROR:
1821 gen_rot_rm_T1(s1, ot, d, 1);
1822 break;
1823 case OP_SHL:
1824 case OP_SHL1:
1825 gen_shift_rm_T1(s1, ot, d, 0, 0);
1826 break;
1827 case OP_SHR:
1828 gen_shift_rm_T1(s1, ot, d, 1, 0);
1829 break;
1830 case OP_SAR:
1831 gen_shift_rm_T1(s1, ot, d, 1, 1);
1832 break;
1833 case OP_RCL:
1834 gen_rotc_rm_T1(s1, ot, d, 0);
1835 break;
1836 case OP_RCR:
1837 gen_rotc_rm_T1(s1, ot, d, 1);
1838 break;
1839 }
1840 }
1841
1842 static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c)
1843 {
1844 switch(op) {
1845 case OP_ROL:
1846 gen_rot_rm_im(s1, ot, d, c, 0);
1847 break;
1848 case OP_ROR:
1849 gen_rot_rm_im(s1, ot, d, c, 1);
1850 break;
1851 case OP_SHL:
1852 case OP_SHL1:
1853 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1854 break;
1855 case OP_SHR:
1856 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1857 break;
1858 case OP_SAR:
1859 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1860 break;
1861 default:
1862 /* currently not optimized */
1863 tcg_gen_movi_tl(cpu_T[1], c);
1864 gen_shift(s1, op, ot, d, OR_TMP1);
1865 break;
1866 }
1867 }
1868
1869 static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
1870 {
1871 target_long disp;
1872 int havesib;
1873 int base;
1874 int index;
1875 int scale;
1876 int mod, rm, code, override, must_add_seg;
1877 TCGv sum;
1878
1879 override = s->override;
1880 must_add_seg = s->addseg;
1881 if (override >= 0)
1882 must_add_seg = 1;
1883 mod = (modrm >> 6) & 3;
1884 rm = modrm & 7;
1885
1886 switch (s->aflag) {
1887 case MO_64:
1888 case MO_32:
1889 havesib = 0;
1890 base = rm;
1891 index = -1;
1892 scale = 0;
1893
1894 if (base == 4) {
1895 havesib = 1;
1896 code = cpu_ldub_code(env, s->pc++);
1897 scale = (code >> 6) & 3;
1898 index = ((code >> 3) & 7) | REX_X(s);
1899 if (index == 4) {
1900 index = -1; /* no index */
1901 }
1902 base = (code & 7);
1903 }
1904 base |= REX_B(s);
1905
1906 switch (mod) {
1907 case 0:
1908 if ((base & 7) == 5) {
1909 base = -1;
1910 disp = (int32_t)cpu_ldl_code(env, s->pc);
1911 s->pc += 4;
1912 if (CODE64(s) && !havesib) {
1913 disp += s->pc + s->rip_offset;
1914 }
1915 } else {
1916 disp = 0;
1917 }
1918 break;
1919 case 1:
1920 disp = (int8_t)cpu_ldub_code(env, s->pc++);
1921 break;
1922 default:
1923 case 2:
1924 disp = (int32_t)cpu_ldl_code(env, s->pc);
1925 s->pc += 4;
1926 break;
1927 }
1928
1929 /* For correct popl handling with esp. */
1930 if (base == R_ESP && s->popl_esp_hack) {
1931 disp += s->popl_esp_hack;
1932 }
1933
1934 /* Compute the address, with a minimum number of TCG ops. */
1935 TCGV_UNUSED(sum);
1936 if (index >= 0) {
1937 if (scale == 0) {
1938 sum = cpu_regs[index];
1939 } else {
1940 tcg_gen_shli_tl(cpu_A0, cpu_regs[index], scale);
1941 sum = cpu_A0;
1942 }
1943 if (base >= 0) {
1944 tcg_gen_add_tl(cpu_A0, sum, cpu_regs[base]);
1945 sum = cpu_A0;
1946 }
1947 } else if (base >= 0) {
1948 sum = cpu_regs[base];
1949 }
1950 if (TCGV_IS_UNUSED(sum)) {
1951 tcg_gen_movi_tl(cpu_A0, disp);
1952 } else {
1953 tcg_gen_addi_tl(cpu_A0, sum, disp);
1954 }
1955
1956 if (must_add_seg) {
1957 if (override < 0) {
1958 if (base == R_EBP || base == R_ESP) {
1959 override = R_SS;
1960 } else {
1961 override = R_DS;
1962 }
1963 }
1964
1965 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
1966 offsetof(CPUX86State, segs[override].base));
1967 if (CODE64(s)) {
1968 if (s->aflag == MO_32) {
1969 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
1970 }
1971 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
1972 return;
1973 }
1974
1975 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
1976 }
1977
1978 if (s->aflag == MO_32) {
1979 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
1980 }
1981 break;
1982
1983 case MO_16:
1984 switch (mod) {
1985 case 0:
1986 if (rm == 6) {
1987 disp = cpu_lduw_code(env, s->pc);
1988 s->pc += 2;
1989 tcg_gen_movi_tl(cpu_A0, disp);
1990 rm = 0; /* avoid SS override */
1991 goto no_rm;
1992 } else {
1993 disp = 0;
1994 }
1995 break;
1996 case 1:
1997 disp = (int8_t)cpu_ldub_code(env, s->pc++);
1998 break;
1999 default:
2000 case 2:
2001 disp = (int16_t)cpu_lduw_code(env, s->pc);
2002 s->pc += 2;
2003 break;
2004 }
2005
2006 sum = cpu_A0;
2007 switch (rm) {
2008 case 0:
2009 tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_ESI]);
2010 break;
2011 case 1:
2012 tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_EDI]);
2013 break;
2014 case 2:
2015 tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_ESI]);
2016 break;
2017 case 3:
2018 tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_EDI]);
2019 break;
2020 case 4:
2021 sum = cpu_regs[R_ESI];
2022 break;
2023 case 5:
2024 sum = cpu_regs[R_EDI];
2025 break;
2026 case 6:
2027 sum = cpu_regs[R_EBP];
2028 break;
2029 default:
2030 case 7:
2031 sum = cpu_regs[R_EBX];
2032 break;
2033 }
2034 tcg_gen_addi_tl(cpu_A0, sum, disp);
2035 tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
2036 no_rm:
2037 if (must_add_seg) {
2038 if (override < 0) {
2039 if (rm == 2 || rm == 3 || rm == 6) {
2040 override = R_SS;
2041 } else {
2042 override = R_DS;
2043 }
2044 }
2045 gen_op_addl_A0_seg(s, override);
2046 }
2047 break;
2048
2049 default:
2050 tcg_abort();
2051 }
2052 }
2053
2054 static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
2055 {
2056 int mod, rm, base, code;
2057
2058 mod = (modrm >> 6) & 3;
2059 if (mod == 3)
2060 return;
2061 rm = modrm & 7;
2062
2063 switch (s->aflag) {
2064 case MO_64:
2065 case MO_32:
2066 base = rm;
2067
2068 if (base == 4) {
2069 code = cpu_ldub_code(env, s->pc++);
2070 base = (code & 7);
2071 }
2072
2073 switch (mod) {
2074 case 0:
2075 if (base == 5) {
2076 s->pc += 4;
2077 }
2078 break;
2079 case 1:
2080 s->pc++;
2081 break;
2082 default:
2083 case 2:
2084 s->pc += 4;
2085 break;
2086 }
2087 break;
2088
2089 case MO_16:
2090 switch (mod) {
2091 case 0:
2092 if (rm == 6) {
2093 s->pc += 2;
2094 }
2095 break;
2096 case 1:
2097 s->pc++;
2098 break;
2099 default:
2100 case 2:
2101 s->pc += 2;
2102 break;
2103 }
2104 break;
2105
2106 default:
2107 tcg_abort();
2108 }
2109 }
2110
2111 /* used for LEA and MOV AX, mem */
2112 static void gen_add_A0_ds_seg(DisasContext *s)
2113 {
2114 int override, must_add_seg;
2115 must_add_seg = s->addseg;
2116 override = R_DS;
2117 if (s->override >= 0) {
2118 override = s->override;
2119 must_add_seg = 1;
2120 }
2121 if (must_add_seg) {
2122 #ifdef TARGET_X86_64
2123 if (CODE64(s)) {
2124 gen_op_addq_A0_seg(override);
2125 } else
2126 #endif
2127 {
2128 gen_op_addl_A0_seg(s, override);
2129 }
2130 }
2131 }
2132
2133 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2134 OR_TMP0 */
2135 static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
2136 TCGMemOp ot, int reg, int is_store)
2137 {
2138 int mod, rm;
2139
2140 mod = (modrm >> 6) & 3;
2141 rm = (modrm & 7) | REX_B(s);
2142 if (mod == 3) {
2143 if (is_store) {
2144 if (reg != OR_TMP0)
2145 gen_op_mov_v_reg(ot, cpu_T[0], reg);
2146 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
2147 } else {
2148 gen_op_mov_v_reg(ot, cpu_T[0], rm);
2149 if (reg != OR_TMP0)
2150 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
2151 }
2152 } else {
2153 gen_lea_modrm(env, s, modrm);
2154 if (is_store) {
2155 if (reg != OR_TMP0)
2156 gen_op_mov_v_reg(ot, cpu_T[0], reg);
2157 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
2158 } else {
2159 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
2160 if (reg != OR_TMP0)
2161 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
2162 }
2163 }
2164 }
2165
2166 static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)
2167 {
2168 uint32_t ret;
2169
2170 switch (ot) {
2171 case MO_8:
2172 ret = cpu_ldub_code(env, s->pc);
2173 s->pc++;
2174 break;
2175 case MO_16:
2176 ret = cpu_lduw_code(env, s->pc);
2177 s->pc += 2;
2178 break;
2179 case MO_32:
2180 #ifdef TARGET_X86_64
2181 case MO_64:
2182 #endif
2183 ret = cpu_ldl_code(env, s->pc);
2184 s->pc += 4;
2185 break;
2186 default:
2187 tcg_abort();
2188 }
2189 return ret;
2190 }
2191
2192 static inline int insn_const_size(TCGMemOp ot)
2193 {
2194 if (ot <= MO_32) {
2195 return 1 << ot;
2196 } else {
2197 return 4;
2198 }
2199 }
2200
2201 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2202 {
2203 TranslationBlock *tb;
2204 target_ulong pc;
2205
2206 pc = s->cs_base + eip;
2207 tb = s->tb;
2208 /* NOTE: we handle the case where the TB spans two pages here */
2209 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2210 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2211 /* jump to same page: we can use a direct jump */
2212 tcg_gen_goto_tb(tb_num);
2213 gen_jmp_im(eip);
2214 tcg_gen_exit_tb((uintptr_t)tb + tb_num);
2215 } else {
2216 /* jump to another page: currently not optimized */
2217 gen_jmp_im(eip);
2218 gen_eob(s);
2219 }
2220 }
2221
2222 static inline void gen_jcc(DisasContext *s, int b,
2223 target_ulong val, target_ulong next_eip)
2224 {
2225 int l1, l2;
2226
2227 if (s->jmp_opt) {
2228 l1 = gen_new_label();
2229 gen_jcc1(s, b, l1);
2230
2231 gen_goto_tb(s, 0, next_eip);
2232
2233 gen_set_label(l1);
2234 gen_goto_tb(s, 1, val);
2235 s->is_jmp = DISAS_TB_JUMP;
2236 } else {
2237 l1 = gen_new_label();
2238 l2 = gen_new_label();
2239 gen_jcc1(s, b, l1);
2240
2241 gen_jmp_im(next_eip);
2242 tcg_gen_br(l2);
2243
2244 gen_set_label(l1);
2245 gen_jmp_im(val);
2246 gen_set_label(l2);
2247 gen_eob(s);
2248 }
2249 }
2250
2251 static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
2252 int modrm, int reg)
2253 {
2254 CCPrepare cc;
2255
2256 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
2257
2258 cc = gen_prepare_cc(s, b, cpu_T[1]);
2259 if (cc.mask != -1) {
2260 TCGv t0 = tcg_temp_new();
2261 tcg_gen_andi_tl(t0, cc.reg, cc.mask);
2262 cc.reg = t0;
2263 }
2264 if (!cc.use_reg2) {
2265 cc.reg2 = tcg_const_tl(cc.imm);
2266 }
2267
2268 tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
2269 cpu_T[0], cpu_regs[reg]);
2270 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
2271
2272 if (cc.mask != -1) {
2273 tcg_temp_free(cc.reg);
2274 }
2275 if (!cc.use_reg2) {
2276 tcg_temp_free(cc.reg2);
2277 }
2278 }
2279
2280 static inline void gen_op_movl_T0_seg(int seg_reg)
2281 {
2282 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2283 offsetof(CPUX86State,segs[seg_reg].selector));
2284 }
2285
2286 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2287 {
2288 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2289 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2290 offsetof(CPUX86State,segs[seg_reg].selector));
2291 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2292 tcg_gen_st_tl(cpu_T[0], cpu_env,
2293 offsetof(CPUX86State,segs[seg_reg].base));
2294 }
2295
2296 /* move T0 to seg_reg and compute if the CPU state may change. Never
2297 call this function with seg_reg == R_CS */
2298 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2299 {
2300 if (s->pe && !s->vm86) {
2301 /* XXX: optimize by finding processor state dynamically */
2302 gen_update_cc_op(s);
2303 gen_jmp_im(cur_eip);
2304 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2305 gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32);
2306 /* abort translation because the addseg value may change or
2307 because ss32 may change. For R_SS, translation must always
2308 stop as a special handling must be done to disable hardware
2309 interrupts for the next instruction */
2310 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2311 s->is_jmp = DISAS_TB_JUMP;
2312 } else {
2313 gen_op_movl_seg_T0_vm(seg_reg);
2314 if (seg_reg == R_SS)
2315 s->is_jmp = DISAS_TB_JUMP;
2316 }
2317 }
2318
2319 static inline int svm_is_rep(int prefixes)
2320 {
2321 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2322 }
2323
2324 static inline void
2325 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2326 uint32_t type, uint64_t param)
2327 {
2328 /* no SVM activated; fast case */
2329 if (likely(!(s->flags & HF_SVMI_MASK)))
2330 return;
2331 gen_update_cc_op(s);
2332 gen_jmp_im(pc_start - s->cs_base);
2333 gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type),
2334 tcg_const_i64(param));
2335 }
2336
2337 static inline void
2338 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2339 {
2340 gen_svm_check_intercept_param(s, pc_start, type, 0);
2341 }
2342
2343 static inline void gen_stack_update(DisasContext *s, int addend)
2344 {
2345 #ifdef TARGET_X86_64
2346 if (CODE64(s)) {
2347 gen_op_add_reg_im(MO_64, R_ESP, addend);
2348 } else
2349 #endif
2350 if (s->ss32) {
2351 gen_op_add_reg_im(MO_32, R_ESP, addend);
2352 } else {
2353 gen_op_add_reg_im(MO_16, R_ESP, addend);
2354 }
2355 }
2356
2357 /* Generate a push. It depends on ss32, addseg and dflag. */
2358 static void gen_push_v(DisasContext *s, TCGv val)
2359 {
2360 TCGMemOp a_ot, d_ot = mo_pushpop(s, s->dflag);
2361 int size = 1 << d_ot;
2362 TCGv new_esp = cpu_A0;
2363
2364 tcg_gen_subi_tl(cpu_A0, cpu_regs[R_ESP], size);
2365
2366 if (CODE64(s)) {
2367 a_ot = MO_64;
2368 } else if (s->ss32) {
2369 a_ot = MO_32;
2370 if (s->addseg) {
2371 new_esp = cpu_tmp4;
2372 tcg_gen_mov_tl(new_esp, cpu_A0);
2373 gen_op_addl_A0_seg(s, R_SS);
2374 } else {
2375 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
2376 }
2377 } else {
2378 a_ot = MO_16;
2379 new_esp = cpu_tmp4;
2380 tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
2381 tcg_gen_mov_tl(new_esp, cpu_A0);
2382 gen_op_addl_A0_seg(s, R_SS);
2383 }
2384
2385 gen_op_st_v(s, d_ot, val, cpu_A0);
2386 gen_op_mov_reg_v(a_ot, R_ESP, new_esp);
2387 }
2388
2389 /* two step pop is necessary for precise exceptions */
2390 static TCGMemOp gen_pop_T0(DisasContext *s)
2391 {
2392 TCGMemOp d_ot = mo_pushpop(s, s->dflag);
2393 TCGv addr = cpu_A0;
2394
2395 if (CODE64(s)) {
2396 addr = cpu_regs[R_ESP];
2397 } else if (!s->ss32) {
2398 tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESP]);
2399 gen_op_addl_A0_seg(s, R_SS);
2400 } else if (s->addseg) {
2401 tcg_gen_mov_tl(cpu_A0, cpu_regs[R_ESP]);
2402 gen_op_addl_A0_seg(s, R_SS);
2403 } else {
2404 tcg_gen_ext32u_tl(cpu_A0, cpu_regs[R_ESP]);
2405 }
2406
2407 gen_op_ld_v(s, d_ot, cpu_T[0], addr);
2408 return d_ot;
2409 }
2410
2411 static void gen_pop_update(DisasContext *s, TCGMemOp ot)
2412 {
2413 gen_stack_update(s, 1 << ot);
2414 }
2415
2416 static void gen_stack_A0(DisasContext *s)
2417 {
2418 gen_op_movl_A0_reg(R_ESP);
2419 if (!s->ss32)
2420 tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
2421 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2422 if (s->addseg)
2423 gen_op_addl_A0_seg(s, R_SS);
2424 }
2425
2426 /* NOTE: wrap around in 16 bit not fully handled */
2427 static void gen_pusha(DisasContext *s)
2428 {
2429 int i;
2430 gen_op_movl_A0_reg(R_ESP);
2431 gen_op_addl_A0_im(-8 << s->dflag);
2432 if (!s->ss32)
2433 tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
2434 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2435 if (s->addseg)
2436 gen_op_addl_A0_seg(s, R_SS);
2437 for(i = 0;i < 8; i++) {
2438 gen_op_mov_v_reg(MO_32, cpu_T[0], 7 - i);
2439 gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
2440 gen_op_addl_A0_im(1 << s->dflag);
2441 }
2442 gen_op_mov_reg_v(MO_16 + s->ss32, R_ESP, cpu_T[1]);
2443 }
2444
2445 /* NOTE: wrap around in 16 bit not fully handled */
2446 static void gen_popa(DisasContext *s)
2447 {
2448 int i;
2449 gen_op_movl_A0_reg(R_ESP);
2450 if (!s->ss32)
2451 tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
2452 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2453 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 8 << s->dflag);
2454 if (s->addseg)
2455 gen_op_addl_A0_seg(s, R_SS);
2456 for(i = 0;i < 8; i++) {
2457 /* ESP is not reloaded */
2458 if (i != 3) {
2459 gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
2460 gen_op_mov_reg_v(s->dflag, 7 - i, cpu_T[0]);
2461 }
2462 gen_op_addl_A0_im(1 << s->dflag);
2463 }
2464 gen_op_mov_reg_v(MO_16 + s->ss32, R_ESP, cpu_T[1]);
2465 }
2466
2467 static void gen_enter(DisasContext *s, int esp_addend, int level)
2468 {
2469 TCGMemOp ot = mo_pushpop(s, s->dflag);
2470 int opsize = 1 << ot;
2471
2472 level &= 0x1f;
2473 #ifdef TARGET_X86_64
2474 if (CODE64(s)) {
2475 gen_op_movl_A0_reg(R_ESP);
2476 gen_op_addq_A0_im(-opsize);
2477 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2478
2479 /* push bp */
2480 gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP);
2481 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
2482 if (level) {
2483 /* XXX: must save state */
2484 gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
2485 tcg_const_i32((ot == MO_64)),
2486 cpu_T[1]);
2487 }
2488 gen_op_mov_reg_v(ot, R_EBP, cpu_T[1]);
2489 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2490 gen_op_mov_reg_v(MO_64, R_ESP, cpu_T[1]);
2491 } else
2492 #endif
2493 {
2494 gen_op_movl_A0_reg(R_ESP);
2495 gen_op_addl_A0_im(-opsize);
2496 if (!s->ss32)
2497 tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
2498 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2499 if (s->addseg)
2500 gen_op_addl_A0_seg(s, R_SS);
2501 /* push bp */
2502 gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP);
2503 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
2504 if (level) {
2505 /* XXX: must save state */
2506 gen_helper_enter_level(cpu_env, tcg_const_i32(level),
2507 tcg_const_i32(s->dflag - 1),
2508 cpu_T[1]);
2509 }
2510 gen_op_mov_reg_v(ot, R_EBP, cpu_T[1]);
2511 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2512 gen_op_mov_reg_v(MO_16 + s->ss32, R_ESP, cpu_T[1]);
2513 }
2514 }
2515
2516 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2517 {
2518 gen_update_cc_op(s);
2519 gen_jmp_im(cur_eip);
2520 gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
2521 s->is_jmp = DISAS_TB_JUMP;
2522 }
2523
2524 /* an interrupt is different from an exception because of the
2525 privilege checks */
2526 static void gen_interrupt(DisasContext *s, int intno,
2527 target_ulong cur_eip, target_ulong next_eip)
2528 {
2529 gen_update_cc_op(s);
2530 gen_jmp_im(cur_eip);
2531 gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno),
2532 tcg_const_i32(next_eip - cur_eip));
2533 s->is_jmp = DISAS_TB_JUMP;
2534 }
2535
2536 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2537 {
2538 gen_update_cc_op(s);
2539 gen_jmp_im(cur_eip);
2540 gen_helper_debug(cpu_env);
2541 s->is_jmp = DISAS_TB_JUMP;
2542 }
2543
2544 /* generate a generic end of block. Trace exception is also generated
2545 if needed */
2546 static void gen_eob(DisasContext *s)
2547 {
2548 gen_update_cc_op(s);
2549 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2550 gen_helper_reset_inhibit_irq(cpu_env);
2551 }
2552 if (s->tb->flags & HF_RF_MASK) {
2553 gen_helper_reset_rf(cpu_env);
2554 }
2555 if (s->singlestep_enabled) {
2556 gen_helper_debug(cpu_env);
2557 } else if (s->tf) {
2558 gen_helper_single_step(cpu_env);
2559 } else {
2560 tcg_gen_exit_tb(0);
2561 }
2562 s->is_jmp = DISAS_TB_JUMP;
2563 }
2564
2565 /* generate a jump to eip. No segment change must happen before as a
2566 direct call to the next block may occur */
2567 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2568 {
2569 gen_update_cc_op(s);
2570 set_cc_op(s, CC_OP_DYNAMIC);
2571 if (s->jmp_opt) {
2572 gen_goto_tb(s, tb_num, eip);
2573 s->is_jmp = DISAS_TB_JUMP;
2574 } else {
2575 gen_jmp_im(eip);
2576 gen_eob(s);
2577 }
2578 }
2579
2580 static void gen_jmp(DisasContext *s, target_ulong eip)
2581 {
2582 gen_jmp_tb(s, eip, 0);
2583 }
2584
2585 static inline void gen_ldq_env_A0(DisasContext *s, int offset)
2586 {
2587 tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
2588 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2589 }
2590
2591 static inline void gen_stq_env_A0(DisasContext *s, int offset)
2592 {
2593 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2594 tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
2595 }
2596
2597 static inline void gen_ldo_env_A0(DisasContext *s, int offset)
2598 {
2599 int mem_index = s->mem_index;
2600 tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
2601 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2602 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2603 tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
2604 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2605 }
2606
2607 static inline void gen_sto_env_A0(DisasContext *s, int offset)
2608 {
2609 int mem_index = s->mem_index;
2610 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2611 tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
2612 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2613 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2614 tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
2615 }
2616
2617 static inline void gen_op_movo(int d_offset, int s_offset)
2618 {
2619 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2620 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2621 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2622 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2623 }
2624
2625 static inline void gen_op_movq(int d_offset, int s_offset)
2626 {
2627 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2628 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2629 }
2630
2631 static inline void gen_op_movl(int d_offset, int s_offset)
2632 {
2633 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2634 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2635 }
2636
2637 static inline void gen_op_movq_env_0(int d_offset)
2638 {
2639 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2640 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2641 }
2642
2643 typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg);
2644 typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg);
2645 typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val);
2646 typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val);
2647 typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b);
2648 typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2649 TCGv_i32 val);
2650 typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
2651 typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2652 TCGv val);
2653
2654 #define SSE_SPECIAL ((void *)1)
2655 #define SSE_DUMMY ((void *)2)
2656
2657 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2658 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2659 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2660
2661 static const SSEFunc_0_epp sse_op_table1[256][4] = {
2662 /* 3DNow! extensions */
2663 [0x0e] = { SSE_DUMMY }, /* femms */
2664 [0x0f] = { SSE_DUMMY }, /* pf... */
2665 /* pure SSE operations */
2666 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2667 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2668 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2669 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2670 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2671 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2672 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2673 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2674
2675 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2676 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2677 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2678 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2679 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2680 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2681 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2682 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2683 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2684 [0x51] = SSE_FOP(sqrt),
2685 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2686 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2687 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2688 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2689 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2690 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2691 [0x58] = SSE_FOP(add),
2692 [0x59] = SSE_FOP(mul),
2693 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2694 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2695 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2696 [0x5c] = SSE_FOP(sub),
2697 [0x5d] = SSE_FOP(min),
2698 [0x5e] = SSE_FOP(div),
2699 [0x5f] = SSE_FOP(max),
2700
2701 [0xc2] = SSE_FOP(cmpeq),
2702 [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps,
2703 (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */
2704
2705 /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
2706 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2707 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2708
2709 /* MMX ops and their SSE extensions */
2710 [0x60] = MMX_OP2(punpcklbw),
2711 [0x61] = MMX_OP2(punpcklwd),
2712 [0x62] = MMX_OP2(punpckldq),
2713 [0x63] = MMX_OP2(packsswb),
2714 [0x64] = MMX_OP2(pcmpgtb),
2715 [0x65] = MMX_OP2(pcmpgtw),
2716 [0x66] = MMX_OP2(pcmpgtl),
2717 [0x67] = MMX_OP2(packuswb),
2718 [0x68] = MMX_OP2(punpckhbw),
2719 [0x69] = MMX_OP2(punpckhwd),
2720 [0x6a] = MMX_OP2(punpckhdq),
2721 [0x6b] = MMX_OP2(packssdw),
2722 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2723 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2724 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2725 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2726 [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx,
2727 (SSEFunc_0_epp)gen_helper_pshufd_xmm,
2728 (SSEFunc_0_epp)gen_helper_pshufhw_xmm,
2729 (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */
2730 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2731 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2732 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2733 [0x74] = MMX_OP2(pcmpeqb),
2734 [0x75] = MMX_OP2(pcmpeqw),
2735 [0x76] = MMX_OP2(pcmpeql),
2736 [0x77] = { SSE_DUMMY }, /* emms */
2737 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2738 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
2739 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2740 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2741 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2742 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2743 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2744 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2745 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2746 [0xd1] = MMX_OP2(psrlw),
2747 [0xd2] = MMX_OP2(psrld),
2748 [0xd3] = MMX_OP2(psrlq),
2749 [0xd4] = MMX_OP2(paddq),
2750 [0xd5] = MMX_OP2(pmullw),
2751 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2752 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2753 [0xd8] = MMX_OP2(psubusb),
2754 [0xd9] = MMX_OP2(psubusw),
2755 [0xda] = MMX_OP2(pminub),
2756 [0xdb] = MMX_OP2(pand),
2757 [0xdc] = MMX_OP2(paddusb),
2758 [0xdd] = MMX_OP2(paddusw),
2759 [0xde] = MMX_OP2(pmaxub),
2760 [0xdf] = MMX_OP2(pandn),
2761 [0xe0] = MMX_OP2(pavgb),
2762 [0xe1] = MMX_OP2(psraw),
2763 [0xe2] = MMX_OP2(psrad),
2764 [0xe3] = MMX_OP2(pavgw),
2765 [0xe4] = MMX_OP2(pmulhuw),
2766 [0xe5] = MMX_OP2(pmulhw),
2767 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2768 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2769 [0xe8] = MMX_OP2(psubsb),
2770 [0xe9] = MMX_OP2(psubsw),
2771 [0xea] = MMX_OP2(pminsw),
2772 [0xeb] = MMX_OP2(por),
2773 [0xec] = MMX_OP2(paddsb),
2774 [0xed] = MMX_OP2(paddsw),
2775 [0xee] = MMX_OP2(pmaxsw),
2776 [0xef] = MMX_OP2(pxor),
2777 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2778 [0xf1] = MMX_OP2(psllw),
2779 [0xf2] = MMX_OP2(pslld),
2780 [0xf3] = MMX_OP2(psllq),
2781 [0xf4] = MMX_OP2(pmuludq),
2782 [0xf5] = MMX_OP2(pmaddwd),
2783 [0xf6] = MMX_OP2(psadbw),
2784 [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx,
2785 (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */
2786 [0xf8] = MMX_OP2(psubb),
2787 [0xf9] = MMX_OP2(psubw),
2788 [0xfa] = MMX_OP2(psubl),
2789 [0xfb] = MMX_OP2(psubq),
2790 [0xfc] = MMX_OP2(paddb),
2791 [0xfd] = MMX_OP2(paddw),
2792 [0xfe] = MMX_OP2(paddl),
2793 };
2794
2795 static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = {
2796 [0 + 2] = MMX_OP2(psrlw),
2797 [0 + 4] = MMX_OP2(psraw),
2798 [0 + 6] = MMX_OP2(psllw),
2799 [8 + 2] = MMX_OP2(psrld),
2800 [8 + 4] = MMX_OP2(psrad),
2801 [8 + 6] = MMX_OP2(pslld),
2802 [16 + 2] = MMX_OP2(psrlq),
2803 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
2804 [16 + 6] = MMX_OP2(psllq),
2805 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
2806 };
2807
2808 static const SSEFunc_0_epi sse_op_table3ai[] = {
2809 gen_helper_cvtsi2ss,
2810 gen_helper_cvtsi2sd
2811 };
2812
2813 #ifdef TARGET_X86_64
2814 static const SSEFunc_0_epl sse_op_table3aq[] = {
2815 gen_helper_cvtsq2ss,
2816 gen_helper_cvtsq2sd
2817 };
2818 #endif
2819
2820 static const SSEFunc_i_ep sse_op_table3bi[] = {
2821 gen_helper_cvttss2si,
2822 gen_helper_cvtss2si,
2823 gen_helper_cvttsd2si,
2824 gen_helper_cvtsd2si
2825 };
2826
2827 #ifdef TARGET_X86_64
2828 static const SSEFunc_l_ep sse_op_table3bq[] = {
2829 gen_helper_cvttss2sq,
2830 gen_helper_cvtss2sq,
2831 gen_helper_cvttsd2sq,
2832 gen_helper_cvtsd2sq
2833 };
2834 #endif
2835
2836 static const SSEFunc_0_epp sse_op_table4[8][4] = {
2837 SSE_FOP(cmpeq),
2838 SSE_FOP(cmplt),
2839 SSE_FOP(cmple),
2840 SSE_FOP(cmpunord),
2841 SSE_FOP(cmpneq),
2842 SSE_FOP(cmpnlt),
2843 SSE_FOP(cmpnle),
2844 SSE_FOP(cmpord),
2845 };
2846
2847 static const SSEFunc_0_epp sse_op_table5[256] = {
2848 [0x0c] = gen_helper_pi2fw,
2849 [0x0d] = gen_helper_pi2fd,
2850 [0x1c] = gen_helper_pf2iw,
2851 [0x1d] = gen_helper_pf2id,
2852 [0x8a] = gen_helper_pfnacc,
2853 [0x8e] = gen_helper_pfpnacc,
2854 [0x90] = gen_helper_pfcmpge,
2855 [0x94] = gen_helper_pfmin,
2856 [0x96] = gen_helper_pfrcp,
2857 [0x97] = gen_helper_pfrsqrt,
2858 [0x9a] = gen_helper_pfsub,
2859 [0x9e] = gen_helper_pfadd,
2860 [0xa0] = gen_helper_pfcmpgt,
2861 [0xa4] = gen_helper_pfmax,
2862 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
2863 [0xa7] = gen_helper_movq, /* pfrsqit1 */
2864 [0xaa] = gen_helper_pfsubr,
2865 [0xae] = gen_helper_pfacc,
2866 [0xb0] = gen_helper_pfcmpeq,
2867 [0xb4] = gen_helper_pfmul,
2868 [0xb6] = gen_helper_movq, /* pfrcpit2 */
2869 [0xb7] = gen_helper_pmulhrw_mmx,
2870 [0xbb] = gen_helper_pswapd,
2871 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
2872 };
2873
2874 struct SSEOpHelper_epp {
2875 SSEFunc_0_epp op[2];
2876 uint32_t ext_mask;
2877 };
2878
2879 struct SSEOpHelper_eppi {
2880 SSEFunc_0_eppi op[2];
2881 uint32_t ext_mask;
2882 };
2883
2884 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
2885 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
2886 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
2887 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
2888 #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
2889 CPUID_EXT_PCLMULQDQ }
2890 #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
2891
2892 static const struct SSEOpHelper_epp sse_op_table6[256] = {
2893 [0x00] = SSSE3_OP(pshufb),
2894 [0x01] = SSSE3_OP(phaddw),
2895 [0x02] = SSSE3_OP(phaddd),
2896 [0x03] = SSSE3_OP(phaddsw),
2897 [0x04] = SSSE3_OP(pmaddubsw),
2898 [0x05] = SSSE3_OP(phsubw),
2899 [0x06] = SSSE3_OP(phsubd),
2900 [0x07] = SSSE3_OP(phsubsw),
2901 [0x08] = SSSE3_OP(psignb),
2902 [0x09] = SSSE3_OP(psignw),
2903 [0x0a] = SSSE3_OP(psignd),
2904 [0x0b] = SSSE3_OP(pmulhrsw),
2905 [0x10] = SSE41_OP(pblendvb),
2906 [0x14] = SSE41_OP(blendvps),
2907 [0x15] = SSE41_OP(blendvpd),
2908 [0x17] = SSE41_OP(ptest),
2909 [0x1c] = SSSE3_OP(pabsb),
2910 [0x1d] = SSSE3_OP(pabsw),
2911 [0x1e] = SSSE3_OP(pabsd),
2912 [0x20] = SSE41_OP(pmovsxbw),
2913 [0x21] = SSE41_OP(pmovsxbd),
2914 [0x22] = SSE41_OP(pmovsxbq),
2915 [0x23] = SSE41_OP(pmovsxwd),
2916 [0x24] = SSE41_OP(pmovsxwq),
2917 [0x25] = SSE41_OP(pmovsxdq),
2918 [0x28] = SSE41_OP(pmuldq),
2919 [0x29] = SSE41_OP(pcmpeqq),
2920 [0x2a] = SSE41_SPECIAL, /* movntqda */
2921 [0x2b] = SSE41_OP(packusdw),
2922 [0x30] = SSE41_OP(pmovzxbw),
2923 [0x31] = SSE41_OP(pmovzxbd),
2924 [0x32] = SSE41_OP(pmovzxbq),
2925 [0x33] = SSE41_OP(pmovzxwd),
2926 [0x34] = SSE41_OP(pmovzxwq),
2927 [0x35] = SSE41_OP(pmovzxdq),
2928 [0x37] = SSE42_OP(pcmpgtq),
2929 [0x38] = SSE41_OP(pminsb),
2930 [0x39] = SSE41_OP(pminsd),
2931 [0x3a] = SSE41_OP(pminuw),
2932 [0x3b] = SSE41_OP(pminud),
2933 [0x3c] = SSE41_OP(pmaxsb),
2934 [0x3d] = SSE41_OP(pmaxsd),
2935 [0x3e] = SSE41_OP(pmaxuw),
2936 [0x3f] = SSE41_OP(pmaxud),
2937 [0x40] = SSE41_OP(pmulld),
2938 [0x41] = SSE41_OP(phminposuw),
2939 [0xdb] = AESNI_OP(aesimc),
2940 [0xdc] = AESNI_OP(aesenc),
2941 [0xdd] = AESNI_OP(aesenclast),
2942 [0xde] = AESNI_OP(aesdec),
2943 [0xdf] = AESNI_OP(aesdeclast),
2944 };
2945
2946 static const struct SSEOpHelper_eppi sse_op_table7[256] = {
2947 [0x08] = SSE41_OP(roundps),
2948 [0x09] = SSE41_OP(roundpd),
2949 [0x0a] = SSE41_OP(roundss),
2950 [0x0b] = SSE41_OP(roundsd),
2951 [0x0c] = SSE41_OP(blendps),
2952 [0x0d] = SSE41_OP(blendpd),
2953 [0x0e] = SSE41_OP(pblendw),
2954 [0x0f] = SSSE3_OP(palignr),
2955 [0x14] = SSE41_SPECIAL, /* pextrb */
2956 [0x15] = SSE41_SPECIAL, /* pextrw */
2957 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
2958 [0x17] = SSE41_SPECIAL, /* extractps */
2959 [0x20] = SSE41_SPECIAL, /* pinsrb */
2960 [0x21] = SSE41_SPECIAL, /* insertps */
2961 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
2962 [0x40] = SSE41_OP(dpps),
2963 [0x41] = SSE41_OP(dppd),
2964 [0x42] = SSE41_OP(mpsadbw),
2965 [0x44] = PCLMULQDQ_OP(pclmulqdq),
2966 [0x60] = SSE42_OP(pcmpestrm),
2967 [0x61] = SSE42_OP(pcmpestri),
2968 [0x62] = SSE42_OP(pcmpistrm),
2969 [0x63] = SSE42_OP(pcmpistri),
2970 [0xdf] = AESNI_OP(aeskeygenassist),
2971 };
2972
2973 static void gen_sse(CPUX86State *env, DisasContext *s, int b,
2974 target_ulong pc_start, int rex_r)
2975 {
2976 int b1, op1_offset, op2_offset, is_xmm, val;
2977 int modrm, mod, rm, reg;
2978 SSEFunc_0_epp sse_fn_epp;
2979 SSEFunc_0_eppi sse_fn_eppi;
2980 SSEFunc_0_ppi sse_fn_ppi;
2981 SSEFunc_0_eppt sse_fn_eppt;
2982 TCGMemOp ot;
2983
2984 b &= 0xff;
2985 if (s->prefix & PREFIX_DATA)
2986 b1 = 1;
2987 else if (s->prefix & PREFIX_REPZ)
2988 b1 = 2;
2989 else if (s->prefix & PREFIX_REPNZ)
2990 b1 = 3;
2991 else
2992 b1 = 0;
2993 sse_fn_epp = sse_op_table1[b][b1];
2994 if (!sse_fn_epp) {
2995 goto illegal_op;
2996 }
2997 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
2998 is_xmm = 1;
2999 } else {
3000 if (b1 == 0) {
3001 /* MMX case */
3002 is_xmm = 0;
3003 } else {
3004 is_xmm = 1;
3005 }
3006 }
3007 /* simple MMX/SSE operation */
3008 if (s->flags & HF_TS_MASK) {
3009 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3010 return;
3011 }
3012 if (s->flags & HF_EM_MASK) {
3013 illegal_op:
3014 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3015 return;
3016 }
3017 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3018 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3019 goto illegal_op;
3020 if (b == 0x0e) {
3021 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3022 goto illegal_op;
3023 /* femms */
3024 gen_helper_emms(cpu_env);
3025 return;
3026 }
3027 if (b == 0x77) {
3028 /* emms */
3029 gen_helper_emms(cpu_env);
3030 return;
3031 }
3032 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3033 the static cpu state) */
3034 if (!is_xmm) {
3035 gen_helper_enter_mmx(cpu_env);
3036 }
3037
3038 modrm = cpu_ldub_code(env, s->pc++);
3039 reg = ((modrm >> 3) & 7);
3040 if (is_xmm)
3041 reg |= rex_r;
3042 mod = (modrm >> 6) & 3;
3043 if (sse_fn_epp == SSE_SPECIAL) {
3044 b |= (b1 << 8);
3045 switch(b) {
3046 case 0x0e7: /* movntq */
3047 if (mod == 3)
3048 goto illegal_op;
3049 gen_lea_modrm(env, s, modrm);
3050 gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
3051 break;
3052 case 0x1e7: /* movntdq */
3053 case 0x02b: /* movntps */
3054 case 0x12b: /* movntps */
3055 if (mod == 3)
3056 goto illegal_op;
3057 gen_lea_modrm(env, s, modrm);
3058 gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
3059 break;
3060 case 0x3f0: /* lddqu */
3061 if (mod == 3)
3062 goto illegal_op;
3063 gen_lea_modrm(env, s, modrm);
3064 gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
3065 break;
3066 case 0x22b: /* movntss */
3067 case 0x32b: /* movntsd */
3068 if (mod == 3)
3069 goto illegal_op;
3070 gen_lea_modrm(env, s, modrm);
3071 if (b1 & 1) {
3072 gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
3073 } else {
3074 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3075 xmm_regs[reg].XMM_L(0)));
3076 gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
3077 }
3078 break;
3079 case 0x6e: /* movd mm, ea */
3080 #ifdef TARGET_X86_64
3081 if (s->dflag == MO_64) {
3082 gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
3083 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3084 } else
3085 #endif
3086 {
3087 gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
3088 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3089 offsetof(CPUX86State,fpregs[reg].mmx));
3090 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3091 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3092 }
3093 break;
3094 case 0x16e: /* movd xmm, ea */
3095 #ifdef TARGET_X86_64
3096 if (s->dflag == MO_64) {
3097 gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
3098 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3099 offsetof(CPUX86State,xmm_regs[reg]));
3100 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3101 } else
3102 #endif
3103 {
3104 gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
3105 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3106 offsetof(CPUX86State,xmm_regs[reg]));
3107 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3108 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3109 }
3110 break;
3111 case 0x6f: /* movq mm, ea */
3112 if (mod != 3) {
3113 gen_lea_modrm(env, s, modrm);
3114 gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
3115 } else {
3116 rm = (modrm & 7);
3117 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3118 offsetof(CPUX86State,fpregs[rm].mmx));
3119 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3120 offsetof(CPUX86State,fpregs[reg].mmx));
3121 }
3122 break;
3123 case 0x010: /* movups */
3124 case 0x110: /* movupd */
3125 case 0x028: /* movaps */
3126 case 0x128: /* movapd */
3127 case 0x16f: /* movdqa xmm, ea */
3128 case 0x26f: /* movdqu xmm, ea */
3129 if (mod != 3) {
3130 gen_lea_modrm(env, s, modrm);
3131 gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
3132 } else {
3133 rm = (modrm & 7) | REX_B(s);
3134 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3135 offsetof(CPUX86State,xmm_regs[rm]));
3136 }
3137 break;
3138 case 0x210: /* movss xmm, ea */
3139 if (mod != 3) {
3140 gen_lea_modrm(env, s, modrm);
3141 gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
3142 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3143 tcg_gen_movi_tl(cpu_T[0], 0);
3144 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3145 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3146 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3147 } else {
3148 rm = (modrm & 7) | REX_B(s);
3149 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3150 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3151 }
3152 break;
3153 case 0x310: /* movsd xmm, ea */
3154 if (mod != 3) {
3155 gen_lea_modrm(env, s, modrm);
3156 gen_ldq_env_A0(s, offsetof(CPUX86State,
3157 xmm_regs[reg].XMM_Q(0)));
3158 tcg_gen_movi_tl(cpu_T[0], 0);
3159 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3160 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3161 } else {
3162 rm = (modrm & 7) | REX_B(s);
3163 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3164 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3165 }
3166 break;
3167 case 0x012: /* movlps */
3168 case 0x112: /* movlpd */
3169 if (mod != 3) {
3170 gen_lea_modrm(env, s, modrm);
3171 gen_ldq_env_A0(s, offsetof(CPUX86State,
3172 xmm_regs[reg].XMM_Q(0)));
3173 } else {
3174 /* movhlps */
3175 rm = (modrm & 7) | REX_B(s);
3176 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3177 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3178 }
3179 break;
3180 case 0x212: /* movsldup */
3181 if (mod != 3) {
3182 gen_lea_modrm(env, s, modrm);
3183 gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
3184 } else {
3185 rm = (modrm & 7) | REX_B(s);
3186 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3187 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3188 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3189 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3190 }
3191 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3192 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3193 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3194 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3195 break;
3196 case 0x312: /* movddup */
3197 if (mod != 3) {
3198 gen_lea_modrm(env, s, modrm);
3199 gen_ldq_env_A0(s, offsetof(CPUX86State,
3200 xmm_regs[reg].XMM_Q(0)));
3201 } else {
3202 rm = (modrm & 7) | REX_B(s);
3203 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3204 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3205 }
3206 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3207 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3208 break;
3209 case 0x016: /* movhps */
3210 case 0x116: /* movhpd */
3211 if (mod != 3) {
3212 gen_lea_modrm(env, s, modrm);
3213 gen_ldq_env_A0(s, offsetof(CPUX86State,
3214 xmm_regs[reg].XMM_Q(1)));
3215 } else {
3216 /* movlhps */
3217 rm = (modrm & 7) | REX_B(s);
3218 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3219 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3220 }
3221 break;
3222 case 0x216: /* movshdup */
3223 if (mod != 3) {
3224 gen_lea_modrm(env, s, modrm);
3225 gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
3226 } else {
3227 rm = (modrm & 7) | REX_B(s);
3228 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3229 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3230 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3231 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3232 }
3233 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3234 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3235 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3236 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3237 break;
3238 case 0x178:
3239 case 0x378:
3240 {
3241 int bit_index, field_length;
3242
3243 if (b1 == 1 && reg != 0)
3244 goto illegal_op;
3245 field_length = cpu_ldub_code(env, s->pc++) & 0x3F;
3246 bit_index = cpu_ldub_code(env, s->pc++) & 0x3F;
3247 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3248 offsetof(CPUX86State,xmm_regs[reg]));
3249 if (b1 == 1)
3250 gen_helper_extrq_i(cpu_env, cpu_ptr0,
3251 tcg_const_i32(bit_index),
3252 tcg_const_i32(field_length));
3253 else
3254 gen_helper_insertq_i(cpu_env, cpu_ptr0,
3255 tcg_const_i32(bit_index),
3256 tcg_const_i32(field_length));
3257 }
3258 break;
3259 case 0x7e: /* movd ea, mm */
3260 #ifdef TARGET_X86_64
3261 if (s->dflag == MO_64) {
3262 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3263 offsetof(CPUX86State,fpregs[reg].mmx));
3264 gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
3265 } else
3266 #endif
3267 {
3268 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3269 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3270 gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
3271 }
3272 break;
3273 case 0x17e: /* movd ea, xmm */
3274 #ifdef TARGET_X86_64
3275 if (s->dflag == MO_64) {
3276 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3277 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3278 gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
3279 } else
3280 #endif
3281 {
3282 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3283 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3284 gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
3285 }
3286 break;
3287 case 0x27e: /* movq xmm, ea */
3288 if (mod != 3) {
3289 gen_lea_modrm(env, s, modrm);
3290 gen_ldq_env_A0(s, offsetof(CPUX86State,
3291 xmm_regs[reg].XMM_Q(0)));
3292 } else {
3293 rm = (modrm & 7) | REX_B(s);
3294 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3295 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3296 }
3297 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3298 break;
3299 case 0x7f: /* movq ea, mm */
3300 if (mod != 3) {
3301 gen_lea_modrm(env, s, modrm);
3302 gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
3303 } else {
3304 rm = (modrm & 7);
3305 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3306 offsetof(CPUX86State,fpregs[reg].mmx));
3307 }
3308 break;
3309 case 0x011: /* movups */
3310 case 0x111: /* movupd */
3311 case 0x029: /* movaps */
3312 case 0x129: /* movapd */
3313 case 0x17f: /* movdqa ea, xmm */
3314 case 0x27f: /* movdqu ea, xmm */
3315 if (mod != 3) {
3316 gen_lea_modrm(env, s, modrm);
3317 gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
3318 } else {
3319 rm = (modrm & 7) | REX_B(s);
3320 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3321 offsetof(CPUX86State,xmm_regs[reg]));
3322 }
3323 break;
3324 case 0x211: /* movss ea, xmm */
3325 if (mod != 3) {
3326 gen_lea_modrm(env, s, modrm);
3327 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3328 gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
3329 } else {
3330 rm = (modrm & 7) | REX_B(s);
3331 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3332 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3333 }
3334 break;
3335 case 0x311: /* movsd ea, xmm */
3336 if (mod != 3) {
3337 gen_lea_modrm(env, s, modrm);
3338 gen_stq_env_A0(s, offsetof(CPUX86State,
3339 xmm_regs[reg].XMM_Q(0)));
3340 } else {
3341 rm = (modrm & 7) | REX_B(s);
3342 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3343 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3344 }
3345 break;
3346 case 0x013: /* movlps */
3347 case 0x113: /* movlpd */
3348 if (mod != 3) {
3349 gen_lea_modrm(env, s, modrm);
3350 gen_stq_env_A0(s, offsetof(CPUX86State,
3351 xmm_regs[reg].XMM_Q(0)));
3352 } else {
3353 goto illegal_op;
3354 }
3355 break;
3356 case 0x017: /* movhps */
3357 case 0x117: /* movhpd */
3358 if (mod != 3) {
3359 gen_lea_modrm(env, s, modrm);
3360 gen_stq_env_A0(s, offsetof(CPUX86State,
3361 xmm_regs[reg].XMM_Q(1)));
3362 } else {
3363 goto illegal_op;
3364 }
3365 break;
3366 case 0x71: /* shift mm, im */
3367 case 0x72:
3368 case 0x73:
3369 case 0x171: /* shift xmm, im */
3370 case 0x172:
3371 case 0x173:
3372 if (b1 >= 2) {
3373 goto illegal_op;
3374 }
3375 val = cpu_ldub_code(env, s->pc++);
3376 if (is_xmm) {
3377 tcg_gen_movi_tl(cpu_T[0], val);
3378 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3379 tcg_gen_movi_tl(cpu_T[0], 0);
3380 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3381 op1_offset = offsetof(CPUX86State,xmm_t0);
3382 } else {
3383 tcg_gen_movi_tl(cpu_T[0], val);
3384 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3385 tcg_gen_movi_tl(cpu_T[0], 0);
3386 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3387 op1_offset = offsetof(CPUX86State,mmx_t0);
3388 }
3389 sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
3390 (((modrm >> 3)) & 7)][b1];
3391 if (!sse_fn_epp) {
3392 goto illegal_op;
3393 }
3394 if (is_xmm) {
3395 rm = (modrm & 7) | REX_B(s);
3396 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3397 } else {
3398 rm = (modrm & 7);
3399 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3400 }
3401 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3402 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3403 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3404 break;
3405 case 0x050: /* movmskps */
3406 rm = (modrm & 7) | REX_B(s);
3407 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3408 offsetof(CPUX86State,xmm_regs[rm]));
3409 gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3410 tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
3411 break;
3412 case 0x150: /* movmskpd */
3413 rm = (modrm & 7) | REX_B(s);
3414 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3415 offsetof(CPUX86State,xmm_regs[rm]));
3416 gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3417 tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
3418 break;
3419 case 0x02a: /* cvtpi2ps */
3420 case 0x12a: /* cvtpi2pd */
3421 gen_helper_enter_mmx(cpu_env);
3422 if (mod != 3) {
3423 gen_lea_modrm(env, s, modrm);
3424 op2_offset = offsetof(CPUX86State,mmx_t0);
3425 gen_ldq_env_A0(s, op2_offset);
3426 } else {
3427 rm = (modrm & 7);
3428 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3429 }
3430 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3431 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3432 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3433 switch(b >> 8) {
3434 case 0x0:
3435 gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1);
3436 break;
3437 default:
3438 case 0x1:
3439 gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1);
3440 break;
3441 }
3442 break;
3443 case 0x22a: /* cvtsi2ss */
3444 case 0x32a: /* cvtsi2sd */
3445 ot = mo_64_32(s->dflag);
3446 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3447 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3448 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3449 if (ot == MO_32) {
3450 SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];
3451 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3452 sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32);
3453 } else {
3454 #ifdef TARGET_X86_64
3455 SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1];
3456 sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]);
3457 #else
3458 goto illegal_op;
3459 #endif
3460 }
3461 break;
3462 case 0x02c: /* cvttps2pi */
3463 case 0x12c: /* cvttpd2pi */
3464 case 0x02d: /* cvtps2pi */
3465 case 0x12d: /* cvtpd2pi */
3466 gen_helper_enter_mmx(cpu_env);
3467 if (mod != 3) {
3468 gen_lea_modrm(env, s, modrm);
3469 op2_offset = offsetof(CPUX86State,xmm_t0);
3470 gen_ldo_env_A0(s, op2_offset);
3471 } else {
3472 rm = (modrm & 7) | REX_B(s);
3473 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3474 }
3475 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3476 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3477 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3478 switch(b) {
3479 case 0x02c:
3480 gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3481 break;
3482 case 0x12c:
3483 gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3484 break;
3485 case 0x02d:
3486 gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3487 break;
3488 case 0x12d:
3489 gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3490 break;
3491 }
3492 break;
3493 case 0x22c: /* cvttss2si */
3494 case 0x32c: /* cvttsd2si */
3495 case 0x22d: /* cvtss2si */
3496 case 0x32d: /* cvtsd2si */
3497 ot = mo_64_32(s->dflag);
3498 if (mod != 3) {
3499 gen_lea_modrm(env, s, modrm);
3500 if ((b >> 8) & 1) {
3501 gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
3502 } else {
3503 gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
3504 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3505 }
3506 op2_offset = offsetof(CPUX86State,xmm_t0);
3507 } else {
3508 rm = (modrm & 7) | REX_B(s);
3509 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3510 }
3511 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3512 if (ot == MO_32) {
3513 SSEFunc_i_ep sse_fn_i_ep =
3514 sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
3515 sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3516 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3517 } else {
3518 #ifdef TARGET_X86_64
3519 SSEFunc_l_ep sse_fn_l_ep =
3520 sse_op_table3bq[((b >> 7) & 2) | (b & 1)];
3521 sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0);
3522 #else
3523 goto illegal_op;
3524 #endif
3525 }
3526 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
3527 break;
3528 case 0xc4: /* pinsrw */
3529 case 0x1c4:
3530 s->rip_offset = 1;
3531 gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
3532 val = cpu_ldub_code(env, s->pc++);
3533 if (b1) {
3534 val &= 7;
3535 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3536 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3537 } else {
3538 val &= 3;
3539 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3540 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3541 }
3542 break;
3543 case 0xc5: /* pextrw */
3544 case 0x1c5:
3545 if (mod != 3)
3546 goto illegal_op;
3547 ot = mo_64_32(s->dflag);
3548 val = cpu_ldub_code(env, s->pc++);
3549 if (b1) {
3550 val &= 7;
3551 rm = (modrm & 7) | REX_B(s);
3552 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3553 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3554 } else {
3555 val &= 3;
3556 rm = (modrm & 7);
3557 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3558 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3559 }
3560 reg = ((modrm >> 3) & 7) | rex_r;
3561 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
3562 break;
3563 case 0x1d6: /* movq ea, xmm */
3564 if (mod != 3) {
3565 gen_lea_modrm(env, s, modrm);
3566 gen_stq_env_A0(s, offsetof(CPUX86State,
3567 xmm_regs[reg].XMM_Q(0)));
3568 } else {
3569 rm = (modrm & 7) | REX_B(s);
3570 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3571 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3572 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3573 }
3574 break;
3575 case 0x2d6: /* movq2dq */
3576 gen_helper_enter_mmx(cpu_env);
3577 rm = (modrm & 7);
3578 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3579 offsetof(CPUX86State,fpregs[rm].mmx));
3580 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3581 break;
3582 case 0x3d6: /* movdq2q */
3583 gen_helper_enter_mmx(cpu_env);
3584 rm = (modrm & 7) | REX_B(s);
3585 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3586 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3587 break;
3588 case 0xd7: /* pmovmskb */
3589 case 0x1d7:
3590 if (mod != 3)
3591 goto illegal_op;
3592 if (b1) {
3593 rm = (modrm & 7) | REX_B(s);
3594 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3595 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3596 } else {
3597 rm = (modrm & 7);
3598 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3599 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3600 }
3601 reg = ((modrm >> 3) & 7) | rex_r;
3602 tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
3603 break;
3604
3605 case 0x138:
3606 case 0x038:
3607 b = modrm;
3608 if ((b & 0xf0) == 0xf0) {
3609 goto do_0f_38_fx;
3610 }
3611 modrm = cpu_ldub_code(env, s->pc++);
3612 rm = modrm & 7;
3613 reg = ((modrm >> 3) & 7) | rex_r;
3614 mod = (modrm >> 6) & 3;
3615 if (b1 >= 2) {
3616 goto illegal_op;
3617 }
3618
3619 sse_fn_epp = sse_op_table6[b].op[b1];
3620 if (!sse_fn_epp) {
3621 goto illegal_op;
3622 }
3623 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3624 goto illegal_op;
3625
3626 if (b1) {
3627 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3628 if (mod == 3) {
3629 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3630 } else {
3631 op2_offset = offsetof(CPUX86State,xmm_t0);
3632 gen_lea_modrm(env, s, modrm);
3633 switch (b) {
3634 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3635 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3636 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3637 gen_ldq_env_A0(s, op2_offset +
3638 offsetof(XMMReg, XMM_Q(0)));
3639 break;
3640 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3641 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3642 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
3643 s->mem_index, MO_LEUL);
3644 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3645 offsetof(XMMReg, XMM_L(0)));
3646 break;
3647 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3648 tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0,
3649 s->mem_index, MO_LEUW);
3650 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3651 offsetof(XMMReg, XMM_W(0)));
3652 break;
3653 case 0x2a: /* movntqda */
3654 gen_ldo_env_A0(s, op1_offset);
3655 return;
3656 default:
3657 gen_ldo_env_A0(s, op2_offset);
3658 }
3659 }
3660 } else {
3661 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3662 if (mod == 3) {
3663 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3664 } else {
3665 op2_offset = offsetof(CPUX86State,mmx_t0);
3666 gen_lea_modrm(env, s, modrm);
3667 gen_ldq_env_A0(s, op2_offset);
3668 }
3669 }
3670 if (sse_fn_epp == SSE_SPECIAL) {
3671 goto illegal_op;
3672 }
3673
3674 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3675 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3676 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3677
3678 if (b == 0x17) {
3679 set_cc_op(s, CC_OP_EFLAGS);
3680 }
3681 break;
3682
3683 case 0x238:
3684 case 0x338:
3685 do_0f_38_fx:
3686 /* Various integer extensions at 0f 38 f[0-f]. */
3687 b = modrm | (b1 << 8);
3688 modrm = cpu_ldub_code(env, s->pc++);
3689 reg = ((modrm >> 3) & 7) | rex_r;
3690
3691 switch (b) {
3692 case 0x3f0: /* crc32 Gd,Eb */
3693 case 0x3f1: /* crc32 Gd,Ey */
3694 do_crc32:
3695 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) {
3696 goto illegal_op;
3697 }
3698 if ((b & 0xff) == 0xf0) {
3699 ot = MO_8;
3700 } else if (s->dflag != MO_64) {
3701 ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
3702 } else {
3703 ot = MO_64;
3704 }
3705
3706 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[reg]);
3707 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3708 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3709 cpu_T[0], tcg_const_i32(8 << ot));
3710
3711 ot = mo_64_32(s->dflag);
3712 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
3713 break;
3714
3715 case 0x1f0: /* crc32 or movbe */
3716 case 0x1f1:
3717 /* For these insns, the f3 prefix is supposed to have priority
3718 over the 66 prefix, but that's not what we implement above
3719 setting b1. */
3720 if (s->prefix & PREFIX_REPNZ) {
3721 goto do_crc32;
3722 }
3723 /* FALLTHRU */
3724 case 0x0f0: /* movbe Gy,My */
3725 case 0x0f1: /* movbe My,Gy */
3726 if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) {
3727 goto illegal_op;
3728 }
3729 if (s->dflag != MO_64) {
3730 ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
3731 } else {
3732 ot = MO_64;
3733 }
3734
3735 gen_lea_modrm(env, s, modrm);
3736 if ((b & 1) == 0) {
3737 tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
3738 s->mem_index, ot | MO_BE);
3739 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
3740 } else {
3741 tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0,
3742 s->mem_index, ot | MO_BE);
3743 }
3744 break;
3745
3746 case 0x0f2: /* andn Gy, By, Ey */
3747 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)
3748 || !(s->prefix & PREFIX_VEX)
3749 || s->vex_l != 0) {
3750 goto illegal_op;
3751 }
3752 ot = mo_64_32(s->dflag);
3753 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3754 tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
3755 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
3756 gen_op_update1_cc();
3757 set_cc_op(s, CC_OP_LOGICB + ot);
3758 break;
3759
3760 case 0x0f7: /* bextr Gy, Ey, By */
3761 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)
3762 || !(s->prefix & PREFIX_VEX)
3763 || s->vex_l != 0) {
3764 goto illegal_op;
3765 }
3766 ot = mo_64_32(s->dflag);
3767 {
3768 TCGv bound, zero;
3769
3770 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3771 /* Extract START, and shift the operand.
3772 Shifts larger than operand size get zeros. */
3773 tcg_gen_ext8u_tl(cpu_A0, cpu_regs[s->vex_v]);
3774 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_A0);
3775
3776 bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
3777 zero = tcg_const_tl(0);
3778 tcg_gen_movcond_tl(TCG_COND_LEU, cpu_T[0], cpu_A0, bound,
3779 cpu_T[0], zero);
3780 tcg_temp_free(zero);
3781
3782 /* Extract the LEN into a mask. Lengths larger than
3783 operand size get all ones. */
3784 tcg_gen_shri_tl(cpu_A0, cpu_regs[s->vex_v], 8);
3785 tcg_gen_ext8u_tl(cpu_A0, cpu_A0);
3786 tcg_gen_movcond_tl(TCG_COND_LEU, cpu_A0, cpu_A0, bound,
3787 cpu_A0, bound);
3788 tcg_temp_free(bound);
3789 tcg_gen_movi_tl(cpu_T[1], 1);
3790 tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_A0);
3791 tcg_gen_subi_tl(cpu_T[1], cpu_T[1], 1);
3792 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3793
3794 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
3795 gen_op_update1_cc();
3796 set_cc_op(s, CC_OP_LOGICB + ot);
3797 }
3798 break;
3799
3800 case 0x0f5: /* bzhi Gy, Ey, By */
3801 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
3802 || !(s->prefix & PREFIX_VEX)
3803 || s->vex_l != 0) {
3804 goto illegal_op;
3805 }
3806 ot = mo_64_32(s->dflag);
3807 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3808 tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]);
3809 {
3810 TCGv bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
3811 /* Note that since we're using BMILG (in order to get O
3812 cleared) we need to store the inverse into C. */
3813 tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src,
3814 cpu_T[1], bound);
3815 tcg_gen_movcond_tl(TCG_COND_GT, cpu_T[1], cpu_T[1],
3816 bound, bound, cpu_T[1]);
3817 tcg_temp_free(bound);
3818 }
3819 tcg_gen_movi_tl(cpu_A0, -1);
3820 tcg_gen_shl_tl(cpu_A0, cpu_A0, cpu_T[1]);
3821 tcg_gen_andc_tl(cpu_T[0], cpu_T[0], cpu_A0);
3822 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
3823 gen_op_update1_cc();
3824 set_cc_op(s, CC_OP_BMILGB + ot);
3825 break;
3826
3827 case 0x3f6: /* mulx By, Gy, rdx, Ey */
3828 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
3829 || !(s->prefix & PREFIX_VEX)
3830 || s->vex_l != 0) {
3831 goto illegal_op;
3832 }
3833 ot = mo_64_32(s->dflag);
3834 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3835 switch (ot) {
3836 default:
3837 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3838 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EDX]);
3839 tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
3840 cpu_tmp2_i32, cpu_tmp3_i32);
3841 tcg_gen_extu_i32_tl(cpu_regs[s->vex_v], cpu_tmp2_i32);
3842 tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp3_i32);
3843 break;
3844 #ifdef TARGET_X86_64
3845 case MO_64:
3846 tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg],
3847 cpu_T[0], cpu_regs[R_EDX]);
3848 break;
3849 #endif
3850 }
3851 break;
3852
3853 case 0x3f5: /* pdep Gy, By, Ey */
3854 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
3855 || !(s->prefix & PREFIX_VEX)
3856 || s->vex_l != 0) {
3857 goto illegal_op;
3858 }
3859 ot = mo_64_32(s->dflag);
3860 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3861 /* Note that by zero-extending the mask operand, we
3862 automatically handle zero-extending the result. */
3863 if (ot == MO_64) {
3864 tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
3865 } else {
3866 tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
3867 }
3868 gen_helper_pdep(cpu_regs[reg], cpu_T[0], cpu_T[1]);
3869 break;
3870
3871 case 0x2f5: /* pext Gy, By, Ey */
3872 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
3873 || !(s->prefix & PREFIX_VEX)
3874 || s->vex_l != 0) {
3875 goto illegal_op;
3876 }
3877 ot = mo_64_32(s->dflag);
3878 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3879 /* Note that by zero-extending the mask operand, we
3880 automatically handle zero-extending the result. */
3881 if (ot == MO_64) {
3882 tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
3883 } else {
3884 tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
3885 }
3886 gen_helper_pext(cpu_regs[reg], cpu_T[0], cpu_T[1]);
3887 break;
3888
3889 case 0x1f6: /* adcx Gy, Ey */
3890 case 0x2f6: /* adox Gy, Ey */
3891 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX)) {
3892 goto illegal_op;
3893 } else {
3894 TCGv carry_in, carry_out, zero;
3895 int end_op;
3896
3897 ot = mo_64_32(s->dflag);
3898 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3899
3900 /* Re-use the carry-out from a previous round. */
3901 TCGV_UNUSED(carry_in);
3902 carry_out = (b == 0x1f6 ? cpu_cc_dst : cpu_cc_src2);
3903 switch (s->cc_op) {
3904 case CC_OP_ADCX:
3905 if (b == 0x1f6) {
3906 carry_in = cpu_cc_dst;
3907 end_op = CC_OP_ADCX;
3908 } else {
3909 end_op = CC_OP_ADCOX;
3910 }
3911 break;
3912 case CC_OP_ADOX:
3913 if (b == 0x1f6) {
3914 end_op = CC_OP_ADCOX;
3915 } else {
3916 carry_in = cpu_cc_src2;
3917 end_op = CC_OP_ADOX;
3918 }
3919 break;
3920 case CC_OP_ADCOX:
3921 end_op = CC_OP_ADCOX;
3922 carry_in = carry_out;
3923 break;
3924 default:
3925 end_op = (b == 0x1f6 ? CC_OP_ADCX : CC_OP_ADOX);
3926 break;
3927 }
3928 /* If we can't reuse carry-out, get it out of EFLAGS. */
3929 if (TCGV_IS_UNUSED(carry_in)) {
3930 if (s->cc_op != CC_OP_ADCX && s->cc_op != CC_OP_ADOX) {
3931 gen_compute_eflags(s);
3932 }
3933 carry_in = cpu_tmp0;
3934 tcg_gen_shri_tl(carry_in, cpu_cc_src,
3935 ctz32(b == 0x1f6 ? CC_C : CC_O));
3936 tcg_gen_andi_tl(carry_in, carry_in, 1);
3937 }
3938
3939 switch (ot) {
3940 #ifdef TARGET_X86_64
3941 case MO_32:
3942 /* If we know TL is 64-bit, and we want a 32-bit
3943 result, just do everything in 64-bit arithmetic. */
3944 tcg_gen_ext32u_i64(cpu_regs[reg], cpu_regs[reg]);
3945 tcg_gen_ext32u_i64(cpu_T[0], cpu_T[0]);
3946 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_regs[reg]);
3947 tcg_gen_add_i64(cpu_T[0], cpu_T[0], carry_in);
3948 tcg_gen_ext32u_i64(cpu_regs[reg], cpu_T[0]);
3949 tcg_gen_shri_i64(carry_out, cpu_T[0], 32);
3950 break;
3951 #endif
3952 default:
3953 /* Otherwise compute the carry-out in two steps. */
3954 zero = tcg_const_tl(0);
3955 tcg_gen_add2_tl(cpu_T[0], carry_out,
3956 cpu_T[0], zero,
3957 carry_in, zero);
3958 tcg_gen_add2_tl(cpu_regs[reg], carry_out,
3959 cpu_regs[reg], carry_out,
3960 cpu_T[0], zero);
3961 tcg_temp_free(zero);
3962 break;
3963 }
3964 set_cc_op(s, end_op);
3965 }
3966 break;
3967
3968 case 0x1f7: /* shlx Gy, Ey, By */
3969 case 0x2f7: /* sarx Gy, Ey, By */
3970 case 0x3f7: /* shrx Gy, Ey, By */
3971 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
3972 || !(s->prefix & PREFIX_VEX)
3973 || s->vex_l != 0) {
3974 goto illegal_op;
3975 }
3976 ot = mo_64_32(s->dflag);
3977 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3978 if (ot == MO_64) {
3979 tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63);
3980 } else {
3981 tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 31);
3982 }
3983 if (b == 0x1f7) {
3984 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3985 } else if (b == 0x2f7) {
3986 if (ot != MO_64) {
3987 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
3988 }
3989 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3990 } else {
3991 if (ot != MO_64) {
3992 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
3993 }
3994 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3995 }
3996 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
3997 break;
3998
3999 case 0x0f3:
4000 case 0x1f3:
4001 case 0x2f3:
4002 case 0x3f3: /* Group 17 */
4003 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)
4004 || !(s->prefix & PREFIX_VEX)
4005 || s->vex_l != 0) {
4006 goto illegal_op;
4007 }
4008 ot = mo_64_32(s->dflag);
4009 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
4010
4011 switch (reg & 7) {
4012 case 1: /* blsr By,Ey */
4013 tcg_gen_neg_tl(cpu_T[1], cpu_T[0]);
4014 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4015 gen_op_mov_reg_v(ot, s->vex_v, cpu_T[0]);
4016 gen_op_update2_cc();
4017 set_cc_op(s, CC_OP_BMILGB + ot);
4018 break;
4019
4020 case 2: /* blsmsk By,Ey */
4021 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4022 tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1);
4023 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_cc_src);
4024 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4025 set_cc_op(s, CC_OP_BMILGB + ot);
4026 break;
4027
4028 case 3: /* blsi By, Ey */
4029 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4030 tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1);
4031 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_cc_src);
4032 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4033 set_cc_op(s, CC_OP_BMILGB + ot);
4034 break;
4035
4036 default:
4037 goto illegal_op;
4038 }
4039 break;
4040
4041 default:
4042 goto illegal_op;
4043 }
4044 break;
4045
4046 case 0x03a:
4047 case 0x13a:
4048 b = modrm;
4049 modrm = cpu_ldub_code(env, s->pc++);
4050 rm = modrm & 7;
4051 reg = ((modrm >> 3) & 7) | rex_r;
4052 mod = (modrm >> 6) & 3;
4053 if (b1 >= 2) {
4054 goto illegal_op;
4055 }
4056
4057 sse_fn_eppi = sse_op_table7[b].op[b1];
4058 if (!sse_fn_eppi) {
4059 goto illegal_op;
4060 }
4061 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
4062 goto illegal_op;
4063
4064 if (sse_fn_eppi == SSE_SPECIAL) {
4065 ot = mo_64_32(s->dflag);
4066 rm = (modrm & 7) | REX_B(s);
4067 if (mod != 3)
4068 gen_lea_modrm(env, s, modrm);
4069 reg = ((modrm >> 3) & 7) | rex_r;
4070 val = cpu_ldub_code(env, s->pc++);
4071 switch (b) {
4072 case 0x14: /* pextrb */
4073 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4074 xmm_regs[reg].XMM_B(val & 15)));
4075 if (mod == 3) {
4076 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
4077 } else {
4078 tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
4079 s->mem_index, MO_UB);
4080 }
4081 break;
4082 case 0x15: /* pextrw */
4083 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4084 xmm_regs[reg].XMM_W(val & 7)));
4085 if (mod == 3) {
4086 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
4087 } else {
4088 tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
4089 s->mem_index, MO_LEUW);
4090 }
4091 break;
4092 case 0x16:
4093 if (ot == MO_32) { /* pextrd */
4094 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
4095 offsetof(CPUX86State,
4096 xmm_regs[reg].XMM_L(val & 3)));
4097 if (mod == 3) {
4098 tcg_gen_extu_i32_tl(cpu_regs[rm], cpu_tmp2_i32);
4099 } else {
4100 tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
4101 s->mem_index, MO_LEUL);
4102 }
4103 } else { /* pextrq */
4104 #ifdef TARGET_X86_64
4105 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
4106 offsetof(CPUX86State,
4107 xmm_regs[reg].XMM_Q(val & 1)));
4108 if (mod == 3) {
4109 tcg_gen_mov_i64(cpu_regs[rm], cpu_tmp1_i64);
4110 } else {
4111 tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
4112 s->mem_index, MO_LEQ);
4113 }
4114 #else
4115 goto illegal_op;
4116 #endif
4117 }
4118 break;
4119 case 0x17: /* extractps */
4120 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4121 xmm_regs[reg].XMM_L(val & 3)));
4122 if (mod == 3) {
4123 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
4124 } else {
4125 tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
4126 s->mem_index, MO_LEUL);
4127 }
4128 break;
4129 case 0x20: /* pinsrb */
4130 if (mod == 3) {
4131 gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
4132 } else {
4133 tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
4134 s->mem_index, MO_UB);
4135 }
4136 tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4137 xmm_regs[reg].XMM_B(val & 15)));
4138 break;
4139 case 0x21: /* insertps */
4140 if (mod == 3) {
4141 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
4142 offsetof(CPUX86State,xmm_regs[rm]
4143 .XMM_L((val >> 6) & 3)));
4144 } else {
4145 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
4146 s->mem_index, MO_LEUL);
4147 }
4148 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4149 offsetof(CPUX86State,xmm_regs[reg]
4150 .XMM_L((val >> 4) & 3)));
4151 if ((val >> 0) & 1)
4152 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4153 cpu_env, offsetof(CPUX86State,
4154 xmm_regs[reg].XMM_L(0)));
4155 if ((val >> 1) & 1)
4156 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4157 cpu_env, offsetof(CPUX86State,
4158 xmm_regs[reg].XMM_L(1)));
4159 if ((val >> 2) & 1)
4160 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4161 cpu_env, offsetof(CPUX86State,
4162 xmm_regs[reg].XMM_L(2)));
4163 if ((val >> 3) & 1)
4164 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4165 cpu_env, offsetof(CPUX86State,
4166 xmm_regs[reg].XMM_L(3)));
4167 break;
4168 case 0x22:
4169 if (ot == MO_32) { /* pinsrd */
4170 if (mod == 3) {
4171 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[rm]);
4172 } else {
4173 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
4174 s->mem_index, MO_LEUL);
4175 }
4176 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4177 offsetof(CPUX86State,
4178 xmm_regs[reg].XMM_L(val & 3)));
4179 } else { /* pinsrq */
4180 #ifdef TARGET_X86_64
4181 if (mod == 3) {
4182 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
4183 } else {
4184 tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0,
4185 s->mem_index, MO_LEQ);
4186 }
4187 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
4188 offsetof(CPUX86State,
4189 xmm_regs[reg].XMM_Q(val & 1)));
4190 #else
4191 goto illegal_op;
4192 #endif
4193 }
4194 break;
4195 }
4196 return;
4197 }
4198
4199 if (b1) {
4200 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4201 if (mod == 3) {
4202 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
4203 } else {
4204 op2_offset = offsetof(CPUX86State,xmm_t0);
4205 gen_lea_modrm(env, s, modrm);
4206 gen_ldo_env_A0(s, op2_offset);
4207 }
4208 } else {
4209 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4210 if (mod == 3) {
4211 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4212 } else {
4213 op2_offset = offsetof(CPUX86State,mmx_t0);
4214 gen_lea_modrm(env, s, modrm);
4215 gen_ldq_env_A0(s, op2_offset);
4216 }
4217 }
4218 val = cpu_ldub_code(env, s->pc++);
4219
4220 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
4221 set_cc_op(s, CC_OP_EFLAGS);
4222
4223 if (s->dflag == MO_64) {
4224 /* The helper must use entire 64-bit gp registers */
4225 val |= 1 << 8;
4226 }
4227 }
4228
4229 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4230 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4231 sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4232 break;
4233
4234 case 0x33a:
4235 /* Various integer extensions at 0f 3a f[0-f]. */
4236 b = modrm | (b1 << 8);
4237 modrm = cpu_ldub_code(env, s->pc++);
4238 reg = ((modrm >> 3) & 7) | rex_r;
4239
4240 switch (b) {
4241 case 0x3f0: /* rorx Gy,Ey, Ib */
4242 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
4243 || !(s->prefix & PREFIX_VEX)
4244 || s->vex_l != 0) {
4245 goto illegal_op;
4246 }
4247 ot = mo_64_32(s->dflag);
4248 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
4249 b = cpu_ldub_code(env, s->pc++);
4250 if (ot == MO_64) {
4251 tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], b & 63);
4252 } else {
4253 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4254 tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, b & 31);
4255 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
4256 }
4257 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
4258 break;
4259
4260 default:
4261 goto illegal_op;
4262 }
4263 break;
4264
4265 default:
4266 goto illegal_op;
4267 }
4268 } else {
4269 /* generic MMX or SSE operation */
4270 switch(b) {
4271 case 0x70: /* pshufx insn */
4272 case 0xc6: /* pshufx insn */
4273 case 0xc2: /* compare insns */
4274 s->rip_offset = 1;
4275 break;
4276 default:
4277 break;
4278 }
4279 if (is_xmm) {
4280 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4281 if (mod != 3) {
4282 int sz = 4;
4283
4284 gen_lea_modrm(env, s, modrm);
4285 op2_offset = offsetof(CPUX86State,xmm_t0);
4286
4287 switch (b) {
4288 case 0x50 ... 0x5a:
4289 case 0x5c ... 0x5f:
4290 case 0xc2:
4291 /* Most sse scalar operations. */
4292 if (b1 == 2) {
4293 sz = 2;
4294 } else if (b1 == 3) {
4295 sz = 3;
4296 }
4297 break;
4298
4299 case 0x2e: /* ucomis[sd] */
4300 case 0x2f: /* comis[sd] */
4301 if (b1 == 0) {
4302 sz = 2;
4303 } else {
4304 sz = 3;
4305 }
4306 break;
4307 }
4308
4309 switch (sz) {
4310 case 2:
4311 /* 32 bit access */
4312 gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
4313 tcg_gen_st32_tl(cpu_T[0], cpu_env,
4314 offsetof(CPUX86State,xmm_t0.XMM_L(0)));
4315 break;
4316 case 3:
4317 /* 64 bit access */
4318 gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_D(0)));
4319 break;
4320 default:
4321 /* 128 bit access */
4322 gen_ldo_env_A0(s, op2_offset);
4323 break;
4324 }
4325 } else {
4326 rm = (modrm & 7) | REX_B(s);
4327 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4328 }
4329 } else {
4330 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4331 if (mod != 3) {
4332 gen_lea_modrm(env, s, modrm);
4333 op2_offset = offsetof(CPUX86State,mmx_t0);
4334 gen_ldq_env_A0(s, op2_offset);
4335 } else {
4336 rm = (modrm & 7);
4337 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4338 }
4339 }
4340 switch(b) {
4341 case 0x0f: /* 3DNow! data insns */
4342 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4343 goto illegal_op;
4344 val = cpu_ldub_code(env, s->pc++);
4345 sse_fn_epp = sse_op_table5[val];
4346 if (!sse_fn_epp) {
4347 goto illegal_op;
4348 }
4349 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4350 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4351 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4352 break;
4353 case 0x70: /* pshufx insn */
4354 case 0xc6: /* pshufx insn */
4355 val = cpu_ldub_code(env, s->pc++);
4356 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4357 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4358 /* XXX: introduce a new table? */
4359 sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp;
4360 sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4361 break;
4362 case 0xc2:
4363 /* compare insns */
4364 val = cpu_ldub_code(env, s->pc++);
4365 if (val >= 8)
4366 goto illegal_op;
4367 sse_fn_epp = sse_op_table4[val][b1];
4368
4369 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4370 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4371 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4372 break;
4373 case 0xf7:
4374 /* maskmov : we must prepare A0 */
4375 if (mod != 3)
4376 goto illegal_op;
4377 tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EDI]);
4378 gen_extu(s->aflag, cpu_A0);
4379 gen_add_A0_ds_seg(s);
4380
4381 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4382 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4383 /* XXX: introduce a new table? */
4384 sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp;
4385 sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0);
4386 break;
4387 default:
4388 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4389 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4390 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4391 break;
4392 }
4393 if (b == 0x2e || b == 0x2f) {
4394 set_cc_op(s, CC_OP_EFLAGS);
4395 }
4396 }
4397 }
4398
4399 /* convert one instruction. s->is_jmp is set if the translation must
4400 be stopped. Return the next pc value */
4401 static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
4402 target_ulong pc_start)
4403 {
4404 int b, prefixes;
4405 int shift;
4406 TCGMemOp ot, aflag, dflag;
4407 int modrm, reg, rm, mod, op, opreg, val;
4408 target_ulong next_eip, tval;
4409 int rex_w, rex_r;
4410
4411 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4412 tcg_gen_debug_insn_start(pc_start);
4413 }
4414 s->pc = pc_start;
4415 prefixes = 0;
4416 s->override = -1;
4417 rex_w = -1;
4418 rex_r = 0;
4419 #ifdef TARGET_X86_64
4420 s->rex_x = 0;
4421 s->rex_b = 0;
4422 x86_64_hregs = 0;
4423 #endif
4424 s->rip_offset = 0; /* for relative ip address */
4425 s->vex_l = 0;
4426 s->vex_v = 0;
4427 next_byte:
4428 b = cpu_ldub_code(env, s->pc);
4429 s->pc++;
4430 /* Collect prefixes. */
4431 switch (b) {
4432 case 0xf3:
4433 prefixes |= PREFIX_REPZ;
4434 goto next_byte;
4435 case 0xf2:
4436 prefixes |= PREFIX_REPNZ;
4437 goto next_byte;
4438 case 0xf0:
4439 prefixes |= PREFIX_LOCK;
4440 goto next_byte;
4441 case 0x2e:
4442 s->override = R_CS;
4443 goto next_byte;
4444 case 0x36:
4445 s->override = R_SS;
4446 goto next_byte;
4447 case 0x3e:
4448 s->override = R_DS;
4449 goto next_byte;
4450 case 0x26:
4451 s->override = R_ES;
4452 goto next_byte;
4453 case 0x64:
4454 s->override = R_FS;
4455 goto next_byte;
4456 case 0x65:
4457 s->override = R_GS;
4458 goto next_byte;
4459 case 0x66:
4460 prefixes |= PREFIX_DATA;
4461 goto next_byte;
4462 case 0x67:
4463 prefixes |= PREFIX_ADR;
4464 goto next_byte;
4465 #ifdef TARGET_X86_64
4466 case 0x40 ... 0x4f:
4467 if (CODE64(s)) {
4468 /* REX prefix */
4469 rex_w = (b >> 3) & 1;
4470 rex_r = (b & 0x4) << 1;
4471 s->rex_x = (b & 0x2) << 2;
4472 REX_B(s) = (b & 0x1) << 3;
4473 x86_64_hregs = 1; /* select uniform byte register addressing */
4474 goto next_byte;
4475 }
4476 break;
4477 #endif
4478 case 0xc5: /* 2-byte VEX */
4479 case 0xc4: /* 3-byte VEX */
4480 /* VEX prefixes cannot be used except in 32-bit mode.
4481 Otherwise the instruction is LES or LDS. */
4482 if (s->code32 && !s->vm86) {
4483 static const int pp_prefix[4] = {
4484 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
4485 };
4486 int vex3, vex2 = cpu_ldub_code(env, s->pc);
4487
4488 if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
4489 /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
4490 otherwise the instruction is LES or LDS. */
4491 break;
4492 }
4493 s->pc++;
4494
4495 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
4496 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ
4497 | PREFIX_LOCK | PREFIX_DATA)) {
4498 goto illegal_op;
4499 }
4500 #ifdef TARGET_X86_64
4501 if (x86_64_hregs) {
4502 goto illegal_op;
4503 }
4504 #endif
4505 rex_r = (~vex2 >> 4) & 8;
4506 if (b == 0xc5) {
4507 vex3 = vex2;
4508 b = cpu_ldub_code(env, s->pc++);
4509 } else {
4510 #ifdef TARGET_X86_64
4511 s->rex_x = (~vex2 >> 3) & 8;
4512 s->rex_b = (~vex2 >> 2) & 8;
4513 #endif
4514 vex3 = cpu_ldub_code(env, s->pc++);
4515 rex_w = (vex3 >> 7) & 1;
4516 switch (vex2 & 0x1f) {
4517 case 0x01: /* Implied 0f leading opcode bytes. */
4518 b = cpu_ldub_code(env, s->pc++) | 0x100;
4519 break;
4520 case 0x02: /* Implied 0f 38 leading opcode bytes. */
4521 b = 0x138;
4522 break;
4523 case 0x03: /* Implied 0f 3a leading opcode bytes. */
4524 b = 0x13a;
4525 break;
4526 default: /* Reserved for future use. */
4527 goto illegal_op;
4528 }
4529 }
4530 s->vex_v = (~vex3 >> 3) & 0xf;
4531 s->vex_l = (vex3 >> 2) & 1;
4532 prefixes |= pp_prefix[vex3 & 3] | PREFIX_VEX;
4533 }
4534 break;
4535 }
4536
4537 /* Post-process prefixes. */
4538 if (CODE64(s)) {
4539 /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
4540 data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
4541 over 0x66 if both are present. */
4542 dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32);
4543 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
4544 aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);
4545 } else {
4546 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
4547 if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {
4548 dflag = MO_32;
4549 } else {
4550 dflag = MO_16;
4551 }
4552 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
4553 if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {
4554 aflag = MO_32;
4555 } else {
4556 aflag = MO_16;
4557 }
4558 }
4559
4560 s->prefix = prefixes;
4561 s->aflag = aflag;
4562 s->dflag = dflag;
4563
4564 /* lock generation */
4565 if (prefixes & PREFIX_LOCK)
4566 gen_helper_lock();
4567
4568 /* now check op code */
4569 reswitch:
4570 switch(b) {
4571 case 0x0f:
4572 /**************************/
4573 /* extended op code */
4574 b = cpu_ldub_code(env, s->pc++) | 0x100;
4575 goto reswitch;
4576
4577 /**************************/
4578 /* arith & logic */
4579 case 0x00 ... 0x05:
4580 case 0x08 ... 0x0d:
4581 case 0x10 ... 0x15:
4582 case 0x18 ... 0x1d:
4583 case 0x20 ... 0x25:
4584 case 0x28 ... 0x2d:
4585 case 0x30 ... 0x35:
4586 case 0x38 ... 0x3d:
4587 {
4588 int op, f, val;
4589 op = (b >> 3) & 7;
4590 f = (b >> 1) & 3;
4591
4592 ot = mo_b_d(b, dflag);
4593
4594 switch(f) {
4595 case 0: /* OP Ev, Gv */
4596 modrm = cpu_ldub_code(env, s->pc++);
4597 reg = ((modrm >> 3) & 7) | rex_r;
4598 mod = (modrm >> 6) & 3;
4599 rm = (modrm & 7) | REX_B(s);
4600 if (mod != 3) {
4601 gen_lea_modrm(env, s, modrm);
4602 opreg = OR_TMP0;
4603 } else if (op == OP_XORL && rm == reg) {
4604 xor_zero:
4605 /* xor reg, reg optimisation */
4606 set_cc_op(s, CC_OP_CLR);
4607 tcg_gen_movi_tl(cpu_T[0], 0);
4608 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
4609 break;
4610 } else {
4611 opreg = rm;
4612 }
4613 gen_op_mov_v_reg(ot, cpu_T[1], reg);
4614 gen_op(s, op, ot, opreg);
4615 break;
4616 case 1: /* OP Gv, Ev */
4617 modrm = cpu_ldub_code(env, s->pc++);
4618 mod = (modrm >> 6) & 3;
4619 reg = ((modrm >> 3) & 7) | rex_r;
4620 rm = (modrm & 7) | REX_B(s);
4621 if (mod != 3) {
4622 gen_lea_modrm(env, s, modrm);
4623 gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
4624 } else if (op == OP_XORL && rm == reg) {
4625 goto xor_zero;
4626 } else {
4627 gen_op_mov_v_reg(ot, cpu_T[1], rm);
4628 }
4629 gen_op(s, op, ot, reg);
4630 break;
4631 case 2: /* OP A, Iv */
4632 val = insn_get(env, s, ot);
4633 tcg_gen_movi_tl(cpu_T[1], val);
4634 gen_op(s, op, ot, OR_EAX);
4635 break;
4636 }
4637 }
4638 break;
4639
4640 case 0x82:
4641 if (CODE64(s))
4642 goto illegal_op;
4643 case 0x80: /* GRP1 */
4644 case 0x81:
4645 case 0x83:
4646 {
4647 int val;
4648
4649 ot = mo_b_d(b, dflag);
4650
4651 modrm = cpu_ldub_code(env, s->pc++);
4652 mod = (modrm >> 6) & 3;
4653 rm = (modrm & 7) | REX_B(s);
4654 op = (modrm >> 3) & 7;
4655
4656 if (mod != 3) {
4657 if (b == 0x83)
4658 s->rip_offset = 1;
4659 else
4660 s->rip_offset = insn_const_size(ot);
4661 gen_lea_modrm(env, s, modrm);
4662 opreg = OR_TMP0;
4663 } else {
4664 opreg = rm;
4665 }
4666
4667 switch(b) {
4668 default:
4669 case 0x80:
4670 case 0x81:
4671 case 0x82:
4672 val = insn_get(env, s, ot);
4673 break;
4674 case 0x83:
4675 val = (int8_t)insn_get(env, s, MO_8);
4676 break;
4677 }
4678 tcg_gen_movi_tl(cpu_T[1], val);
4679 gen_op(s, op, ot, opreg);
4680 }
4681 break;
4682
4683 /**************************/
4684 /* inc, dec, and other misc arith */
4685 case 0x40 ... 0x47: /* inc Gv */
4686 ot = dflag;
4687 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4688 break;
4689 case 0x48 ... 0x4f: /* dec Gv */
4690 ot = dflag;
4691 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4692 break;
4693 case 0xf6: /* GRP3 */
4694 case 0xf7:
4695 ot = mo_b_d(b, dflag);
4696
4697 modrm = cpu_ldub_code(env, s->pc++);
4698 mod = (modrm >> 6) & 3;
4699 rm = (modrm & 7) | REX_B(s);
4700 op = (modrm >> 3) & 7;
4701 if (mod != 3) {
4702 if (op == 0)
4703 s->rip_offset = insn_const_size(ot);
4704 gen_lea_modrm(env, s, modrm);
4705 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
4706 } else {
4707 gen_op_mov_v_reg(ot, cpu_T[0], rm);
4708 }
4709
4710 switch(op) {
4711 case 0: /* test */
4712 val = insn_get(env, s, ot);
4713 tcg_gen_movi_tl(cpu_T[1], val);
4714 gen_op_testl_T0_T1_cc();
4715 set_cc_op(s, CC_OP_LOGICB + ot);
4716 break;
4717 case 2: /* not */
4718 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4719 if (mod != 3) {
4720 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
4721 } else {
4722 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
4723 }
4724 break;
4725 case 3: /* neg */
4726 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4727 if (mod != 3) {
4728 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
4729 } else {
4730 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
4731 }
4732 gen_op_update_neg_cc();
4733 set_cc_op(s, CC_OP_SUBB + ot);
4734 break;
4735 case 4: /* mul */
4736 switch(ot) {
4737 case MO_8:
4738 gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
4739 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4740 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4741 /* XXX: use 32 bit mul which could be faster */
4742 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4743 gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
4744 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4745 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4746 set_cc_op(s, CC_OP_MULB);
4747 break;
4748 case MO_16:
4749 gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
4750 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4751 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4752 /* XXX: use 32 bit mul which could be faster */
4753 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4754 gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
4755 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4756 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4757 gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
4758 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4759 set_cc_op(s, CC_OP_MULW);
4760 break;
4761 default:
4762 case MO_32:
4763 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4764 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
4765 tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
4766 cpu_tmp2_i32, cpu_tmp3_i32);
4767 tcg_gen_extu_i32_tl(cpu_regs[R_EAX], cpu_tmp2_i32);
4768 tcg_gen_extu_i32_tl(cpu_regs[R_EDX], cpu_tmp3_i32);
4769 tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
4770 tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]);
4771 set_cc_op(s, CC_OP_MULL);
4772 break;
4773 #ifdef TARGET_X86_64
4774 case MO_64:
4775 tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
4776 cpu_T[0], cpu_regs[R_EAX]);
4777 tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
4778 tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]);
4779 set_cc_op(s, CC_OP_MULQ);
4780 break;
4781 #endif
4782 }
4783 break;
4784 case 5: /* imul */
4785 switch(ot) {
4786 case MO_8:
4787 gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
4788 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4789 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4790 /* XXX: use 32 bit mul which could be faster */
4791 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4792 gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
4793 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4794 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4795 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4796 set_cc_op(s, CC_OP_MULB);
4797 break;
4798 case MO_16:
4799 gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
4800 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4801 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4802 /* XXX: use 32 bit mul which could be faster */
4803 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4804 gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
4805 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4806 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4807 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4808 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4809 gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
4810 set_cc_op(s, CC_OP_MULW);
4811 break;
4812 default:
4813 case MO_32:
4814 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4815 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
4816 tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
4817 cpu_tmp2_i32, cpu_tmp3_i32);
4818 tcg_gen_extu_i32_tl(cpu_regs[R_EAX], cpu_tmp2_i32);
4819 tcg_gen_extu_i32_tl(cpu_regs[R_EDX], cpu_tmp3_i32);
4820 tcg_gen_sari_i32(cpu_tmp2_i32, cpu_tmp2_i32, 31);
4821 tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
4822 tcg_gen_sub_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
4823 tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32);
4824 set_cc_op(s, CC_OP_MULL);
4825 break;
4826 #ifdef TARGET_X86_64
4827 case MO_64:
4828 tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
4829 cpu_T[0], cpu_regs[R_EAX]);
4830 tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
4831 tcg_gen_sari_tl(cpu_cc_src, cpu_regs[R_EAX], 63);
4832 tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_regs[R_EDX]);
4833 set_cc_op(s, CC_OP_MULQ);
4834 break;
4835 #endif
4836 }
4837 break;
4838 case 6: /* div */
4839 switch(ot) {
4840 case MO_8:
4841 gen_jmp_im(pc_start - s->cs_base);
4842 gen_helper_divb_AL(cpu_env, cpu_T[0]);
4843 break;
4844 case MO_16:
4845 gen_jmp_im(pc_start - s->cs_base);
4846 gen_helper_divw_AX(cpu_env, cpu_T[0]);
4847 break;
4848 default:
4849 case MO_32:
4850 gen_jmp_im(pc_start - s->cs_base);
4851 gen_helper_divl_EAX(cpu_env, cpu_T[0]);
4852 break;
4853 #ifdef TARGET_X86_64
4854 case MO_64:
4855 gen_jmp_im(pc_start - s->cs_base);
4856 gen_helper_divq_EAX(cpu_env, cpu_T[0]);
4857 break;
4858 #endif
4859 }
4860 break;
4861 case 7: /* idiv */
4862 switch(ot) {
4863 case MO_8:
4864 gen_jmp_im(pc_start - s->cs_base);
4865 gen_helper_idivb_AL(cpu_env, cpu_T[0]);
4866 break;
4867 case MO_16:
4868 gen_jmp_im(pc_start - s->cs_base);
4869 gen_helper_idivw_AX(cpu_env, cpu_T[0]);
4870 break;
4871 default:
4872 case MO_32:
4873 gen_jmp_im(pc_start - s->cs_base);
4874 gen_helper_idivl_EAX(cpu_env, cpu_T[0]);
4875 break;
4876 #ifdef TARGET_X86_64
4877 case MO_64:
4878 gen_jmp_im(pc_start - s->cs_base);
4879 gen_helper_idivq_EAX(cpu_env, cpu_T[0]);
4880 break;
4881 #endif
4882 }
4883 break;
4884 default:
4885 goto illegal_op;
4886 }
4887 break;
4888
4889 case 0xfe: /* GRP4 */
4890 case 0xff: /* GRP5 */
4891 ot = mo_b_d(b, dflag);
4892
4893 modrm = cpu_ldub_code(env, s->pc++);
4894 mod = (modrm >> 6) & 3;
4895 rm = (modrm & 7) | REX_B(s);
4896 op = (modrm >> 3) & 7;
4897 if (op >= 2 && b == 0xfe) {
4898 goto illegal_op;
4899 }
4900 if (CODE64(s)) {
4901 if (op == 2 || op == 4) {
4902 /* operand size for jumps is 64 bit */
4903 ot = MO_64;
4904 } else if (op == 3 || op == 5) {
4905 ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16;
4906 } else if (op == 6) {
4907 /* default push size is 64 bit */
4908 ot = mo_pushpop(s, dflag);
4909 }
4910 }
4911 if (mod != 3) {
4912 gen_lea_modrm(env, s, modrm);
4913 if (op >= 2 && op != 3 && op != 5)
4914 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
4915 } else {
4916 gen_op_mov_v_reg(ot, cpu_T[0], rm);
4917 }
4918
4919 switch(op) {
4920 case 0: /* inc Ev */
4921 if (mod != 3)
4922 opreg = OR_TMP0;
4923 else
4924 opreg = rm;
4925 gen_inc(s, ot, opreg, 1);
4926 break;
4927 case 1: /* dec Ev */
4928 if (mod != 3)
4929 opreg = OR_TMP0;
4930 else
4931 opreg = rm;
4932 gen_inc(s, ot, opreg, -1);
4933 break;
4934 case 2: /* call Ev */
4935 /* XXX: optimize if memory (no 'and' is necessary) */
4936 if (dflag == MO_16) {
4937 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4938 }
4939 next_eip = s->pc - s->cs_base;
4940 tcg_gen_movi_tl(cpu_T[1], next_eip);
4941 gen_push_v(s, cpu_T[1]);
4942 gen_op_jmp_v(cpu_T[0]);
4943 gen_eob(s);
4944 break;
4945 case 3: /* lcall Ev */
4946 gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
4947 gen_add_A0_im(s, 1 << ot);
4948 gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
4949 do_lcall:
4950 if (s->pe && !s->vm86) {
4951 gen_update_cc_op(s);
4952 gen_jmp_im(pc_start - s->cs_base);
4953 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4954 gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
4955 tcg_const_i32(dflag - 1),
4956 tcg_const_i32(s->pc - pc_start));
4957 } else {
4958 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4959 gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1],
4960 tcg_const_i32(dflag - 1),
4961 tcg_const_i32(s->pc - s->cs_base));
4962 }
4963 gen_eob(s);
4964 break;
4965 case 4: /* jmp Ev */
4966 if (dflag == MO_16) {
4967 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4968 }
4969 gen_op_jmp_v(cpu_T[0]);
4970 gen_eob(s);
4971 break;
4972 case 5: /* ljmp Ev */
4973 gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
4974 gen_add_A0_im(s, 1 << ot);
4975 gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
4976 do_ljmp:
4977 if (s->pe && !s->vm86) {
4978 gen_update_cc_op(s);
4979 gen_jmp_im(pc_start - s->cs_base);
4980 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4981 gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
4982 tcg_const_i32(s->pc - pc_start));
4983 } else {
4984 gen_op_movl_seg_T0_vm(R_CS);
4985 gen_op_jmp_v(cpu_T[1]);
4986 }
4987 gen_eob(s);
4988 break;
4989 case 6: /* push Ev */
4990 gen_push_v(s, cpu_T[0]);
4991 break;
4992 default:
4993 goto illegal_op;
4994 }
4995 break;
4996
4997 case 0x84: /* test Ev, Gv */
4998 case 0x85:
4999 ot = mo_b_d(b, dflag);
5000
5001 modrm = cpu_ldub_code(env, s->pc++);
5002 reg = ((modrm >> 3) & 7) | rex_r;
5003
5004 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
5005 gen_op_mov_v_reg(ot, cpu_T[1], reg);
5006 gen_op_testl_T0_T1_cc();
5007 set_cc_op(s, CC_OP_LOGICB + ot);
5008 break;
5009
5010 case 0xa8: /* test eAX, Iv */
5011 case 0xa9:
5012 ot = mo_b_d(b, dflag);
5013 val = insn_get(env, s, ot);
5014
5015 gen_op_mov_v_reg(ot, cpu_T[0], OR_EAX);
5016 tcg_gen_movi_tl(cpu_T[1], val);
5017 gen_op_testl_T0_T1_cc();
5018 set_cc_op(s, CC_OP_LOGICB + ot);
5019 break;
5020
5021 case 0x98: /* CWDE/CBW */
5022 switch (dflag) {
5023 #ifdef TARGET_X86_64
5024 case MO_64:
5025 gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
5026 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
5027 gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]);
5028 break;
5029 #endif
5030 case MO_32:
5031 gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
5032 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5033 gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]);
5034 break;
5035 case MO_16:
5036 gen_op_mov_v_reg(MO_8, cpu_T[0], R_EAX);
5037 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5038 gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
5039 break;
5040 default:
5041 tcg_abort();
5042 }
5043 break;
5044 case 0x99: /* CDQ/CWD */
5045 switch (dflag) {
5046 #ifdef TARGET_X86_64
5047 case MO_64:
5048 gen_op_mov_v_reg(MO_64, cpu_T[0], R_EAX);
5049 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
5050 gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]);
5051 break;
5052 #endif
5053 case MO_32:
5054 gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
5055 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
5056 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
5057 gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]);
5058 break;
5059 case MO_16:
5060 gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
5061 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5062 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
5063 gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
5064 break;
5065 default:
5066 tcg_abort();
5067 }
5068 break;
5069 case 0x1af: /* imul Gv, Ev */
5070 case 0x69: /* imul Gv, Ev, I */
5071 case 0x6b:
5072 ot = dflag;
5073 modrm = cpu_ldub_code(env, s->pc++);
5074 reg = ((modrm >> 3) & 7) | rex_r;
5075 if (b == 0x69)
5076 s->rip_offset = insn_const_size(ot);
5077 else if (b == 0x6b)
5078 s->rip_offset = 1;
5079 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
5080 if (b == 0x69) {
5081 val = insn_get(env, s, ot);
5082 tcg_gen_movi_tl(cpu_T[1], val);
5083 } else if (b == 0x6b) {
5084 val = (int8_t)insn_get(env, s, MO_8);
5085 tcg_gen_movi_tl(cpu_T[1], val);
5086 } else {
5087 gen_op_mov_v_reg(ot, cpu_T[1], reg);
5088 }
5089 switch (ot) {
5090 #ifdef TARGET_X86_64
5091 case MO_64:
5092 tcg_gen_muls2_i64(cpu_regs[reg], cpu_T[1], cpu_T[0], cpu_T[1]);
5093 tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
5094 tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63);
5095 tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_T[1]);
5096 break;
5097 #endif
5098 case MO_32:
5099 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5100 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5101 tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
5102 cpu_tmp2_i32, cpu_tmp3_i32);
5103 tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
5104 tcg_gen_sari_i32(cpu_tmp2_i32, cpu_tmp2_i32, 31);
5105 tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
5106 tcg_gen_sub_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
5107 tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32);
5108 break;
5109 default:
5110 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5111 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
5112 /* XXX: use 32 bit mul which could be faster */
5113 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5114 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
5115 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
5116 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
5117 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
5118 break;
5119 }
5120 set_cc_op(s, CC_OP_MULB + ot);
5121 break;
5122 case 0x1c0:
5123 case 0x1c1: /* xadd Ev, Gv */
5124 ot = mo_b_d(b, dflag);
5125 modrm = cpu_ldub_code(env, s->pc++);
5126 reg = ((modrm >> 3) & 7) | rex_r;
5127 mod = (modrm >> 6) & 3;
5128 if (mod == 3) {
5129 rm = (modrm & 7) | REX_B(s);
5130 gen_op_mov_v_reg(ot, cpu_T[0], reg);
5131 gen_op_mov_v_reg(ot, cpu_T[1], rm);
5132 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5133 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
5134 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
5135 } else {
5136 gen_lea_modrm(env, s, modrm);
5137 gen_op_mov_v_reg(ot, cpu_T[0], reg);
5138 gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
5139 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5140 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
5141 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
5142 }
5143 gen_op_update2_cc();
5144 set_cc_op(s, CC_OP_ADDB + ot);
5145 break;
5146 case 0x1b0:
5147 case 0x1b1: /* cmpxchg Ev, Gv */
5148 {
5149 int label1, label2;
5150 TCGv t0, t1, t2, a0;
5151
5152 ot = mo_b_d(b, dflag);
5153 modrm = cpu_ldub_code(env, s->pc++);
5154 reg = ((modrm >> 3) & 7) | rex_r;
5155 mod = (modrm >> 6) & 3;
5156 t0 = tcg_temp_local_new();
5157 t1 = tcg_temp_local_new();
5158 t2 = tcg_temp_local_new();
5159 a0 = tcg_temp_local_new();
5160 gen_op_mov_v_reg(ot, t1, reg);
5161 if (mod == 3) {
5162 rm = (modrm & 7) | REX_B(s);
5163 gen_op_mov_v_reg(ot, t0, rm);
5164 } else {
5165 gen_lea_modrm(env, s, modrm);
5166 tcg_gen_mov_tl(a0, cpu_A0);
5167 gen_op_ld_v(s, ot, t0, a0);
5168 rm = 0; /* avoid warning */
5169 }
5170 label1 = gen_new_label();
5171 tcg_gen_mov_tl(t2, cpu_regs[R_EAX]);
5172 gen_extu(ot, t0);
5173 gen_extu(ot, t2);
5174 tcg_gen_brcond_tl(TCG_COND_EQ, t2, t0, label1);
5175 label2 = gen_new_label();
5176 if (mod == 3) {
5177 gen_op_mov_reg_v(ot, R_EAX, t0);
5178 tcg_gen_br(label2);
5179 gen_set_label(label1);
5180 gen_op_mov_reg_v(ot, rm, t1);
5181 } else {
5182 /* perform no-op store cycle like physical cpu; must be
5183 before changing accumulator to ensure idempotency if
5184 the store faults and the instruction is restarted */
5185 gen_op_st_v(s, ot, t0, a0);
5186 gen_op_mov_reg_v(ot, R_EAX, t0);
5187 tcg_gen_br(label2);
5188 gen_set_label(label1);
5189 gen_op_st_v(s, ot, t1, a0);
5190 }
5191 gen_set_label(label2);
5192 tcg_gen_mov_tl(cpu_cc_src, t0);
5193 tcg_gen_mov_tl(cpu_cc_srcT, t2);
5194 tcg_gen_sub_tl(cpu_cc_dst, t2, t0);
5195 set_cc_op(s, CC_OP_SUBB + ot);
5196 tcg_temp_free(t0);
5197 tcg_temp_free(t1);
5198 tcg_temp_free(t2);
5199 tcg_temp_free(a0);
5200 }
5201 break;
5202 case 0x1c7: /* cmpxchg8b */
5203 modrm = cpu_ldub_code(env, s->pc++);
5204 mod = (modrm >> 6) & 3;
5205 if ((mod == 3) || ((modrm & 0x38) != 0x8))
5206 goto illegal_op;
5207 #ifdef TARGET_X86_64
5208 if (dflag == MO_64) {
5209 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
5210 goto illegal_op;
5211 gen_jmp_im(pc_start - s->cs_base);
5212 gen_update_cc_op(s);
5213 gen_lea_modrm(env, s, modrm);
5214 gen_helper_cmpxchg16b(cpu_env, cpu_A0);
5215 } else
5216 #endif
5217 {
5218 if (!(s->cpuid_features & CPUID_CX8))
5219 goto illegal_op;
5220 gen_jmp_im(pc_start - s->cs_base);
5221 gen_update_cc_op(s);
5222 gen_lea_modrm(env, s, modrm);
5223 gen_helper_cmpxchg8b(cpu_env, cpu_A0);
5224 }
5225 set_cc_op(s, CC_OP_EFLAGS);
5226 break;
5227
5228 /**************************/
5229 /* push/pop */
5230 case 0x50 ... 0x57: /* push */
5231 gen_op_mov_v_reg(MO_32, cpu_T[0], (b & 7) | REX_B(s));
5232 gen_push_v(s, cpu_T[0]);
5233 break;
5234 case 0x58 ... 0x5f: /* pop */
5235 ot = gen_pop_T0(s);
5236 /* NOTE: order is important for pop %sp */
5237 gen_pop_update(s, ot);
5238 gen_op_mov_reg_v(ot, (b & 7) | REX_B(s), cpu_T[0]);
5239 break;
5240 case 0x60: /* pusha */
5241 if (CODE64(s))
5242 goto illegal_op;
5243 gen_pusha(s);
5244 break;
5245 case 0x61: /* popa */
5246 if (CODE64(s))
5247 goto illegal_op;
5248 gen_popa(s);
5249 break;
5250 case 0x68: /* push Iv */
5251 case 0x6a:
5252 ot = mo_pushpop(s, dflag);
5253 if (b == 0x68)
5254 val = insn_get(env, s, ot);
5255 else
5256 val = (int8_t)insn_get(env, s, MO_8);
5257 tcg_gen_movi_tl(cpu_T[0], val);
5258 gen_push_v(s, cpu_T[0]);
5259 break;
5260 case 0x8f: /* pop Ev */
5261 modrm = cpu_ldub_code(env, s->pc++);
5262 mod = (modrm >> 6) & 3;
5263 ot = gen_pop_T0(s);
5264 if (mod == 3) {
5265 /* NOTE: order is important for pop %sp */
5266 gen_pop_update(s, ot);
5267 rm = (modrm & 7) | REX_B(s);
5268 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
5269 } else {
5270 /* NOTE: order is important too for MMU exceptions */
5271 s->popl_esp_hack = 1 << ot;
5272 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
5273 s->popl_esp_hack = 0;
5274 gen_pop_update(s, ot);
5275 }
5276 break;
5277 case 0xc8: /* enter */
5278 {
5279 int level;
5280 val = cpu_lduw_code(env, s->pc);
5281 s->pc += 2;
5282 level = cpu_ldub_code(env, s->pc++);
5283 gen_enter(s, val, level);
5284 }
5285 break;
5286 case 0xc9: /* leave */
5287 /* XXX: exception not precise (ESP is updated before potential exception) */
5288 if (CODE64(s)) {
5289 gen_op_mov_v_reg(MO_64, cpu_T[0], R_EBP);
5290 gen_op_mov_reg_v(MO_64, R_ESP, cpu_T[0]);
5291 } else if (s->ss32) {
5292 gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP);
5293 gen_op_mov_reg_v(MO_32, R_ESP, cpu_T[0]);
5294 } else {
5295 gen_op_mov_v_reg(MO_16, cpu_T[0], R_EBP);
5296 gen_op_mov_reg_v(MO_16, R_ESP, cpu_T[0]);
5297 }
5298 ot = gen_pop_T0(s);
5299 gen_op_mov_reg_v(ot, R_EBP, cpu_T[0]);
5300 gen_pop_update(s, ot);
5301 break;
5302 case 0x06: /* push es */
5303 case 0x0e: /* push cs */
5304 case 0x16: /* push ss */
5305 case 0x1e: /* push ds */
5306 if (CODE64(s))
5307 goto illegal_op;
5308 gen_op_movl_T0_seg(b >> 3);
5309 gen_push_v(s, cpu_T[0]);
5310 break;
5311 case 0x1a0: /* push fs */
5312 case 0x1a8: /* push gs */
5313 gen_op_movl_T0_seg((b >> 3) & 7);
5314 gen_push_v(s, cpu_T[0]);
5315 break;
5316 case 0x07: /* pop es */
5317 case 0x17: /* pop ss */
5318 case 0x1f: /* pop ds */
5319 if (CODE64(s))
5320 goto illegal_op;
5321 reg = b >> 3;
5322 ot = gen_pop_T0(s);
5323 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5324 gen_pop_update(s, ot);
5325 if (reg == R_SS) {
5326 /* if reg == SS, inhibit interrupts/trace. */
5327 /* If several instructions disable interrupts, only the
5328 _first_ does it */
5329 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5330 gen_helper_set_inhibit_irq(cpu_env);
5331 s->tf = 0;
5332 }
5333 if (s->is_jmp) {
5334 gen_jmp_im(s->pc - s->cs_base);
5335 gen_eob(s);
5336 }
5337 break;
5338 case 0x1a1: /* pop fs */
5339 case 0x1a9: /* pop gs */
5340 ot = gen_pop_T0(s);
5341 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5342 gen_pop_update(s, ot);
5343 if (s->is_jmp) {
5344 gen_jmp_im(s->pc - s->cs_base);
5345 gen_eob(s);
5346 }
5347 break;
5348
5349 /**************************/
5350 /* mov */
5351 case 0x88:
5352 case 0x89: /* mov Gv, Ev */
5353 ot = mo_b_d(b, dflag);
5354 modrm = cpu_ldub_code(env, s->pc++);
5355 reg = ((modrm >> 3) & 7) | rex_r;
5356
5357 /* generate a generic store */
5358 gen_ldst_modrm(env, s, modrm, ot, reg, 1);
5359 break;
5360 case 0xc6:
5361 case 0xc7: /* mov Ev, Iv */
5362 ot = mo_b_d(b, dflag);
5363 modrm = cpu_ldub_code(env, s->pc++);
5364 mod = (modrm >> 6) & 3;
5365 if (mod != 3) {
5366 s->rip_offset = insn_const_size(ot);
5367 gen_lea_modrm(env, s, modrm);
5368 }
5369 val = insn_get(env, s, ot);
5370 tcg_gen_movi_tl(cpu_T[0], val);
5371 if (mod != 3) {
5372 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
5373 } else {
5374 gen_op_mov_reg_v(ot, (modrm & 7) | REX_B(s), cpu_T[0]);
5375 }
5376 break;
5377 case 0x8a:
5378 case 0x8b: /* mov Ev, Gv */
5379 ot = mo_b_d(b, dflag);
5380 modrm = cpu_ldub_code(env, s->pc++);
5381 reg = ((modrm >> 3) & 7) | rex_r;
5382
5383 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
5384 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
5385 break;
5386 case 0x8e: /* mov seg, Gv */
5387 modrm = cpu_ldub_code(env, s->pc++);
5388 reg = (modrm >> 3) & 7;
5389 if (reg >= 6 || reg == R_CS)
5390 goto illegal_op;
5391 gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
5392 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5393 if (reg == R_SS) {
5394 /* if reg == SS, inhibit interrupts/trace */
5395 /* If several instructions disable interrupts, only the
5396 _first_ does it */
5397 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5398 gen_helper_set_inhibit_irq(cpu_env);
5399 s->tf = 0;
5400 }
5401 if (s->is_jmp) {
5402 gen_jmp_im(s->pc - s->cs_base);
5403 gen_eob(s);
5404 }
5405 break;
5406 case 0x8c: /* mov Gv, seg */
5407 modrm = cpu_ldub_code(env, s->pc++);
5408 reg = (modrm >> 3) & 7;
5409 mod = (modrm >> 6) & 3;
5410 if (reg >= 6)
5411 goto illegal_op;
5412 gen_op_movl_T0_seg(reg);
5413 ot = mod == 3 ? dflag : MO_16;
5414 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
5415 break;
5416
5417 case 0x1b6: /* movzbS Gv, Eb */
5418 case 0x1b7: /* movzwS Gv, Eb */
5419 case 0x1be: /* movsbS Gv, Eb */
5420 case 0x1bf: /* movswS Gv, Eb */
5421 {
5422 TCGMemOp d_ot;
5423 TCGMemOp s_ot;
5424
5425 /* d_ot is the size of destination */
5426 d_ot = dflag;
5427 /* ot is the size of source */
5428 ot = (b & 1) + MO_8;
5429 /* s_ot is the sign+size of source */
5430 s_ot = b & 8 ? MO_SIGN | ot : ot;
5431
5432 modrm = cpu_ldub_code(env, s->pc++);
5433 reg = ((modrm >> 3) & 7) | rex_r;
5434 mod = (modrm >> 6) & 3;
5435 rm = (modrm & 7) | REX_B(s);
5436
5437 if (mod == 3) {
5438 gen_op_mov_v_reg(ot, cpu_T[0], rm);
5439 switch (s_ot) {
5440 case MO_UB:
5441 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5442 break;
5443 case MO_SB:
5444 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5445 break;
5446 case MO_UW:
5447 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5448 break;
5449 default:
5450 case MO_SW:
5451 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5452 break;
5453 }
5454 gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
5455 } else {
5456 gen_lea_modrm(env, s, modrm);
5457 gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
5458 gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
5459 }
5460 }
5461 break;
5462
5463 case 0x8d: /* lea */
5464 ot = dflag;
5465 modrm = cpu_ldub_code(env, s->pc++);
5466 mod = (modrm >> 6) & 3;
5467 if (mod == 3)
5468 goto illegal_op;
5469 reg = ((modrm >> 3) & 7) | rex_r;
5470 /* we must ensure that no segment is added */
5471 s->override = -1;
5472 val = s->addseg;
5473 s->addseg = 0;
5474 gen_lea_modrm(env, s, modrm);
5475 s->addseg = val;
5476 gen_op_mov_reg_v(ot, reg, cpu_A0);
5477 break;
5478
5479 case 0xa0: /* mov EAX, Ov */
5480 case 0xa1:
5481 case 0xa2: /* mov Ov, EAX */
5482 case 0xa3:
5483 {
5484 target_ulong offset_addr;
5485
5486 ot = mo_b_d(b, dflag);
5487 switch (s->aflag) {
5488 #ifdef TARGET_X86_64
5489 case MO_64:
5490 offset_addr = cpu_ldq_code(env, s->pc);
5491 s->pc += 8;
5492 break;
5493 #endif
5494 default:
5495 offset_addr = insn_get(env, s, s->aflag);
5496 break;
5497 }
5498 tcg_gen_movi_tl(cpu_A0, offset_addr);
5499 gen_add_A0_ds_seg(s);
5500 if ((b & 2) == 0) {
5501 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
5502 gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
5503 } else {
5504 gen_op_mov_v_reg(ot, cpu_T[0], R_EAX);
5505 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
5506 }
5507 }
5508 break;
5509 case 0xd7: /* xlat */
5510 tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EBX]);
5511 tcg_gen_ext8u_tl(cpu_T[0], cpu_regs[R_EAX]);
5512 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5513 gen_extu(s->aflag, cpu_A0);
5514 gen_add_A0_ds_seg(s);
5515 gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
5516 gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
5517 break;
5518 case 0xb0 ... 0xb7: /* mov R, Ib */
5519 val = insn_get(env, s, MO_8);
5520 tcg_gen_movi_tl(cpu_T[0], val);
5521 gen_op_mov_reg_v(MO_8, (b & 7) | REX_B(s), cpu_T[0]);
5522 break;
5523 case 0xb8 ... 0xbf: /* mov R, Iv */
5524 #ifdef TARGET_X86_64
5525 if (dflag == MO_64) {
5526 uint64_t tmp;
5527 /* 64 bit case */
5528 tmp = cpu_ldq_code(env, s->pc);
5529 s->pc += 8;
5530 reg = (b & 7) | REX_B(s);
5531 tcg_gen_movi_tl(cpu_T[0], tmp);
5532 gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
5533 } else
5534 #endif
5535 {
5536 ot = dflag;
5537 val = insn_get(env, s, ot);
5538 reg = (b & 7) | REX_B(s);
5539 tcg_gen_movi_tl(cpu_T[0], val);
5540 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
5541 }
5542 break;
5543
5544 case 0x91 ... 0x97: /* xchg R, EAX */
5545 do_xchg_reg_eax:
5546 ot = dflag;
5547 reg = (b & 7) | REX_B(s);
5548 rm = R_EAX;
5549 goto do_xchg_reg;
5550 case 0x86:
5551 case 0x87: /* xchg Ev, Gv */
5552 ot = mo_b_d(b, dflag);
5553 modrm = cpu_ldub_code(env, s->pc++);
5554 reg = ((modrm >> 3) & 7) | rex_r;
5555 mod = (modrm >> 6) & 3;
5556 if (mod == 3) {
5557 rm = (modrm & 7) | REX_B(s);
5558 do_xchg_reg:
5559 gen_op_mov_v_reg(ot, cpu_T[0], reg);
5560 gen_op_mov_v_reg(ot, cpu_T[1], rm);
5561 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
5562 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
5563 } else {
5564 gen_lea_modrm(env, s, modrm);
5565 gen_op_mov_v_reg(ot, cpu_T[0], reg);
5566 /* for xchg, lock is implicit */
5567 if (!(prefixes & PREFIX_LOCK))
5568 gen_helper_lock();
5569 gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
5570 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
5571 if (!(prefixes & PREFIX_LOCK))
5572 gen_helper_unlock();
5573 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
5574 }
5575 break;
5576 case 0xc4: /* les Gv */
5577 /* In CODE64 this is VEX3; see above. */
5578 op = R_ES;
5579 goto do_lxx;
5580 case 0xc5: /* lds Gv */
5581 /* In CODE64 this is VEX2; see above. */
5582 op = R_DS;
5583 goto do_lxx;
5584 case 0x1b2: /* lss Gv */
5585 op = R_SS;
5586 goto do_lxx;
5587 case 0x1b4: /* lfs Gv */
5588 op = R_FS;
5589 goto do_lxx;
5590 case 0x1b5: /* lgs Gv */
5591 op = R_GS;
5592 do_lxx:
5593 ot = dflag != MO_16 ? MO_32 : MO_16;
5594 modrm = cpu_ldub_code(env, s->pc++);
5595 reg = ((modrm >> 3) & 7) | rex_r;
5596 mod = (modrm >> 6) & 3;
5597 if (mod == 3)
5598 goto illegal_op;
5599 gen_lea_modrm(env, s, modrm);
5600 gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
5601 gen_add_A0_im(s, 1 << ot);
5602 /* load the segment first to handle exceptions properly */
5603 gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
5604 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5605 /* then put the data */
5606 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
5607 if (s->is_jmp) {
5608 gen_jmp_im(s->pc - s->cs_base);
5609 gen_eob(s);
5610 }
5611 break;
5612
5613 /************************/
5614 /* shifts */
5615 case 0xc0:
5616 case 0xc1:
5617 /* shift Ev,Ib */
5618 shift = 2;
5619 grp2:
5620 {
5621 ot = mo_b_d(b, dflag);
5622 modrm = cpu_ldub_code(env, s->pc++);
5623 mod = (modrm >> 6) & 3;
5624 op = (modrm >> 3) & 7;
5625
5626 if (mod != 3) {
5627 if (shift == 2) {
5628 s->rip_offset = 1;
5629 }
5630 gen_lea_modrm(env, s, modrm);
5631 opreg = OR_TMP0;
5632 } else {
5633 opreg = (modrm & 7) | REX_B(s);
5634 }
5635
5636 /* simpler op */
5637 if (shift == 0) {
5638 gen_shift(s, op, ot, opreg, OR_ECX);
5639 } else {
5640 if (shift == 2) {
5641 shift = cpu_ldub_code(env, s->pc++);
5642 }
5643 gen_shifti(s, op, ot, opreg, shift);
5644 }
5645 }
5646 break;
5647 case 0xd0:
5648 case 0xd1:
5649 /* shift Ev,1 */
5650 shift = 1;
5651 goto grp2;
5652 case 0xd2:
5653 case 0xd3:
5654 /* shift Ev,cl */
5655 shift = 0;
5656 goto grp2;
5657
5658 case 0x1a4: /* shld imm */
5659 op = 0;
5660 shift = 1;
5661 goto do_shiftd;
5662 case 0x1a5: /* shld cl */
5663 op = 0;
5664 shift = 0;
5665 goto do_shiftd;
5666 case 0x1ac: /* shrd imm */
5667 op = 1;
5668 shift = 1;
5669 goto do_shiftd;
5670 case 0x1ad: /* shrd cl */
5671 op = 1;
5672 shift = 0;
5673 do_shiftd:
5674 ot = dflag;
5675 modrm = cpu_ldub_code(env, s->pc++);
5676 mod = (modrm >> 6) & 3;
5677 rm = (modrm & 7) | REX_B(s);
5678 reg = ((modrm >> 3) & 7) | rex_r;
5679 if (mod != 3) {
5680 gen_lea_modrm(env, s, modrm);
5681 opreg = OR_TMP0;
5682 } else {
5683 opreg = rm;
5684 }
5685 gen_op_mov_v_reg(ot, cpu_T[1], reg);
5686
5687 if (shift) {
5688 TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++));
5689 gen_shiftd_rm_T1(s, ot, opreg, op, imm);
5690 tcg_temp_free(imm);
5691 } else {
5692 gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
5693 }
5694 break;
5695
5696 /************************/
5697 /* floats */
5698 case 0xd8 ... 0xdf:
5699 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5700 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5701 /* XXX: what to do if illegal op ? */
5702 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5703 break;
5704 }
5705 modrm = cpu_ldub_code(env, s->pc++);
5706 mod = (modrm >> 6) & 3;
5707 rm = modrm & 7;
5708 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5709 if (mod != 3) {
5710 /* memory op */
5711 gen_lea_modrm(env, s, modrm);
5712 switch(op) {
5713 case 0x00 ... 0x07: /* fxxxs */
5714 case 0x10 ... 0x17: /* fixxxl */
5715 case 0x20 ... 0x27: /* fxxxl */
5716 case 0x30 ... 0x37: /* fixxx */
5717 {
5718 int op1;
5719 op1 = op & 7;
5720
5721 switch(op >> 4) {
5722 case 0:
5723 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
5724 s->mem_index, MO_LEUL);
5725 gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
5726 break;
5727 case 1:
5728 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
5729 s->mem_index, MO_LEUL);
5730 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5731 break;
5732 case 2:
5733 tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0,
5734 s->mem_index, MO_LEQ);
5735 gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
5736 break;
5737 case 3:
5738 default:
5739 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
5740 s->mem_index, MO_LESW);
5741 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5742 break;
5743 }
5744
5745 gen_helper_fp_arith_ST0_FT0(op1);
5746 if (op1 == 3) {
5747 /* fcomp needs pop */
5748 gen_helper_fpop(cpu_env);
5749 }
5750 }
5751 break;
5752 case 0x08: /* flds */
5753 case 0x0a: /* fsts */
5754 case 0x0b: /* fstps */
5755 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5756 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5757 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5758 switch(op & 7) {
5759 case 0:
5760 switch(op >> 4) {
5761 case 0:
5762 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
5763 s->mem_index, MO_LEUL);
5764 gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
5765 break;
5766 case 1:
5767 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
5768 s->mem_index, MO_LEUL);
5769 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5770 break;
5771 case 2:
5772 tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0,
5773 s->mem_index, MO_LEQ);
5774 gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
5775 break;
5776 case 3:
5777 default:
5778 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
5779 s->mem_index, MO_LESW);
5780 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5781 break;
5782 }
5783 break;
5784 case 1:
5785 /* XXX: the corresponding CPUID bit must be tested ! */
5786 switch(op >> 4) {
5787 case 1:
5788 gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
5789 tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
5790 s->mem_index, MO_LEUL);
5791 break;
5792 case 2:
5793 gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
5794 tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
5795 s->mem_index, MO_LEQ);
5796 break;
5797 case 3:
5798 default:
5799 gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
5800 tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
5801 s->mem_index, MO_LEUW);
5802 break;
5803 }
5804 gen_helper_fpop(cpu_env);
5805 break;
5806 default:
5807 switch(op >> 4) {
5808 case 0:
5809 gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
5810 tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
5811 s->mem_index, MO_LEUL);
5812 break;
5813 case 1:
5814 gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
5815 tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
5816 s->mem_index, MO_LEUL);
5817 break;
5818 case 2:
5819 gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
5820 tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
5821 s->mem_index, MO_LEQ);
5822 break;
5823 case 3:
5824 default:
5825 gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
5826 tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
5827 s->mem_index, MO_LEUW);
5828 break;
5829 }
5830 if ((op & 7) == 3)
5831 gen_helper_fpop(cpu_env);
5832 break;
5833 }
5834 break;
5835 case 0x0c: /* fldenv mem */
5836 gen_update_cc_op(s);
5837 gen_jmp_im(pc_start - s->cs_base);
5838 gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
5839 break;
5840 case 0x0d: /* fldcw mem */
5841 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
5842 s->mem_index, MO_LEUW);
5843 gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
5844 break;
5845 case 0x0e: /* fnstenv mem */
5846 gen_update_cc_op(s);
5847 gen_jmp_im(pc_start - s->cs_base);
5848 gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
5849 break;
5850 case 0x0f: /* fnstcw mem */
5851 gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
5852 tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
5853 s->mem_index, MO_LEUW);
5854 break;
5855 case 0x1d: /* fldt mem */
5856 gen_update_cc_op(s);
5857 gen_jmp_im(pc_start - s->cs_base);
5858 gen_helper_fldt_ST0(cpu_env, cpu_A0);
5859 break;
5860 case 0x1f: /* fstpt mem */
5861 gen_update_cc_op(s);
5862 gen_jmp_im(pc_start - s->cs_base);
5863 gen_helper_fstt_ST0(cpu_env, cpu_A0);
5864 gen_helper_fpop(cpu_env);
5865 break;
5866 case 0x2c: /* frstor mem */
5867 gen_update_cc_op(s);
5868 gen_jmp_im(pc_start - s->cs_base);
5869 gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
5870 break;
5871 case 0x2e: /* fnsave mem */
5872 gen_update_cc_op(s);
5873 gen_jmp_im(pc_start - s->cs_base);
5874 gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
5875 break;
5876 case 0x2f: /* fnstsw mem */
5877 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
5878 tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
5879 s->mem_index, MO_LEUW);
5880 break;
5881 case 0x3c: /* fbld */
5882 gen_update_cc_op(s);
5883 gen_jmp_im(pc_start - s->cs_base);
5884 gen_helper_fbld_ST0(cpu_env, cpu_A0);
5885 break;
5886 case 0x3e: /* fbstp */
5887 gen_update_cc_op(s);
5888 gen_jmp_im(pc_start - s->cs_base);
5889 gen_helper_fbst_ST0(cpu_env, cpu_A0);
5890 gen_helper_fpop(cpu_env);
5891 break;
5892 case 0x3d: /* fildll */
5893 tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
5894 gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
5895 break;
5896 case 0x3f: /* fistpll */
5897 gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
5898 tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
5899 gen_helper_fpop(cpu_env);
5900 break;
5901 default:
5902 goto illegal_op;
5903 }
5904 } else {
5905 /* register float ops */
5906 opreg = rm;
5907
5908 switch(op) {
5909 case 0x08: /* fld sti */
5910 gen_helper_fpush(cpu_env);
5911 gen_helper_fmov_ST0_STN(cpu_env,
5912 tcg_const_i32((opreg + 1) & 7));
5913 break;
5914 case 0x09: /* fxchg sti */
5915 case 0x29: /* fxchg4 sti, undocumented op */
5916 case 0x39: /* fxchg7 sti, undocumented op */
5917 gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg));
5918 break;
5919 case 0x0a: /* grp d9/2 */
5920 switch(rm) {
5921 case 0: /* fnop */
5922 /* check exceptions (FreeBSD FPU probe) */
5923 gen_update_cc_op(s);
5924 gen_jmp_im(pc_start - s->cs_base);
5925 gen_helper_fwait(cpu_env);
5926 break;
5927 default:
5928 goto illegal_op;
5929 }
5930 break;
5931 case 0x0c: /* grp d9/4 */
5932 switch(rm) {
5933 case 0: /* fchs */
5934 gen_helper_fchs_ST0(cpu_env);
5935 break;
5936 case 1: /* fabs */
5937 gen_helper_fabs_ST0(cpu_env);
5938 break;
5939 case 4: /* ftst */
5940 gen_helper_fldz_FT0(cpu_env);
5941 gen_helper_fcom_ST0_FT0(cpu_env);
5942 break;
5943 case 5: /* fxam */
5944 gen_helper_fxam_ST0(cpu_env);
5945 break;
5946 default:
5947 goto illegal_op;
5948 }
5949 break;
5950 case 0x0d: /* grp d9/5 */
5951 {
5952 switch(rm) {
5953 case 0:
5954 gen_helper_fpush(cpu_env);
5955 gen_helper_fld1_ST0(cpu_env);
5956 break;
5957 case 1:
5958 gen_helper_fpush(cpu_env);
5959 gen_helper_fldl2t_ST0(cpu_env);
5960 break;
5961 case 2:
5962 gen_helper_fpush(cpu_env);
5963 gen_helper_fldl2e_ST0(cpu_env);
5964 break;
5965 case 3:
5966 gen_helper_fpush(cpu_env);
5967 gen_helper_fldpi_ST0(cpu_env);
5968 break;
5969 case 4:
5970 gen_helper_fpush(cpu_env);
5971 gen_helper_fldlg2_ST0(cpu_env);
5972 break;
5973 case 5:
5974 gen_helper_fpush(cpu_env);
5975 gen_helper_fldln2_ST0(cpu_env);
5976 break;
5977 case 6:
5978 gen_helper_fpush(cpu_env);
5979 gen_helper_fldz_ST0(cpu_env);
5980 break;
5981 default:
5982 goto illegal_op;
5983 }
5984 }
5985 break;
5986 case 0x0e: /* grp d9/6 */
5987 switch(rm) {
5988 case 0: /* f2xm1 */
5989 gen_helper_f2xm1(cpu_env);
5990 break;
5991 case 1: /* fyl2x */
5992 gen_helper_fyl2x(cpu_env);
5993 break;
5994 case 2: /* fptan */
5995 gen_helper_fptan(cpu_env);
5996 break;
5997 case 3: /* fpatan */
5998 gen_helper_fpatan(cpu_env);
5999 break;
6000 case 4: /* fxtract */
6001 gen_helper_fxtract(cpu_env);
6002 break;
6003 case 5: /* fprem1 */
6004 gen_helper_fprem1(cpu_env);
6005 break;
6006 case 6: /* fdecstp */
6007 gen_helper_fdecstp(cpu_env);
6008 break;
6009 default:
6010 case 7: /* fincstp */
6011 gen_helper_fincstp(cpu_env);
6012 break;
6013 }
6014 break;
6015 case 0x0f: /* grp d9/7 */
6016 switch(rm) {
6017 case 0: /* fprem */
6018 gen_helper_fprem(cpu_env);
6019 break;
6020 case 1: /* fyl2xp1 */
6021 gen_helper_fyl2xp1(cpu_env);
6022 break;
6023 case 2: /* fsqrt */
6024 gen_helper_fsqrt(cpu_env);
6025 break;
6026 case 3: /* fsincos */
6027 gen_helper_fsincos(cpu_env);
6028 break;
6029 case 5: /* fscale */
6030 gen_helper_fscale(cpu_env);
6031 break;
6032 case 4: /* frndint */
6033 gen_helper_frndint(cpu_env);
6034 break;
6035 case 6: /* fsin */
6036 gen_helper_fsin(cpu_env);
6037 break;
6038 default:
6039 case 7: /* fcos */
6040 gen_helper_fcos(cpu_env);
6041 break;
6042 }
6043 break;
6044 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6045 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6046 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6047 {
6048 int op1;
6049
6050 op1 = op & 7;
6051 if (op >= 0x20) {
6052 gen_helper_fp_arith_STN_ST0(op1, opreg);
6053 if (op >= 0x30)
6054 gen_helper_fpop(cpu_env);
6055 } else {
6056 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6057 gen_helper_fp_arith_ST0_FT0(op1);
6058 }
6059 }
6060 break;
6061 case 0x02: /* fcom */
6062 case 0x22: /* fcom2, undocumented op */
6063 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6064 gen_helper_fcom_ST0_FT0(cpu_env);
6065 break;
6066 case 0x03: /* fcomp */
6067 case 0x23: /* fcomp3, undocumented op */
6068 case 0x32: /* fcomp5, undocumented op */
6069 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6070 gen_helper_fcom_ST0_FT0(cpu_env);
6071 gen_helper_fpop(cpu_env);
6072 break;
6073 case 0x15: /* da/5 */
6074 switch(rm) {
6075 case 1: /* fucompp */
6076 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
6077 gen_helper_fucom_ST0_FT0(cpu_env);
6078 gen_helper_fpop(cpu_env);
6079 gen_helper_fpop(cpu_env);
6080 break;
6081 default:
6082 goto illegal_op;
6083 }
6084 break;
6085 case 0x1c:
6086 switch(rm) {
6087 case 0: /* feni (287 only, just do nop here) */
6088 break;
6089 case 1: /* fdisi (287 only, just do nop here) */
6090 break;
6091 case 2: /* fclex */
6092 gen_helper_fclex(cpu_env);
6093 break;
6094 case 3: /* fninit */
6095 gen_helper_fninit(cpu_env);
6096 break;
6097 case 4: /* fsetpm (287 only, just do nop here) */
6098 break;
6099 default:
6100 goto illegal_op;
6101 }
6102 break;
6103 case 0x1d: /* fucomi */
6104 if (!(s->cpuid_features & CPUID_CMOV)) {
6105 goto illegal_op;
6106 }
6107 gen_update_cc_op(s);
6108 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6109 gen_helper_fucomi_ST0_FT0(cpu_env);
6110 set_cc_op(s, CC_OP_EFLAGS);
6111 break;
6112 case 0x1e: /* fcomi */
6113 if (!(s->cpuid_features & CPUID_CMOV)) {
6114 goto illegal_op;
6115 }
6116 gen_update_cc_op(s);
6117 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6118 gen_helper_fcomi_ST0_FT0(cpu_env);
6119 set_cc_op(s, CC_OP_EFLAGS);
6120 break;
6121 case 0x28: /* ffree sti */
6122 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
6123 break;
6124 case 0x2a: /* fst sti */
6125 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
6126 break;
6127 case 0x2b: /* fstp sti */
6128 case 0x0b: /* fstp1 sti, undocumented op */
6129 case 0x3a: /* fstp8 sti, undocumented op */
6130 case 0x3b: /* fstp9 sti, undocumented op */
6131 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
6132 gen_helper_fpop(cpu_env);
6133 break;
6134 case 0x2c: /* fucom st(i) */
6135 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6136 gen_helper_fucom_ST0_FT0(cpu_env);
6137 break;
6138 case 0x2d: /* fucomp st(i) */
6139 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6140 gen_helper_fucom_ST0_FT0(cpu_env);
6141 gen_helper_fpop(cpu_env);
6142 break;
6143 case 0x33: /* de/3 */
6144 switch(rm) {
6145 case 1: /* fcompp */
6146 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
6147 gen_helper_fcom_ST0_FT0(cpu_env);
6148 gen_helper_fpop(cpu_env);
6149 gen_helper_fpop(cpu_env);
6150 break;
6151 default:
6152 goto illegal_op;
6153 }
6154 break;
6155 case 0x38: /* ffreep sti, undocumented op */
6156 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
6157 gen_helper_fpop(cpu_env);
6158 break;
6159 case 0x3c: /* df/4 */
6160 switch(rm) {
6161 case 0:
6162 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
6163 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
6164 gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
6165 break;
6166 default:
6167 goto illegal_op;
6168 }
6169 break;
6170 case 0x3d: /* fucomip */
6171 if (!(s->cpuid_features & CPUID_CMOV)) {
6172 goto illegal_op;
6173 }
6174 gen_update_cc_op(s);
6175 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6176 gen_helper_fucomi_ST0_FT0(cpu_env);
6177 gen_helper_fpop(cpu_env);
6178 set_cc_op(s, CC_OP_EFLAGS);
6179 break;
6180 case 0x3e: /* fcomip */
6181 if (!(s->cpuid_features & CPUID_CMOV)) {
6182 goto illegal_op;
6183 }
6184 gen_update_cc_op(s);
6185 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6186 gen_helper_fcomi_ST0_FT0(cpu_env);
6187 gen_helper_fpop(cpu_env);
6188 set_cc_op(s, CC_OP_EFLAGS);
6189 break;
6190 case 0x10 ... 0x13: /* fcmovxx */
6191 case 0x18 ... 0x1b:
6192 {
6193 int op1, l1;
6194 static const uint8_t fcmov_cc[8] = {
6195 (JCC_B << 1),
6196 (JCC_Z << 1),
6197 (JCC_BE << 1),
6198 (JCC_P << 1),
6199 };
6200
6201 if (!(s->cpuid_features & CPUID_CMOV)) {
6202 goto illegal_op;
6203 }
6204 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
6205 l1 = gen_new_label();
6206 gen_jcc1_noeob(s, op1, l1);
6207 gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg));
6208 gen_set_label(l1);
6209 }
6210 break;
6211 default:
6212 goto illegal_op;
6213 }
6214 }
6215 break;
6216 /************************/
6217 /* string ops */
6218
6219 case 0xa4: /* movsS */
6220 case 0xa5:
6221 ot = mo_b_d(b, dflag);
6222 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6223 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6224 } else {
6225 gen_movs(s, ot);
6226 }
6227 break;
6228
6229 case 0xaa: /* stosS */
6230 case 0xab:
6231 ot = mo_b_d(b, dflag);
6232 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6233 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6234 } else {
6235 gen_stos(s, ot);
6236 }
6237 break;
6238 case 0xac: /* lodsS */
6239 case 0xad:
6240 ot = mo_b_d(b, dflag);
6241 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6242 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6243 } else {
6244 gen_lods(s, ot);
6245 }
6246 break;
6247 case 0xae: /* scasS */
6248 case 0xaf:
6249 ot = mo_b_d(b, dflag);
6250 if (prefixes & PREFIX_REPNZ) {
6251 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6252 } else if (prefixes & PREFIX_REPZ) {
6253 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6254 } else {
6255 gen_scas(s, ot);
6256 }
6257 break;
6258
6259 case 0xa6: /* cmpsS */
6260 case 0xa7:
6261 ot = mo_b_d(b, dflag);
6262 if (prefixes & PREFIX_REPNZ) {
6263 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6264 } else if (prefixes & PREFIX_REPZ) {
6265 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6266 } else {
6267 gen_cmps(s, ot);
6268 }
6269 break;
6270 case 0x6c: /* insS */
6271 case 0x6d:
6272 ot = mo_b_d32(b, dflag);
6273 tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
6274 gen_check_io(s, ot, pc_start - s->cs_base,
6275 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6276 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6277 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6278 } else {
6279 gen_ins(s, ot);
6280 if (use_icount) {
6281 gen_jmp(s, s->pc - s->cs_base);
6282 }
6283 }
6284 break;
6285 case 0x6e: /* outsS */
6286 case 0x6f:
6287 ot = mo_b_d32(b, dflag);
6288 tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
6289 gen_check_io(s, ot, pc_start - s->cs_base,
6290 svm_is_rep(prefixes) | 4);
6291 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6292 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6293 } else {
6294 gen_outs(s, ot);
6295 if (use_icount) {
6296 gen_jmp(s, s->pc - s->cs_base);
6297 }
6298 }
6299 break;
6300
6301 /************************/
6302 /* port I/O */
6303
6304 case 0xe4:
6305 case 0xe5:
6306 ot = mo_b_d32(b, dflag);
6307 val = cpu_ldub_code(env, s->pc++);
6308 tcg_gen_movi_tl(cpu_T[0], val);
6309 gen_check_io(s, ot, pc_start - s->cs_base,
6310 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6311 if (use_icount)
6312 gen_io_start();
6313 tcg_gen_movi_i32(cpu_tmp2_i32, val);
6314 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6315 gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
6316 if (use_icount) {
6317 gen_io_end();
6318 gen_jmp(s, s->pc - s->cs_base);
6319 }
6320 break;
6321 case 0xe6:
6322 case 0xe7:
6323 ot = mo_b_d32(b, dflag);
6324 val = cpu_ldub_code(env, s->pc++);
6325 tcg_gen_movi_tl(cpu_T[0], val);
6326 gen_check_io(s, ot, pc_start - s->cs_base,
6327 svm_is_rep(prefixes));
6328 gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
6329
6330 if (use_icount)
6331 gen_io_start();
6332 tcg_gen_movi_i32(cpu_tmp2_i32, val);
6333 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6334 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6335 if (use_icount) {
6336 gen_io_end();
6337 gen_jmp(s, s->pc - s->cs_base);
6338 }
6339 break;
6340 case 0xec:
6341 case 0xed:
6342 ot = mo_b_d32(b, dflag);
6343 tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
6344 gen_check_io(s, ot, pc_start - s->cs_base,
6345 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6346 if (use_icount)
6347 gen_io_start();
6348 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6349 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6350 gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
6351 if (use_icount) {
6352 gen_io_end();
6353 gen_jmp(s, s->pc - s->cs_base);
6354 }
6355 break;
6356 case 0xee:
6357 case 0xef:
6358 ot = mo_b_d32(b, dflag);
6359 tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
6360 gen_check_io(s, ot, pc_start - s->cs_base,
6361 svm_is_rep(prefixes));
6362 gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
6363
6364 if (use_icount)
6365 gen_io_start();
6366 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6367 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6368 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6369 if (use_icount) {
6370 gen_io_end();
6371 gen_jmp(s, s->pc - s->cs_base);
6372 }
6373 break;
6374
6375 /************************/
6376 /* control */
6377 case 0xc2: /* ret im */
6378 val = cpu_ldsw_code(env, s->pc);
6379 s->pc += 2;
6380 ot = gen_pop_T0(s);
6381 gen_stack_update(s, val + (1 << ot));
6382 /* Note that gen_pop_T0 uses a zero-extending load. */
6383 gen_op_jmp_v(cpu_T[0]);
6384 gen_eob(s);
6385 break;
6386 case 0xc3: /* ret */
6387 ot = gen_pop_T0(s);
6388 gen_pop_update(s, ot);
6389 /* Note that gen_pop_T0 uses a zero-extending load. */
6390 gen_op_jmp_v(cpu_T[0]);
6391 gen_eob(s);
6392 break;
6393 case 0xca: /* lret im */
6394 val = cpu_ldsw_code(env, s->pc);
6395 s->pc += 2;
6396 do_lret:
6397 if (s->pe && !s->vm86) {
6398 gen_update_cc_op(s);
6399 gen_jmp_im(pc_start - s->cs_base);
6400 gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1),
6401 tcg_const_i32(val));
6402 } else {
6403 gen_stack_A0(s);
6404 /* pop offset */
6405 gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
6406 /* NOTE: keeping EIP updated is not a problem in case of
6407 exception */
6408 gen_op_jmp_v(cpu_T[0]);
6409 /* pop selector */
6410 gen_op_addl_A0_im(1 << dflag);
6411 gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
6412 gen_op_movl_seg_T0_vm(R_CS);
6413 /* add stack offset */
6414 gen_stack_update(s, val + (2 << dflag));
6415 }
6416 gen_eob(s);
6417 break;
6418 case 0xcb: /* lret */
6419 val = 0;
6420 goto do_lret;
6421 case 0xcf: /* iret */
6422 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6423 if (!s->pe) {
6424 /* real mode */
6425 gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
6426 set_cc_op(s, CC_OP_EFLAGS);
6427 } else if (s->vm86) {
6428 if (s->iopl != 3) {
6429 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6430 } else {
6431 gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
6432 set_cc_op(s, CC_OP_EFLAGS);
6433 }
6434 } else {
6435 gen_update_cc_op(s);
6436 gen_jmp_im(pc_start - s->cs_base);
6437 gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1),
6438 tcg_const_i32(s->pc - s->cs_base));
6439 set_cc_op(s, CC_OP_EFLAGS);
6440 }
6441 gen_eob(s);
6442 break;
6443 case 0xe8: /* call im */
6444 {
6445 if (dflag != MO_16) {
6446 tval = (int32_t)insn_get(env, s, MO_32);
6447 } else {
6448 tval = (int16_t)insn_get(env, s, MO_16);
6449 }
6450 next_eip = s->pc - s->cs_base;
6451 tval += next_eip;
6452 if (dflag == MO_16) {
6453 tval &= 0xffff;
6454 } else if (!CODE64(s)) {
6455 tval &= 0xffffffff;
6456 }
6457 tcg_gen_movi_tl(cpu_T[0], next_eip);
6458 gen_push_v(s, cpu_T[0]);
6459 gen_jmp(s, tval);
6460 }
6461 break;
6462 case 0x9a: /* lcall im */
6463 {
6464 unsigned int selector, offset;
6465
6466 if (CODE64(s))
6467 goto illegal_op;
6468 ot = dflag;
6469 offset = insn_get(env, s, ot);
6470 selector = insn_get(env, s, MO_16);
6471
6472 tcg_gen_movi_tl(cpu_T[0], selector);
6473 tcg_gen_movi_tl(cpu_T[1], offset);
6474 }
6475 goto do_lcall;
6476 case 0xe9: /* jmp im */
6477 if (dflag != MO_16) {
6478 tval = (int32_t)insn_get(env, s, MO_32);
6479 } else {
6480 tval = (int16_t)insn_get(env, s, MO_16);
6481 }
6482 tval += s->pc - s->cs_base;
6483 if (dflag == MO_16) {
6484 tval &= 0xffff;
6485 } else if (!CODE64(s)) {
6486 tval &= 0xffffffff;
6487 }
6488 gen_jmp(s, tval);
6489 break;
6490 case 0xea: /* ljmp im */
6491 {
6492 unsigned int selector, offset;
6493
6494 if (CODE64(s))
6495 goto illegal_op;
6496 ot = dflag;
6497 offset = insn_get(env, s, ot);
6498 selector = insn_get(env, s, MO_16);
6499
6500 tcg_gen_movi_tl(cpu_T[0], selector);
6501 tcg_gen_movi_tl(cpu_T[1], offset);
6502 }
6503 goto do_ljmp;
6504 case 0xeb: /* jmp Jb */
6505 tval = (int8_t)insn_get(env, s, MO_8);
6506 tval += s->pc - s->cs_base;
6507 if (dflag == MO_16) {
6508 tval &= 0xffff;
6509 }
6510 gen_jmp(s, tval);
6511 break;
6512 case 0x70 ... 0x7f: /* jcc Jb */
6513 tval = (int8_t)insn_get(env, s, MO_8);
6514 goto do_jcc;
6515 case 0x180 ... 0x18f: /* jcc Jv */
6516 if (dflag != MO_16) {
6517 tval = (int32_t)insn_get(env, s, MO_32);
6518 } else {
6519 tval = (int16_t)insn_get(env, s, MO_16);
6520 }
6521 do_jcc:
6522 next_eip = s->pc - s->cs_base;
6523 tval += next_eip;
6524 if (dflag == MO_16) {
6525 tval &= 0xffff;
6526 }
6527 gen_jcc(s, b, tval, next_eip);
6528 break;
6529
6530 case 0x190 ... 0x19f: /* setcc Gv */
6531 modrm = cpu_ldub_code(env, s->pc++);
6532 gen_setcc1(s, b, cpu_T[0]);
6533 gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1);
6534 break;
6535 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6536 if (!(s->cpuid_features & CPUID_CMOV)) {
6537 goto illegal_op;
6538 }
6539 ot = dflag;
6540 modrm = cpu_ldub_code(env, s->pc++);
6541 reg = ((modrm >> 3) & 7) | rex_r;
6542 gen_cmovcc1(env, s, ot, b, modrm, reg);
6543 break;
6544
6545 /************************/
6546 /* flags */
6547 case 0x9c: /* pushf */
6548 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6549 if (s->vm86 && s->iopl != 3) {
6550 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6551 } else {
6552 gen_update_cc_op(s);
6553 gen_helper_read_eflags(cpu_T[0], cpu_env);
6554 gen_push_v(s, cpu_T[0]);
6555 }
6556 break;
6557 case 0x9d: /* popf */
6558 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6559 if (s->vm86 && s->iopl != 3) {
6560 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6561 } else {
6562 ot = gen_pop_T0(s);
6563 if (s->cpl == 0) {
6564 if (dflag != MO_16) {
6565 gen_helper_write_eflags(cpu_env, cpu_T[0],
6566 tcg_const_i32((TF_MASK | AC_MASK |
6567 ID_MASK | NT_MASK |
6568 IF_MASK |
6569 IOPL_MASK)));
6570 } else {
6571 gen_helper_write_eflags(cpu_env, cpu_T[0],
6572 tcg_const_i32((TF_MASK | AC_MASK |
6573 ID_MASK | NT_MASK |
6574 IF_MASK | IOPL_MASK)
6575 & 0xffff));
6576 }
6577 } else {
6578 if (s->cpl <= s->iopl) {
6579 if (dflag != MO_16) {
6580 gen_helper_write_eflags(cpu_env, cpu_T[0],
6581 tcg_const_i32((TF_MASK |
6582 AC_MASK |
6583 ID_MASK |
6584 NT_MASK |
6585 IF_MASK)));
6586 } else {
6587 gen_helper_write_eflags(cpu_env, cpu_T[0],
6588 tcg_const_i32((TF_MASK |
6589 AC_MASK |
6590 ID_MASK |
6591 NT_MASK |
6592 IF_MASK)
6593 & 0xffff));
6594 }
6595 } else {
6596 if (dflag != MO_16) {
6597 gen_helper_write_eflags(cpu_env, cpu_T[0],
6598 tcg_const_i32((TF_MASK | AC_MASK |
6599 ID_MASK | NT_MASK)));
6600 } else {
6601 gen_helper_write_eflags(cpu_env, cpu_T[0],
6602 tcg_const_i32((TF_MASK | AC_MASK |
6603 ID_MASK | NT_MASK)
6604 & 0xffff));
6605 }
6606 }
6607 }
6608 gen_pop_update(s, ot);
6609 set_cc_op(s, CC_OP_EFLAGS);
6610 /* abort translation because TF/AC flag may change */
6611 gen_jmp_im(s->pc - s->cs_base);
6612 gen_eob(s);
6613 }
6614 break;
6615 case 0x9e: /* sahf */
6616 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6617 goto illegal_op;
6618 gen_op_mov_v_reg(MO_8, cpu_T[0], R_AH);
6619 gen_compute_eflags(s);
6620 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6621 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6622 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6623 break;
6624 case 0x9f: /* lahf */
6625 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6626 goto illegal_op;
6627 gen_compute_eflags(s);
6628 /* Note: gen_compute_eflags() only gives the condition codes */
6629 tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
6630 gen_op_mov_reg_v(MO_8, R_AH, cpu_T[0]);
6631 break;
6632 case 0xf5: /* cmc */
6633 gen_compute_eflags(s);
6634 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6635 break;
6636 case 0xf8: /* clc */
6637 gen_compute_eflags(s);
6638 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6639 break;
6640 case 0xf9: /* stc */
6641 gen_compute_eflags(s);
6642 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6643 break;
6644 case 0xfc: /* cld */
6645 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6646 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6647 break;
6648 case 0xfd: /* std */
6649 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6650 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6651 break;
6652
6653 /************************/
6654 /* bit operations */
6655 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6656 ot = dflag;
6657 modrm = cpu_ldub_code(env, s->pc++);
6658 op = (modrm >> 3) & 7;
6659 mod = (modrm >> 6) & 3;
6660 rm = (modrm & 7) | REX_B(s);
6661 if (mod != 3) {
6662 s->rip_offset = 1;
6663 gen_lea_modrm(env, s, modrm);
6664 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
6665 } else {
6666 gen_op_mov_v_reg(ot, cpu_T[0], rm);
6667 }
6668 /* load shift */
6669 val = cpu_ldub_code(env, s->pc++);
6670 tcg_gen_movi_tl(cpu_T[1], val);
6671 if (op < 4)
6672 goto illegal_op;
6673 op -= 4;
6674 goto bt_op;
6675 case 0x1a3: /* bt Gv, Ev */
6676 op = 0;
6677 goto do_btx;
6678 case 0x1ab: /* bts */
6679 op = 1;
6680 goto do_btx;
6681 case 0x1b3: /* btr */
6682 op = 2;
6683 goto do_btx;
6684 case 0x1bb: /* btc */
6685 op = 3;
6686 do_btx:
6687 ot = dflag;
6688 modrm = cpu_ldub_code(env, s->pc++);
6689 reg = ((modrm >> 3) & 7) | rex_r;
6690 mod = (modrm >> 6) & 3;
6691 rm = (modrm & 7) | REX_B(s);
6692 gen_op_mov_v_reg(MO_32, cpu_T[1], reg);
6693 if (mod != 3) {
6694 gen_lea_modrm(env, s, modrm);
6695 /* specific case: we need to add a displacement */
6696 gen_exts(ot, cpu_T[1]);
6697 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6698 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6699 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6700 gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
6701 } else {
6702 gen_op_mov_v_reg(ot, cpu_T[0], rm);
6703 }
6704 bt_op:
6705 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6706 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6707 switch(op) {
6708 case 0:
6709 break;
6710 case 1:
6711 tcg_gen_movi_tl(cpu_tmp0, 1);
6712 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6713 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6714 break;
6715 case 2:
6716 tcg_gen_movi_tl(cpu_tmp0, 1);
6717 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6718 tcg_gen_andc_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6719 break;
6720 default:
6721 case 3:
6722 tcg_gen_movi_tl(cpu_tmp0, 1);
6723 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6724 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6725 break;
6726 }
6727 if (op != 0) {
6728 if (mod != 3) {
6729 gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
6730 } else {
6731 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
6732 }
6733 }
6734
6735 /* Delay all CC updates until after the store above. Note that
6736 C is the result of the test, Z is unchanged, and the others
6737 are all undefined. */
6738 switch (s->cc_op) {
6739 case CC_OP_MULB ... CC_OP_MULQ:
6740 case CC_OP_ADDB ... CC_OP_ADDQ:
6741 case CC_OP_ADCB ... CC_OP_ADCQ:
6742 case CC_OP_SUBB ... CC_OP_SUBQ:
6743 case CC_OP_SBBB ... CC_OP_SBBQ:
6744 case CC_OP_LOGICB ... CC_OP_LOGICQ:
6745 case CC_OP_INCB ... CC_OP_INCQ:
6746 case CC_OP_DECB ... CC_OP_DECQ:
6747 case CC_OP_SHLB ... CC_OP_SHLQ:
6748 case CC_OP_SARB ... CC_OP_SARQ:
6749 case CC_OP_BMILGB ... CC_OP_BMILGQ:
6750 /* Z was going to be computed from the non-zero status of CC_DST.
6751 We can get that same Z value (and the new C value) by leaving
6752 CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the
6753 same width. */
6754 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6755 set_cc_op(s, ((s->cc_op - CC_OP_MULB) & 3) + CC_OP_SARB);
6756 break;
6757 default:
6758 /* Otherwise, generate EFLAGS and replace the C bit. */
6759 gen_compute_eflags(s);
6760 tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, cpu_tmp4,
6761 ctz32(CC_C), 1);
6762 break;
6763 }
6764 break;
6765 case 0x1bc: /* bsf / tzcnt */
6766 case 0x1bd: /* bsr / lzcnt */
6767 ot = dflag;
6768 modrm = cpu_ldub_code(env, s->pc++);
6769 reg = ((modrm >> 3) & 7) | rex_r;
6770 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
6771 gen_extu(ot, cpu_T[0]);
6772
6773 /* Note that lzcnt and tzcnt are in different extensions. */
6774 if ((prefixes & PREFIX_REPZ)
6775 && (b & 1
6776 ? s->cpuid_ext3_features & CPUID_EXT3_ABM
6777 : s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) {
6778 int size = 8 << ot;
6779 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
6780 if (b & 1) {
6781 /* For lzcnt, reduce the target_ulong result by the
6782 number of zeros that we expect to find at the top. */
6783 gen_helper_clz(cpu_T[0], cpu_T[0]);
6784 tcg_gen_subi_tl(cpu_T[0], cpu_T[0], TARGET_LONG_BITS - size);
6785 } else {
6786 /* For tzcnt, a zero input must return the operand size:
6787 force all bits outside the operand size to 1. */
6788 target_ulong mask = (target_ulong)-2 << (size - 1);
6789 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], mask);
6790 gen_helper_ctz(cpu_T[0], cpu_T[0]);
6791 }
6792 /* For lzcnt/tzcnt, C and Z bits are defined and are
6793 related to the result. */
6794 gen_op_update1_cc();
6795 set_cc_op(s, CC_OP_BMILGB + ot);
6796 } else {
6797 /* For bsr/bsf, only the Z bit is defined and it is related
6798 to the input and not the result. */
6799 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
6800 set_cc_op(s, CC_OP_LOGICB + ot);
6801 if (b & 1) {
6802 /* For bsr, return the bit index of the first 1 bit,
6803 not the count of leading zeros. */
6804 gen_helper_clz(cpu_T[0], cpu_T[0]);
6805 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], TARGET_LONG_BITS - 1);
6806 } else {
6807 gen_helper_ctz(cpu_T[0], cpu_T[0]);
6808 }
6809 /* ??? The manual says that the output is undefined when the
6810 input is zero, but real hardware leaves it unchanged, and
6811 real programs appear to depend on that. */
6812 tcg_gen_movi_tl(cpu_tmp0, 0);
6813 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[0], cpu_cc_dst, cpu_tmp0,
6814 cpu_regs[reg], cpu_T[0]);
6815 }
6816 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
6817 break;
6818 /************************/
6819 /* bcd */
6820 case 0x27: /* daa */
6821 if (CODE64(s))
6822 goto illegal_op;
6823 gen_update_cc_op(s);
6824 gen_helper_daa(cpu_env);
6825 set_cc_op(s, CC_OP_EFLAGS);
6826 break;
6827 case 0x2f: /* das */
6828 if (CODE64(s))
6829 goto illegal_op;
6830 gen_update_cc_op(s);
6831 gen_helper_das(cpu_env);
6832 set_cc_op(s, CC_OP_EFLAGS);
6833 break;
6834 case 0x37: /* aaa */
6835 if (CODE64(s))
6836 goto illegal_op;
6837 gen_update_cc_op(s);
6838 gen_helper_aaa(cpu_env);
6839 set_cc_op(s, CC_OP_EFLAGS);
6840 break;
6841 case 0x3f: /* aas */
6842 if (CODE64(s))
6843 goto illegal_op;
6844 gen_update_cc_op(s);
6845 gen_helper_aas(cpu_env);
6846 set_cc_op(s, CC_OP_EFLAGS);
6847 break;
6848 case 0xd4: /* aam */
6849 if (CODE64(s))
6850 goto illegal_op;
6851 val = cpu_ldub_code(env, s->pc++);
6852 if (val == 0) {
6853 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6854 } else {
6855 gen_helper_aam(cpu_env, tcg_const_i32(val));
6856 set_cc_op(s, CC_OP_LOGICB);
6857 }
6858 break;
6859 case 0xd5: /* aad */
6860 if (CODE64(s))
6861 goto illegal_op;
6862 val = cpu_ldub_code(env, s->pc++);
6863 gen_helper_aad(cpu_env, tcg_const_i32(val));
6864 set_cc_op(s, CC_OP_LOGICB);
6865 break;
6866 /************************/
6867 /* misc */
6868 case 0x90: /* nop */
6869 /* XXX: correct lock test for all insn */
6870 if (prefixes & PREFIX_LOCK) {
6871 goto illegal_op;
6872 }
6873 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6874 if (REX_B(s)) {
6875 goto do_xchg_reg_eax;
6876 }
6877 if (prefixes & PREFIX_REPZ) {
6878 gen_update_cc_op(s);
6879 gen_jmp_im(pc_start - s->cs_base);
6880 gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start));
6881 s->is_jmp = DISAS_TB_JUMP;
6882 }
6883 break;
6884 case 0x9b: /* fwait */
6885 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6886 (HF_MP_MASK | HF_TS_MASK)) {
6887 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6888 } else {
6889 gen_update_cc_op(s);
6890 gen_jmp_im(pc_start - s->cs_base);
6891 gen_helper_fwait(cpu_env);
6892 }
6893 break;
6894 case 0xcc: /* int3 */
6895 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6896 break;
6897 case 0xcd: /* int N */
6898 val = cpu_ldub_code(env, s->pc++);
6899 if (s->vm86 && s->iopl != 3) {
6900 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6901 } else {
6902 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6903 }
6904 break;
6905 case 0xce: /* into */
6906 if (CODE64(s))
6907 goto illegal_op;
6908 gen_update_cc_op(s);
6909 gen_jmp_im(pc_start - s->cs_base);
6910 gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start));
6911 break;
6912 #ifdef WANT_ICEBP
6913 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6914 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6915 #if 1
6916 gen_debug(s, pc_start - s->cs_base);
6917 #else
6918 /* start debug */
6919 tb_flush(env);
6920 qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6921 #endif
6922 break;
6923 #endif
6924 case 0xfa: /* cli */
6925 if (!s->vm86) {
6926 if (s->cpl <= s->iopl) {
6927 gen_helper_cli(cpu_env);
6928 } else {
6929 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6930 }
6931 } else {
6932 if (s->iopl == 3) {
6933 gen_helper_cli(cpu_env);
6934 } else {
6935 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6936 }
6937 }
6938 break;
6939 case 0xfb: /* sti */
6940 if (!s->vm86) {
6941 if (s->cpl <= s->iopl) {
6942 gen_sti:
6943 gen_helper_sti(cpu_env);
6944 /* interruptions are enabled only the first insn after sti */
6945 /* If several instructions disable interrupts, only the
6946 _first_ does it */
6947 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6948 gen_helper_set_inhibit_irq(cpu_env);
6949 /* give a chance to handle pending irqs */
6950 gen_jmp_im(s->pc - s->cs_base);
6951 gen_eob(s);
6952 } else {
6953 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6954 }
6955 } else {
6956 if (s->iopl == 3) {
6957 goto gen_sti;
6958 } else {
6959 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6960 }
6961 }
6962 break;
6963 case 0x62: /* bound */
6964 if (CODE64(s))
6965 goto illegal_op;
6966 ot = dflag;
6967 modrm = cpu_ldub_code(env, s->pc++);
6968 reg = (modrm >> 3) & 7;
6969 mod = (modrm >> 6) & 3;
6970 if (mod == 3)
6971 goto illegal_op;
6972 gen_op_mov_v_reg(ot, cpu_T[0], reg);
6973 gen_lea_modrm(env, s, modrm);
6974 gen_jmp_im(pc_start - s->cs_base);
6975 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6976 if (ot == MO_16) {
6977 gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32);
6978 } else {
6979 gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32);
6980 }
6981 break;
6982 case 0x1c8 ... 0x1cf: /* bswap reg */
6983 reg = (b & 7) | REX_B(s);
6984 #ifdef TARGET_X86_64
6985 if (dflag == MO_64) {
6986 gen_op_mov_v_reg(MO_64, cpu_T[0], reg);
6987 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6988 gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
6989 } else
6990 #endif
6991 {
6992 gen_op_mov_v_reg(MO_32, cpu_T[0], reg);
6993 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6994 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6995 gen_op_mov_reg_v(MO_32, reg, cpu_T[0]);
6996 }
6997 break;
6998 case 0xd6: /* salc */
6999 if (CODE64(s))
7000 goto illegal_op;
7001 gen_compute_eflags_c(s, cpu_T[0]);
7002 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
7003 gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
7004 break;
7005 case 0xe0: /* loopnz */
7006 case 0xe1: /* loopz */
7007 case 0xe2: /* loop */
7008 case 0xe3: /* jecxz */
7009 {
7010 int l1, l2, l3;
7011
7012 tval = (int8_t)insn_get(env, s, MO_8);
7013 next_eip = s->pc - s->cs_base;
7014 tval += next_eip;
7015 if (dflag == MO_16) {
7016 tval &= 0xffff;
7017 }
7018
7019 l1 = gen_new_label();
7020 l2 = gen_new_label();
7021 l3 = gen_new_label();
7022 b &= 3;
7023 switch(b) {
7024 case 0: /* loopnz */
7025 case 1: /* loopz */
7026 gen_op_add_reg_im(s->aflag, R_ECX, -1);
7027 gen_op_jz_ecx(s->aflag, l3);
7028 gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
7029 break;
7030 case 2: /* loop */
7031 gen_op_add_reg_im(s->aflag, R_ECX, -1);
7032 gen_op_jnz_ecx(s->aflag, l1);
7033 break;
7034 default:
7035 case 3: /* jcxz */
7036 gen_op_jz_ecx(s->aflag, l1);
7037 break;
7038 }
7039
7040 gen_set_label(l3);
7041 gen_jmp_im(next_eip);
7042 tcg_gen_br(l2);
7043
7044 gen_set_label(l1);
7045 gen_jmp_im(tval);
7046 gen_set_label(l2);
7047 gen_eob(s);
7048 }
7049 break;
7050 case 0x130: /* wrmsr */
7051 case 0x132: /* rdmsr */
7052 if (s->cpl != 0) {
7053 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7054 } else {
7055 gen_update_cc_op(s);
7056 gen_jmp_im(pc_start - s->cs_base);
7057 if (b & 2) {
7058 gen_helper_rdmsr(cpu_env);
7059 } else {
7060 gen_helper_wrmsr(cpu_env);
7061 }
7062 }
7063 break;
7064 case 0x131: /* rdtsc */
7065 gen_update_cc_op(s);
7066 gen_jmp_im(pc_start - s->cs_base);
7067 if (use_icount)
7068 gen_io_start();
7069 gen_helper_rdtsc(cpu_env);
7070 if (use_icount) {
7071 gen_io_end();
7072 gen_jmp(s, s->pc - s->cs_base);
7073 }
7074 break;
7075 case 0x133: /* rdpmc */
7076 gen_update_cc_op(s);
7077 gen_jmp_im(pc_start - s->cs_base);
7078 gen_helper_rdpmc(cpu_env);
7079 break;
7080 case 0x134: /* sysenter */
7081 /* For Intel SYSENTER is valid on 64-bit */
7082 if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
7083 goto illegal_op;
7084 if (!s->pe) {
7085 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7086 } else {
7087 gen_update_cc_op(s);
7088 gen_jmp_im(pc_start - s->cs_base);
7089 gen_helper_sysenter(cpu_env);
7090 gen_eob(s);
7091 }
7092 break;
7093 case 0x135: /* sysexit */
7094 /* For Intel SYSEXIT is valid on 64-bit */
7095 if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
7096 goto illegal_op;
7097 if (!s->pe) {
7098 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7099 } else {
7100 gen_update_cc_op(s);
7101 gen_jmp_im(pc_start - s->cs_base);
7102 gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1));
7103 gen_eob(s);
7104 }
7105 break;
7106 #ifdef TARGET_X86_64
7107 case 0x105: /* syscall */
7108 /* XXX: is it usable in real mode ? */
7109 gen_update_cc_op(s);
7110 gen_jmp_im(pc_start - s->cs_base);
7111 gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start));
7112 gen_eob(s);
7113 break;
7114 case 0x107: /* sysret */
7115 if (!s->pe) {
7116 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7117 } else {
7118 gen_update_cc_op(s);
7119 gen_jmp_im(pc_start - s->cs_base);
7120 gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1));
7121 /* condition codes are modified only in long mode */
7122 if (s->lma) {
7123 set_cc_op(s, CC_OP_EFLAGS);
7124 }
7125 gen_eob(s);
7126 }
7127 break;
7128 #endif
7129 case 0x1a2: /* cpuid */
7130 gen_update_cc_op(s);
7131 gen_jmp_im(pc_start - s->cs_base);
7132 gen_helper_cpuid(cpu_env);
7133 break;
7134 case 0xf4: /* hlt */
7135 if (s->cpl != 0) {
7136 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7137 } else {
7138 gen_update_cc_op(s);
7139 gen_jmp_im(pc_start - s->cs_base);
7140 gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start));
7141 s->is_jmp = DISAS_TB_JUMP;
7142 }
7143 break;
7144 case 0x100:
7145 modrm = cpu_ldub_code(env, s->pc++);
7146 mod = (modrm >> 6) & 3;
7147 op = (modrm >> 3) & 7;
7148 switch(op) {
7149 case 0: /* sldt */
7150 if (!s->pe || s->vm86)
7151 goto illegal_op;
7152 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
7153 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
7154 ot = mod == 3 ? dflag : MO_16;
7155 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
7156 break;
7157 case 2: /* lldt */
7158 if (!s->pe || s->vm86)
7159 goto illegal_op;
7160 if (s->cpl != 0) {
7161 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7162 } else {
7163 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
7164 gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
7165 gen_jmp_im(pc_start - s->cs_base);
7166 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7167 gen_helper_lldt(cpu_env, cpu_tmp2_i32);
7168 }
7169 break;
7170 case 1: /* str */
7171 if (!s->pe || s->vm86)
7172 goto illegal_op;
7173 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
7174 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
7175 ot = mod == 3 ? dflag : MO_16;
7176 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
7177 break;
7178 case 3: /* ltr */
7179 if (!s->pe || s->vm86)
7180 goto illegal_op;
7181 if (s->cpl != 0) {
7182 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7183 } else {
7184 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
7185 gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
7186 gen_jmp_im(pc_start - s->cs_base);
7187 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7188 gen_helper_ltr(cpu_env, cpu_tmp2_i32);
7189 }
7190 break;
7191 case 4: /* verr */
7192 case 5: /* verw */
7193 if (!s->pe || s->vm86)
7194 goto illegal_op;
7195 gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
7196 gen_update_cc_op(s);
7197 if (op == 4) {
7198 gen_helper_verr(cpu_env, cpu_T[0]);
7199 } else {
7200 gen_helper_verw(cpu_env, cpu_T[0]);
7201 }
7202 set_cc_op(s, CC_OP_EFLAGS);
7203 break;
7204 default:
7205 goto illegal_op;
7206 }
7207 break;
7208 case 0x101:
7209 modrm = cpu_ldub_code(env, s->pc++);
7210 mod = (modrm >> 6) & 3;
7211 op = (modrm >> 3) & 7;
7212 rm = modrm & 7;
7213 switch(op) {
7214 case 0: /* sgdt */
7215 if (mod == 3)
7216 goto illegal_op;
7217 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
7218 gen_lea_modrm(env, s, modrm);
7219 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7220 gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
7221 gen_add_A0_im(s, 2);
7222 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7223 if (dflag == MO_16) {
7224 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
7225 }
7226 gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
7227 break;
7228 case 1:
7229 if (mod == 3) {
7230 switch (rm) {
7231 case 0: /* monitor */
7232 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7233 s->cpl != 0)
7234 goto illegal_op;
7235 gen_update_cc_op(s);
7236 gen_jmp_im(pc_start - s->cs_base);
7237 tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EAX]);
7238 gen_extu(s->aflag, cpu_A0);
7239 gen_add_A0_ds_seg(s);
7240 gen_helper_monitor(cpu_env, cpu_A0);
7241 break;
7242 case 1: /* mwait */
7243 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7244 s->cpl != 0)
7245 goto illegal_op;
7246 gen_update_cc_op(s);
7247 gen_jmp_im(pc_start - s->cs_base);
7248 gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start));
7249 gen_eob(s);
7250 break;
7251 case 2: /* clac */
7252 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) ||
7253 s->cpl != 0) {
7254 goto illegal_op;
7255 }
7256 gen_helper_clac(cpu_env);
7257 gen_jmp_im(s->pc - s->cs_base);
7258 gen_eob(s);
7259 break;
7260 case 3: /* stac */
7261 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) ||
7262 s->cpl != 0) {
7263 goto illegal_op;
7264 }
7265 gen_helper_stac(cpu_env);
7266 gen_jmp_im(s->pc - s->cs_base);
7267 gen_eob(s);
7268 break;
7269 default:
7270 goto illegal_op;
7271 }
7272 } else { /* sidt */
7273 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7274 gen_lea_modrm(env, s, modrm);
7275 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7276 gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
7277 gen_add_A0_im(s, 2);
7278 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7279 if (dflag == MO_16) {
7280 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
7281 }
7282 gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
7283 }
7284 break;
7285 case 2: /* lgdt */
7286 case 3: /* lidt */
7287 if (mod == 3) {
7288 gen_update_cc_op(s);
7289 gen_jmp_im(pc_start - s->cs_base);
7290 switch(rm) {
7291 case 0: /* VMRUN */
7292 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7293 goto illegal_op;
7294 if (s->cpl != 0) {
7295 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7296 break;
7297 } else {
7298 gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1),
7299 tcg_const_i32(s->pc - pc_start));
7300 tcg_gen_exit_tb(0);
7301 s->is_jmp = DISAS_TB_JUMP;
7302 }
7303 break;
7304 case 1: /* VMMCALL */
7305 if (!(s->flags & HF_SVME_MASK))
7306 goto illegal_op;
7307 gen_helper_vmmcall(cpu_env);
7308 break;
7309 case 2: /* VMLOAD */
7310 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7311 goto illegal_op;
7312 if (s->cpl != 0) {
7313 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7314 break;
7315 } else {
7316 gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1));
7317 }
7318 break;
7319 case 3: /* VMSAVE */
7320 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7321 goto illegal_op;
7322 if (s->cpl != 0) {
7323 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7324 break;
7325 } else {
7326 gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1));
7327 }
7328 break;
7329 case 4: /* STGI */
7330 if ((!(s->flags & HF_SVME_MASK) &&
7331 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7332 !s->pe)
7333 goto illegal_op;
7334 if (s->cpl != 0) {
7335 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7336 break;
7337 } else {
7338 gen_helper_stgi(cpu_env);
7339 }
7340 break;
7341 case 5: /* CLGI */
7342 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7343 goto illegal_op;
7344 if (s->cpl != 0) {
7345 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7346 break;
7347 } else {
7348 gen_helper_clgi(cpu_env);
7349 }
7350 break;
7351 case 6: /* SKINIT */
7352 if ((!(s->flags & HF_SVME_MASK) &&
7353 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7354 !s->pe)
7355 goto illegal_op;
7356 gen_helper_skinit(cpu_env);
7357 break;
7358 case 7: /* INVLPGA */
7359 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7360 goto illegal_op;
7361 if (s->cpl != 0) {
7362 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7363 break;
7364 } else {
7365 gen_helper_invlpga(cpu_env,
7366 tcg_const_i32(s->aflag - 1));
7367 }
7368 break;
7369 default:
7370 goto illegal_op;
7371 }
7372 } else if (s->cpl != 0) {
7373 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7374 } else {
7375 gen_svm_check_intercept(s, pc_start,
7376 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7377 gen_lea_modrm(env, s, modrm);
7378 gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
7379 gen_add_A0_im(s, 2);
7380 gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
7381 if (dflag == MO_16) {
7382 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
7383 }
7384 if (op == 2) {
7385 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7386 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7387 } else {
7388 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7389 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7390 }
7391 }
7392 break;
7393 case 4: /* smsw */
7394 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7395 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7396 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7397 #else
7398 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7399 #endif
7400 gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1);
7401 break;
7402 case 6: /* lmsw */
7403 if (s->cpl != 0) {
7404 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7405 } else {
7406 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7407 gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
7408 gen_helper_lmsw(cpu_env, cpu_T[0]);
7409 gen_jmp_im(s->pc - s->cs_base);
7410 gen_eob(s);
7411 }
7412 break;
7413 case 7:
7414 if (mod != 3) { /* invlpg */
7415 if (s->cpl != 0) {
7416 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7417 } else {
7418 gen_update_cc_op(s);
7419 gen_jmp_im(pc_start - s->cs_base);
7420 gen_lea_modrm(env, s, modrm);
7421 gen_helper_invlpg(cpu_env, cpu_A0);
7422 gen_jmp_im(s->pc - s->cs_base);
7423 gen_eob(s);
7424 }
7425 } else {
7426 switch (rm) {
7427 case 0: /* swapgs */
7428 #ifdef TARGET_X86_64
7429 if (CODE64(s)) {
7430 if (s->cpl != 0) {
7431 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7432 } else {
7433 tcg_gen_ld_tl(cpu_T[0], cpu_env,
7434 offsetof(CPUX86State,segs[R_GS].base));
7435 tcg_gen_ld_tl(cpu_T[1], cpu_env,
7436 offsetof(CPUX86State,kernelgsbase));
7437 tcg_gen_st_tl(cpu_T[1], cpu_env,
7438 offsetof(CPUX86State,segs[R_GS].base));
7439 tcg_gen_st_tl(cpu_T[0], cpu_env,
7440 offsetof(CPUX86State,kernelgsbase));
7441 }
7442 } else
7443 #endif
7444 {
7445 goto illegal_op;
7446 }
7447 break;
7448 case 1: /* rdtscp */
7449 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7450 goto illegal_op;
7451 gen_update_cc_op(s);
7452 gen_jmp_im(pc_start - s->cs_base);
7453 if (use_icount)
7454 gen_io_start();
7455 gen_helper_rdtscp(cpu_env);
7456 if (use_icount) {
7457 gen_io_end();
7458 gen_jmp(s, s->pc - s->cs_base);
7459 }
7460 break;
7461 default:
7462 goto illegal_op;
7463 }
7464 }
7465 break;
7466 default:
7467 goto illegal_op;
7468 }
7469 break;
7470 case 0x108: /* invd */
7471 case 0x109: /* wbinvd */
7472 if (s->cpl != 0) {
7473 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7474 } else {
7475 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7476 /* nothing to do */
7477 }
7478 break;
7479 case 0x63: /* arpl or movslS (x86_64) */
7480 #ifdef TARGET_X86_64
7481 if (CODE64(s)) {
7482 int d_ot;
7483 /* d_ot is the size of destination */
7484 d_ot = dflag;
7485
7486 modrm = cpu_ldub_code(env, s->pc++);
7487 reg = ((modrm >> 3) & 7) | rex_r;
7488 mod = (modrm >> 6) & 3;
7489 rm = (modrm & 7) | REX_B(s);
7490
7491 if (mod == 3) {
7492 gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
7493 /* sign extend */
7494 if (d_ot == MO_64) {
7495 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7496 }
7497 gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
7498 } else {
7499 gen_lea_modrm(env, s, modrm);
7500 gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
7501 gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
7502 }
7503 } else
7504 #endif
7505 {
7506 int label1;
7507 TCGv t0, t1, t2, a0;
7508
7509 if (!s->pe || s->vm86)
7510 goto illegal_op;
7511 t0 = tcg_temp_local_new();
7512 t1 = tcg_temp_local_new();
7513 t2 = tcg_temp_local_new();
7514 ot = MO_16;
7515 modrm = cpu_ldub_code(env, s->pc++);
7516 reg = (modrm >> 3) & 7;
7517 mod = (modrm >> 6) & 3;
7518 rm = modrm & 7;
7519 if (mod != 3) {
7520 gen_lea_modrm(env, s, modrm);
7521 gen_op_ld_v(s, ot, t0, cpu_A0);
7522 a0 = tcg_temp_local_new();
7523 tcg_gen_mov_tl(a0, cpu_A0);
7524 } else {
7525 gen_op_mov_v_reg(ot, t0, rm);
7526 TCGV_UNUSED(a0);
7527 }
7528 gen_op_mov_v_reg(ot, t1, reg);
7529 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7530 tcg_gen_andi_tl(t1, t1, 3);
7531 tcg_gen_movi_tl(t2, 0);
7532 label1 = gen_new_label();
7533 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7534 tcg_gen_andi_tl(t0, t0, ~3);
7535 tcg_gen_or_tl(t0, t0, t1);
7536 tcg_gen_movi_tl(t2, CC_Z);
7537 gen_set_label(label1);
7538 if (mod != 3) {
7539 gen_op_st_v(s, ot, t0, a0);
7540 tcg_temp_free(a0);
7541 } else {
7542 gen_op_mov_reg_v(ot, rm, t0);
7543 }
7544 gen_compute_eflags(s);
7545 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7546 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7547 tcg_temp_free(t0);
7548 tcg_temp_free(t1);
7549 tcg_temp_free(t2);
7550 }
7551 break;
7552 case 0x102: /* lar */
7553 case 0x103: /* lsl */
7554 {
7555 int label1;
7556 TCGv t0;
7557 if (!s->pe || s->vm86)
7558 goto illegal_op;
7559 ot = dflag != MO_16 ? MO_32 : MO_16;
7560 modrm = cpu_ldub_code(env, s->pc++);
7561 reg = ((modrm >> 3) & 7) | rex_r;
7562 gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
7563 t0 = tcg_temp_local_new();
7564 gen_update_cc_op(s);
7565 if (b == 0x102) {
7566 gen_helper_lar(t0, cpu_env, cpu_T[0]);
7567 } else {
7568 gen_helper_lsl(t0, cpu_env, cpu_T[0]);
7569 }
7570 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7571 label1 = gen_new_label();
7572 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7573 gen_op_mov_reg_v(ot, reg, t0);
7574 gen_set_label(label1);
7575 set_cc_op(s, CC_OP_EFLAGS);
7576 tcg_temp_free(t0);
7577 }
7578 break;
7579 case 0x118:
7580 modrm = cpu_ldub_code(env, s->pc++);
7581 mod = (modrm >> 6) & 3;
7582 op = (modrm >> 3) & 7;
7583 switch(op) {
7584 case 0: /* prefetchnta */
7585 case 1: /* prefetchnt0 */
7586 case 2: /* prefetchnt0 */
7587 case 3: /* prefetchnt0 */
7588 if (mod == 3)
7589 goto illegal_op;
7590 gen_lea_modrm(env, s, modrm);
7591 /* nothing more to do */
7592 break;
7593 default: /* nop (multi byte) */
7594 gen_nop_modrm(env, s, modrm);
7595 break;
7596 }
7597 break;
7598 case 0x119 ... 0x11f: /* nop (multi byte) */
7599 modrm = cpu_ldub_code(env, s->pc++);
7600 gen_nop_modrm(env, s, modrm);
7601 break;
7602 case 0x120: /* mov reg, crN */
7603 case 0x122: /* mov crN, reg */
7604 if (s->cpl != 0) {
7605 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7606 } else {
7607 modrm = cpu_ldub_code(env, s->pc++);
7608 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7609 * AMD documentation (24594.pdf) and testing of
7610 * intel 386 and 486 processors all show that the mod bits
7611 * are assumed to be 1's, regardless of actual values.
7612 */
7613 rm = (modrm & 7) | REX_B(s);
7614 reg = ((modrm >> 3) & 7) | rex_r;
7615 if (CODE64(s))
7616 ot = MO_64;
7617 else
7618 ot = MO_32;
7619 if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7620 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7621 reg = 8;
7622 }
7623 switch(reg) {
7624 case 0:
7625 case 2:
7626 case 3:
7627 case 4:
7628 case 8:
7629 gen_update_cc_op(s);
7630 gen_jmp_im(pc_start - s->cs_base);
7631 if (b & 2) {
7632 gen_op_mov_v_reg(ot, cpu_T[0], rm);
7633 gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
7634 cpu_T[0]);
7635 gen_jmp_im(s->pc - s->cs_base);
7636 gen_eob(s);
7637 } else {
7638 gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
7639 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
7640 }
7641 break;
7642 default:
7643 goto illegal_op;
7644 }
7645 }
7646 break;
7647 case 0x121: /* mov reg, drN */
7648 case 0x123: /* mov drN, reg */
7649 if (s->cpl != 0) {
7650 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7651 } else {
7652 modrm = cpu_ldub_code(env, s->pc++);
7653 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7654 * AMD documentation (24594.pdf) and testing of
7655 * intel 386 and 486 processors all show that the mod bits
7656 * are assumed to be 1's, regardless of actual values.
7657 */
7658 rm = (modrm & 7) | REX_B(s);
7659 reg = ((modrm >> 3) & 7) | rex_r;
7660 if (CODE64(s))
7661 ot = MO_64;
7662 else
7663 ot = MO_32;
7664 /* XXX: do it dynamically with CR4.DE bit */
7665 if (reg == 4 || reg == 5 || reg >= 8)
7666 goto illegal_op;
7667 if (b & 2) {
7668 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7669 gen_op_mov_v_reg(ot, cpu_T[0], rm);
7670 gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
7671 gen_jmp_im(s->pc - s->cs_base);
7672 gen_eob(s);
7673 } else {
7674 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7675 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7676 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
7677 }
7678 }
7679 break;
7680 case 0x106: /* clts */
7681 if (s->cpl != 0) {
7682 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7683 } else {
7684 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7685 gen_helper_clts(cpu_env);
7686 /* abort block because static cpu state changed */
7687 gen_jmp_im(s->pc - s->cs_base);
7688 gen_eob(s);
7689 }
7690 break;
7691 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7692 case 0x1c3: /* MOVNTI reg, mem */
7693 if (!(s->cpuid_features & CPUID_SSE2))
7694 goto illegal_op;
7695 ot = mo_64_32(dflag);
7696 modrm = cpu_ldub_code(env, s->pc++);
7697 mod = (modrm >> 6) & 3;
7698 if (mod == 3)
7699 goto illegal_op;
7700 reg = ((modrm >> 3) & 7) | rex_r;
7701 /* generate a generic store */
7702 gen_ldst_modrm(env, s, modrm, ot, reg, 1);
7703 break;
7704 case 0x1ae:
7705 modrm = cpu_ldub_code(env, s->pc++);
7706 mod = (modrm >> 6) & 3;
7707 op = (modrm >> 3) & 7;
7708 switch(op) {
7709 case 0: /* fxsave */
7710 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7711 (s->prefix & PREFIX_LOCK))
7712 goto illegal_op;
7713 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7714 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7715 break;
7716 }
7717 gen_lea_modrm(env, s, modrm);
7718 gen_update_cc_op(s);
7719 gen_jmp_im(pc_start - s->cs_base);
7720 gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
7721 break;
7722 case 1: /* fxrstor */
7723 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7724 (s->prefix & PREFIX_LOCK))
7725 goto illegal_op;
7726 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7727 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7728 break;
7729 }
7730 gen_lea_modrm(env, s, modrm);
7731 gen_update_cc_op(s);
7732 gen_jmp_im(pc_start - s->cs_base);
7733 gen_helper_fxrstor(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
7734 break;
7735 case 2: /* ldmxcsr */
7736 case 3: /* stmxcsr */
7737 if (s->flags & HF_TS_MASK) {
7738 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7739 break;
7740 }
7741 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7742 mod == 3)
7743 goto illegal_op;
7744 gen_lea_modrm(env, s, modrm);
7745 if (op == 2) {
7746 tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
7747 s->mem_index, MO_LEUL);
7748 gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
7749 } else {
7750 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7751 gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
7752 }
7753 break;
7754 case 5: /* lfence */
7755 case 6: /* mfence */
7756 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2))
7757 goto illegal_op;
7758 break;
7759 case 7: /* sfence / clflush */
7760 if ((modrm & 0xc7) == 0xc0) {
7761 /* sfence */
7762 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7763 if (!(s->cpuid_features & CPUID_SSE))
7764 goto illegal_op;
7765 } else {
7766 /* clflush */
7767 if (!(s->cpuid_features & CPUID_CLFLUSH))
7768 goto illegal_op;
7769 gen_lea_modrm(env, s, modrm);
7770 }
7771 break;
7772 default:
7773 goto illegal_op;
7774 }
7775 break;
7776 case 0x10d: /* 3DNow! prefetch(w) */
7777 modrm = cpu_ldub_code(env, s->pc++);
7778 mod = (modrm >> 6) & 3;
7779 if (mod == 3)
7780 goto illegal_op;
7781 gen_lea_modrm(env, s, modrm);
7782 /* ignore for now */
7783 break;
7784 case 0x1aa: /* rsm */
7785 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7786 if (!(s->flags & HF_SMM_MASK))
7787 goto illegal_op;
7788 gen_update_cc_op(s);
7789 gen_jmp_im(s->pc - s->cs_base);
7790 gen_helper_rsm(cpu_env);
7791 gen_eob(s);
7792 break;
7793 case 0x1b8: /* SSE4.2 popcnt */
7794 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7795 PREFIX_REPZ)
7796 goto illegal_op;
7797 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7798 goto illegal_op;
7799
7800 modrm = cpu_ldub_code(env, s->pc++);
7801 reg = ((modrm >> 3) & 7) | rex_r;
7802
7803 if (s->prefix & PREFIX_DATA) {
7804 ot = MO_16;
7805 } else {
7806 ot = mo_64_32(dflag);
7807 }
7808
7809 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
7810 gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
7811 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
7812
7813 set_cc_op(s, CC_OP_EFLAGS);
7814 break;
7815 case 0x10e ... 0x10f:
7816 /* 3DNow! instructions, ignore prefixes */
7817 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7818 case 0x110 ... 0x117:
7819 case 0x128 ... 0x12f:
7820 case 0x138 ... 0x13a:
7821 case 0x150 ... 0x179:
7822 case 0x17c ... 0x17f:
7823 case 0x1c2:
7824 case 0x1c4 ... 0x1c6:
7825 case 0x1d0 ... 0x1fe:
7826 gen_sse(env, s, b, pc_start, rex_r);
7827 break;
7828 default:
7829 goto illegal_op;
7830 }
7831 /* lock generation */
7832 if (s->prefix & PREFIX_LOCK)
7833 gen_helper_unlock();
7834 return s->pc;
7835 illegal_op:
7836 if (s->prefix & PREFIX_LOCK)
7837 gen_helper_unlock();
7838 /* XXX: ensure that no lock was generated */
7839 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7840 return s->pc;
7841 }
7842
7843 void optimize_flags_init(void)
7844 {
7845 static const char reg_names[CPU_NB_REGS][4] = {
7846 #ifdef TARGET_X86_64
7847 [R_EAX] = "rax",
7848 [R_EBX] = "rbx",
7849 [R_ECX] = "rcx",
7850 [R_EDX] = "rdx",
7851 [R_ESI] = "rsi",
7852 [R_EDI] = "rdi",
7853 [R_EBP] = "rbp",
7854 [R_ESP] = "rsp",
7855 [8] = "r8",
7856 [9] = "r9",
7857 [10] = "r10",
7858 [11] = "r11",
7859 [12] = "r12",
7860 [13] = "r13",
7861 [14] = "r14",
7862 [15] = "r15",
7863 #else
7864 [R_EAX] = "eax",
7865 [R_EBX] = "ebx",
7866 [R_ECX] = "ecx",
7867 [R_EDX] = "edx",
7868 [R_ESI] = "esi",
7869 [R_EDI] = "edi",
7870 [R_EBP] = "ebp",
7871 [R_ESP] = "esp",
7872 #endif
7873 };
7874 int i;
7875
7876 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7877 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7878 offsetof(CPUX86State, cc_op), "cc_op");
7879 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst),
7880 "cc_dst");
7881 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src),
7882 "cc_src");
7883 cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src2),
7884 "cc_src2");
7885
7886 for (i = 0; i < CPU_NB_REGS; ++i) {
7887 cpu_regs[i] = tcg_global_mem_new(TCG_AREG0,
7888 offsetof(CPUX86State, regs[i]),
7889 reg_names[i]);
7890 }
7891 }
7892
7893 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7894 basic block 'tb'. If search_pc is TRUE, also generate PC
7895 information for each intermediate instruction. */
7896 static inline void gen_intermediate_code_internal(X86CPU *cpu,
7897 TranslationBlock *tb,
7898 bool search_pc)
7899 {
7900 CPUState *cs = CPU(cpu);
7901 CPUX86State *env = &cpu->env;
7902 DisasContext dc1, *dc = &dc1;
7903 target_ulong pc_ptr;
7904 uint16_t *gen_opc_end;
7905 CPUBreakpoint *bp;
7906 int j, lj;
7907 uint64_t flags;
7908 target_ulong pc_start;
7909 target_ulong cs_base;
7910 int num_insns;
7911 int max_insns;
7912
7913 /* generate intermediate code */
7914 pc_start = tb->pc;
7915 cs_base = tb->cs_base;
7916 flags = tb->flags;
7917
7918 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7919 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7920 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7921 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7922 dc->f_st = 0;
7923 dc->vm86 = (flags >> VM_SHIFT) & 1;
7924 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7925 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7926 dc->tf = (flags >> TF_SHIFT) & 1;
7927 dc->singlestep_enabled = cs->singlestep_enabled;
7928 dc->cc_op = CC_OP_DYNAMIC;
7929 dc->cc_op_dirty = false;
7930 dc->cs_base = cs_base;
7931 dc->tb = tb;
7932 dc->popl_esp_hack = 0;
7933 /* select memory access functions */
7934 dc->mem_index = 0;
7935 if (flags & HF_SOFTMMU_MASK) {
7936 dc->mem_index = cpu_mmu_index(env);
7937 }
7938 dc->cpuid_features = env->features[FEAT_1_EDX];
7939 dc->cpuid_ext_features = env->features[FEAT_1_ECX];
7940 dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX];
7941 dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
7942 dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
7943 #ifdef TARGET_X86_64
7944 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7945 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7946 #endif
7947 dc->flags = flags;
7948 dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
7949 (flags & HF_INHIBIT_IRQ_MASK)
7950 #ifndef CONFIG_SOFTMMU
7951 || (flags & HF_SOFTMMU_MASK)
7952 #endif
7953 );
7954 #if 0
7955 /* check addseg logic */
7956 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7957 printf("ERROR addseg\n");
7958 #endif
7959
7960 cpu_T[0] = tcg_temp_new();
7961 cpu_T[1] = tcg_temp_new();
7962 cpu_A0 = tcg_temp_new();
7963
7964 cpu_tmp0 = tcg_temp_new();
7965 cpu_tmp1_i64 = tcg_temp_new_i64();
7966 cpu_tmp2_i32 = tcg_temp_new_i32();
7967 cpu_tmp3_i32 = tcg_temp_new_i32();
7968 cpu_tmp4 = tcg_temp_new();
7969 cpu_ptr0 = tcg_temp_new_ptr();
7970 cpu_ptr1 = tcg_temp_new_ptr();
7971 cpu_cc_srcT = tcg_temp_local_new();
7972
7973 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
7974
7975 dc->is_jmp = DISAS_NEXT;
7976 pc_ptr = pc_start;
7977 lj = -1;
7978 num_insns = 0;
7979 max_insns = tb->cflags & CF_COUNT_MASK;
7980 if (max_insns == 0)
7981 max_insns = CF_COUNT_MASK;
7982
7983 gen_tb_start();
7984 for(;;) {
7985 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
7986 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
7987 if (bp->pc == pc_ptr &&
7988 !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
7989 gen_debug(dc, pc_ptr - dc->cs_base);
7990 break;
7991 }
7992 }
7993 }
7994 if (search_pc) {
7995 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
7996 if (lj < j) {
7997 lj++;
7998 while (lj < j)
7999 tcg_ctx.gen_opc_instr_start[lj++] = 0;
8000 }
8001 tcg_ctx.gen_opc_pc[lj] = pc_ptr;
8002 gen_opc_cc_op[lj] = dc->cc_op;
8003 tcg_ctx.gen_opc_instr_start[lj] = 1;
8004 tcg_ctx.gen_opc_icount[lj] = num_insns;
8005 }
8006 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8007 gen_io_start();
8008
8009 pc_ptr = disas_insn(env, dc, pc_ptr);
8010 num_insns++;
8011 /* stop translation if indicated */
8012 if (dc->is_jmp)
8013 break;
8014 /* if single step mode, we generate only one instruction and
8015 generate an exception */
8016 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
8017 the flag and abort the translation to give the irqs a
8018 change to be happen */
8019 if (dc->tf || dc->singlestep_enabled ||
8020 (flags & HF_INHIBIT_IRQ_MASK)) {
8021 gen_jmp_im(pc_ptr - dc->cs_base);
8022 gen_eob(dc);
8023 break;
8024 }
8025 /* if too long translation, stop generation too */
8026 if (tcg_ctx.gen_opc_ptr >= gen_opc_end ||
8027 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
8028 num_insns >= max_insns) {
8029 gen_jmp_im(pc_ptr - dc->cs_base);
8030 gen_eob(dc);
8031 break;
8032 }
8033 if (singlestep) {
8034 gen_jmp_im(pc_ptr - dc->cs_base);
8035 gen_eob(dc);
8036 break;
8037 }
8038 }
8039 if (tb->cflags & CF_LAST_IO)
8040 gen_io_end();
8041 gen_tb_end(tb, num_insns);
8042 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
8043 /* we don't forget to fill the last values */
8044 if (search_pc) {
8045 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
8046 lj++;
8047 while (lj <= j)
8048 tcg_ctx.gen_opc_instr_start[lj++] = 0;
8049 }
8050
8051 #ifdef DEBUG_DISAS
8052 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8053 int disas_flags;
8054 qemu_log("----------------\n");
8055 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8056 #ifdef TARGET_X86_64
8057 if (dc->code64)
8058 disas_flags = 2;
8059 else
8060 #endif
8061 disas_flags = !dc->code32;
8062 log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags);
8063 qemu_log("\n");
8064 }
8065 #endif
8066
8067 if (!search_pc) {
8068 tb->size = pc_ptr - pc_start;
8069 tb->icount = num_insns;
8070 }
8071 }
8072
8073 void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
8074 {
8075 gen_intermediate_code_internal(x86_env_get_cpu(env), tb, false);
8076 }
8077
8078 void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
8079 {
8080 gen_intermediate_code_internal(x86_env_get_cpu(env), tb, true);
8081 }
8082
8083 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)
8084 {
8085 int cc_op;
8086 #ifdef DEBUG_DISAS
8087 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
8088 int i;
8089 qemu_log("RESTORE:\n");
8090 for(i = 0;i <= pc_pos; i++) {
8091 if (tcg_ctx.gen_opc_instr_start[i]) {
8092 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i,
8093 tcg_ctx.gen_opc_pc[i]);
8094 }
8095 }
8096 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
8097 pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base,
8098 (uint32_t)tb->cs_base);
8099 }
8100 #endif
8101 env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base;
8102 cc_op = gen_opc_cc_op[pc_pos];
8103 if (cc_op != CC_OP_DYNAMIC)
8104 env->cc_op = cc_op;
8105 }
QEmu