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pc-dimm: pass in the machine and to the MemoryHotplugState
[qemu.git] / hw / sparc / sun4m.c
blob0ee779fafe362914aa931fdef32ebb8e197b7007
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m_iommu.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
36 #include "net/net.h"
37 #include "hw/boards.h"
38 #include "hw/scsi/esp.h"
39 #include "hw/isa/isa.h"
40 #include "hw/nvram/sun_nvram.h"
41 #include "hw/nvram/chrp_nvram.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/empty_slot.h"
45 #include "hw/loader.h"
46 #include "elf.h"
47 #include "trace.h"
48 #include "qemu/cutils.h"
49
50 /*
51 * Sun4m architecture was used in the following machines:
52 *
53 * SPARCserver 6xxMP/xx
54 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
55 * SPARCclassic X (4/10)
56 * SPARCstation LX/ZX (4/30)
57 * SPARCstation Voyager
58 * SPARCstation 10/xx, SPARCserver 10/xx
59 * SPARCstation 5, SPARCserver 5
60 * SPARCstation 20/xx, SPARCserver 20
61 * SPARCstation 4
62 *
63 * See for example: http://www.sunhelp.org/faq/sunref1.html
64 */
65
66 #define KERNEL_LOAD_ADDR 0x00004000
67 #define CMDLINE_ADDR 0x007ff000
68 #define INITRD_LOAD_ADDR 0x00800000
69 #define PROM_SIZE_MAX (1024 * 1024)
70 #define PROM_VADDR 0xffd00000
71 #define PROM_FILENAME "openbios-sparc32"
72 #define CFG_ADDR 0xd00000510ULL
73 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
74 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
75 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
76
77 #define MAX_CPUS 16
78 #define MAX_PILS 16
79 #define MAX_VSIMMS 4
80
81 #define ESCC_CLOCK 4915200
82
83 struct sun4m_hwdef {
84 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
85 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
86 hwaddr serial_base, fd_base;
87 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
88 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
89 hwaddr bpp_base, dbri_base, sx_base;
90 struct {
91 hwaddr reg_base, vram_base;
92 } vsimm[MAX_VSIMMS];
93 hwaddr ecc_base;
94 uint64_t max_mem;
95 uint32_t ecc_version;
96 uint32_t iommu_version;
97 uint16_t machine_id;
98 uint8_t nvram_machine_id;
99 };
100
101 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
102 Error **errp)
103 {
104 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
105 }
106
107 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
108 const char *cmdline, const char *boot_devices,
109 ram_addr_t RAM_size, uint32_t kernel_size,
110 int width, int height, int depth,
111 int nvram_machine_id, const char *arch)
112 {
113 unsigned int i;
114 int sysp_end;
115 uint8_t image[0x1ff0];
116 NvramClass *k = NVRAM_GET_CLASS(nvram);
117
118 memset(image, '\0', sizeof(image));
119
120 /* OpenBIOS nvram variables partition */
121 sysp_end = chrp_nvram_create_system_partition(image, 0);
122
123 /* Free space partition */
124 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
125
126 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
127 nvram_machine_id);
128
129 for (i = 0; i < sizeof(image); i++) {
130 (k->write)(nvram, i, image[i]);
131 }
132 }
133
134 void cpu_check_irqs(CPUSPARCState *env)
135 {
136 CPUState *cs;
137
138 /* We should be holding the BQL before we mess with IRQs */
139 g_assert(qemu_mutex_iothread_locked());
140
141 if (env->pil_in && (env->interrupt_index == 0 ||
142 (env->interrupt_index & ~15) == TT_EXTINT)) {
143 unsigned int i;
144
145 for (i = 15; i > 0; i--) {
146 if (env->pil_in & (1 << i)) {
147 int old_interrupt = env->interrupt_index;
148
149 env->interrupt_index = TT_EXTINT | i;
150 if (old_interrupt != env->interrupt_index) {
151 cs = CPU(sparc_env_get_cpu(env));
152 trace_sun4m_cpu_interrupt(i);
153 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
154 }
155 break;
156 }
157 }
158 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
159 cs = CPU(sparc_env_get_cpu(env));
160 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
161 env->interrupt_index = 0;
162 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
163 }
164 }
165
166 static void cpu_kick_irq(SPARCCPU *cpu)
167 {
168 CPUSPARCState *env = &cpu->env;
169 CPUState *cs = CPU(cpu);
170
171 cs->halted = 0;
172 cpu_check_irqs(env);
173 qemu_cpu_kick(cs);
174 }
175
176 static void cpu_set_irq(void *opaque, int irq, int level)
177 {
178 SPARCCPU *cpu = opaque;
179 CPUSPARCState *env = &cpu->env;
180
181 if (level) {
182 trace_sun4m_cpu_set_irq_raise(irq);
183 env->pil_in |= 1 << irq;
184 cpu_kick_irq(cpu);
185 } else {
186 trace_sun4m_cpu_set_irq_lower(irq);
187 env->pil_in &= ~(1 << irq);
188 cpu_check_irqs(env);
189 }
190 }
191
192 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
193 {
194 }
195
196 static void main_cpu_reset(void *opaque)
197 {
198 SPARCCPU *cpu = opaque;
199 CPUState *cs = CPU(cpu);
200
201 cpu_reset(cs);
202 cs->halted = 0;
203 }
204
205 static void secondary_cpu_reset(void *opaque)
206 {
207 SPARCCPU *cpu = opaque;
208 CPUState *cs = CPU(cpu);
209
210 cpu_reset(cs);
211 cs->halted = 1;
212 }
213
214 static void cpu_halt_signal(void *opaque, int irq, int level)
215 {
216 if (level && current_cpu) {
217 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
218 }
219 }
220
221 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
222 {
223 return addr - 0xf0000000ULL;
224 }
225
226 static unsigned long sun4m_load_kernel(const char *kernel_filename,
227 const char *initrd_filename,
228 ram_addr_t RAM_size)
229 {
230 int linux_boot;
231 unsigned int i;
232 long initrd_size, kernel_size;
233 uint8_t *ptr;
234
235 linux_boot = (kernel_filename != NULL);
236
237 kernel_size = 0;
238 if (linux_boot) {
239 int bswap_needed;
240
241 #ifdef BSWAP_NEEDED
242 bswap_needed = 1;
243 #else
244 bswap_needed = 0;
245 #endif
246 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
247 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
248 if (kernel_size < 0)
249 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
250 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
251 TARGET_PAGE_SIZE);
252 if (kernel_size < 0)
253 kernel_size = load_image_targphys(kernel_filename,
254 KERNEL_LOAD_ADDR,
255 RAM_size - KERNEL_LOAD_ADDR);
256 if (kernel_size < 0) {
257 error_report("could not load kernel '%s'", kernel_filename);
258 exit(1);
259 }
260
261 /* load initrd */
262 initrd_size = 0;
263 if (initrd_filename) {
264 initrd_size = load_image_targphys(initrd_filename,
265 INITRD_LOAD_ADDR,
266 RAM_size - INITRD_LOAD_ADDR);
267 if (initrd_size < 0) {
268 error_report("could not load initial ram disk '%s'",
269 initrd_filename);
270 exit(1);
271 }
272 }
273 if (initrd_size > 0) {
274 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
275 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
276 if (ldl_p(ptr) == 0x48647253) { // HdrS
277 stl_p(ptr + 16, INITRD_LOAD_ADDR);
278 stl_p(ptr + 20, initrd_size);
279 break;
280 }
281 }
282 }
283 }
284 return kernel_size;
285 }
286
287 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
288 {
289 DeviceState *dev;
290 SysBusDevice *s;
291
292 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
293 qdev_prop_set_uint32(dev, "version", version);
294 qdev_init_nofail(dev);
295 s = SYS_BUS_DEVICE(dev);
296 sysbus_connect_irq(s, 0, irq);
297 sysbus_mmio_map(s, 0, addr);
298
299 return s;
300 }
301
302 static void *sparc32_dma_init(hwaddr dma_base,
303 hwaddr esp_base, qemu_irq espdma_irq,
304 hwaddr le_base, qemu_irq ledma_irq)
305 {
306 DeviceState *dma;
307 ESPDMADeviceState *espdma;
308 LEDMADeviceState *ledma;
309 SysBusESPState *esp;
310 SysBusPCNetState *lance;
311
312 dma = qdev_create(NULL, TYPE_SPARC32_DMA);
313 qdev_init_nofail(dma);
314 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
315
316 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
317 OBJECT(dma), "espdma"));
318 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
319
320 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
321 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
322 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
323
324 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
325 OBJECT(dma), "ledma"));
326 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
327
328 lance = SYSBUS_PCNET(object_resolve_path_component(
329 OBJECT(ledma), "lance"));
330 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
331
332 return dma;
333 }
334
335 static DeviceState *slavio_intctl_init(hwaddr addr,
336 hwaddr addrg,
337 qemu_irq **parent_irq)
338 {
339 DeviceState *dev;
340 SysBusDevice *s;
341 unsigned int i, j;
342
343 dev = qdev_create(NULL, "slavio_intctl");
344 qdev_init_nofail(dev);
345
346 s = SYS_BUS_DEVICE(dev);
347
348 for (i = 0; i < MAX_CPUS; i++) {
349 for (j = 0; j < MAX_PILS; j++) {
350 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
351 }
352 }
353 sysbus_mmio_map(s, 0, addrg);
354 for (i = 0; i < MAX_CPUS; i++) {
355 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
356 }
357
358 return dev;
359 }
360
361 #define SYS_TIMER_OFFSET 0x10000ULL
362 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
363
364 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
365 qemu_irq *cpu_irqs, unsigned int num_cpus)
366 {
367 DeviceState *dev;
368 SysBusDevice *s;
369 unsigned int i;
370
371 dev = qdev_create(NULL, "slavio_timer");
372 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
373 qdev_init_nofail(dev);
374 s = SYS_BUS_DEVICE(dev);
375 sysbus_connect_irq(s, 0, master_irq);
376 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
377
378 for (i = 0; i < MAX_CPUS; i++) {
379 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
380 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
381 }
382 }
383
384 static qemu_irq slavio_system_powerdown;
385
386 static void slavio_powerdown_req(Notifier *n, void *opaque)
387 {
388 qemu_irq_raise(slavio_system_powerdown);
389 }
390
391 static Notifier slavio_system_powerdown_notifier = {
392 .notify = slavio_powerdown_req
393 };
394
395 #define MISC_LEDS 0x01600000
396 #define MISC_CFG 0x01800000
397 #define MISC_DIAG 0x01a00000
398 #define MISC_MDM 0x01b00000
399 #define MISC_SYS 0x01f00000
400
401 static void slavio_misc_init(hwaddr base,
402 hwaddr aux1_base,
403 hwaddr aux2_base, qemu_irq irq,
404 qemu_irq fdc_tc)
405 {
406 DeviceState *dev;
407 SysBusDevice *s;
408
409 dev = qdev_create(NULL, "slavio_misc");
410 qdev_init_nofail(dev);
411 s = SYS_BUS_DEVICE(dev);
412 if (base) {
413 /* 8 bit registers */
414 /* Slavio control */
415 sysbus_mmio_map(s, 0, base + MISC_CFG);
416 /* Diagnostics */
417 sysbus_mmio_map(s, 1, base + MISC_DIAG);
418 /* Modem control */
419 sysbus_mmio_map(s, 2, base + MISC_MDM);
420 /* 16 bit registers */
421 /* ss600mp diag LEDs */
422 sysbus_mmio_map(s, 3, base + MISC_LEDS);
423 /* 32 bit registers */
424 /* System control */
425 sysbus_mmio_map(s, 4, base + MISC_SYS);
426 }
427 if (aux1_base) {
428 /* AUX 1 (Misc System Functions) */
429 sysbus_mmio_map(s, 5, aux1_base);
430 }
431 if (aux2_base) {
432 /* AUX 2 (Software Powerdown Control) */
433 sysbus_mmio_map(s, 6, aux2_base);
434 }
435 sysbus_connect_irq(s, 0, irq);
436 sysbus_connect_irq(s, 1, fdc_tc);
437 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
438 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
439 }
440
441 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
442 {
443 DeviceState *dev;
444 SysBusDevice *s;
445
446 dev = qdev_create(NULL, "eccmemctl");
447 qdev_prop_set_uint32(dev, "version", version);
448 qdev_init_nofail(dev);
449 s = SYS_BUS_DEVICE(dev);
450 sysbus_connect_irq(s, 0, irq);
451 sysbus_mmio_map(s, 0, base);
452 if (version == 0) { // SS-600MP only
453 sysbus_mmio_map(s, 1, base + 0x1000);
454 }
455 }
456
457 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
458 {
459 DeviceState *dev;
460 SysBusDevice *s;
461
462 dev = qdev_create(NULL, "apc");
463 qdev_init_nofail(dev);
464 s = SYS_BUS_DEVICE(dev);
465 /* Power management (APC) XXX: not a Slavio device */
466 sysbus_mmio_map(s, 0, power_base);
467 sysbus_connect_irq(s, 0, cpu_halt);
468 }
469
470 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
471 int height, int depth)
472 {
473 DeviceState *dev;
474 SysBusDevice *s;
475
476 dev = qdev_create(NULL, "SUNW,tcx");
477 qdev_prop_set_uint32(dev, "vram_size", vram_size);
478 qdev_prop_set_uint16(dev, "width", width);
479 qdev_prop_set_uint16(dev, "height", height);
480 qdev_prop_set_uint16(dev, "depth", depth);
481 qdev_init_nofail(dev);
482 s = SYS_BUS_DEVICE(dev);
483
484 /* 10/ROM : FCode ROM */
485 sysbus_mmio_map(s, 0, addr);
486 /* 2/STIP : Stipple */
487 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
488 /* 3/BLIT : Blitter */
489 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
490 /* 5/RSTIP : Raw Stipple */
491 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
492 /* 6/RBLIT : Raw Blitter */
493 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
494 /* 7/TEC : Transform Engine */
495 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
496 /* 8/CMAP : DAC */
497 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
498 /* 9/THC : */
499 if (depth == 8) {
500 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
501 } else {
502 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
503 }
504 /* 11/DHC : */
505 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
506 /* 12/ALT : */
507 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
508 /* 0/DFB8 : 8-bit plane */
509 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
510 /* 1/DFB24 : 24bit plane */
511 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
512 /* 4/RDFB32: Raw framebuffer. Control plane */
513 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
514 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
515 if (depth == 8) {
516 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
517 }
518
519 sysbus_connect_irq(s, 0, irq);
520 }
521
522 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
523 int height, int depth)
524 {
525 DeviceState *dev;
526 SysBusDevice *s;
527
528 dev = qdev_create(NULL, "cgthree");
529 qdev_prop_set_uint32(dev, "vram-size", vram_size);
530 qdev_prop_set_uint16(dev, "width", width);
531 qdev_prop_set_uint16(dev, "height", height);
532 qdev_prop_set_uint16(dev, "depth", depth);
533 qdev_init_nofail(dev);
534 s = SYS_BUS_DEVICE(dev);
535
536 /* FCode ROM */
537 sysbus_mmio_map(s, 0, addr);
538 /* DAC */
539 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
540 /* 8-bit plane */
541 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
542
543 sysbus_connect_irq(s, 0, irq);
544 }
545
546 /* NCR89C100/MACIO Internal ID register */
547
548 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
549
550 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
551
552 static void idreg_init(hwaddr addr)
553 {
554 DeviceState *dev;
555 SysBusDevice *s;
556
557 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
558 qdev_init_nofail(dev);
559 s = SYS_BUS_DEVICE(dev);
560
561 sysbus_mmio_map(s, 0, addr);
562 cpu_physical_memory_write_rom(&address_space_memory,
563 addr, idreg_data, sizeof(idreg_data));
564 }
565
566 #define MACIO_ID_REGISTER(obj) \
567 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
568
569 typedef struct IDRegState {
570 SysBusDevice parent_obj;
571
572 MemoryRegion mem;
573 } IDRegState;
574
575 static void idreg_init1(Object *obj)
576 {
577 IDRegState *s = MACIO_ID_REGISTER(obj);
578 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
579
580 memory_region_init_ram_nomigrate(&s->mem, obj,
581 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
582 vmstate_register_ram_global(&s->mem);
583 memory_region_set_readonly(&s->mem, true);
584 sysbus_init_mmio(dev, &s->mem);
585 }
586
587 static const TypeInfo idreg_info = {
588 .name = TYPE_MACIO_ID_REGISTER,
589 .parent = TYPE_SYS_BUS_DEVICE,
590 .instance_size = sizeof(IDRegState),
591 .instance_init = idreg_init1,
592 };
593
594 #define TYPE_TCX_AFX "tcx_afx"
595 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
596
597 typedef struct AFXState {
598 SysBusDevice parent_obj;
599
600 MemoryRegion mem;
601 } AFXState;
602
603 /* SS-5 TCX AFX register */
604 static void afx_init(hwaddr addr)
605 {
606 DeviceState *dev;
607 SysBusDevice *s;
608
609 dev = qdev_create(NULL, TYPE_TCX_AFX);
610 qdev_init_nofail(dev);
611 s = SYS_BUS_DEVICE(dev);
612
613 sysbus_mmio_map(s, 0, addr);
614 }
615
616 static void afx_init1(Object *obj)
617 {
618 AFXState *s = TCX_AFX(obj);
619 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
620
621 memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal);
622 vmstate_register_ram_global(&s->mem);
623 sysbus_init_mmio(dev, &s->mem);
624 }
625
626 static const TypeInfo afx_info = {
627 .name = TYPE_TCX_AFX,
628 .parent = TYPE_SYS_BUS_DEVICE,
629 .instance_size = sizeof(AFXState),
630 .instance_init = afx_init1,
631 };
632
633 #define TYPE_OPENPROM "openprom"
634 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
635
636 typedef struct PROMState {
637 SysBusDevice parent_obj;
638
639 MemoryRegion prom;
640 } PROMState;
641
642 /* Boot PROM (OpenBIOS) */
643 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
644 {
645 hwaddr *base_addr = (hwaddr *)opaque;
646 return addr + *base_addr - PROM_VADDR;
647 }
648
649 static void prom_init(hwaddr addr, const char *bios_name)
650 {
651 DeviceState *dev;
652 SysBusDevice *s;
653 char *filename;
654 int ret;
655
656 dev = qdev_create(NULL, TYPE_OPENPROM);
657 qdev_init_nofail(dev);
658 s = SYS_BUS_DEVICE(dev);
659
660 sysbus_mmio_map(s, 0, addr);
661
662 /* load boot prom */
663 if (bios_name == NULL) {
664 bios_name = PROM_FILENAME;
665 }
666 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
667 if (filename) {
668 ret = load_elf(filename, translate_prom_address, &addr, NULL,
669 NULL, NULL, 1, EM_SPARC, 0, 0);
670 if (ret < 0 || ret > PROM_SIZE_MAX) {
671 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
672 }
673 g_free(filename);
674 } else {
675 ret = -1;
676 }
677 if (ret < 0 || ret > PROM_SIZE_MAX) {
678 error_report("could not load prom '%s'", bios_name);
679 exit(1);
680 }
681 }
682
683 static void prom_init1(Object *obj)
684 {
685 PROMState *s = OPENPROM(obj);
686 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
687
688 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX,
689 &error_fatal);
690 vmstate_register_ram_global(&s->prom);
691 memory_region_set_readonly(&s->prom, true);
692 sysbus_init_mmio(dev, &s->prom);
693 }
694
695 static Property prom_properties[] = {
696 {/* end of property list */},
697 };
698
699 static void prom_class_init(ObjectClass *klass, void *data)
700 {
701 DeviceClass *dc = DEVICE_CLASS(klass);
702
703 dc->props = prom_properties;
704 }
705
706 static const TypeInfo prom_info = {
707 .name = TYPE_OPENPROM,
708 .parent = TYPE_SYS_BUS_DEVICE,
709 .instance_size = sizeof(PROMState),
710 .class_init = prom_class_init,
711 .instance_init = prom_init1,
712 };
713
714 #define TYPE_SUN4M_MEMORY "memory"
715 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
716
717 typedef struct RamDevice {
718 SysBusDevice parent_obj;
719
720 MemoryRegion ram;
721 uint64_t size;
722 } RamDevice;
723
724 /* System RAM */
725 static void ram_realize(DeviceState *dev, Error **errp)
726 {
727 RamDevice *d = SUN4M_RAM(dev);
728 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
729
730 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
731 d->size);
732 sysbus_init_mmio(sbd, &d->ram);
733 }
734
735 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
736 uint64_t max_mem)
737 {
738 DeviceState *dev;
739 SysBusDevice *s;
740 RamDevice *d;
741
742 /* allocate RAM */
743 if ((uint64_t)RAM_size > max_mem) {
744 error_report("Too much memory for this machine: %d, maximum %d",
745 (unsigned int)(RAM_size / (1024 * 1024)),
746 (unsigned int)(max_mem / (1024 * 1024)));
747 exit(1);
748 }
749 dev = qdev_create(NULL, "memory");
750 s = SYS_BUS_DEVICE(dev);
751
752 d = SUN4M_RAM(dev);
753 d->size = RAM_size;
754 qdev_init_nofail(dev);
755
756 sysbus_mmio_map(s, 0, addr);
757 }
758
759 static Property ram_properties[] = {
760 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
761 DEFINE_PROP_END_OF_LIST(),
762 };
763
764 static void ram_class_init(ObjectClass *klass, void *data)
765 {
766 DeviceClass *dc = DEVICE_CLASS(klass);
767
768 dc->realize = ram_realize;
769 dc->props = ram_properties;
770 }
771
772 static const TypeInfo ram_info = {
773 .name = TYPE_SUN4M_MEMORY,
774 .parent = TYPE_SYS_BUS_DEVICE,
775 .instance_size = sizeof(RamDevice),
776 .class_init = ram_class_init,
777 };
778
779 static void cpu_devinit(const char *cpu_type, unsigned int id,
780 uint64_t prom_addr, qemu_irq **cpu_irqs)
781 {
782 CPUState *cs;
783 SPARCCPU *cpu;
784 CPUSPARCState *env;
785
786 cpu = SPARC_CPU(cpu_create(cpu_type));
787 env = &cpu->env;
788
789 cpu_sparc_set_id(env, id);
790 if (id == 0) {
791 qemu_register_reset(main_cpu_reset, cpu);
792 } else {
793 qemu_register_reset(secondary_cpu_reset, cpu);
794 cs = CPU(cpu);
795 cs->halted = 1;
796 }
797 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
798 env->prom_addr = prom_addr;
799 }
800
801 static void dummy_fdc_tc(void *opaque, int irq, int level)
802 {
803 }
804
805 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
806 MachineState *machine)
807 {
808 DeviceState *slavio_intctl;
809 unsigned int i;
810 void *nvram;
811 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
812 qemu_irq fdc_tc;
813 unsigned long kernel_size;
814 DriveInfo *fd[MAX_FD];
815 FWCfgState *fw_cfg;
816 unsigned int num_vsimms;
817 DeviceState *dev;
818 SysBusDevice *s;
819
820 /* init CPUs */
821 for(i = 0; i < smp_cpus; i++) {
822 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
823 }
824
825 for (i = smp_cpus; i < MAX_CPUS; i++)
826 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
827
828
829 /* set up devices */
830 ram_init(0, machine->ram_size, hwdef->max_mem);
831 /* models without ECC don't trap when missing ram is accessed */
832 if (!hwdef->ecc_base) {
833 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
834 }
835
836 prom_init(hwdef->slavio_base, bios_name);
837
838 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
839 hwdef->intctl_base + 0x10000ULL,
840 cpu_irqs);
841
842 for (i = 0; i < 32; i++) {
843 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
844 }
845 for (i = 0; i < MAX_CPUS; i++) {
846 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
847 }
848
849 if (hwdef->idreg_base) {
850 idreg_init(hwdef->idreg_base);
851 }
852
853 if (hwdef->afx_base) {
854 afx_init(hwdef->afx_base);
855 }
856
857 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
858
859 if (hwdef->iommu_pad_base) {
860 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
861 Software shouldn't use aliased addresses, neither should it crash
862 when does. Using empty_slot instead of aliasing can help with
863 debugging such accesses */
864 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
865 }
866
867 sparc32_dma_init(hwdef->dma_base,
868 hwdef->esp_base, slavio_irq[18],
869 hwdef->le_base, slavio_irq[16]);
870
871 if (graphic_depth != 8 && graphic_depth != 24) {
872 error_report("Unsupported depth: %d", graphic_depth);
873 exit (1);
874 }
875 num_vsimms = 0;
876 if (num_vsimms == 0) {
877 if (vga_interface_type == VGA_CG3) {
878 if (graphic_depth != 8) {
879 error_report("Unsupported depth: %d", graphic_depth);
880 exit(1);
881 }
882
883 if (!(graphic_width == 1024 && graphic_height == 768) &&
884 !(graphic_width == 1152 && graphic_height == 900)) {
885 error_report("Unsupported resolution: %d x %d", graphic_width,
886 graphic_height);
887 exit(1);
888 }
889
890 /* sbus irq 5 */
891 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
892 graphic_width, graphic_height, graphic_depth);
893 } else {
894 /* If no display specified, default to TCX */
895 if (graphic_depth != 8 && graphic_depth != 24) {
896 error_report("Unsupported depth: %d", graphic_depth);
897 exit(1);
898 }
899
900 if (!(graphic_width == 1024 && graphic_height == 768)) {
901 error_report("Unsupported resolution: %d x %d",
902 graphic_width, graphic_height);
903 exit(1);
904 }
905
906 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
907 graphic_width, graphic_height, graphic_depth);
908 }
909 }
910
911 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
912 /* vsimm registers probed by OBP */
913 if (hwdef->vsimm[i].reg_base) {
914 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
915 }
916 }
917
918 if (hwdef->sx_base) {
919 empty_slot_init(hwdef->sx_base, 0x2000);
920 }
921
922 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
923
924 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
925
926 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
927 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
928 dev = qdev_create(NULL, TYPE_ESCC);
929 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
930 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
931 qdev_prop_set_uint32(dev, "it_shift", 1);
932 qdev_prop_set_chr(dev, "chrB", NULL);
933 qdev_prop_set_chr(dev, "chrA", NULL);
934 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
935 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
936 qdev_init_nofail(dev);
937 s = SYS_BUS_DEVICE(dev);
938 sysbus_connect_irq(s, 0, slavio_irq[14]);
939 sysbus_connect_irq(s, 1, slavio_irq[14]);
940 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
941
942 dev = qdev_create(NULL, TYPE_ESCC);
943 qdev_prop_set_uint32(dev, "disabled", 0);
944 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
945 qdev_prop_set_uint32(dev, "it_shift", 1);
946 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
947 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
948 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
949 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
950 qdev_init_nofail(dev);
951
952 s = SYS_BUS_DEVICE(dev);
953 sysbus_connect_irq(s, 0, slavio_irq[15]);
954 sysbus_connect_irq(s, 1, slavio_irq[15]);
955 sysbus_mmio_map(s, 0, hwdef->serial_base);
956
957 if (hwdef->apc_base) {
958 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
959 }
960
961 if (hwdef->fd_base) {
962 /* there is zero or one floppy drive */
963 memset(fd, 0, sizeof(fd));
964 fd[0] = drive_get(IF_FLOPPY, 0, 0);
965 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
966 &fdc_tc);
967 } else {
968 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
969 }
970
971 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
972 slavio_irq[30], fdc_tc);
973
974 if (hwdef->cs_base) {
975 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
976 slavio_irq[5]);
977 }
978
979 if (hwdef->dbri_base) {
980 /* ISDN chip with attached CS4215 audio codec */
981 /* prom space */
982 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
983 /* reg space */
984 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
985 }
986
987 if (hwdef->bpp_base) {
988 /* parallel port */
989 empty_slot_init(hwdef->bpp_base, 0x20);
990 }
991
992 kernel_size = sun4m_load_kernel(machine->kernel_filename,
993 machine->initrd_filename,
994 machine->ram_size);
995
996 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
997 machine->boot_order, machine->ram_size, kernel_size,
998 graphic_width, graphic_height, graphic_depth,
999 hwdef->nvram_machine_id, "Sun4m");
1000
1001 if (hwdef->ecc_base)
1002 ecc_init(hwdef->ecc_base, slavio_irq[28],
1003 hwdef->ecc_version);
1004
1005 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1006 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1007 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1008 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1009 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1010 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1011 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1012 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1013 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1014 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1015 if (machine->kernel_cmdline) {
1016 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1017 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1018 machine->kernel_cmdline);
1019 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1020 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1021 strlen(machine->kernel_cmdline) + 1);
1022 } else {
1023 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1024 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1025 }
1026 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1027 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1028 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1029 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1030 }
1031
1032 enum {
1033 ss5_id = 32,
1034 vger_id,
1035 lx_id,
1036 ss4_id,
1037 scls_id,
1038 sbook_id,
1039 ss10_id = 64,
1040 ss20_id,
1041 ss600mp_id,
1042 };
1043
1044 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1045 /* SS-5 */
1046 {
1047 .iommu_base = 0x10000000,
1048 .iommu_pad_base = 0x10004000,
1049 .iommu_pad_len = 0x0fffb000,
1050 .tcx_base = 0x50000000,
1051 .cs_base = 0x6c000000,
1052 .slavio_base = 0x70000000,
1053 .ms_kb_base = 0x71000000,
1054 .serial_base = 0x71100000,
1055 .nvram_base = 0x71200000,
1056 .fd_base = 0x71400000,
1057 .counter_base = 0x71d00000,
1058 .intctl_base = 0x71e00000,
1059 .idreg_base = 0x78000000,
1060 .dma_base = 0x78400000,
1061 .esp_base = 0x78800000,
1062 .le_base = 0x78c00000,
1063 .apc_base = 0x6a000000,
1064 .afx_base = 0x6e000000,
1065 .aux1_base = 0x71900000,
1066 .aux2_base = 0x71910000,
1067 .nvram_machine_id = 0x80,
1068 .machine_id = ss5_id,
1069 .iommu_version = 0x05000000,
1070 .max_mem = 0x10000000,
1071 },
1072 /* SS-10 */
1073 {
1074 .iommu_base = 0xfe0000000ULL,
1075 .tcx_base = 0xe20000000ULL,
1076 .slavio_base = 0xff0000000ULL,
1077 .ms_kb_base = 0xff1000000ULL,
1078 .serial_base = 0xff1100000ULL,
1079 .nvram_base = 0xff1200000ULL,
1080 .fd_base = 0xff1700000ULL,
1081 .counter_base = 0xff1300000ULL,
1082 .intctl_base = 0xff1400000ULL,
1083 .idreg_base = 0xef0000000ULL,
1084 .dma_base = 0xef0400000ULL,
1085 .esp_base = 0xef0800000ULL,
1086 .le_base = 0xef0c00000ULL,
1087 .apc_base = 0xefa000000ULL, // XXX should not exist
1088 .aux1_base = 0xff1800000ULL,
1089 .aux2_base = 0xff1a01000ULL,
1090 .ecc_base = 0xf00000000ULL,
1091 .ecc_version = 0x10000000, // version 0, implementation 1
1092 .nvram_machine_id = 0x72,
1093 .machine_id = ss10_id,
1094 .iommu_version = 0x03000000,
1095 .max_mem = 0xf00000000ULL,
1096 },
1097 /* SS-600MP */
1098 {
1099 .iommu_base = 0xfe0000000ULL,
1100 .tcx_base = 0xe20000000ULL,
1101 .slavio_base = 0xff0000000ULL,
1102 .ms_kb_base = 0xff1000000ULL,
1103 .serial_base = 0xff1100000ULL,
1104 .nvram_base = 0xff1200000ULL,
1105 .counter_base = 0xff1300000ULL,
1106 .intctl_base = 0xff1400000ULL,
1107 .dma_base = 0xef0081000ULL,
1108 .esp_base = 0xef0080000ULL,
1109 .le_base = 0xef0060000ULL,
1110 .apc_base = 0xefa000000ULL, // XXX should not exist
1111 .aux1_base = 0xff1800000ULL,
1112 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1113 .ecc_base = 0xf00000000ULL,
1114 .ecc_version = 0x00000000, // version 0, implementation 0
1115 .nvram_machine_id = 0x71,
1116 .machine_id = ss600mp_id,
1117 .iommu_version = 0x01000000,
1118 .max_mem = 0xf00000000ULL,
1119 },
1120 /* SS-20 */
1121 {
1122 .iommu_base = 0xfe0000000ULL,
1123 .tcx_base = 0xe20000000ULL,
1124 .slavio_base = 0xff0000000ULL,
1125 .ms_kb_base = 0xff1000000ULL,
1126 .serial_base = 0xff1100000ULL,
1127 .nvram_base = 0xff1200000ULL,
1128 .fd_base = 0xff1700000ULL,
1129 .counter_base = 0xff1300000ULL,
1130 .intctl_base = 0xff1400000ULL,
1131 .idreg_base = 0xef0000000ULL,
1132 .dma_base = 0xef0400000ULL,
1133 .esp_base = 0xef0800000ULL,
1134 .le_base = 0xef0c00000ULL,
1135 .bpp_base = 0xef4800000ULL,
1136 .apc_base = 0xefa000000ULL, // XXX should not exist
1137 .aux1_base = 0xff1800000ULL,
1138 .aux2_base = 0xff1a01000ULL,
1139 .dbri_base = 0xee0000000ULL,
1140 .sx_base = 0xf80000000ULL,
1141 .vsimm = {
1142 {
1143 .reg_base = 0x9c000000ULL,
1144 .vram_base = 0xfc000000ULL
1145 }, {
1146 .reg_base = 0x90000000ULL,
1147 .vram_base = 0xf0000000ULL
1148 }, {
1149 .reg_base = 0x94000000ULL
1150 }, {
1151 .reg_base = 0x98000000ULL
1152 }
1153 },
1154 .ecc_base = 0xf00000000ULL,
1155 .ecc_version = 0x20000000, // version 0, implementation 2
1156 .nvram_machine_id = 0x72,
1157 .machine_id = ss20_id,
1158 .iommu_version = 0x13000000,
1159 .max_mem = 0xf00000000ULL,
1160 },
1161 /* Voyager */
1162 {
1163 .iommu_base = 0x10000000,
1164 .tcx_base = 0x50000000,
1165 .slavio_base = 0x70000000,
1166 .ms_kb_base = 0x71000000,
1167 .serial_base = 0x71100000,
1168 .nvram_base = 0x71200000,
1169 .fd_base = 0x71400000,
1170 .counter_base = 0x71d00000,
1171 .intctl_base = 0x71e00000,
1172 .idreg_base = 0x78000000,
1173 .dma_base = 0x78400000,
1174 .esp_base = 0x78800000,
1175 .le_base = 0x78c00000,
1176 .apc_base = 0x71300000, // pmc
1177 .aux1_base = 0x71900000,
1178 .aux2_base = 0x71910000,
1179 .nvram_machine_id = 0x80,
1180 .machine_id = vger_id,
1181 .iommu_version = 0x05000000,
1182 .max_mem = 0x10000000,
1183 },
1184 /* LX */
1185 {
1186 .iommu_base = 0x10000000,
1187 .iommu_pad_base = 0x10004000,
1188 .iommu_pad_len = 0x0fffb000,
1189 .tcx_base = 0x50000000,
1190 .slavio_base = 0x70000000,
1191 .ms_kb_base = 0x71000000,
1192 .serial_base = 0x71100000,
1193 .nvram_base = 0x71200000,
1194 .fd_base = 0x71400000,
1195 .counter_base = 0x71d00000,
1196 .intctl_base = 0x71e00000,
1197 .idreg_base = 0x78000000,
1198 .dma_base = 0x78400000,
1199 .esp_base = 0x78800000,
1200 .le_base = 0x78c00000,
1201 .aux1_base = 0x71900000,
1202 .aux2_base = 0x71910000,
1203 .nvram_machine_id = 0x80,
1204 .machine_id = lx_id,
1205 .iommu_version = 0x04000000,
1206 .max_mem = 0x10000000,
1207 },
1208 /* SS-4 */
1209 {
1210 .iommu_base = 0x10000000,
1211 .tcx_base = 0x50000000,
1212 .cs_base = 0x6c000000,
1213 .slavio_base = 0x70000000,
1214 .ms_kb_base = 0x71000000,
1215 .serial_base = 0x71100000,
1216 .nvram_base = 0x71200000,
1217 .fd_base = 0x71400000,
1218 .counter_base = 0x71d00000,
1219 .intctl_base = 0x71e00000,
1220 .idreg_base = 0x78000000,
1221 .dma_base = 0x78400000,
1222 .esp_base = 0x78800000,
1223 .le_base = 0x78c00000,
1224 .apc_base = 0x6a000000,
1225 .aux1_base = 0x71900000,
1226 .aux2_base = 0x71910000,
1227 .nvram_machine_id = 0x80,
1228 .machine_id = ss4_id,
1229 .iommu_version = 0x05000000,
1230 .max_mem = 0x10000000,
1231 },
1232 /* SPARCClassic */
1233 {
1234 .iommu_base = 0x10000000,
1235 .tcx_base = 0x50000000,
1236 .slavio_base = 0x70000000,
1237 .ms_kb_base = 0x71000000,
1238 .serial_base = 0x71100000,
1239 .nvram_base = 0x71200000,
1240 .fd_base = 0x71400000,
1241 .counter_base = 0x71d00000,
1242 .intctl_base = 0x71e00000,
1243 .idreg_base = 0x78000000,
1244 .dma_base = 0x78400000,
1245 .esp_base = 0x78800000,
1246 .le_base = 0x78c00000,
1247 .apc_base = 0x6a000000,
1248 .aux1_base = 0x71900000,
1249 .aux2_base = 0x71910000,
1250 .nvram_machine_id = 0x80,
1251 .machine_id = scls_id,
1252 .iommu_version = 0x05000000,
1253 .max_mem = 0x10000000,
1254 },
1255 /* SPARCbook */
1256 {
1257 .iommu_base = 0x10000000,
1258 .tcx_base = 0x50000000, // XXX
1259 .slavio_base = 0x70000000,
1260 .ms_kb_base = 0x71000000,
1261 .serial_base = 0x71100000,
1262 .nvram_base = 0x71200000,
1263 .fd_base = 0x71400000,
1264 .counter_base = 0x71d00000,
1265 .intctl_base = 0x71e00000,
1266 .idreg_base = 0x78000000,
1267 .dma_base = 0x78400000,
1268 .esp_base = 0x78800000,
1269 .le_base = 0x78c00000,
1270 .apc_base = 0x6a000000,
1271 .aux1_base = 0x71900000,
1272 .aux2_base = 0x71910000,
1273 .nvram_machine_id = 0x80,
1274 .machine_id = sbook_id,
1275 .iommu_version = 0x05000000,
1276 .max_mem = 0x10000000,
1277 },
1278 };
1279
1280 /* SPARCstation 5 hardware initialisation */
1281 static void ss5_init(MachineState *machine)
1282 {
1283 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1284 }
1285
1286 /* SPARCstation 10 hardware initialisation */
1287 static void ss10_init(MachineState *machine)
1288 {
1289 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1290 }
1291
1292 /* SPARCserver 600MP hardware initialisation */
1293 static void ss600mp_init(MachineState *machine)
1294 {
1295 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1296 }
1297
1298 /* SPARCstation 20 hardware initialisation */
1299 static void ss20_init(MachineState *machine)
1300 {
1301 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1302 }
1303
1304 /* SPARCstation Voyager hardware initialisation */
1305 static void vger_init(MachineState *machine)
1306 {
1307 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1308 }
1309
1310 /* SPARCstation LX hardware initialisation */
1311 static void ss_lx_init(MachineState *machine)
1312 {
1313 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1314 }
1315
1316 /* SPARCstation 4 hardware initialisation */
1317 static void ss4_init(MachineState *machine)
1318 {
1319 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1320 }
1321
1322 /* SPARCClassic hardware initialisation */
1323 static void scls_init(MachineState *machine)
1324 {
1325 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1326 }
1327
1328 /* SPARCbook hardware initialisation */
1329 static void sbook_init(MachineState *machine)
1330 {
1331 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1332 }
1333
1334 static void ss5_class_init(ObjectClass *oc, void *data)
1335 {
1336 MachineClass *mc = MACHINE_CLASS(oc);
1337
1338 mc->desc = "Sun4m platform, SPARCstation 5";
1339 mc->init = ss5_init;
1340 mc->block_default_type = IF_SCSI;
1341 mc->is_default = 1;
1342 mc->default_boot_order = "c";
1343 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1344 }
1345
1346 static const TypeInfo ss5_type = {
1347 .name = MACHINE_TYPE_NAME("SS-5"),
1348 .parent = TYPE_MACHINE,
1349 .class_init = ss5_class_init,
1350 };
1351
1352 static void ss10_class_init(ObjectClass *oc, void *data)
1353 {
1354 MachineClass *mc = MACHINE_CLASS(oc);
1355
1356 mc->desc = "Sun4m platform, SPARCstation 10";
1357 mc->init = ss10_init;
1358 mc->block_default_type = IF_SCSI;
1359 mc->max_cpus = 4;
1360 mc->default_boot_order = "c";
1361 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1362 }
1363
1364 static const TypeInfo ss10_type = {
1365 .name = MACHINE_TYPE_NAME("SS-10"),
1366 .parent = TYPE_MACHINE,
1367 .class_init = ss10_class_init,
1368 };
1369
1370 static void ss600mp_class_init(ObjectClass *oc, void *data)
1371 {
1372 MachineClass *mc = MACHINE_CLASS(oc);
1373
1374 mc->desc = "Sun4m platform, SPARCserver 600MP";
1375 mc->init = ss600mp_init;
1376 mc->block_default_type = IF_SCSI;
1377 mc->max_cpus = 4;
1378 mc->default_boot_order = "c";
1379 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1380 }
1381
1382 static const TypeInfo ss600mp_type = {
1383 .name = MACHINE_TYPE_NAME("SS-600MP"),
1384 .parent = TYPE_MACHINE,
1385 .class_init = ss600mp_class_init,
1386 };
1387
1388 static void ss20_class_init(ObjectClass *oc, void *data)
1389 {
1390 MachineClass *mc = MACHINE_CLASS(oc);
1391
1392 mc->desc = "Sun4m platform, SPARCstation 20";
1393 mc->init = ss20_init;
1394 mc->block_default_type = IF_SCSI;
1395 mc->max_cpus = 4;
1396 mc->default_boot_order = "c";
1397 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1398 }
1399
1400 static const TypeInfo ss20_type = {
1401 .name = MACHINE_TYPE_NAME("SS-20"),
1402 .parent = TYPE_MACHINE,
1403 .class_init = ss20_class_init,
1404 };
1405
1406 static void voyager_class_init(ObjectClass *oc, void *data)
1407 {
1408 MachineClass *mc = MACHINE_CLASS(oc);
1409
1410 mc->desc = "Sun4m platform, SPARCstation Voyager";
1411 mc->init = vger_init;
1412 mc->block_default_type = IF_SCSI;
1413 mc->default_boot_order = "c";
1414 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1415 }
1416
1417 static const TypeInfo voyager_type = {
1418 .name = MACHINE_TYPE_NAME("Voyager"),
1419 .parent = TYPE_MACHINE,
1420 .class_init = voyager_class_init,
1421 };
1422
1423 static void ss_lx_class_init(ObjectClass *oc, void *data)
1424 {
1425 MachineClass *mc = MACHINE_CLASS(oc);
1426
1427 mc->desc = "Sun4m platform, SPARCstation LX";
1428 mc->init = ss_lx_init;
1429 mc->block_default_type = IF_SCSI;
1430 mc->default_boot_order = "c";
1431 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1432 }
1433
1434 static const TypeInfo ss_lx_type = {
1435 .name = MACHINE_TYPE_NAME("LX"),
1436 .parent = TYPE_MACHINE,
1437 .class_init = ss_lx_class_init,
1438 };
1439
1440 static void ss4_class_init(ObjectClass *oc, void *data)
1441 {
1442 MachineClass *mc = MACHINE_CLASS(oc);
1443
1444 mc->desc = "Sun4m platform, SPARCstation 4";
1445 mc->init = ss4_init;
1446 mc->block_default_type = IF_SCSI;
1447 mc->default_boot_order = "c";
1448 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1449 }
1450
1451 static const TypeInfo ss4_type = {
1452 .name = MACHINE_TYPE_NAME("SS-4"),
1453 .parent = TYPE_MACHINE,
1454 .class_init = ss4_class_init,
1455 };
1456
1457 static void scls_class_init(ObjectClass *oc, void *data)
1458 {
1459 MachineClass *mc = MACHINE_CLASS(oc);
1460
1461 mc->desc = "Sun4m platform, SPARCClassic";
1462 mc->init = scls_init;
1463 mc->block_default_type = IF_SCSI;
1464 mc->default_boot_order = "c";
1465 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1466 }
1467
1468 static const TypeInfo scls_type = {
1469 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1470 .parent = TYPE_MACHINE,
1471 .class_init = scls_class_init,
1472 };
1473
1474 static void sbook_class_init(ObjectClass *oc, void *data)
1475 {
1476 MachineClass *mc = MACHINE_CLASS(oc);
1477
1478 mc->desc = "Sun4m platform, SPARCbook";
1479 mc->init = sbook_init;
1480 mc->block_default_type = IF_SCSI;
1481 mc->default_boot_order = "c";
1482 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1483 }
1484
1485 static const TypeInfo sbook_type = {
1486 .name = MACHINE_TYPE_NAME("SPARCbook"),
1487 .parent = TYPE_MACHINE,
1488 .class_init = sbook_class_init,
1489 };
1490
1491 static void sun4m_register_types(void)
1492 {
1493 type_register_static(&idreg_info);
1494 type_register_static(&afx_info);
1495 type_register_static(&prom_info);
1496 type_register_static(&ram_info);
1497
1498 type_register_static(&ss5_type);
1499 type_register_static(&ss10_type);
1500 type_register_static(&ss600mp_type);
1501 type_register_static(&ss20_type);
1502 type_register_static(&voyager_type);
1503 type_register_static(&ss_lx_type);
1504 type_register_static(&ss4_type);
1505 type_register_static(&scls_type);
1506 type_register_static(&sbook_type);
1507 }
1508
1509 type_init(sun4m_register_types)
QEmu