2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, see <http://www.gnu.org/licenses/>.
14 * Copyright IBM Corp. 2008
16 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 /* This file implements emulation of the 32-bit PCI controller found in some
20 * 4xx SoCs, such as the 440EP. */
22 #include "qemu/osdep.h"
24 #include "hw/ppc/ppc.h"
25 #include "hw/ppc/ppc4xx.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/pci_host.h"
28 #include "exec/address-spaces.h"
43 #define PPC4xx_PCI_HOST_BRIDGE(obj) \
44 OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
46 #define PPC4xx_PCI_NR_PMMS 3
47 #define PPC4xx_PCI_NR_PTMS 2
49 struct PPC4xxPCIState
{
50 PCIHostState parent_obj
;
52 struct PCIMasterMap pmm
[PPC4xx_PCI_NR_PMMS
];
53 struct PCITargetMap ptm
[PPC4xx_PCI_NR_PTMS
];
56 MemoryRegion container
;
59 typedef struct PPC4xxPCIState PPC4xxPCIState
;
61 #define PCIC0_CFGADDR 0x0
62 #define PCIC0_CFGDATA 0x4
64 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
66 #define PCIL0_PMM0LA 0x0
67 #define PCIL0_PMM0MA 0x4
68 #define PCIL0_PMM0PCILA 0x8
69 #define PCIL0_PMM0PCIHA 0xc
70 #define PCIL0_PMM1LA 0x10
71 #define PCIL0_PMM1MA 0x14
72 #define PCIL0_PMM1PCILA 0x18
73 #define PCIL0_PMM1PCIHA 0x1c
74 #define PCIL0_PMM2LA 0x20
75 #define PCIL0_PMM2MA 0x24
76 #define PCIL0_PMM2PCILA 0x28
77 #define PCIL0_PMM2PCIHA 0x2c
79 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
81 #define PCIL0_PTM1MS 0x30
82 #define PCIL0_PTM1LA 0x34
83 #define PCIL0_PTM2MS 0x38
84 #define PCIL0_PTM2LA 0x3c
85 #define PCI_REG_BASE 0x800000
86 #define PCI_REG_SIZE 0x40
88 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
90 static void ppc4xx_pci_reg_write4(void *opaque
, hwaddr offset
,
91 uint64_t value
, unsigned size
)
93 struct PPC4xxPCIState
*pci
= opaque
;
95 /* We ignore all target attempts at PCI configuration, effectively
96 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
100 pci
->pmm
[0].la
= value
;
103 pci
->pmm
[0].ma
= value
;
105 case PCIL0_PMM0PCIHA
:
106 pci
->pmm
[0].pciha
= value
;
108 case PCIL0_PMM0PCILA
:
109 pci
->pmm
[0].pcila
= value
;
113 pci
->pmm
[1].la
= value
;
116 pci
->pmm
[1].ma
= value
;
118 case PCIL0_PMM1PCIHA
:
119 pci
->pmm
[1].pciha
= value
;
121 case PCIL0_PMM1PCILA
:
122 pci
->pmm
[1].pcila
= value
;
126 pci
->pmm
[2].la
= value
;
129 pci
->pmm
[2].ma
= value
;
131 case PCIL0_PMM2PCIHA
:
132 pci
->pmm
[2].pciha
= value
;
134 case PCIL0_PMM2PCILA
:
135 pci
->pmm
[2].pcila
= value
;
139 pci
->ptm
[0].ms
= value
;
142 pci
->ptm
[0].la
= value
;
145 pci
->ptm
[1].ms
= value
;
148 pci
->ptm
[1].la
= value
;
152 printf("%s: unhandled PCI internal register 0x%lx\n", __func__
,
153 (unsigned long)offset
);
158 static uint64_t ppc4xx_pci_reg_read4(void *opaque
, hwaddr offset
,
161 struct PPC4xxPCIState
*pci
= opaque
;
166 value
= pci
->pmm
[0].la
;
169 value
= pci
->pmm
[0].ma
;
171 case PCIL0_PMM0PCIHA
:
172 value
= pci
->pmm
[0].pciha
;
174 case PCIL0_PMM0PCILA
:
175 value
= pci
->pmm
[0].pcila
;
179 value
= pci
->pmm
[1].la
;
182 value
= pci
->pmm
[1].ma
;
184 case PCIL0_PMM1PCIHA
:
185 value
= pci
->pmm
[1].pciha
;
187 case PCIL0_PMM1PCILA
:
188 value
= pci
->pmm
[1].pcila
;
192 value
= pci
->pmm
[2].la
;
195 value
= pci
->pmm
[2].ma
;
197 case PCIL0_PMM2PCIHA
:
198 value
= pci
->pmm
[2].pciha
;
200 case PCIL0_PMM2PCILA
:
201 value
= pci
->pmm
[2].pcila
;
205 value
= pci
->ptm
[0].ms
;
208 value
= pci
->ptm
[0].la
;
211 value
= pci
->ptm
[1].ms
;
214 value
= pci
->ptm
[1].la
;
218 printf("%s: invalid PCI internal register 0x%lx\n", __func__
,
219 (unsigned long)offset
);
226 static const MemoryRegionOps pci_reg_ops
= {
227 .read
= ppc4xx_pci_reg_read4
,
228 .write
= ppc4xx_pci_reg_write4
,
229 .endianness
= DEVICE_LITTLE_ENDIAN
,
232 static void ppc4xx_pci_reset(void *opaque
)
234 struct PPC4xxPCIState
*pci
= opaque
;
236 memset(pci
->pmm
, 0, sizeof(pci
->pmm
));
237 memset(pci
->ptm
, 0, sizeof(pci
->ptm
));
240 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
241 * may need further refactoring for other boards. */
242 static int ppc4xx_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
244 int slot
= pci_dev
->devfn
>> 3;
246 trace_ppc4xx_pci_map_irq(pci_dev
->devfn
, irq_num
, slot
);
251 static void ppc4xx_pci_set_irq(void *opaque
, int irq_num
, int level
)
253 qemu_irq
*pci_irqs
= opaque
;
255 trace_ppc4xx_pci_set_irq(irq_num
);
257 fprintf(stderr
, "%s: PCI irq %d\n", __func__
, irq_num
);
260 qemu_set_irq(pci_irqs
[irq_num
], level
);
263 static const VMStateDescription vmstate_pci_master_map
= {
264 .name
= "pci_master_map",
266 .minimum_version_id
= 0,
267 .fields
= (VMStateField
[]) {
268 VMSTATE_UINT32(la
, struct PCIMasterMap
),
269 VMSTATE_UINT32(ma
, struct PCIMasterMap
),
270 VMSTATE_UINT32(pcila
, struct PCIMasterMap
),
271 VMSTATE_UINT32(pciha
, struct PCIMasterMap
),
272 VMSTATE_END_OF_LIST()
276 static const VMStateDescription vmstate_pci_target_map
= {
277 .name
= "pci_target_map",
279 .minimum_version_id
= 0,
280 .fields
= (VMStateField
[]) {
281 VMSTATE_UINT32(ms
, struct PCITargetMap
),
282 VMSTATE_UINT32(la
, struct PCITargetMap
),
283 VMSTATE_END_OF_LIST()
287 static const VMStateDescription vmstate_ppc4xx_pci
= {
288 .name
= "ppc4xx_pci",
290 .minimum_version_id
= 1,
291 .fields
= (VMStateField
[]) {
292 VMSTATE_STRUCT_ARRAY(pmm
, PPC4xxPCIState
, PPC4xx_PCI_NR_PMMS
, 1,
293 vmstate_pci_master_map
,
294 struct PCIMasterMap
),
295 VMSTATE_STRUCT_ARRAY(ptm
, PPC4xxPCIState
, PPC4xx_PCI_NR_PTMS
, 1,
296 vmstate_pci_target_map
,
297 struct PCITargetMap
),
298 VMSTATE_END_OF_LIST()
302 /* XXX Interrupt acknowledge cycles not supported. */
303 static int ppc4xx_pcihost_initfn(SysBusDevice
*dev
)
310 h
= PCI_HOST_BRIDGE(dev
);
311 s
= PPC4xx_PCI_HOST_BRIDGE(dev
);
313 for (i
= 0; i
< ARRAY_SIZE(s
->irq
); i
++) {
314 sysbus_init_irq(dev
, &s
->irq
[i
]);
317 b
= pci_register_root_bus(DEVICE(dev
), NULL
, ppc4xx_pci_set_irq
,
318 ppc4xx_pci_map_irq
, s
->irq
, get_system_memory(),
319 get_system_io(), 0, 4, TYPE_PCI_BUS
);
322 pci_create_simple(b
, 0, "ppc4xx-host-bridge");
324 /* XXX split into 2 memory regions, one for config space, one for regs */
325 memory_region_init(&s
->container
, OBJECT(s
), "pci-container", PCI_ALL_SIZE
);
326 memory_region_init_io(&h
->conf_mem
, OBJECT(s
), &pci_host_conf_le_ops
, h
,
328 memory_region_init_io(&h
->data_mem
, OBJECT(s
), &pci_host_data_le_ops
, h
,
330 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pci_reg_ops
, s
,
331 "pci.reg", PCI_REG_SIZE
);
332 memory_region_add_subregion(&s
->container
, PCIC0_CFGADDR
, &h
->conf_mem
);
333 memory_region_add_subregion(&s
->container
, PCIC0_CFGDATA
, &h
->data_mem
);
334 memory_region_add_subregion(&s
->container
, PCI_REG_BASE
, &s
->iomem
);
335 sysbus_init_mmio(dev
, &s
->container
);
336 qemu_register_reset(ppc4xx_pci_reset
, s
);
341 static void ppc4xx_host_bridge_class_init(ObjectClass
*klass
, void *data
)
343 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
344 DeviceClass
*dc
= DEVICE_CLASS(klass
);
346 dc
->desc
= "Host bridge";
347 k
->vendor_id
= PCI_VENDOR_ID_IBM
;
348 k
->device_id
= PCI_DEVICE_ID_IBM_440GX
;
349 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
351 * PCI-facing part of the host bridge, not usable without the
352 * host-facing part, which can't be device_add'ed, yet.
354 dc
->user_creatable
= false;
357 static const TypeInfo ppc4xx_host_bridge_info
= {
358 .name
= "ppc4xx-host-bridge",
359 .parent
= TYPE_PCI_DEVICE
,
360 .instance_size
= sizeof(PCIDevice
),
361 .class_init
= ppc4xx_host_bridge_class_init
,
362 .interfaces
= (InterfaceInfo
[]) {
363 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
368 static void ppc4xx_pcihost_class_init(ObjectClass
*klass
, void *data
)
370 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
371 DeviceClass
*dc
= DEVICE_CLASS(klass
);
373 k
->init
= ppc4xx_pcihost_initfn
;
374 dc
->vmsd
= &vmstate_ppc4xx_pci
;
377 static const TypeInfo ppc4xx_pcihost_info
= {
378 .name
= TYPE_PPC4xx_PCI_HOST_BRIDGE
,
379 .parent
= TYPE_PCI_HOST_BRIDGE
,
380 .instance_size
= sizeof(PPC4xxPCIState
),
381 .class_init
= ppc4xx_pcihost_class_init
,
384 static void ppc4xx_pci_register_types(void)
386 type_register_static(&ppc4xx_pcihost_info
);
387 type_register_static(&ppc4xx_host_bridge_info
);
390 type_init(ppc4xx_pci_register_types
)