2 * QEMU PowerPC 440 embedded processors emulation
4 * Copyright (c) 2012 François Revol
5 * Copyright (c) 2016-2018 BALATON Zoltan
7 * This work is licensed under the GNU GPL license version 2 or later.
11 #include "qemu/osdep.h"
12 #include "qemu-common.h"
13 #include "qemu/cutils.h"
14 #include "qemu/error-report.h"
15 #include "qapi/error.h"
18 #include "exec/address-spaces.h"
19 #include "exec/memory.h"
20 #include "hw/ppc/ppc.h"
21 #include "hw/pci/pci.h"
22 #include "sysemu/block-backend.h"
23 #include "hw/ppc/ppc440.h"
25 /*****************************************************************************/
26 /* L2 Cache as SRAM */
29 DCR_L2CACHE_BASE
= 0x30,
30 DCR_L2CACHE_CFG
= DCR_L2CACHE_BASE
,
38 DCR_L2CACHE_END
= DCR_L2CACHE_SNP1
,
41 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
43 DCR_ISRAM0_BASE
= 0x20,
44 DCR_ISRAM0_SB0CR
= DCR_ISRAM0_BASE
,
55 DCR_ISRAM0_END
= DCR_ISRAM0_DPC
59 DCR_ISRAM1_BASE
= 0xb0,
60 DCR_ISRAM1_SB0CR
= DCR_ISRAM1_BASE
,
62 DCR_ISRAM1_BEAR
= DCR_ISRAM1_BASE
+ 0x04,
69 DCR_ISRAM1_END
= DCR_ISRAM1_DPC
72 typedef struct ppc4xx_l2sram_t
{
79 static void l2sram_update_mappings(ppc4xx_l2sram_t
*l2sram
,
80 uint32_t isarc
, uint32_t isacntl
,
81 uint32_t dsarc
, uint32_t dsacntl
)
83 if (l2sram
->isarc
!= isarc
||
84 (l2sram
->isacntl
& 0x80000000) != (isacntl
& 0x80000000)) {
85 if (l2sram
->isacntl
& 0x80000000) {
86 /* Unmap previously assigned memory region */
87 memory_region_del_subregion(get_system_memory(),
90 if (isacntl
& 0x80000000) {
91 /* Map new instruction memory region */
92 memory_region_add_subregion(get_system_memory(), isarc
,
96 if (l2sram
->dsarc
!= dsarc
||
97 (l2sram
->dsacntl
& 0x80000000) != (dsacntl
& 0x80000000)) {
98 if (l2sram
->dsacntl
& 0x80000000) {
99 /* Beware not to unmap the region we just mapped */
100 if (!(isacntl
& 0x80000000) || l2sram
->dsarc
!= isarc
) {
101 /* Unmap previously assigned memory region */
102 memory_region_del_subregion(get_system_memory(),
106 if (dsacntl
& 0x80000000) {
107 /* Beware not to remap the region we just mapped */
108 if (!(isacntl
& 0x80000000) || dsarc
!= isarc
) {
109 /* Map new data memory region */
110 memory_region_add_subregion(get_system_memory(), dsarc
,
118 static uint32_t dcr_read_l2sram(void *opaque
, int dcrn
)
120 ppc4xx_l2sram_t
*l2sram
= opaque
;
124 case DCR_L2CACHE_CFG
:
125 case DCR_L2CACHE_CMD
:
126 case DCR_L2CACHE_ADDR
:
127 case DCR_L2CACHE_DATA
:
128 case DCR_L2CACHE_STAT
:
129 case DCR_L2CACHE_CVER
:
130 case DCR_L2CACHE_SNP0
:
131 case DCR_L2CACHE_SNP1
:
132 ret
= l2sram
->l2cache
[dcrn
- DCR_L2CACHE_BASE
];
135 case DCR_ISRAM0_SB0CR
:
136 case DCR_ISRAM0_SB1CR
:
137 case DCR_ISRAM0_SB2CR
:
138 case DCR_ISRAM0_SB3CR
:
139 case DCR_ISRAM0_BEAR
:
140 case DCR_ISRAM0_BESR0
:
141 case DCR_ISRAM0_BESR1
:
142 case DCR_ISRAM0_PMEG
:
144 case DCR_ISRAM0_REVID
:
146 ret
= l2sram
->isram0
[dcrn
- DCR_ISRAM0_BASE
];
156 static void dcr_write_l2sram(void *opaque
, int dcrn
, uint32_t val
)
158 /*ppc4xx_l2sram_t *l2sram = opaque;*/
159 /* FIXME: Actually handle L2 cache mapping */
162 case DCR_L2CACHE_CFG
:
163 case DCR_L2CACHE_CMD
:
164 case DCR_L2CACHE_ADDR
:
165 case DCR_L2CACHE_DATA
:
166 case DCR_L2CACHE_STAT
:
167 case DCR_L2CACHE_CVER
:
168 case DCR_L2CACHE_SNP0
:
169 case DCR_L2CACHE_SNP1
:
170 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
173 case DCR_ISRAM0_SB0CR
:
174 case DCR_ISRAM0_SB1CR
:
175 case DCR_ISRAM0_SB2CR
:
176 case DCR_ISRAM0_SB3CR
:
177 case DCR_ISRAM0_BEAR
:
178 case DCR_ISRAM0_BESR0
:
179 case DCR_ISRAM0_BESR1
:
180 case DCR_ISRAM0_PMEG
:
182 case DCR_ISRAM0_REVID
:
184 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
187 case DCR_ISRAM1_SB0CR
:
188 case DCR_ISRAM1_BEAR
:
189 case DCR_ISRAM1_BESR0
:
190 case DCR_ISRAM1_BESR1
:
191 case DCR_ISRAM1_PMEG
:
193 case DCR_ISRAM1_REVID
:
195 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
198 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
201 static void l2sram_reset(void *opaque
)
203 ppc4xx_l2sram_t
*l2sram
= opaque
;
205 memset(l2sram
->l2cache
, 0, sizeof(l2sram
->l2cache
));
206 l2sram
->l2cache
[DCR_L2CACHE_STAT
- DCR_L2CACHE_BASE
] = 0x80000000;
207 memset(l2sram
->isram0
, 0, sizeof(l2sram
->isram0
));
208 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
211 void ppc4xx_l2sram_init(CPUPPCState
*env
)
213 ppc4xx_l2sram_t
*l2sram
;
215 l2sram
= g_malloc0(sizeof(*l2sram
));
216 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
217 memory_region_init_ram(&l2sram
->bank
[0], NULL
, "ppc4xx.l2sram_bank0",
218 64 * K_BYTE
, &error_abort
);
219 memory_region_init_ram(&l2sram
->bank
[1], NULL
, "ppc4xx.l2sram_bank1",
220 64 * K_BYTE
, &error_abort
);
221 memory_region_init_ram(&l2sram
->bank
[2], NULL
, "ppc4xx.l2sram_bank2",
222 64 * K_BYTE
, &error_abort
);
223 memory_region_init_ram(&l2sram
->bank
[3], NULL
, "ppc4xx.l2sram_bank3",
224 64 * K_BYTE
, &error_abort
);
225 qemu_register_reset(&l2sram_reset
, l2sram
);
226 ppc_dcr_register(env
, DCR_L2CACHE_CFG
,
227 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
228 ppc_dcr_register(env
, DCR_L2CACHE_CMD
,
229 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
230 ppc_dcr_register(env
, DCR_L2CACHE_ADDR
,
231 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
232 ppc_dcr_register(env
, DCR_L2CACHE_DATA
,
233 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
234 ppc_dcr_register(env
, DCR_L2CACHE_STAT
,
235 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
236 ppc_dcr_register(env
, DCR_L2CACHE_CVER
,
237 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
238 ppc_dcr_register(env
, DCR_L2CACHE_SNP0
,
239 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
240 ppc_dcr_register(env
, DCR_L2CACHE_SNP1
,
241 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
243 ppc_dcr_register(env
, DCR_ISRAM0_SB0CR
,
244 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
245 ppc_dcr_register(env
, DCR_ISRAM0_SB1CR
,
246 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
247 ppc_dcr_register(env
, DCR_ISRAM0_SB2CR
,
248 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
249 ppc_dcr_register(env
, DCR_ISRAM0_SB3CR
,
250 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
251 ppc_dcr_register(env
, DCR_ISRAM0_PMEG
,
252 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
253 ppc_dcr_register(env
, DCR_ISRAM0_DPC
,
254 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
256 ppc_dcr_register(env
, DCR_ISRAM1_SB0CR
,
257 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
258 ppc_dcr_register(env
, DCR_ISRAM1_PMEG
,
259 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
260 ppc_dcr_register(env
, DCR_ISRAM1_DPC
,
261 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
264 /*****************************************************************************/
265 /* Clocking Power on Reset */
277 typedef struct ppc4xx_cpr_t
{
281 static uint32_t dcr_read_cpr(void *opaque
, int dcrn
)
283 ppc4xx_cpr_t
*cpr
= opaque
;
293 ret
= (0xb5 << 24) | (1 << 16) | (9 << 8);
316 static void dcr_write_cpr(void *opaque
, int dcrn
, uint32_t val
)
318 ppc4xx_cpr_t
*cpr
= opaque
;
331 static void ppc4xx_cpr_reset(void *opaque
)
333 ppc4xx_cpr_t
*cpr
= opaque
;
338 void ppc4xx_cpr_init(CPUPPCState
*env
)
342 cpr
= g_malloc0(sizeof(*cpr
));
343 ppc_dcr_register(env
, CPR0_CFGADDR
, cpr
, &dcr_read_cpr
, &dcr_write_cpr
);
344 ppc_dcr_register(env
, CPR0_CFGDATA
, cpr
, &dcr_read_cpr
, &dcr_write_cpr
);
345 qemu_register_reset(ppc4xx_cpr_reset
, cpr
);
348 /*****************************************************************************/
350 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t
;
351 struct ppc4xx_sdr_t
{
356 SDR0_CFGADDR
= 0x00e,
372 PESDR0_RSTSTA
= 0x310,
376 PESDR1_RSTSTA
= 0x365,
379 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
380 #define SDR0_DDR0_DDRM_DDR1 0x20000000
381 #define SDR0_DDR0_DDRM_DDR2 0x40000000
383 static uint32_t dcr_read_sdr(void *opaque
, int dcrn
)
385 ppc4xx_sdr_t
*sdr
= opaque
;
395 ret
= (0xb5 << 8) | (1 << 4) | 9;
398 ret
= (5 << 29) | (2 << 26) | (1 << 24);
401 ret
= 1 << 20; /* No Security/Kasumi support */
404 ret
= SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1
;
408 ret
= (1 << 24) | (1 << 16);
412 ret
= (1 << 16) | (1 << 12);
433 static void dcr_write_sdr(void *opaque
, int dcrn
, uint32_t val
)
435 ppc4xx_sdr_t
*sdr
= opaque
;
443 case 0x00: /* B0CR */
454 static void sdr_reset(void *opaque
)
456 ppc4xx_sdr_t
*sdr
= opaque
;
461 void ppc4xx_sdr_init(CPUPPCState
*env
)
465 sdr
= g_malloc0(sizeof(*sdr
));
466 qemu_register_reset(&sdr_reset
, sdr
);
467 ppc_dcr_register(env
, SDR0_CFGADDR
,
468 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
469 ppc_dcr_register(env
, SDR0_CFGDATA
,
470 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
471 ppc_dcr_register(env
, SDR0_102
,
472 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
473 ppc_dcr_register(env
, SDR0_103
,
474 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
475 ppc_dcr_register(env
, SDR0_128
,
476 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
477 ppc_dcr_register(env
, SDR0_USB0
,
478 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
481 /*****************************************************************************/
482 /* SDRAM controller */
483 typedef struct ppc4xx_sdram_t
{
486 MemoryRegion containers
[4]; /* used for clipping */
487 MemoryRegion
*ram_memories
;
494 SDRAM0_CFGADDR
= 0x10,
500 SDRAM_CONF1HB
= 0x45,
501 SDRAM_PLBADDULL
= 0x4a,
502 SDRAM_CONF1LL
= 0x4b,
503 SDRAM_CONFPATHB
= 0x4f,
504 SDRAM_PLBADDUHB
= 0x50,
507 /* XXX: TOFIX: some patches have made this code become inconsistent:
508 * there are type inconsistencies, mixing hwaddr, target_ulong
511 static uint32_t sdram_bcr(hwaddr ram_base
, hwaddr ram_size
)
541 error_report("invalid RAM size " TARGET_FMT_plx
, ram_size
);
544 bcr
|= ram_base
& 0xFF800000;
550 static inline hwaddr
sdram_base(uint32_t bcr
)
552 return bcr
& 0xFF800000;
555 static target_ulong
sdram_size(uint32_t bcr
)
560 sh
= 1024 - ((bcr
>> 6) & 0x3ff);
564 size
= 8 * M_BYTE
* sh
;
570 static void sdram_set_bcr(ppc4xx_sdram_t
*sdram
,
571 uint32_t *bcrp
, uint32_t bcr
, int enabled
)
573 unsigned n
= bcrp
- sdram
->bcr
;
577 memory_region_del_subregion(get_system_memory(),
578 &sdram
->containers
[n
]);
579 memory_region_del_subregion(&sdram
->containers
[n
],
580 &sdram
->ram_memories
[n
]);
581 object_unparent(OBJECT(&sdram
->containers
[n
]));
583 *bcrp
= bcr
& 0xFFDEE001;
584 if (enabled
&& (bcr
& 1)) {
585 memory_region_init(&sdram
->containers
[n
], NULL
, "sdram-containers",
587 memory_region_add_subregion(&sdram
->containers
[n
], 0,
588 &sdram
->ram_memories
[n
]);
589 memory_region_add_subregion(get_system_memory(),
591 &sdram
->containers
[n
]);
595 static void sdram_map_bcr(ppc4xx_sdram_t
*sdram
)
599 for (i
= 0; i
< sdram
->nbanks
; i
++) {
600 if (sdram
->ram_sizes
[i
] != 0) {
603 sdram_bcr(sdram
->ram_bases
[i
], sdram
->ram_sizes
[i
]),
606 sdram_set_bcr(sdram
, &sdram
->bcr
[i
], 0, 0);
611 static uint32_t dcr_read_sdram(void *opaque
, int dcrn
)
613 ppc4xx_sdram_t
*sdram
= opaque
;
621 ret
= sdram_bcr(sdram
->ram_bases
[dcrn
- SDRAM_R0BAS
],
622 sdram
->ram_sizes
[dcrn
- SDRAM_R0BAS
]);
626 case SDRAM_CONFPATHB
:
627 case SDRAM_PLBADDULL
:
628 case SDRAM_PLBADDUHB
:
634 switch (sdram
->addr
) {
635 case 0x14: /* SDRAM_MCSTAT (405EX) */
639 case 0x21: /* SDRAM_MCOPT2 */
642 case 0x40: /* SDRAM_MB0CF */
645 case 0x7A: /* SDRAM_DLCR */
648 case 0xE1: /* SDR0_DDR0 */
649 ret
= SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1
;
662 static void dcr_write_sdram(void *opaque
, int dcrn
, uint32_t val
)
664 ppc4xx_sdram_t
*sdram
= opaque
;
673 case SDRAM_CONFPATHB
:
674 case SDRAM_PLBADDULL
:
675 case SDRAM_PLBADDUHB
:
681 switch (sdram
->addr
) {
682 case 0x00: /* B0CR */
693 static void sdram_reset(void *opaque
)
695 ppc4xx_sdram_t
*sdram
= opaque
;
700 void ppc440_sdram_init(CPUPPCState
*env
, int nbanks
,
701 MemoryRegion
*ram_memories
,
702 hwaddr
*ram_bases
, hwaddr
*ram_sizes
,
705 ppc4xx_sdram_t
*sdram
;
707 sdram
= g_malloc0(sizeof(*sdram
));
708 sdram
->nbanks
= nbanks
;
709 sdram
->ram_memories
= ram_memories
;
710 memcpy(sdram
->ram_bases
, ram_bases
, nbanks
* sizeof(hwaddr
));
711 memcpy(sdram
->ram_sizes
, ram_sizes
, nbanks
* sizeof(hwaddr
));
712 qemu_register_reset(&sdram_reset
, sdram
);
713 ppc_dcr_register(env
, SDRAM0_CFGADDR
,
714 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
715 ppc_dcr_register(env
, SDRAM0_CFGDATA
,
716 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
718 sdram_map_bcr(sdram
);
721 ppc_dcr_register(env
, SDRAM_R0BAS
,
722 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
723 ppc_dcr_register(env
, SDRAM_R1BAS
,
724 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
725 ppc_dcr_register(env
, SDRAM_R2BAS
,
726 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
727 ppc_dcr_register(env
, SDRAM_R3BAS
,
728 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
729 ppc_dcr_register(env
, SDRAM_CONF1HB
,
730 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
731 ppc_dcr_register(env
, SDRAM_PLBADDULL
,
732 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
733 ppc_dcr_register(env
, SDRAM_CONF1LL
,
734 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
735 ppc_dcr_register(env
, SDRAM_CONFPATHB
,
736 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
737 ppc_dcr_register(env
, SDRAM_PLBADDUHB
,
738 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
741 /*****************************************************************************/
742 /* PLB to AHB bridge */
748 typedef struct ppc4xx_ahb_t
{
753 static uint32_t dcr_read_ahb(void *opaque
, int dcrn
)
755 ppc4xx_ahb_t
*ahb
= opaque
;
772 static void dcr_write_ahb(void *opaque
, int dcrn
, uint32_t val
)
774 ppc4xx_ahb_t
*ahb
= opaque
;
786 static void ppc4xx_ahb_reset(void *opaque
)
788 ppc4xx_ahb_t
*ahb
= opaque
;
795 void ppc4xx_ahb_init(CPUPPCState
*env
)
799 ahb
= g_malloc0(sizeof(*ahb
));
800 ppc_dcr_register(env
, AHB_TOP
, ahb
, &dcr_read_ahb
, &dcr_write_ahb
);
801 ppc_dcr_register(env
, AHB_BOT
, ahb
, &dcr_read_ahb
, &dcr_write_ahb
);
802 qemu_register_reset(ppc4xx_ahb_reset
, ahb
);
805 /*****************************************************************************/
806 /* PCI Express controller */
807 /* FIXME: This is not complete and does not work, only implemented partially
808 * to allow firmware and guests to find an empty bus. Cards should use PCI.
810 #include "hw/pci/pcie_host.h"
812 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
813 #define PPC460EX_PCIE_HOST(obj) \
814 OBJECT_CHECK(PPC460EXPCIEState, (obj), TYPE_PPC460EX_PCIE_HOST)
816 typedef struct PPC460EXPCIEState
{
839 #define DCRN_PCIE0_BASE 0x100
840 #define DCRN_PCIE1_BASE 0x120
868 static uint32_t dcr_read_pcie(void *opaque
, int dcrn
)
870 PPC460EXPCIEState
*state
= opaque
;
873 switch (dcrn
- state
->dcrn_base
) {
875 ret
= state
->cfg_base
>> 32;
878 ret
= state
->cfg_base
;
881 ret
= state
->cfg_mask
;
884 ret
= state
->msg_base
>> 32;
887 ret
= state
->msg_base
;
890 ret
= state
->msg_mask
;
893 ret
= state
->omr1_base
>> 32;
896 ret
= state
->omr1_base
;
899 ret
= state
->omr1_mask
>> 32;
902 ret
= state
->omr1_mask
;
905 ret
= state
->omr2_base
>> 32;
908 ret
= state
->omr2_base
;
911 ret
= state
->omr2_mask
>> 32;
914 ret
= state
->omr3_mask
;
917 ret
= state
->omr3_base
>> 32;
920 ret
= state
->omr3_base
;
923 ret
= state
->omr3_mask
>> 32;
926 ret
= state
->omr3_mask
;
929 ret
= state
->reg_base
>> 32;
932 ret
= state
->reg_base
;
935 ret
= state
->reg_mask
;
938 ret
= state
->special
;
948 static void dcr_write_pcie(void *opaque
, int dcrn
, uint32_t val
)
950 PPC460EXPCIEState
*s
= opaque
;
953 switch (dcrn
- s
->dcrn_base
) {
955 s
->cfg_base
= ((uint64_t)val
<< 32) | (s
->cfg_base
& 0xffffffff);
958 s
->cfg_base
= (s
->cfg_base
& 0xffffffff00000000ULL
) | val
;
962 size
= ~(val
& 0xfffffffe) + 1;
963 qemu_mutex_lock_iothread();
964 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s
), val
& 1, s
->cfg_base
, size
);
965 qemu_mutex_unlock_iothread();
968 s
->msg_base
= ((uint64_t)val
<< 32) | (s
->msg_base
& 0xffffffff);
971 s
->msg_base
= (s
->msg_base
& 0xffffffff00000000ULL
) | val
;
977 s
->omr1_base
= ((uint64_t)val
<< 32) | (s
->omr1_base
& 0xffffffff);
980 s
->omr1_base
= (s
->omr1_base
& 0xffffffff00000000ULL
) | val
;
983 s
->omr1_mask
= ((uint64_t)val
<< 32) | (s
->omr1_mask
& 0xffffffff);
986 s
->omr1_mask
= (s
->omr1_mask
& 0xffffffff00000000ULL
) | val
;
989 s
->omr2_base
= ((uint64_t)val
<< 32) | (s
->omr2_base
& 0xffffffff);
992 s
->omr2_base
= (s
->omr2_base
& 0xffffffff00000000ULL
) | val
;
995 s
->omr2_mask
= ((uint64_t)val
<< 32) | (s
->omr2_mask
& 0xffffffff);
998 s
->omr2_mask
= (s
->omr2_mask
& 0xffffffff00000000ULL
) | val
;
1001 s
->omr3_base
= ((uint64_t)val
<< 32) | (s
->omr3_base
& 0xffffffff);
1004 s
->omr3_base
= (s
->omr3_base
& 0xffffffff00000000ULL
) | val
;
1006 case PEGPL_OMR3MSKH
:
1007 s
->omr3_mask
= ((uint64_t)val
<< 32) | (s
->omr3_mask
& 0xffffffff);
1009 case PEGPL_OMR3MSKL
:
1010 s
->omr3_mask
= (s
->omr3_mask
& 0xffffffff00000000ULL
) | val
;
1013 s
->reg_base
= ((uint64_t)val
<< 32) | (s
->reg_base
& 0xffffffff);
1016 s
->reg_base
= (s
->reg_base
& 0xffffffff00000000ULL
) | val
;
1020 /* FIXME: how is size encoded? */
1021 size
= (val
== 0x7001 ? 4096 : ~(val
& 0xfffffffe) + 1);
1032 static void ppc460ex_set_irq(void *opaque
, int irq_num
, int level
)
1034 PPC460EXPCIEState
*s
= opaque
;
1035 qemu_set_irq(s
->irq
[irq_num
], level
);
1038 static void ppc460ex_pcie_realize(DeviceState
*dev
, Error
**errp
)
1040 PPC460EXPCIEState
*s
= PPC460EX_PCIE_HOST(dev
);
1041 PCIHostState
*pci
= PCI_HOST_BRIDGE(dev
);
1045 switch (s
->dcrn_base
) {
1046 case DCRN_PCIE0_BASE
:
1049 case DCRN_PCIE1_BASE
:
1053 error_setg(errp
, "invalid PCIe DCRN base");
1056 snprintf(buf
, sizeof(buf
), "pcie%d-io", id
);
1057 memory_region_init(&s
->iomem
, OBJECT(s
), buf
, UINT64_MAX
);
1058 for (i
= 0; i
< 4; i
++) {
1059 sysbus_init_irq(SYS_BUS_DEVICE(dev
), &s
->irq
[i
]);
1061 snprintf(buf
, sizeof(buf
), "pcie.%d", id
);
1062 pci
->bus
= pci_register_root_bus(DEVICE(s
), buf
, ppc460ex_set_irq
,
1063 pci_swizzle_map_irq_fn
, s
, &s
->iomem
,
1064 get_system_io(), 0, 4, TYPE_PCIE_BUS
);
1067 static Property ppc460ex_pcie_props
[] = {
1068 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState
, dcrn_base
, -1),
1069 DEFINE_PROP_END_OF_LIST(),
1072 static void ppc460ex_pcie_class_init(ObjectClass
*klass
, void *data
)
1074 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1076 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1077 dc
->realize
= ppc460ex_pcie_realize
;
1078 dc
->props
= ppc460ex_pcie_props
;
1079 dc
->hotpluggable
= false;
1082 static const TypeInfo ppc460ex_pcie_host_info
= {
1083 .name
= TYPE_PPC460EX_PCIE_HOST
,
1084 .parent
= TYPE_PCIE_HOST_BRIDGE
,
1085 .instance_size
= sizeof(PPC460EXPCIEState
),
1086 .class_init
= ppc460ex_pcie_class_init
,
1089 static void ppc460ex_pcie_register(void)
1091 type_register_static(&ppc460ex_pcie_host_info
);
1094 type_init(ppc460ex_pcie_register
)
1096 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState
*s
, CPUPPCState
*env
)
1098 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_CFGBAH
, s
,
1099 &dcr_read_pcie
, &dcr_write_pcie
);
1100 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_CFGBAL
, s
,
1101 &dcr_read_pcie
, &dcr_write_pcie
);
1102 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_CFGMSK
, s
,
1103 &dcr_read_pcie
, &dcr_write_pcie
);
1104 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_MSGBAH
, s
,
1105 &dcr_read_pcie
, &dcr_write_pcie
);
1106 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_MSGBAL
, s
,
1107 &dcr_read_pcie
, &dcr_write_pcie
);
1108 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_MSGMSK
, s
,
1109 &dcr_read_pcie
, &dcr_write_pcie
);
1110 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR1BAH
, s
,
1111 &dcr_read_pcie
, &dcr_write_pcie
);
1112 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR1BAL
, s
,
1113 &dcr_read_pcie
, &dcr_write_pcie
);
1114 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR1MSKH
, s
,
1115 &dcr_read_pcie
, &dcr_write_pcie
);
1116 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR1MSKL
, s
,
1117 &dcr_read_pcie
, &dcr_write_pcie
);
1118 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR2BAH
, s
,
1119 &dcr_read_pcie
, &dcr_write_pcie
);
1120 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR2BAL
, s
,
1121 &dcr_read_pcie
, &dcr_write_pcie
);
1122 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR2MSKH
, s
,
1123 &dcr_read_pcie
, &dcr_write_pcie
);
1124 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR2MSKL
, s
,
1125 &dcr_read_pcie
, &dcr_write_pcie
);
1126 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR3BAH
, s
,
1127 &dcr_read_pcie
, &dcr_write_pcie
);
1128 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR3BAL
, s
,
1129 &dcr_read_pcie
, &dcr_write_pcie
);
1130 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR3MSKH
, s
,
1131 &dcr_read_pcie
, &dcr_write_pcie
);
1132 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_OMR3MSKL
, s
,
1133 &dcr_read_pcie
, &dcr_write_pcie
);
1134 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_REGBAH
, s
,
1135 &dcr_read_pcie
, &dcr_write_pcie
);
1136 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_REGBAL
, s
,
1137 &dcr_read_pcie
, &dcr_write_pcie
);
1138 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_REGMSK
, s
,
1139 &dcr_read_pcie
, &dcr_write_pcie
);
1140 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_SPECIAL
, s
,
1141 &dcr_read_pcie
, &dcr_write_pcie
);
1142 ppc_dcr_register(env
, s
->dcrn_base
+ PEGPL_CFG
, s
,
1143 &dcr_read_pcie
, &dcr_write_pcie
);
1146 void ppc460ex_pcie_init(CPUPPCState
*env
)
1150 dev
= qdev_create(NULL
, TYPE_PPC460EX_PCIE_HOST
);
1151 qdev_prop_set_int32(dev
, "dcrn-base", DCRN_PCIE0_BASE
);
1152 qdev_init_nofail(dev
);
1153 object_property_set_bool(OBJECT(dev
), true, "realized", NULL
);
1154 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev
), env
);
1156 dev
= qdev_create(NULL
, TYPE_PPC460EX_PCIE_HOST
);
1157 qdev_prop_set_int32(dev
, "dcrn-base", DCRN_PCIE1_BASE
);
1158 qdev_init_nofail(dev
);
1159 object_property_set_bool(OBJECT(dev
), true, "realized", NULL
);
1160 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev
), env
);