2 * QEMU PowerPC e500-based platforms
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include "qemu/osdep.h"
18 #include "qapi/error.h"
20 #include "e500-ccsr.h"
22 #include "qemu/config-file.h"
24 #include "hw/char/serial.h"
25 #include "hw/pci/pci.h"
26 #include "hw/boards.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/kvm.h"
30 #include "sysemu/device_tree.h"
31 #include "hw/ppc/openpic.h"
32 #include "hw/ppc/openpic_kvm.h"
33 #include "hw/ppc/ppc.h"
34 #include "hw/loader.h"
36 #include "hw/sysbus.h"
37 #include "exec/address-spaces.h"
38 #include "qemu/host-utils.h"
39 #include "qemu/option.h"
40 #include "hw/pci-host/ppce500.h"
41 #include "qemu/error-report.h"
42 #include "hw/platform-bus.h"
43 #include "hw/net/fsl_etsec/etsec.h"
45 #define EPAPR_MAGIC (0x45504150)
46 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
47 #define DTC_LOAD_PAD 0x1800000
48 #define DTC_PAD_MASK 0xFFFFF
49 #define DTB_MAX_SIZE (8 * 1024 * 1024)
50 #define INITRD_LOAD_PAD 0x2000000
51 #define INITRD_PAD_MASK 0xFFFFFF
53 #define RAM_SIZES_ALIGN (64UL << 20)
55 /* TODO: parameterize */
56 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
57 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
58 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
59 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
60 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
61 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
62 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
63 #define MPC8544_UTIL_OFFSET 0xe0000ULL
64 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
65 #define MPC8XXX_GPIO_IRQ 47
74 static uint32_t *pci_map_create(void *fdt
, uint32_t mpic
, int first_slot
,
75 int nr_slots
, int *len
)
81 int last_slot
= first_slot
+ nr_slots
;
84 *len
= nr_slots
* 4 * 7 * sizeof(uint32_t);
85 pci_map
= g_malloc(*len
);
87 for (slot
= first_slot
; slot
< last_slot
; slot
++) {
88 for (pci_irq
= 0; pci_irq
< 4; pci_irq
++) {
89 pci_map
[i
++] = cpu_to_be32(slot
<< 11);
90 pci_map
[i
++] = cpu_to_be32(0x0);
91 pci_map
[i
++] = cpu_to_be32(0x0);
92 pci_map
[i
++] = cpu_to_be32(pci_irq
+ 1);
93 pci_map
[i
++] = cpu_to_be32(mpic
);
94 host_irq
= ppce500_pci_map_irq_slot(slot
, pci_irq
);
95 pci_map
[i
++] = cpu_to_be32(host_irq
+ 1);
96 pci_map
[i
++] = cpu_to_be32(0x1);
100 assert((i
* sizeof(uint32_t)) == *len
);
105 static void dt_serial_create(void *fdt
, unsigned long long offset
,
106 const char *soc
, const char *mpic
,
107 const char *alias
, int idx
, bool defcon
)
111 snprintf(ser
, sizeof(ser
), "%s/serial@%llx", soc
, offset
);
112 qemu_fdt_add_subnode(fdt
, ser
);
113 qemu_fdt_setprop_string(fdt
, ser
, "device_type", "serial");
114 qemu_fdt_setprop_string(fdt
, ser
, "compatible", "ns16550");
115 qemu_fdt_setprop_cells(fdt
, ser
, "reg", offset
, 0x100);
116 qemu_fdt_setprop_cell(fdt
, ser
, "cell-index", idx
);
117 qemu_fdt_setprop_cell(fdt
, ser
, "clock-frequency", 0);
118 qemu_fdt_setprop_cells(fdt
, ser
, "interrupts", 42, 2);
119 qemu_fdt_setprop_phandle(fdt
, ser
, "interrupt-parent", mpic
);
120 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, ser
);
124 * "linux,stdout-path" and "stdout" properties are deprecated by linux
125 * kernel. New platforms should only use the "stdout-path" property. Set
126 * the new property and continue using older property to remain
127 * compatible with the existing firmware.
129 qemu_fdt_setprop_string(fdt
, "/chosen", "linux,stdout-path", ser
);
130 qemu_fdt_setprop_string(fdt
, "/chosen", "stdout-path", ser
);
134 static void create_dt_mpc8xxx_gpio(void *fdt
, const char *soc
, const char *mpic
)
136 hwaddr mmio0
= MPC8XXX_GPIO_OFFSET
;
137 int irq0
= MPC8XXX_GPIO_IRQ
;
138 gchar
*node
= g_strdup_printf("%s/gpio@%"PRIx64
, soc
, mmio0
);
139 gchar
*poweroff
= g_strdup_printf("%s/power-off", soc
);
142 qemu_fdt_add_subnode(fdt
, node
);
143 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,qoriq-gpio");
144 qemu_fdt_setprop_cells(fdt
, node
, "reg", mmio0
, 0x1000);
145 qemu_fdt_setprop_cells(fdt
, node
, "interrupts", irq0
, 0x2);
146 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
147 qemu_fdt_setprop_cells(fdt
, node
, "#gpio-cells", 2);
148 qemu_fdt_setprop(fdt
, node
, "gpio-controller", NULL
, 0);
149 gpio_ph
= qemu_fdt_alloc_phandle(fdt
);
150 qemu_fdt_setprop_cell(fdt
, node
, "phandle", gpio_ph
);
151 qemu_fdt_setprop_cell(fdt
, node
, "linux,phandle", gpio_ph
);
154 qemu_fdt_add_subnode(fdt
, poweroff
);
155 qemu_fdt_setprop_string(fdt
, poweroff
, "compatible", "gpio-poweroff");
156 qemu_fdt_setprop_cells(fdt
, poweroff
, "gpios", gpio_ph
, 0, 0);
162 typedef struct PlatformDevtreeData
{
167 PlatformBusDevice
*pbus
;
168 } PlatformDevtreeData
;
170 static int create_devtree_etsec(SysBusDevice
*sbdev
, PlatformDevtreeData
*data
)
172 eTSEC
*etsec
= ETSEC_COMMON(sbdev
);
173 PlatformBusDevice
*pbus
= data
->pbus
;
174 hwaddr mmio0
= platform_bus_get_mmio_addr(pbus
, sbdev
, 0);
175 int irq0
= platform_bus_get_irqn(pbus
, sbdev
, 0);
176 int irq1
= platform_bus_get_irqn(pbus
, sbdev
, 1);
177 int irq2
= platform_bus_get_irqn(pbus
, sbdev
, 2);
178 gchar
*node
= g_strdup_printf("/platform/ethernet@%"PRIx64
, mmio0
);
179 gchar
*group
= g_strdup_printf("%s/queue-group", node
);
180 void *fdt
= data
->fdt
;
182 assert((int64_t)mmio0
>= 0);
187 qemu_fdt_add_subnode(fdt
, node
);
188 qemu_fdt_setprop_string(fdt
, node
, "device_type", "network");
189 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,etsec2");
190 qemu_fdt_setprop_string(fdt
, node
, "model", "eTSEC");
191 qemu_fdt_setprop(fdt
, node
, "local-mac-address", etsec
->conf
.macaddr
.a
, 6);
192 qemu_fdt_setprop_cells(fdt
, node
, "fixed-link", 0, 1, 1000, 0, 0);
194 qemu_fdt_add_subnode(fdt
, group
);
195 qemu_fdt_setprop_cells(fdt
, group
, "reg", mmio0
, 0x1000);
196 qemu_fdt_setprop_cells(fdt
, group
, "interrupts",
197 data
->irq_start
+ irq0
, 0x2,
198 data
->irq_start
+ irq1
, 0x2,
199 data
->irq_start
+ irq2
, 0x2);
207 static void sysbus_device_create_devtree(SysBusDevice
*sbdev
, void *opaque
)
209 PlatformDevtreeData
*data
= opaque
;
210 bool matched
= false;
212 if (object_dynamic_cast(OBJECT(sbdev
), TYPE_ETSEC_COMMON
)) {
213 create_devtree_etsec(sbdev
, data
);
218 error_report("Device %s is not supported by this machine yet.",
219 qdev_fw_name(DEVICE(sbdev
)));
224 static void platform_bus_create_devtree(const PPCE500MachineClass
*pmc
,
225 void *fdt
, const char *mpic
)
227 gchar
*node
= g_strdup_printf("/platform@%"PRIx64
, pmc
->platform_bus_base
);
228 const char platcomp
[] = "qemu,platform\0simple-bus";
229 uint64_t addr
= pmc
->platform_bus_base
;
230 uint64_t size
= pmc
->platform_bus_size
;
231 int irq_start
= pmc
->platform_bus_first_irq
;
232 PlatformBusDevice
*pbus
;
235 /* Create a /platform node that we can put all devices into */
237 qemu_fdt_add_subnode(fdt
, node
);
238 qemu_fdt_setprop(fdt
, node
, "compatible", platcomp
, sizeof(platcomp
));
240 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
242 qemu_fdt_setprop_cells(fdt
, node
, "#size-cells", 1);
243 qemu_fdt_setprop_cells(fdt
, node
, "#address-cells", 1);
244 qemu_fdt_setprop_cells(fdt
, node
, "ranges", 0, addr
>> 32, addr
, size
);
246 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
248 dev
= qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE
);
249 pbus
= PLATFORM_BUS_DEVICE(dev
);
251 /* We can only create dt nodes for dynamic devices when they're ready */
252 if (pbus
->done_gathering
) {
253 PlatformDevtreeData data
= {
256 .irq_start
= irq_start
,
261 /* Loop through all dynamic sysbus devices and create nodes for them */
262 foreach_dynamic_sysbus_device(sysbus_device_create_devtree
, &data
);
268 static int ppce500_load_device_tree(PPCE500MachineState
*pms
,
276 MachineState
*machine
= MACHINE(pms
);
277 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
278 CPUPPCState
*env
= first_cpu
->env_ptr
;
280 uint64_t mem_reg_property
[] = { 0, cpu_to_be64(machine
->ram_size
) };
283 uint8_t hypercall
[16];
284 uint32_t clock_freq
= 400000000;
285 uint32_t tb_freq
= 400000000;
287 char compatible_sb
[] = "fsl,mpc8544-immr\0simple-bus";
295 uint32_t *pci_map
= NULL
;
297 uint32_t pci_ranges
[14] =
299 0x2000000, 0x0, pmc
->pci_mmio_bus_base
,
300 pmc
->pci_mmio_base
>> 32, pmc
->pci_mmio_base
,
304 pmc
->pci_pio_base
>> 32, pmc
->pci_pio_base
,
307 QemuOpts
*machine_opts
= qemu_get_machine_opts();
308 const char *dtb_file
= qemu_opt_get(machine_opts
, "dtb");
309 const char *toplevel_compat
= qemu_opt_get(machine_opts
, "dt_compatible");
313 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, dtb_file
);
318 fdt
= load_device_tree(filename
, &fdt_size
);
326 fdt
= create_device_tree(&fdt_size
);
331 /* Manipulate device tree in memory. */
332 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 2);
333 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 2);
335 qemu_fdt_add_subnode(fdt
, "/memory");
336 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
337 qemu_fdt_setprop(fdt
, "/memory", "reg", mem_reg_property
,
338 sizeof(mem_reg_property
));
340 qemu_fdt_add_subnode(fdt
, "/chosen");
342 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
345 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
348 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
349 (initrd_base
+ initrd_size
));
351 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
356 if (kernel_base
!= -1ULL) {
357 qemu_fdt_setprop_cells(fdt
, "/chosen", "qemu,boot-kernel",
358 kernel_base
>> 32, kernel_base
,
359 kernel_size
>> 32, kernel_size
);
362 ret
= qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs",
363 machine
->kernel_cmdline
);
365 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
368 /* Read out host's frequencies */
369 clock_freq
= kvmppc_get_clockfreq();
370 tb_freq
= kvmppc_get_tbfreq();
372 /* indicate KVM hypercall interface */
373 qemu_fdt_add_subnode(fdt
, "/hypervisor");
374 qemu_fdt_setprop_string(fdt
, "/hypervisor", "compatible",
376 kvmppc_get_hypercall(env
, hypercall
, sizeof(hypercall
));
377 qemu_fdt_setprop(fdt
, "/hypervisor", "hcall-instructions",
378 hypercall
, sizeof(hypercall
));
379 /* if KVM supports the idle hcall, set property indicating this */
380 if (kvmppc_get_hasidle(env
)) {
381 qemu_fdt_setprop(fdt
, "/hypervisor", "has-idle", NULL
, 0);
385 /* Create CPU nodes */
386 qemu_fdt_add_subnode(fdt
, "/cpus");
387 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 1);
388 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0);
390 /* We need to generate the cpu nodes in reverse order, so Linux can pick
391 the first node as boot node and be happy */
392 for (i
= smp_cpus
- 1; i
>= 0; i
--) {
395 uint64_t cpu_release_addr
= pmc
->spin_base
+ (i
* 0x20);
397 cpu
= qemu_get_cpu(i
);
403 snprintf(cpu_name
, sizeof(cpu_name
), "/cpus/PowerPC,8544@%x", i
);
404 qemu_fdt_add_subnode(fdt
, cpu_name
);
405 qemu_fdt_setprop_cell(fdt
, cpu_name
, "clock-frequency", clock_freq
);
406 qemu_fdt_setprop_cell(fdt
, cpu_name
, "timebase-frequency", tb_freq
);
407 qemu_fdt_setprop_string(fdt
, cpu_name
, "device_type", "cpu");
408 qemu_fdt_setprop_cell(fdt
, cpu_name
, "reg", i
);
409 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-line-size",
410 env
->dcache_line_size
);
411 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-line-size",
412 env
->icache_line_size
);
413 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-size", 0x8000);
414 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-size", 0x8000);
415 qemu_fdt_setprop_cell(fdt
, cpu_name
, "bus-frequency", 0);
416 if (cpu
->cpu_index
) {
417 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "disabled");
418 qemu_fdt_setprop_string(fdt
, cpu_name
, "enable-method",
420 qemu_fdt_setprop_u64(fdt
, cpu_name
, "cpu-release-addr",
423 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "okay");
427 qemu_fdt_add_subnode(fdt
, "/aliases");
428 /* XXX These should go into their respective devices' code */
429 snprintf(soc
, sizeof(soc
), "/soc@%"PRIx64
, pmc
->ccsrbar_base
);
430 qemu_fdt_add_subnode(fdt
, soc
);
431 qemu_fdt_setprop_string(fdt
, soc
, "device_type", "soc");
432 qemu_fdt_setprop(fdt
, soc
, "compatible", compatible_sb
,
433 sizeof(compatible_sb
));
434 qemu_fdt_setprop_cell(fdt
, soc
, "#address-cells", 1);
435 qemu_fdt_setprop_cell(fdt
, soc
, "#size-cells", 1);
436 qemu_fdt_setprop_cells(fdt
, soc
, "ranges", 0x0,
437 pmc
->ccsrbar_base
>> 32, pmc
->ccsrbar_base
,
438 MPC8544_CCSRBAR_SIZE
);
439 /* XXX should contain a reasonable value */
440 qemu_fdt_setprop_cell(fdt
, soc
, "bus-frequency", 0);
442 snprintf(mpic
, sizeof(mpic
), "%s/pic@%llx", soc
, MPC8544_MPIC_REGS_OFFSET
);
443 qemu_fdt_add_subnode(fdt
, mpic
);
444 qemu_fdt_setprop_string(fdt
, mpic
, "device_type", "open-pic");
445 qemu_fdt_setprop_string(fdt
, mpic
, "compatible", "fsl,mpic");
446 qemu_fdt_setprop_cells(fdt
, mpic
, "reg", MPC8544_MPIC_REGS_OFFSET
,
448 qemu_fdt_setprop_cell(fdt
, mpic
, "#address-cells", 0);
449 qemu_fdt_setprop_cell(fdt
, mpic
, "#interrupt-cells", 2);
450 mpic_ph
= qemu_fdt_alloc_phandle(fdt
);
451 qemu_fdt_setprop_cell(fdt
, mpic
, "phandle", mpic_ph
);
452 qemu_fdt_setprop_cell(fdt
, mpic
, "linux,phandle", mpic_ph
);
453 qemu_fdt_setprop(fdt
, mpic
, "interrupt-controller", NULL
, 0);
456 * We have to generate ser1 first, because Linux takes the first
457 * device it finds in the dt as serial output device. And we generate
458 * devices in reverse order to the dt.
461 dt_serial_create(fdt
, MPC8544_SERIAL1_REGS_OFFSET
,
462 soc
, mpic
, "serial1", 1, false);
466 dt_serial_create(fdt
, MPC8544_SERIAL0_REGS_OFFSET
,
467 soc
, mpic
, "serial0", 0, true);
470 snprintf(gutil
, sizeof(gutil
), "%s/global-utilities@%llx", soc
,
471 MPC8544_UTIL_OFFSET
);
472 qemu_fdt_add_subnode(fdt
, gutil
);
473 qemu_fdt_setprop_string(fdt
, gutil
, "compatible", "fsl,mpc8544-guts");
474 qemu_fdt_setprop_cells(fdt
, gutil
, "reg", MPC8544_UTIL_OFFSET
, 0x1000);
475 qemu_fdt_setprop(fdt
, gutil
, "fsl,has-rstcr", NULL
, 0);
477 snprintf(msi
, sizeof(msi
), "/%s/msi@%llx", soc
, MPC8544_MSI_REGS_OFFSET
);
478 qemu_fdt_add_subnode(fdt
, msi
);
479 qemu_fdt_setprop_string(fdt
, msi
, "compatible", "fsl,mpic-msi");
480 qemu_fdt_setprop_cells(fdt
, msi
, "reg", MPC8544_MSI_REGS_OFFSET
, 0x200);
481 msi_ph
= qemu_fdt_alloc_phandle(fdt
);
482 qemu_fdt_setprop_cells(fdt
, msi
, "msi-available-ranges", 0x0, 0x100);
483 qemu_fdt_setprop_phandle(fdt
, msi
, "interrupt-parent", mpic
);
484 qemu_fdt_setprop_cells(fdt
, msi
, "interrupts",
493 qemu_fdt_setprop_cell(fdt
, msi
, "phandle", msi_ph
);
494 qemu_fdt_setprop_cell(fdt
, msi
, "linux,phandle", msi_ph
);
496 snprintf(pci
, sizeof(pci
), "/pci@%llx",
497 pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
);
498 qemu_fdt_add_subnode(fdt
, pci
);
499 qemu_fdt_setprop_cell(fdt
, pci
, "cell-index", 0);
500 qemu_fdt_setprop_string(fdt
, pci
, "compatible", "fsl,mpc8540-pci");
501 qemu_fdt_setprop_string(fdt
, pci
, "device_type", "pci");
502 qemu_fdt_setprop_cells(fdt
, pci
, "interrupt-map-mask", 0xf800, 0x0,
504 pci_map
= pci_map_create(fdt
, qemu_fdt_get_phandle(fdt
, mpic
),
505 pmc
->pci_first_slot
, pmc
->pci_nr_slots
,
507 qemu_fdt_setprop(fdt
, pci
, "interrupt-map", pci_map
, len
);
508 qemu_fdt_setprop_phandle(fdt
, pci
, "interrupt-parent", mpic
);
509 qemu_fdt_setprop_cells(fdt
, pci
, "interrupts", 24, 2);
510 qemu_fdt_setprop_cells(fdt
, pci
, "bus-range", 0, 255);
511 for (i
= 0; i
< 14; i
++) {
512 pci_ranges
[i
] = cpu_to_be32(pci_ranges
[i
]);
514 qemu_fdt_setprop_cell(fdt
, pci
, "fsl,msi", msi_ph
);
515 qemu_fdt_setprop(fdt
, pci
, "ranges", pci_ranges
, sizeof(pci_ranges
));
516 qemu_fdt_setprop_cells(fdt
, pci
, "reg",
517 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
) >> 32,
518 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
),
520 qemu_fdt_setprop_cell(fdt
, pci
, "clock-frequency", 66666666);
521 qemu_fdt_setprop_cell(fdt
, pci
, "#interrupt-cells", 1);
522 qemu_fdt_setprop_cell(fdt
, pci
, "#size-cells", 2);
523 qemu_fdt_setprop_cell(fdt
, pci
, "#address-cells", 3);
524 qemu_fdt_setprop_string(fdt
, "/aliases", "pci0", pci
);
526 if (pmc
->has_mpc8xxx_gpio
) {
527 create_dt_mpc8xxx_gpio(fdt
, soc
, mpic
);
530 if (pmc
->has_platform_bus
) {
531 platform_bus_create_devtree(pmc
, fdt
, mpic
);
534 pmc
->fixup_devtree(fdt
);
536 if (toplevel_compat
) {
537 qemu_fdt_setprop(fdt
, "/", "compatible", toplevel_compat
,
538 strlen(toplevel_compat
) + 1);
543 qemu_fdt_dumpdtb(fdt
, fdt_size
);
544 cpu_physical_memory_write(addr
, fdt
, fdt_size
);
554 typedef struct DeviceTreeParams
{
555 PPCE500MachineState
*machine
;
564 static void ppce500_reset_device_tree(void *opaque
)
566 DeviceTreeParams
*p
= opaque
;
567 ppce500_load_device_tree(p
->machine
, p
->addr
, p
->initrd_base
,
568 p
->initrd_size
, p
->kernel_base
, p
->kernel_size
,
572 static void ppce500_init_notify(Notifier
*notifier
, void *data
)
574 DeviceTreeParams
*p
= container_of(notifier
, DeviceTreeParams
, notifier
);
575 ppce500_reset_device_tree(p
);
578 static int ppce500_prep_device_tree(PPCE500MachineState
*machine
,
585 DeviceTreeParams
*p
= g_new(DeviceTreeParams
, 1);
586 p
->machine
= machine
;
588 p
->initrd_base
= initrd_base
;
589 p
->initrd_size
= initrd_size
;
590 p
->kernel_base
= kernel_base
;
591 p
->kernel_size
= kernel_size
;
593 qemu_register_reset(ppce500_reset_device_tree
, p
);
594 p
->notifier
.notify
= ppce500_init_notify
;
595 qemu_add_machine_init_done_notifier(&p
->notifier
);
597 /* Issue the device tree loader once, so that we get the size of the blob */
598 return ppce500_load_device_tree(machine
, addr
, initrd_base
, initrd_size
,
599 kernel_base
, kernel_size
, true);
602 /* Create -kernel TLB entries for BookE. */
603 hwaddr
booke206_page_size_to_tlb(uint64_t size
)
605 return 63 - clz64(size
>> 10);
608 static int booke206_initial_map_tsize(CPUPPCState
*env
)
610 struct boot_info
*bi
= env
->load_info
;
614 /* Our initial TLB entry needs to cover everything from 0 to
615 the device tree top */
616 dt_end
= bi
->dt_base
+ bi
->dt_size
;
617 ps
= booke206_page_size_to_tlb(dt_end
) + 1;
619 /* e500v2 can only do even TLB size bits */
625 static uint64_t mmubooke_initial_mapsize(CPUPPCState
*env
)
629 tsize
= booke206_initial_map_tsize(env
);
630 return (1ULL << 10 << tsize
);
633 static void mmubooke_create_initial_mapping(CPUPPCState
*env
)
635 ppcmas_tlb_t
*tlb
= booke206_get_tlbm(env
, 1, 0, 0);
639 ps
= booke206_initial_map_tsize(env
);
640 size
= (ps
<< MAS1_TSIZE_SHIFT
);
641 tlb
->mas1
= MAS1_VALID
| size
;
644 tlb
->mas7_3
|= MAS3_UR
| MAS3_UW
| MAS3_UX
| MAS3_SR
| MAS3_SW
| MAS3_SX
;
646 env
->tlb_dirty
= true;
649 static void ppce500_cpu_reset_sec(void *opaque
)
651 PowerPCCPU
*cpu
= opaque
;
652 CPUState
*cs
= CPU(cpu
);
656 /* Secondary CPU starts in halted state for now. Needs to change when
657 implementing non-kernel boot. */
659 cs
->exception_index
= EXCP_HLT
;
662 static void ppce500_cpu_reset(void *opaque
)
664 PowerPCCPU
*cpu
= opaque
;
665 CPUState
*cs
= CPU(cpu
);
666 CPUPPCState
*env
= &cpu
->env
;
667 struct boot_info
*bi
= env
->load_info
;
671 /* Set initial guest state. */
673 env
->gpr
[1] = (16<<20) - 8;
674 env
->gpr
[3] = bi
->dt_base
;
677 env
->gpr
[6] = EPAPR_MAGIC
;
678 env
->gpr
[7] = mmubooke_initial_mapsize(env
);
681 env
->nip
= bi
->entry
;
682 mmubooke_create_initial_mapping(env
);
685 static DeviceState
*ppce500_init_mpic_qemu(PPCE500MachineState
*pms
,
691 MachineState
*machine
= MACHINE(pms
);
692 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
694 dev
= qdev_create(NULL
, TYPE_OPENPIC
);
695 object_property_add_child(OBJECT(machine
), "pic", OBJECT(dev
),
697 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
698 qdev_prop_set_uint32(dev
, "nb_cpus", smp_cpus
);
700 qdev_init_nofail(dev
);
701 s
= SYS_BUS_DEVICE(dev
);
704 for (i
= 0; i
< smp_cpus
; i
++) {
705 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
706 sysbus_connect_irq(s
, k
++, irqs
[i
][j
]);
713 static DeviceState
*ppce500_init_mpic_kvm(const PPCE500MachineClass
*pmc
,
714 qemu_irq
**irqs
, Error
**errp
)
720 dev
= qdev_create(NULL
, TYPE_KVM_OPENPIC
);
721 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
723 object_property_set_bool(OBJECT(dev
), true, "realized", &err
);
725 error_propagate(errp
, err
);
726 object_unparent(OBJECT(dev
));
731 if (kvm_openpic_connect_vcpu(dev
, cs
)) {
732 fprintf(stderr
, "%s: failed to connect vcpu to irqchip\n",
741 static DeviceState
*ppce500_init_mpic(PPCE500MachineState
*pms
,
745 MachineState
*machine
= MACHINE(pms
);
746 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
747 DeviceState
*dev
= NULL
;
753 if (machine_kernel_irqchip_allowed(machine
)) {
754 dev
= ppce500_init_mpic_kvm(pmc
, irqs
, &err
);
756 if (machine_kernel_irqchip_required(machine
) && !dev
) {
757 error_reportf_err(err
,
758 "kernel_irqchip requested but unavailable: ");
764 dev
= ppce500_init_mpic_qemu(pms
, irqs
);
767 s
= SYS_BUS_DEVICE(dev
);
768 memory_region_add_subregion(ccsr
, MPC8544_MPIC_REGS_OFFSET
,
774 static void ppce500_power_off(void *opaque
, int line
, int on
)
777 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
781 void ppce500_init(MachineState
*machine
)
783 MemoryRegion
*address_space_mem
= get_system_memory();
784 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
785 PPCE500MachineState
*pms
= PPCE500_MACHINE(machine
);
786 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(machine
);
788 CPUPPCState
*env
= NULL
;
790 hwaddr kernel_base
= -1LL;
793 hwaddr initrd_base
= 0;
797 const char *payload_name
;
798 bool kernel_as_payload
;
799 hwaddr bios_entry
= 0;
800 target_long payload_size
;
801 struct boot_info
*boot_info
;
804 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
806 unsigned int pci_irq_nrs
[PCI_NUM_PINS
] = {1, 2, 3, 4};
808 DeviceState
*dev
, *mpicdev
;
809 CPUPPCState
*firstenv
= NULL
;
810 MemoryRegion
*ccsr_addr_space
;
812 PPCE500CCSRState
*ccsr
;
814 irqs
= g_malloc0(smp_cpus
* sizeof(qemu_irq
*));
815 irqs
[0] = g_malloc0(smp_cpus
* sizeof(qemu_irq
) * OPENPIC_OUTPUT_NB
);
816 for (i
= 0; i
< smp_cpus
; i
++) {
821 cpu
= POWERPC_CPU(cpu_create(machine
->cpu_type
));
825 if (env
->mmu_model
!= POWERPC_MMU_BOOKE206
) {
826 error_report("MMU model %i not supported by this machine",
835 irqs
[i
] = irqs
[0] + (i
* OPENPIC_OUTPUT_NB
);
836 input
= (qemu_irq
*)env
->irq_inputs
;
837 irqs
[i
][OPENPIC_OUTPUT_INT
] = input
[PPCE500_INPUT_INT
];
838 irqs
[i
][OPENPIC_OUTPUT_CINT
] = input
[PPCE500_INPUT_CINT
];
839 env
->spr_cb
[SPR_BOOKE_PIR
].default_value
= cs
->cpu_index
= i
;
840 env
->mpic_iack
= pmc
->ccsrbar_base
+ MPC8544_MPIC_REGS_OFFSET
+ 0xa0;
842 ppc_booke_timers_init(cpu
, 400000000, PPC_TIMER_E500
);
844 /* Register reset handler */
847 struct boot_info
*boot_info
;
848 boot_info
= g_malloc0(sizeof(struct boot_info
));
849 qemu_register_reset(ppce500_cpu_reset
, cpu
);
850 env
->load_info
= boot_info
;
853 qemu_register_reset(ppce500_cpu_reset_sec
, cpu
);
859 /* Fixup Memory size on a alignment boundary */
860 ram_size
&= ~(RAM_SIZES_ALIGN
- 1);
861 machine
->ram_size
= ram_size
;
863 /* Register Memory */
864 memory_region_allocate_system_memory(ram
, NULL
, "mpc8544ds.ram", ram_size
);
865 memory_region_add_subregion(address_space_mem
, 0, ram
);
867 dev
= qdev_create(NULL
, "e500-ccsr");
868 object_property_add_child(qdev_get_machine(), "e500-ccsr",
870 qdev_init_nofail(dev
);
872 ccsr_addr_space
= &ccsr
->ccsr_space
;
873 memory_region_add_subregion(address_space_mem
, pmc
->ccsrbar_base
,
876 mpicdev
= ppce500_init_mpic(pms
, ccsr_addr_space
, irqs
);
880 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL0_REGS_OFFSET
,
881 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
882 serial_hd(0), DEVICE_BIG_ENDIAN
);
886 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL1_REGS_OFFSET
,
887 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
888 serial_hd(1), DEVICE_BIG_ENDIAN
);
891 /* General Utility device */
892 dev
= qdev_create(NULL
, "mpc8544-guts");
893 qdev_init_nofail(dev
);
894 s
= SYS_BUS_DEVICE(dev
);
895 memory_region_add_subregion(ccsr_addr_space
, MPC8544_UTIL_OFFSET
,
896 sysbus_mmio_get_region(s
, 0));
899 dev
= qdev_create(NULL
, "e500-pcihost");
900 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev
),
902 qdev_prop_set_uint32(dev
, "first_slot", pmc
->pci_first_slot
);
903 qdev_prop_set_uint32(dev
, "first_pin_irq", pci_irq_nrs
[0]);
904 qdev_init_nofail(dev
);
905 s
= SYS_BUS_DEVICE(dev
);
906 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
907 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, pci_irq_nrs
[i
]));
910 memory_region_add_subregion(ccsr_addr_space
, MPC8544_PCI_REGS_OFFSET
,
911 sysbus_mmio_get_region(s
, 0));
913 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci.0");
915 printf("couldn't create PCI controller!\n");
918 /* Register network interfaces. */
919 for (i
= 0; i
< nb_nics
; i
++) {
920 pci_nic_init_nofail(&nd_table
[i
], pci_bus
, "virtio-net-pci", NULL
);
924 /* Register spinning region */
925 sysbus_create_simple("e500-spin", pmc
->spin_base
, NULL
);
927 if (pmc
->has_mpc8xxx_gpio
) {
928 qemu_irq poweroff_irq
;
930 dev
= qdev_create(NULL
, "mpc8xxx_gpio");
931 s
= SYS_BUS_DEVICE(dev
);
932 qdev_init_nofail(dev
);
933 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC8XXX_GPIO_IRQ
));
934 memory_region_add_subregion(ccsr_addr_space
, MPC8XXX_GPIO_OFFSET
,
935 sysbus_mmio_get_region(s
, 0));
937 /* Power Off GPIO at Pin 0 */
938 poweroff_irq
= qemu_allocate_irq(ppce500_power_off
, NULL
, 0);
939 qdev_connect_gpio_out(dev
, 0, poweroff_irq
);
942 /* Platform Bus Device */
943 if (pmc
->has_platform_bus
) {
944 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
945 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
946 qdev_prop_set_uint32(dev
, "num_irqs", pmc
->platform_bus_num_irqs
);
947 qdev_prop_set_uint32(dev
, "mmio_size", pmc
->platform_bus_size
);
948 qdev_init_nofail(dev
);
949 s
= SYS_BUS_DEVICE(dev
);
951 for (i
= 0; i
< pmc
->platform_bus_num_irqs
; i
++) {
952 int irqn
= pmc
->platform_bus_first_irq
+ i
;
953 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, irqn
));
956 memory_region_add_subregion(address_space_mem
,
957 pmc
->platform_bus_base
,
958 sysbus_mmio_get_region(s
, 0));
962 * Smart firmware defaults ahead!
964 * We follow the following table to select which payload we execute.
966 * -kernel | -bios | payload
967 * ---------+-------+---------
973 * This ensures backwards compatibility with how we used to expose
974 * -kernel to users but allows them to run through u-boot as well.
976 kernel_as_payload
= false;
977 if (bios_name
== NULL
) {
978 if (machine
->kernel_filename
) {
979 payload_name
= machine
->kernel_filename
;
980 kernel_as_payload
= true;
982 payload_name
= "u-boot.e500";
985 payload_name
= bios_name
;
988 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, payload_name
);
990 payload_size
= load_elf(filename
, NULL
, NULL
, &bios_entry
, &loadaddr
, NULL
,
991 1, PPC_ELF_MACHINE
, 0, 0);
992 if (payload_size
< 0) {
994 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
995 * ePAPR compliant kernel
997 payload_size
= load_uimage(filename
, &bios_entry
, &loadaddr
, NULL
,
999 if (payload_size
< 0) {
1000 error_report("qemu: could not load firmware '%s'", filename
);
1007 if (kernel_as_payload
) {
1008 kernel_base
= loadaddr
;
1009 kernel_size
= payload_size
;
1012 cur_base
= loadaddr
+ payload_size
;
1013 if (cur_base
< (32 * 1024 * 1024)) {
1014 /* u-boot occupies memory up to 32MB, so load blobs above */
1015 cur_base
= (32 * 1024 * 1024);
1018 /* Load bare kernel only if no bios/u-boot has been provided */
1019 if (machine
->kernel_filename
&& !kernel_as_payload
) {
1020 kernel_base
= cur_base
;
1021 kernel_size
= load_image_targphys(machine
->kernel_filename
,
1023 ram_size
- cur_base
);
1024 if (kernel_size
< 0) {
1025 error_report("could not load kernel '%s'",
1026 machine
->kernel_filename
);
1030 cur_base
+= kernel_size
;
1034 if (machine
->initrd_filename
) {
1035 initrd_base
= (cur_base
+ INITRD_LOAD_PAD
) & ~INITRD_PAD_MASK
;
1036 initrd_size
= load_image_targphys(machine
->initrd_filename
, initrd_base
,
1037 ram_size
- initrd_base
);
1039 if (initrd_size
< 0) {
1040 error_report("could not load initial ram disk '%s'",
1041 machine
->initrd_filename
);
1045 cur_base
= initrd_base
+ initrd_size
;
1049 * Reserve space for dtb behind the kernel image because Linux has a bug
1050 * where it can only handle the dtb if it's within the first 64MB of where
1051 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1052 * ensures enough space between kernel and initrd.
1054 dt_base
= (loadaddr
+ payload_size
+ DTC_LOAD_PAD
) & ~DTC_PAD_MASK
;
1055 if (dt_base
+ DTB_MAX_SIZE
> ram_size
) {
1056 error_report("qemu: not enough memory for device tree");
1060 dt_size
= ppce500_prep_device_tree(pms
, dt_base
,
1061 initrd_base
, initrd_size
,
1062 kernel_base
, kernel_size
);
1064 error_report("couldn't load device tree");
1067 assert(dt_size
< DTB_MAX_SIZE
);
1069 boot_info
= env
->load_info
;
1070 boot_info
->entry
= bios_entry
;
1071 boot_info
->dt_base
= dt_base
;
1072 boot_info
->dt_size
= dt_size
;
1075 static void e500_ccsr_initfn(Object
*obj
)
1077 PPCE500CCSRState
*ccsr
= CCSR(obj
);
1078 memory_region_init(&ccsr
->ccsr_space
, obj
, "e500-ccsr",
1079 MPC8544_CCSRBAR_SIZE
);
1082 static const TypeInfo e500_ccsr_info
= {
1084 .parent
= TYPE_SYS_BUS_DEVICE
,
1085 .instance_size
= sizeof(PPCE500CCSRState
),
1086 .instance_init
= e500_ccsr_initfn
,
1089 static const TypeInfo ppce500_info
= {
1090 .name
= TYPE_PPCE500_MACHINE
,
1091 .parent
= TYPE_MACHINE
,
1093 .class_size
= sizeof(PPCE500MachineClass
),
1096 static void e500_register_types(void)
1098 type_register_static(&e500_ccsr_info
);
1099 type_register_static(&ppce500_info
);
1102 type_init(e500_register_types
)