pc-dimm: pass in the machine and to the MemoryHotplugState
[qemu.git] / hw / i386 / pc.c
blobe94e63dc6c23d2519d47796d46ae826312341de4
1 /*
2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/i386/apic.h"
31 #include "hw/i386/topology.h"
32 #include "sysemu/cpus.h"
33 #include "hw/block/fdc.h"
34 #include "hw/ide.h"
35 #include "hw/pci/pci.h"
36 #include "hw/pci/pci_bus.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/timer/hpet.h"
39 #include "hw/smbios/smbios.h"
40 #include "hw/loader.h"
41 #include "elf.h"
42 #include "multiboot.h"
43 #include "hw/timer/mc146818rtc.h"
44 #include "hw/dma/i8257.h"
45 #include "hw/timer/i8254.h"
46 #include "hw/input/i8042.h"
47 #include "hw/audio/pcspk.h"
48 #include "hw/pci/msi.h"
49 #include "hw/sysbus.h"
50 #include "sysemu/sysemu.h"
51 #include "sysemu/numa.h"
52 #include "sysemu/kvm.h"
53 #include "sysemu/qtest.h"
54 #include "kvm_i386.h"
55 #include "hw/xen/xen.h"
56 #include "ui/qemu-spice.h"
57 #include "exec/memory.h"
58 #include "exec/address-spaces.h"
59 #include "sysemu/arch_init.h"
60 #include "qemu/bitmap.h"
61 #include "qemu/config-file.h"
62 #include "qemu/error-report.h"
63 #include "qemu/option.h"
64 #include "hw/acpi/acpi.h"
65 #include "hw/acpi/cpu_hotplug.h"
66 #include "hw/boards.h"
67 #include "hw/pci/pci_host.h"
68 #include "acpi-build.h"
69 #include "hw/mem/pc-dimm.h"
70 #include "qapi/error.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/visitor.h"
73 #include "qom/cpu.h"
74 #include "hw/nmi.h"
75 #include "hw/i386/intel_iommu.h"
76 #include "hw/net/ne2000-isa.h"
78 /* debug PC/ISA interrupts */
79 //#define DEBUG_IRQ
81 #ifdef DEBUG_IRQ
82 #define DPRINTF(fmt, ...) \
83 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
84 #else
85 #define DPRINTF(fmt, ...)
86 #endif
88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
94 #define E820_NR_ENTRIES 16
96 struct e820_entry {
97 uint64_t address;
98 uint64_t length;
99 uint32_t type;
100 } QEMU_PACKED __attribute((__aligned__(4)));
102 struct e820_table {
103 uint32_t count;
104 struct e820_entry entry[E820_NR_ENTRIES];
105 } QEMU_PACKED __attribute((__aligned__(4)));
107 static struct e820_table e820_reserve;
108 static struct e820_entry *e820_table;
109 static unsigned e820_entries;
110 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
112 void gsi_handler(void *opaque, int n, int level)
114 GSIState *s = opaque;
116 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
117 if (n < ISA_NUM_IRQS) {
118 qemu_set_irq(s->i8259_irq[n], level);
120 qemu_set_irq(s->ioapic_irq[n], level);
123 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
124 unsigned size)
128 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
130 return 0xffffffffffffffffULL;
133 /* MSDOS compatibility mode FPU exception support */
134 static qemu_irq ferr_irq;
136 void pc_register_ferr_irq(qemu_irq irq)
138 ferr_irq = irq;
141 /* XXX: add IGNNE support */
142 void cpu_set_ferr(CPUX86State *s)
144 qemu_irq_raise(ferr_irq);
147 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
148 unsigned size)
150 qemu_irq_lower(ferr_irq);
153 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
155 return 0xffffffffffffffffULL;
158 /* TSC handling */
159 uint64_t cpu_get_tsc(CPUX86State *env)
161 return cpu_get_ticks();
164 /* IRQ handling */
165 int cpu_get_pic_interrupt(CPUX86State *env)
167 X86CPU *cpu = x86_env_get_cpu(env);
168 int intno;
170 if (!kvm_irqchip_in_kernel()) {
171 intno = apic_get_interrupt(cpu->apic_state);
172 if (intno >= 0) {
173 return intno;
175 /* read the irq from the PIC */
176 if (!apic_accept_pic_intr(cpu->apic_state)) {
177 return -1;
181 intno = pic_read_irq(isa_pic);
182 return intno;
185 static void pic_irq_request(void *opaque, int irq, int level)
187 CPUState *cs = first_cpu;
188 X86CPU *cpu = X86_CPU(cs);
190 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
191 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
192 CPU_FOREACH(cs) {
193 cpu = X86_CPU(cs);
194 if (apic_accept_pic_intr(cpu->apic_state)) {
195 apic_deliver_pic_intr(cpu->apic_state, level);
198 } else {
199 if (level) {
200 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
201 } else {
202 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
207 /* PC cmos mappings */
209 #define REG_EQUIPMENT_BYTE 0x14
211 int cmos_get_fd_drive_type(FloppyDriveType fd0)
213 int val;
215 switch (fd0) {
216 case FLOPPY_DRIVE_TYPE_144:
217 /* 1.44 Mb 3"5 drive */
218 val = 4;
219 break;
220 case FLOPPY_DRIVE_TYPE_288:
221 /* 2.88 Mb 3"5 drive */
222 val = 5;
223 break;
224 case FLOPPY_DRIVE_TYPE_120:
225 /* 1.2 Mb 5"5 drive */
226 val = 2;
227 break;
228 case FLOPPY_DRIVE_TYPE_NONE:
229 default:
230 val = 0;
231 break;
233 return val;
236 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
237 int16_t cylinders, int8_t heads, int8_t sectors)
239 rtc_set_memory(s, type_ofs, 47);
240 rtc_set_memory(s, info_ofs, cylinders);
241 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
242 rtc_set_memory(s, info_ofs + 2, heads);
243 rtc_set_memory(s, info_ofs + 3, 0xff);
244 rtc_set_memory(s, info_ofs + 4, 0xff);
245 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
246 rtc_set_memory(s, info_ofs + 6, cylinders);
247 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
248 rtc_set_memory(s, info_ofs + 8, sectors);
251 /* convert boot_device letter to something recognizable by the bios */
252 static int boot_device2nibble(char boot_device)
254 switch(boot_device) {
255 case 'a':
256 case 'b':
257 return 0x01; /* floppy boot */
258 case 'c':
259 return 0x02; /* hard drive boot */
260 case 'd':
261 return 0x03; /* CD-ROM boot */
262 case 'n':
263 return 0x04; /* Network boot */
265 return 0;
268 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
270 #define PC_MAX_BOOT_DEVICES 3
271 int nbds, bds[3] = { 0, };
272 int i;
274 nbds = strlen(boot_device);
275 if (nbds > PC_MAX_BOOT_DEVICES) {
276 error_setg(errp, "Too many boot devices for PC");
277 return;
279 for (i = 0; i < nbds; i++) {
280 bds[i] = boot_device2nibble(boot_device[i]);
281 if (bds[i] == 0) {
282 error_setg(errp, "Invalid boot device for PC: '%c'",
283 boot_device[i]);
284 return;
287 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
288 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
291 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
293 set_boot_dev(opaque, boot_device, errp);
296 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
298 int val, nb, i;
299 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
300 FLOPPY_DRIVE_TYPE_NONE };
302 /* floppy type */
303 if (floppy) {
304 for (i = 0; i < 2; i++) {
305 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
308 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
309 cmos_get_fd_drive_type(fd_type[1]);
310 rtc_set_memory(rtc_state, 0x10, val);
312 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
313 nb = 0;
314 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
315 nb++;
317 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
318 nb++;
320 switch (nb) {
321 case 0:
322 break;
323 case 1:
324 val |= 0x01; /* 1 drive, ready for boot */
325 break;
326 case 2:
327 val |= 0x41; /* 2 drives, ready for boot */
328 break;
330 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
333 typedef struct pc_cmos_init_late_arg {
334 ISADevice *rtc_state;
335 BusState *idebus[2];
336 } pc_cmos_init_late_arg;
338 typedef struct check_fdc_state {
339 ISADevice *floppy;
340 bool multiple;
341 } CheckFdcState;
343 static int check_fdc(Object *obj, void *opaque)
345 CheckFdcState *state = opaque;
346 Object *fdc;
347 uint32_t iobase;
348 Error *local_err = NULL;
350 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
351 if (!fdc) {
352 return 0;
355 iobase = object_property_get_uint(obj, "iobase", &local_err);
356 if (local_err || iobase != 0x3f0) {
357 error_free(local_err);
358 return 0;
361 if (state->floppy) {
362 state->multiple = true;
363 } else {
364 state->floppy = ISA_DEVICE(obj);
366 return 0;
369 static const char * const fdc_container_path[] = {
370 "/unattached", "/peripheral", "/peripheral-anon"
374 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
375 * and ACPI objects.
377 ISADevice *pc_find_fdc0(void)
379 int i;
380 Object *container;
381 CheckFdcState state = { 0 };
383 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
384 container = container_get(qdev_get_machine(), fdc_container_path[i]);
385 object_child_foreach(container, check_fdc, &state);
388 if (state.multiple) {
389 warn_report("multiple floppy disk controllers with "
390 "iobase=0x3f0 have been found");
391 error_printf("the one being picked for CMOS setup might not reflect "
392 "your intent");
395 return state.floppy;
398 static void pc_cmos_init_late(void *opaque)
400 pc_cmos_init_late_arg *arg = opaque;
401 ISADevice *s = arg->rtc_state;
402 int16_t cylinders;
403 int8_t heads, sectors;
404 int val;
405 int i, trans;
407 val = 0;
408 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
409 &cylinders, &heads, &sectors) >= 0) {
410 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
411 val |= 0xf0;
413 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
414 &cylinders, &heads, &sectors) >= 0) {
415 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
416 val |= 0x0f;
418 rtc_set_memory(s, 0x12, val);
420 val = 0;
421 for (i = 0; i < 4; i++) {
422 /* NOTE: ide_get_geometry() returns the physical
423 geometry. It is always such that: 1 <= sects <= 63, 1
424 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
425 geometry can be different if a translation is done. */
426 if (arg->idebus[i / 2] &&
427 ide_get_geometry(arg->idebus[i / 2], i % 2,
428 &cylinders, &heads, &sectors) >= 0) {
429 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
430 assert((trans & ~3) == 0);
431 val |= trans << (i * 2);
434 rtc_set_memory(s, 0x39, val);
436 pc_cmos_init_floppy(s, pc_find_fdc0());
438 qemu_unregister_reset(pc_cmos_init_late, opaque);
441 void pc_cmos_init(PCMachineState *pcms,
442 BusState *idebus0, BusState *idebus1,
443 ISADevice *s)
445 int val;
446 static pc_cmos_init_late_arg arg;
448 /* various important CMOS locations needed by PC/Bochs bios */
450 /* memory size */
451 /* base memory (first MiB) */
452 val = MIN(pcms->below_4g_mem_size / 1024, 640);
453 rtc_set_memory(s, 0x15, val);
454 rtc_set_memory(s, 0x16, val >> 8);
455 /* extended memory (next 64MiB) */
456 if (pcms->below_4g_mem_size > 1024 * 1024) {
457 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024;
458 } else {
459 val = 0;
461 if (val > 65535)
462 val = 65535;
463 rtc_set_memory(s, 0x17, val);
464 rtc_set_memory(s, 0x18, val >> 8);
465 rtc_set_memory(s, 0x30, val);
466 rtc_set_memory(s, 0x31, val >> 8);
467 /* memory between 16MiB and 4GiB */
468 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) {
469 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536;
470 } else {
471 val = 0;
473 if (val > 65535)
474 val = 65535;
475 rtc_set_memory(s, 0x34, val);
476 rtc_set_memory(s, 0x35, val >> 8);
477 /* memory above 4GiB */
478 val = pcms->above_4g_mem_size / 65536;
479 rtc_set_memory(s, 0x5b, val);
480 rtc_set_memory(s, 0x5c, val >> 8);
481 rtc_set_memory(s, 0x5d, val >> 16);
483 object_property_add_link(OBJECT(pcms), "rtc_state",
484 TYPE_ISA_DEVICE,
485 (Object **)&pcms->rtc,
486 object_property_allow_set_link,
487 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
488 object_property_set_link(OBJECT(pcms), OBJECT(s),
489 "rtc_state", &error_abort);
491 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
493 val = 0;
494 val |= 0x02; /* FPU is there */
495 val |= 0x04; /* PS/2 mouse installed */
496 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
498 /* hard drives and FDC */
499 arg.rtc_state = s;
500 arg.idebus[0] = idebus0;
501 arg.idebus[1] = idebus1;
502 qemu_register_reset(pc_cmos_init_late, &arg);
505 #define TYPE_PORT92 "port92"
506 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
508 /* port 92 stuff: could be split off */
509 typedef struct Port92State {
510 ISADevice parent_obj;
512 MemoryRegion io;
513 uint8_t outport;
514 qemu_irq a20_out;
515 } Port92State;
517 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
518 unsigned size)
520 Port92State *s = opaque;
521 int oldval = s->outport;
523 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
524 s->outport = val;
525 qemu_set_irq(s->a20_out, (val >> 1) & 1);
526 if ((val & 1) && !(oldval & 1)) {
527 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
531 static uint64_t port92_read(void *opaque, hwaddr addr,
532 unsigned size)
534 Port92State *s = opaque;
535 uint32_t ret;
537 ret = s->outport;
538 DPRINTF("port92: read 0x%02x\n", ret);
539 return ret;
542 static void port92_init(ISADevice *dev, qemu_irq a20_out)
544 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
547 static const VMStateDescription vmstate_port92_isa = {
548 .name = "port92",
549 .version_id = 1,
550 .minimum_version_id = 1,
551 .fields = (VMStateField[]) {
552 VMSTATE_UINT8(outport, Port92State),
553 VMSTATE_END_OF_LIST()
557 static void port92_reset(DeviceState *d)
559 Port92State *s = PORT92(d);
561 s->outport &= ~1;
564 static const MemoryRegionOps port92_ops = {
565 .read = port92_read,
566 .write = port92_write,
567 .impl = {
568 .min_access_size = 1,
569 .max_access_size = 1,
571 .endianness = DEVICE_LITTLE_ENDIAN,
574 static void port92_initfn(Object *obj)
576 Port92State *s = PORT92(obj);
578 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
580 s->outport = 0;
582 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
585 static void port92_realizefn(DeviceState *dev, Error **errp)
587 ISADevice *isadev = ISA_DEVICE(dev);
588 Port92State *s = PORT92(dev);
590 isa_register_ioport(isadev, &s->io, 0x92);
593 static void port92_class_initfn(ObjectClass *klass, void *data)
595 DeviceClass *dc = DEVICE_CLASS(klass);
597 dc->realize = port92_realizefn;
598 dc->reset = port92_reset;
599 dc->vmsd = &vmstate_port92_isa;
601 * Reason: unlike ordinary ISA devices, this one needs additional
602 * wiring: its A20 output line needs to be wired up by
603 * port92_init().
605 dc->user_creatable = false;
608 static const TypeInfo port92_info = {
609 .name = TYPE_PORT92,
610 .parent = TYPE_ISA_DEVICE,
611 .instance_size = sizeof(Port92State),
612 .instance_init = port92_initfn,
613 .class_init = port92_class_initfn,
616 static void port92_register_types(void)
618 type_register_static(&port92_info);
621 type_init(port92_register_types)
623 static void handle_a20_line_change(void *opaque, int irq, int level)
625 X86CPU *cpu = opaque;
627 /* XXX: send to all CPUs ? */
628 /* XXX: add logic to handle multiple A20 line sources */
629 x86_cpu_set_a20(cpu, level);
632 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
634 int index = le32_to_cpu(e820_reserve.count);
635 struct e820_entry *entry;
637 if (type != E820_RAM) {
638 /* old FW_CFG_E820_TABLE entry -- reservations only */
639 if (index >= E820_NR_ENTRIES) {
640 return -EBUSY;
642 entry = &e820_reserve.entry[index++];
644 entry->address = cpu_to_le64(address);
645 entry->length = cpu_to_le64(length);
646 entry->type = cpu_to_le32(type);
648 e820_reserve.count = cpu_to_le32(index);
651 /* new "etc/e820" file -- include ram too */
652 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
653 e820_table[e820_entries].address = cpu_to_le64(address);
654 e820_table[e820_entries].length = cpu_to_le64(length);
655 e820_table[e820_entries].type = cpu_to_le32(type);
656 e820_entries++;
658 return e820_entries;
661 int e820_get_num_entries(void)
663 return e820_entries;
666 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
668 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
669 *address = le64_to_cpu(e820_table[idx].address);
670 *length = le64_to_cpu(e820_table[idx].length);
671 return true;
673 return false;
676 /* Enables contiguous-apic-ID mode, for compatibility */
677 static bool compat_apic_id_mode;
679 void enable_compat_apic_id_mode(void)
681 compat_apic_id_mode = true;
684 /* Calculates initial APIC ID for a specific CPU index
686 * Currently we need to be able to calculate the APIC ID from the CPU index
687 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
688 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
689 * all CPUs up to max_cpus.
691 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
693 uint32_t correct_id;
694 static bool warned;
696 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
697 if (compat_apic_id_mode) {
698 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
699 error_report("APIC IDs set in compatibility mode, "
700 "CPU topology won't match the configuration");
701 warned = true;
703 return cpu_index;
704 } else {
705 return correct_id;
709 static void pc_build_smbios(PCMachineState *pcms)
711 uint8_t *smbios_tables, *smbios_anchor;
712 size_t smbios_tables_len, smbios_anchor_len;
713 struct smbios_phys_mem_area *mem_array;
714 unsigned i, array_count;
715 MachineState *ms = MACHINE(pcms);
716 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
718 /* tell smbios about cpuid version and features */
719 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
721 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
722 if (smbios_tables) {
723 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
724 smbios_tables, smbios_tables_len);
727 /* build the array of physical mem area from e820 table */
728 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
729 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
730 uint64_t addr, len;
732 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
733 mem_array[array_count].address = addr;
734 mem_array[array_count].length = len;
735 array_count++;
738 smbios_get_tables(mem_array, array_count,
739 &smbios_tables, &smbios_tables_len,
740 &smbios_anchor, &smbios_anchor_len);
741 g_free(mem_array);
743 if (smbios_anchor) {
744 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
745 smbios_tables, smbios_tables_len);
746 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
747 smbios_anchor, smbios_anchor_len);
751 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
753 FWCfgState *fw_cfg;
754 uint64_t *numa_fw_cfg;
755 int i;
756 const CPUArchIdList *cpus;
757 MachineClass *mc = MACHINE_GET_CLASS(pcms);
759 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
760 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
762 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
764 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
765 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
766 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
767 * for CPU hotplug also uses APIC ID and not "CPU index".
768 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
769 * but the "limit to the APIC ID values SeaBIOS may see".
771 * So for compatibility reasons with old BIOSes we are stuck with
772 * "etc/max-cpus" actually being apic_id_limit
774 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
775 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
776 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
777 acpi_tables, acpi_tables_len);
778 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
780 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
781 &e820_reserve, sizeof(e820_reserve));
782 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
783 sizeof(struct e820_entry) * e820_entries);
785 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
786 /* allocate memory for the NUMA channel: one (64bit) word for the number
787 * of nodes, one word for each VCPU->node and one word for each node to
788 * hold the amount of memory.
790 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
791 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
792 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
793 for (i = 0; i < cpus->len; i++) {
794 unsigned int apic_id = cpus->cpus[i].arch_id;
795 assert(apic_id < pcms->apic_id_limit);
796 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
798 for (i = 0; i < nb_numa_nodes; i++) {
799 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
800 cpu_to_le64(numa_info[i].node_mem);
802 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
803 (1 + pcms->apic_id_limit + nb_numa_nodes) *
804 sizeof(*numa_fw_cfg));
806 return fw_cfg;
809 static long get_file_size(FILE *f)
811 long where, size;
813 /* XXX: on Unix systems, using fstat() probably makes more sense */
815 where = ftell(f);
816 fseek(f, 0, SEEK_END);
817 size = ftell(f);
818 fseek(f, where, SEEK_SET);
820 return size;
823 /* setup_data types */
824 #define SETUP_NONE 0
825 #define SETUP_E820_EXT 1
826 #define SETUP_DTB 2
827 #define SETUP_PCI 3
828 #define SETUP_EFI 4
830 struct setup_data {
831 uint64_t next;
832 uint32_t type;
833 uint32_t len;
834 uint8_t data[0];
835 } __attribute__((packed));
837 static void load_linux(PCMachineState *pcms,
838 FWCfgState *fw_cfg)
840 uint16_t protocol;
841 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
842 int dtb_size, setup_data_offset;
843 uint32_t initrd_max;
844 uint8_t header[8192], *setup, *kernel, *initrd_data;
845 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
846 FILE *f;
847 char *vmode;
848 MachineState *machine = MACHINE(pcms);
849 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
850 struct setup_data *setup_data;
851 const char *kernel_filename = machine->kernel_filename;
852 const char *initrd_filename = machine->initrd_filename;
853 const char *dtb_filename = machine->dtb;
854 const char *kernel_cmdline = machine->kernel_cmdline;
856 /* Align to 16 bytes as a paranoia measure */
857 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
859 /* load the kernel header */
860 f = fopen(kernel_filename, "rb");
861 if (!f || !(kernel_size = get_file_size(f)) ||
862 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
863 MIN(ARRAY_SIZE(header), kernel_size)) {
864 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
865 kernel_filename, strerror(errno));
866 exit(1);
869 /* kernel protocol version */
870 #if 0
871 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
872 #endif
873 if (ldl_p(header+0x202) == 0x53726448) {
874 protocol = lduw_p(header+0x206);
875 } else {
876 /* This looks like a multiboot kernel. If it is, let's stop
877 treating it like a Linux kernel. */
878 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
879 kernel_cmdline, kernel_size, header)) {
880 return;
882 protocol = 0;
885 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
886 /* Low kernel */
887 real_addr = 0x90000;
888 cmdline_addr = 0x9a000 - cmdline_size;
889 prot_addr = 0x10000;
890 } else if (protocol < 0x202) {
891 /* High but ancient kernel */
892 real_addr = 0x90000;
893 cmdline_addr = 0x9a000 - cmdline_size;
894 prot_addr = 0x100000;
895 } else {
896 /* High and recent kernel */
897 real_addr = 0x10000;
898 cmdline_addr = 0x20000;
899 prot_addr = 0x100000;
902 #if 0
903 fprintf(stderr,
904 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
905 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
906 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
907 real_addr,
908 cmdline_addr,
909 prot_addr);
910 #endif
912 /* highest address for loading the initrd */
913 if (protocol >= 0x203) {
914 initrd_max = ldl_p(header+0x22c);
915 } else {
916 initrd_max = 0x37ffffff;
919 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
920 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
923 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
924 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
925 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
927 if (protocol >= 0x202) {
928 stl_p(header+0x228, cmdline_addr);
929 } else {
930 stw_p(header+0x20, 0xA33F);
931 stw_p(header+0x22, cmdline_addr-real_addr);
934 /* handle vga= parameter */
935 vmode = strstr(kernel_cmdline, "vga=");
936 if (vmode) {
937 unsigned int video_mode;
938 /* skip "vga=" */
939 vmode += 4;
940 if (!strncmp(vmode, "normal", 6)) {
941 video_mode = 0xffff;
942 } else if (!strncmp(vmode, "ext", 3)) {
943 video_mode = 0xfffe;
944 } else if (!strncmp(vmode, "ask", 3)) {
945 video_mode = 0xfffd;
946 } else {
947 video_mode = strtol(vmode, NULL, 0);
949 stw_p(header+0x1fa, video_mode);
952 /* loader type */
953 /* High nybble = B reserved for QEMU; low nybble is revision number.
954 If this code is substantially changed, you may want to consider
955 incrementing the revision. */
956 if (protocol >= 0x200) {
957 header[0x210] = 0xB0;
959 /* heap */
960 if (protocol >= 0x201) {
961 header[0x211] |= 0x80; /* CAN_USE_HEAP */
962 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
965 /* load initrd */
966 if (initrd_filename) {
967 if (protocol < 0x200) {
968 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
969 exit(1);
972 initrd_size = get_image_size(initrd_filename);
973 if (initrd_size < 0) {
974 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
975 initrd_filename, strerror(errno));
976 exit(1);
979 initrd_addr = (initrd_max-initrd_size) & ~4095;
981 initrd_data = g_malloc(initrd_size);
982 load_image(initrd_filename, initrd_data);
984 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
985 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
986 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
988 stl_p(header+0x218, initrd_addr);
989 stl_p(header+0x21c, initrd_size);
992 /* load kernel and setup */
993 setup_size = header[0x1f1];
994 if (setup_size == 0) {
995 setup_size = 4;
997 setup_size = (setup_size+1)*512;
998 if (setup_size > kernel_size) {
999 fprintf(stderr, "qemu: invalid kernel header\n");
1000 exit(1);
1002 kernel_size -= setup_size;
1004 setup = g_malloc(setup_size);
1005 kernel = g_malloc(kernel_size);
1006 fseek(f, 0, SEEK_SET);
1007 if (fread(setup, 1, setup_size, f) != setup_size) {
1008 fprintf(stderr, "fread() failed\n");
1009 exit(1);
1011 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1012 fprintf(stderr, "fread() failed\n");
1013 exit(1);
1015 fclose(f);
1017 /* append dtb to kernel */
1018 if (dtb_filename) {
1019 if (protocol < 0x209) {
1020 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1021 exit(1);
1024 dtb_size = get_image_size(dtb_filename);
1025 if (dtb_size <= 0) {
1026 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1027 dtb_filename, strerror(errno));
1028 exit(1);
1031 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1032 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1033 kernel = g_realloc(kernel, kernel_size);
1035 stq_p(header+0x250, prot_addr + setup_data_offset);
1037 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1038 setup_data->next = 0;
1039 setup_data->type = cpu_to_le32(SETUP_DTB);
1040 setup_data->len = cpu_to_le32(dtb_size);
1042 load_image_size(dtb_filename, setup_data->data, dtb_size);
1045 memcpy(setup, header, MIN(sizeof(header), setup_size));
1047 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1048 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1049 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1051 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1052 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1053 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1055 option_rom[nb_option_roms].bootindex = 0;
1056 option_rom[nb_option_roms].name = "linuxboot.bin";
1057 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1058 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1060 nb_option_roms++;
1063 #define NE2000_NB_MAX 6
1065 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1066 0x280, 0x380 };
1067 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1069 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1071 static int nb_ne2k = 0;
1073 if (nb_ne2k == NE2000_NB_MAX)
1074 return;
1075 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1076 ne2000_irq[nb_ne2k], nd);
1077 nb_ne2k++;
1080 DeviceState *cpu_get_current_apic(void)
1082 if (current_cpu) {
1083 X86CPU *cpu = X86_CPU(current_cpu);
1084 return cpu->apic_state;
1085 } else {
1086 return NULL;
1090 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1092 X86CPU *cpu = opaque;
1094 if (level) {
1095 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1099 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
1101 Object *cpu = NULL;
1102 Error *local_err = NULL;
1104 cpu = object_new(typename);
1106 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1107 object_property_set_bool(cpu, true, "realized", &local_err);
1109 object_unref(cpu);
1110 error_propagate(errp, local_err);
1113 void pc_hot_add_cpu(const int64_t id, Error **errp)
1115 MachineState *ms = MACHINE(qdev_get_machine());
1116 int64_t apic_id = x86_cpu_apic_id_from_index(id);
1117 Error *local_err = NULL;
1119 if (id < 0) {
1120 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1121 return;
1124 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1125 error_setg(errp, "Unable to add CPU: %" PRIi64
1126 ", resulting APIC ID (%" PRIi64 ") is too large",
1127 id, apic_id);
1128 return;
1131 pc_new_cpu(ms->cpu_type, apic_id, &local_err);
1132 if (local_err) {
1133 error_propagate(errp, local_err);
1134 return;
1138 void pc_cpus_init(PCMachineState *pcms)
1140 int i;
1141 const CPUArchIdList *possible_cpus;
1142 MachineState *ms = MACHINE(pcms);
1143 MachineClass *mc = MACHINE_GET_CLASS(pcms);
1145 /* Calculates the limit to CPU APIC ID values
1147 * Limit for the APIC ID value, so that all
1148 * CPU APIC IDs are < pcms->apic_id_limit.
1150 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1152 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1153 possible_cpus = mc->possible_cpu_arch_ids(ms);
1154 for (i = 0; i < smp_cpus; i++) {
1155 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1156 &error_fatal);
1160 static void pc_build_feature_control_file(PCMachineState *pcms)
1162 MachineState *ms = MACHINE(pcms);
1163 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1164 CPUX86State *env = &cpu->env;
1165 uint32_t unused, ecx, edx;
1166 uint64_t feature_control_bits = 0;
1167 uint64_t *val;
1169 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1170 if (ecx & CPUID_EXT_VMX) {
1171 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1174 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1175 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1176 (env->mcg_cap & MCG_LMCE_P)) {
1177 feature_control_bits |= FEATURE_CONTROL_LMCE;
1180 if (!feature_control_bits) {
1181 return;
1184 val = g_malloc(sizeof(*val));
1185 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1186 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1189 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1191 if (cpus_count > 0xff) {
1192 /* If the number of CPUs can't be represented in 8 bits, the
1193 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1194 * to make old BIOSes fail more predictably.
1196 rtc_set_memory(rtc, 0x5f, 0);
1197 } else {
1198 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1202 static
1203 void pc_machine_done(Notifier *notifier, void *data)
1205 PCMachineState *pcms = container_of(notifier,
1206 PCMachineState, machine_done);
1207 PCIBus *bus = pcms->bus;
1209 /* set the number of CPUs */
1210 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1212 if (bus) {
1213 int extra_hosts = 0;
1215 QLIST_FOREACH(bus, &bus->child, sibling) {
1216 /* look for expander root buses */
1217 if (pci_bus_is_root(bus)) {
1218 extra_hosts++;
1221 if (extra_hosts && pcms->fw_cfg) {
1222 uint64_t *val = g_malloc(sizeof(*val));
1223 *val = cpu_to_le64(extra_hosts);
1224 fw_cfg_add_file(pcms->fw_cfg,
1225 "etc/extra-pci-roots", val, sizeof(*val));
1229 acpi_setup();
1230 if (pcms->fw_cfg) {
1231 pc_build_smbios(pcms);
1232 pc_build_feature_control_file(pcms);
1233 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1234 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1237 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1238 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1240 if (!iommu || !iommu->x86_iommu.intr_supported ||
1241 iommu->intr_eim != ON_OFF_AUTO_ON) {
1242 error_report("current -smp configuration requires "
1243 "Extended Interrupt Mode enabled. "
1244 "You can add an IOMMU using: "
1245 "-device intel-iommu,intremap=on,eim=on");
1246 exit(EXIT_FAILURE);
1251 void pc_guest_info_init(PCMachineState *pcms)
1253 int i;
1255 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1256 pcms->numa_nodes = nb_numa_nodes;
1257 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1258 sizeof *pcms->node_mem);
1259 for (i = 0; i < nb_numa_nodes; i++) {
1260 pcms->node_mem[i] = numa_info[i].node_mem;
1263 pcms->machine_done.notify = pc_machine_done;
1264 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1267 /* setup pci memory address space mapping into system address space */
1268 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1269 MemoryRegion *pci_address_space)
1271 /* Set to lower priority than RAM */
1272 memory_region_add_subregion_overlap(system_memory, 0x0,
1273 pci_address_space, -1);
1276 void pc_acpi_init(const char *default_dsdt)
1278 char *filename;
1280 if (acpi_tables != NULL) {
1281 /* manually set via -acpitable, leave it alone */
1282 return;
1285 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1286 if (filename == NULL) {
1287 warn_report("failed to find %s", default_dsdt);
1288 } else {
1289 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1290 &error_abort);
1291 Error *err = NULL;
1293 qemu_opt_set(opts, "file", filename, &error_abort);
1295 acpi_table_add_builtin(opts, &err);
1296 if (err) {
1297 warn_reportf_err(err, "failed to load %s: ", filename);
1299 g_free(filename);
1303 void xen_load_linux(PCMachineState *pcms)
1305 int i;
1306 FWCfgState *fw_cfg;
1308 assert(MACHINE(pcms)->kernel_filename != NULL);
1310 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1311 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1312 rom_set_fw(fw_cfg);
1314 load_linux(pcms, fw_cfg);
1315 for (i = 0; i < nb_option_roms; i++) {
1316 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1317 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1318 !strcmp(option_rom[i].name, "multiboot.bin"));
1319 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1321 pcms->fw_cfg = fw_cfg;
1324 void pc_memory_init(PCMachineState *pcms,
1325 MemoryRegion *system_memory,
1326 MemoryRegion *rom_memory,
1327 MemoryRegion **ram_memory)
1329 int linux_boot, i;
1330 MemoryRegion *ram, *option_rom_mr;
1331 MemoryRegion *ram_below_4g, *ram_above_4g;
1332 FWCfgState *fw_cfg;
1333 MachineState *machine = MACHINE(pcms);
1334 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1336 assert(machine->ram_size == pcms->below_4g_mem_size +
1337 pcms->above_4g_mem_size);
1339 linux_boot = (machine->kernel_filename != NULL);
1341 /* Allocate RAM. We allocate it as a single memory region and use
1342 * aliases to address portions of it, mostly for backwards compatibility
1343 * with older qemus that used qemu_ram_alloc().
1345 ram = g_malloc(sizeof(*ram));
1346 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1347 machine->ram_size);
1348 *ram_memory = ram;
1349 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1350 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1351 0, pcms->below_4g_mem_size);
1352 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1353 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1354 if (pcms->above_4g_mem_size > 0) {
1355 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1356 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1357 pcms->below_4g_mem_size,
1358 pcms->above_4g_mem_size);
1359 memory_region_add_subregion(system_memory, 0x100000000ULL,
1360 ram_above_4g);
1361 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1364 if (!pcmc->has_reserved_memory &&
1365 (machine->ram_slots ||
1366 (machine->maxram_size > machine->ram_size))) {
1367 MachineClass *mc = MACHINE_GET_CLASS(machine);
1369 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1370 mc->name);
1371 exit(EXIT_FAILURE);
1374 /* always allocate the device memory information */
1375 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1377 /* initialize hotplug memory address space */
1378 if (pcmc->has_reserved_memory &&
1379 (machine->ram_size < machine->maxram_size)) {
1380 ram_addr_t hotplug_mem_size =
1381 machine->maxram_size - machine->ram_size;
1383 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1384 error_report("unsupported amount of memory slots: %"PRIu64,
1385 machine->ram_slots);
1386 exit(EXIT_FAILURE);
1389 if (QEMU_ALIGN_UP(machine->maxram_size,
1390 TARGET_PAGE_SIZE) != machine->maxram_size) {
1391 error_report("maximum memory size must by aligned to multiple of "
1392 "%d bytes", TARGET_PAGE_SIZE);
1393 exit(EXIT_FAILURE);
1396 machine->device_memory->base =
1397 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30);
1399 if (pcmc->enforce_aligned_dimm) {
1400 /* size hotplug region assuming 1G page max alignment per slot */
1401 hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
1404 if ((machine->device_memory->base + hotplug_mem_size) <
1405 hotplug_mem_size) {
1406 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1407 machine->maxram_size);
1408 exit(EXIT_FAILURE);
1411 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1412 "hotplug-memory", hotplug_mem_size);
1413 memory_region_add_subregion(system_memory, machine->device_memory->base,
1414 &machine->device_memory->mr);
1417 /* Initialize PC system firmware */
1418 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1420 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1421 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1422 &error_fatal);
1423 if (pcmc->pci_enabled) {
1424 memory_region_set_readonly(option_rom_mr, true);
1426 memory_region_add_subregion_overlap(rom_memory,
1427 PC_ROM_MIN_VGA,
1428 option_rom_mr,
1431 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1433 rom_set_fw(fw_cfg);
1435 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1436 uint64_t *val = g_malloc(sizeof(*val));
1437 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1438 uint64_t res_mem_end = machine->device_memory->base;
1440 if (!pcmc->broken_reserved_end) {
1441 res_mem_end += memory_region_size(&machine->device_memory->mr);
1443 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30));
1444 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1447 if (linux_boot) {
1448 load_linux(pcms, fw_cfg);
1451 for (i = 0; i < nb_option_roms; i++) {
1452 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1454 pcms->fw_cfg = fw_cfg;
1456 /* Init default IOAPIC address space */
1457 pcms->ioapic_as = &address_space_memory;
1461 * The 64bit pci hole starts after "above 4G RAM" and
1462 * potentially the space reserved for memory hotplug.
1464 uint64_t pc_pci_hole64_start(void)
1466 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1467 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1468 MachineState *ms = MACHINE(pcms);
1469 uint64_t hole64_start = 0;
1471 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1472 hole64_start = ms->device_memory->base;
1473 if (!pcmc->broken_reserved_end) {
1474 hole64_start += memory_region_size(&ms->device_memory->mr);
1476 } else {
1477 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1480 return ROUND_UP(hole64_start, 1ULL << 30);
1483 qemu_irq pc_allocate_cpu_irq(void)
1485 return qemu_allocate_irq(pic_irq_request, NULL, 0);
1488 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1490 DeviceState *dev = NULL;
1492 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1493 if (pci_bus) {
1494 PCIDevice *pcidev = pci_vga_init(pci_bus);
1495 dev = pcidev ? &pcidev->qdev : NULL;
1496 } else if (isa_bus) {
1497 ISADevice *isadev = isa_vga_init(isa_bus);
1498 dev = isadev ? DEVICE(isadev) : NULL;
1500 rom_reset_order_override();
1501 return dev;
1504 static const MemoryRegionOps ioport80_io_ops = {
1505 .write = ioport80_write,
1506 .read = ioport80_read,
1507 .endianness = DEVICE_NATIVE_ENDIAN,
1508 .impl = {
1509 .min_access_size = 1,
1510 .max_access_size = 1,
1514 static const MemoryRegionOps ioportF0_io_ops = {
1515 .write = ioportF0_write,
1516 .read = ioportF0_read,
1517 .endianness = DEVICE_NATIVE_ENDIAN,
1518 .impl = {
1519 .min_access_size = 1,
1520 .max_access_size = 1,
1524 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1526 int i;
1527 DriveInfo *fd[MAX_FD];
1528 qemu_irq *a20_line;
1529 ISADevice *i8042, *port92, *vmmouse;
1531 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1532 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1534 for (i = 0; i < MAX_FD; i++) {
1535 fd[i] = drive_get(IF_FLOPPY, 0, i);
1536 create_fdctrl |= !!fd[i];
1538 if (create_fdctrl) {
1539 fdctrl_init_isa(isa_bus, fd);
1542 i8042 = isa_create_simple(isa_bus, "i8042");
1543 if (!no_vmport) {
1544 vmport_init(isa_bus);
1545 vmmouse = isa_try_create(isa_bus, "vmmouse");
1546 } else {
1547 vmmouse = NULL;
1549 if (vmmouse) {
1550 DeviceState *dev = DEVICE(vmmouse);
1551 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1552 qdev_init_nofail(dev);
1554 port92 = isa_create_simple(isa_bus, "port92");
1556 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1557 i8042_setup_a20_line(i8042, a20_line[0]);
1558 port92_init(port92, a20_line[1]);
1559 g_free(a20_line);
1562 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1563 ISADevice **rtc_state,
1564 bool create_fdctrl,
1565 bool no_vmport,
1566 bool has_pit,
1567 uint32_t hpet_irqs)
1569 int i;
1570 DeviceState *hpet = NULL;
1571 int pit_isa_irq = 0;
1572 qemu_irq pit_alt_irq = NULL;
1573 qemu_irq rtc_irq = NULL;
1574 ISADevice *pit = NULL;
1575 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1576 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1578 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1579 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1581 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1582 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1585 * Check if an HPET shall be created.
1587 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1588 * when the HPET wants to take over. Thus we have to disable the latter.
1590 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1591 /* In order to set property, here not using sysbus_try_create_simple */
1592 hpet = qdev_try_create(NULL, TYPE_HPET);
1593 if (hpet) {
1594 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1595 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1596 * IRQ8 and IRQ2.
1598 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1599 HPET_INTCAP, NULL);
1600 if (!compat) {
1601 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1603 qdev_init_nofail(hpet);
1604 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1606 for (i = 0; i < GSI_NUM_PINS; i++) {
1607 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1609 pit_isa_irq = -1;
1610 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1611 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1614 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1616 qemu_register_boot_set(pc_boot_set, *rtc_state);
1618 if (!xen_enabled() && has_pit) {
1619 if (kvm_pit_in_kernel()) {
1620 pit = kvm_pit_init(isa_bus, 0x40);
1621 } else {
1622 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1624 if (hpet) {
1625 /* connect PIT to output control line of the HPET */
1626 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1628 pcspk_init(isa_bus, pit);
1631 i8257_dma_init(isa_bus, 0);
1633 /* Super I/O */
1634 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1637 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1639 int i;
1641 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1642 for (i = 0; i < nb_nics; i++) {
1643 NICInfo *nd = &nd_table[i];
1644 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1646 if (g_str_equal(model, "ne2k_isa")) {
1647 pc_init_ne2k_isa(isa_bus, nd);
1648 } else {
1649 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1652 rom_reset_order_override();
1655 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1657 DeviceState *dev;
1658 SysBusDevice *d;
1659 unsigned int i;
1661 if (kvm_ioapic_in_kernel()) {
1662 dev = qdev_create(NULL, "kvm-ioapic");
1663 } else {
1664 dev = qdev_create(NULL, "ioapic");
1666 if (parent_name) {
1667 object_property_add_child(object_resolve_path(parent_name, NULL),
1668 "ioapic", OBJECT(dev), NULL);
1670 qdev_init_nofail(dev);
1671 d = SYS_BUS_DEVICE(dev);
1672 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1674 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1675 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1679 static void pc_dimm_plug(HotplugHandler *hotplug_dev,
1680 DeviceState *dev, Error **errp)
1682 HotplugHandlerClass *hhc;
1683 Error *local_err = NULL;
1684 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1685 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1686 PCDIMMDevice *dimm = PC_DIMM(dev);
1687 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1688 MemoryRegion *mr;
1689 uint64_t align = TARGET_PAGE_SIZE;
1690 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1692 mr = ddc->get_memory_region(dimm, &local_err);
1693 if (local_err) {
1694 goto out;
1697 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) {
1698 align = memory_region_get_alignment(mr);
1702 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1703 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1704 * addition to cover this case.
1706 if (!pcms->acpi_dev || !acpi_enabled) {
1707 error_setg(&local_err,
1708 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1709 goto out;
1712 if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
1713 error_setg(&local_err,
1714 "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1715 goto out;
1718 pc_dimm_memory_plug(dev, MACHINE(pcms), align, &local_err);
1719 if (local_err) {
1720 goto out;
1723 if (is_nvdimm) {
1724 nvdimm_plug(&pcms->acpi_nvdimm_state);
1727 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1728 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1729 out:
1730 error_propagate(errp, local_err);
1733 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev,
1734 DeviceState *dev, Error **errp)
1736 HotplugHandlerClass *hhc;
1737 Error *local_err = NULL;
1738 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1741 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1742 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1743 * addition to cover this case.
1745 if (!pcms->acpi_dev || !acpi_enabled) {
1746 error_setg(&local_err,
1747 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1748 goto out;
1751 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1752 error_setg(&local_err,
1753 "nvdimm device hot unplug is not supported yet.");
1754 goto out;
1757 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1758 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1760 out:
1761 error_propagate(errp, local_err);
1764 static void pc_dimm_unplug(HotplugHandler *hotplug_dev,
1765 DeviceState *dev, Error **errp)
1767 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1768 HotplugHandlerClass *hhc;
1769 Error *local_err = NULL;
1771 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1772 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1774 if (local_err) {
1775 goto out;
1778 pc_dimm_memory_unplug(dev, MACHINE(pcms));
1779 object_unparent(OBJECT(dev));
1781 out:
1782 error_propagate(errp, local_err);
1785 static int pc_apic_cmp(const void *a, const void *b)
1787 CPUArchId *apic_a = (CPUArchId *)a;
1788 CPUArchId *apic_b = (CPUArchId *)b;
1790 return apic_a->arch_id - apic_b->arch_id;
1793 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1794 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1795 * entry corresponding to CPU's apic_id returns NULL.
1797 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1799 CPUArchId apic_id, *found_cpu;
1801 apic_id.arch_id = id;
1802 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1803 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1804 pc_apic_cmp);
1805 if (found_cpu && idx) {
1806 *idx = found_cpu - ms->possible_cpus->cpus;
1808 return found_cpu;
1811 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1812 DeviceState *dev, Error **errp)
1814 CPUArchId *found_cpu;
1815 HotplugHandlerClass *hhc;
1816 Error *local_err = NULL;
1817 X86CPU *cpu = X86_CPU(dev);
1818 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1820 if (pcms->acpi_dev) {
1821 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1822 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1823 if (local_err) {
1824 goto out;
1828 /* increment the number of CPUs */
1829 pcms->boot_cpus++;
1830 if (pcms->rtc) {
1831 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1833 if (pcms->fw_cfg) {
1834 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1837 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1838 found_cpu->cpu = OBJECT(dev);
1839 out:
1840 error_propagate(errp, local_err);
1842 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1843 DeviceState *dev, Error **errp)
1845 int idx = -1;
1846 HotplugHandlerClass *hhc;
1847 Error *local_err = NULL;
1848 X86CPU *cpu = X86_CPU(dev);
1849 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1851 if (!pcms->acpi_dev) {
1852 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1853 goto out;
1856 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1857 assert(idx != -1);
1858 if (idx == 0) {
1859 error_setg(&local_err, "Boot CPU is unpluggable");
1860 goto out;
1863 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1864 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1866 if (local_err) {
1867 goto out;
1870 out:
1871 error_propagate(errp, local_err);
1875 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1876 DeviceState *dev, Error **errp)
1878 CPUArchId *found_cpu;
1879 HotplugHandlerClass *hhc;
1880 Error *local_err = NULL;
1881 X86CPU *cpu = X86_CPU(dev);
1882 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1884 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1885 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1887 if (local_err) {
1888 goto out;
1891 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1892 found_cpu->cpu = NULL;
1893 object_unparent(OBJECT(dev));
1895 /* decrement the number of CPUs */
1896 pcms->boot_cpus--;
1897 /* Update the number of CPUs in CMOS */
1898 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1899 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1900 out:
1901 error_propagate(errp, local_err);
1904 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1905 DeviceState *dev, Error **errp)
1907 int idx;
1908 CPUState *cs;
1909 CPUArchId *cpu_slot;
1910 X86CPUTopoInfo topo;
1911 X86CPU *cpu = X86_CPU(dev);
1912 MachineState *ms = MACHINE(hotplug_dev);
1913 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1915 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1916 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1917 ms->cpu_type);
1918 return;
1921 /* if APIC ID is not set, set it based on socket/core/thread properties */
1922 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1923 int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
1925 if (cpu->socket_id < 0) {
1926 error_setg(errp, "CPU socket-id is not set");
1927 return;
1928 } else if (cpu->socket_id > max_socket) {
1929 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1930 cpu->socket_id, max_socket);
1931 return;
1933 if (cpu->core_id < 0) {
1934 error_setg(errp, "CPU core-id is not set");
1935 return;
1936 } else if (cpu->core_id > (smp_cores - 1)) {
1937 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1938 cpu->core_id, smp_cores - 1);
1939 return;
1941 if (cpu->thread_id < 0) {
1942 error_setg(errp, "CPU thread-id is not set");
1943 return;
1944 } else if (cpu->thread_id > (smp_threads - 1)) {
1945 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1946 cpu->thread_id, smp_threads - 1);
1947 return;
1950 topo.pkg_id = cpu->socket_id;
1951 topo.core_id = cpu->core_id;
1952 topo.smt_id = cpu->thread_id;
1953 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
1956 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1957 if (!cpu_slot) {
1958 MachineState *ms = MACHINE(pcms);
1960 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1961 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1962 " APIC ID %" PRIu32 ", valid index range 0:%d",
1963 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
1964 ms->possible_cpus->len - 1);
1965 return;
1968 if (cpu_slot->cpu) {
1969 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1970 idx, cpu->apic_id);
1971 return;
1974 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1975 * so that machine_query_hotpluggable_cpus would show correct values
1977 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1978 * once -smp refactoring is complete and there will be CPU private
1979 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1980 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1981 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1982 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1983 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1984 return;
1986 cpu->socket_id = topo.pkg_id;
1988 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1989 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1990 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1991 return;
1993 cpu->core_id = topo.core_id;
1995 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1996 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1997 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1998 return;
2000 cpu->thread_id = topo.smt_id;
2002 cs = CPU(cpu);
2003 cs->cpu_index = idx;
2005 numa_cpu_pre_plug(cpu_slot, dev, errp);
2008 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2009 DeviceState *dev, Error **errp)
2011 if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2012 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2016 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2017 DeviceState *dev, Error **errp)
2019 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2020 pc_dimm_plug(hotplug_dev, dev, errp);
2021 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2022 pc_cpu_plug(hotplug_dev, dev, errp);
2026 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2027 DeviceState *dev, Error **errp)
2029 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2030 pc_dimm_unplug_request(hotplug_dev, dev, errp);
2031 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2032 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2033 } else {
2034 error_setg(errp, "acpi: device unplug request for not supported device"
2035 " type: %s", object_get_typename(OBJECT(dev)));
2039 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2040 DeviceState *dev, Error **errp)
2042 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2043 pc_dimm_unplug(hotplug_dev, dev, errp);
2044 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2045 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2046 } else {
2047 error_setg(errp, "acpi: device unplug for not supported device"
2048 " type: %s", object_get_typename(OBJECT(dev)));
2052 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2053 DeviceState *dev)
2055 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
2057 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2058 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2059 return HOTPLUG_HANDLER(machine);
2062 return pcmc->get_hotplug_handler ?
2063 pcmc->get_hotplug_handler(machine, dev) : NULL;
2066 static void
2067 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v,
2068 const char *name, void *opaque,
2069 Error **errp)
2071 MachineState *ms = MACHINE(obj);
2072 int64_t value = memory_region_size(&ms->device_memory->mr);
2074 visit_type_int(v, name, &value, errp);
2077 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2078 const char *name, void *opaque,
2079 Error **errp)
2081 PCMachineState *pcms = PC_MACHINE(obj);
2082 uint64_t value = pcms->max_ram_below_4g;
2084 visit_type_size(v, name, &value, errp);
2087 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2088 const char *name, void *opaque,
2089 Error **errp)
2091 PCMachineState *pcms = PC_MACHINE(obj);
2092 Error *error = NULL;
2093 uint64_t value;
2095 visit_type_size(v, name, &value, &error);
2096 if (error) {
2097 error_propagate(errp, error);
2098 return;
2100 if (value > (1ULL << 32)) {
2101 error_setg(&error,
2102 "Machine option 'max-ram-below-4g=%"PRIu64
2103 "' expects size less than or equal to 4G", value);
2104 error_propagate(errp, error);
2105 return;
2108 if (value < (1ULL << 20)) {
2109 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2110 "BIOS may not work with less than 1MiB", value);
2113 pcms->max_ram_below_4g = value;
2116 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2117 void *opaque, Error **errp)
2119 PCMachineState *pcms = PC_MACHINE(obj);
2120 OnOffAuto vmport = pcms->vmport;
2122 visit_type_OnOffAuto(v, name, &vmport, errp);
2125 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2126 void *opaque, Error **errp)
2128 PCMachineState *pcms = PC_MACHINE(obj);
2130 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2133 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2135 bool smm_available = false;
2137 if (pcms->smm == ON_OFF_AUTO_OFF) {
2138 return false;
2141 if (tcg_enabled() || qtest_enabled()) {
2142 smm_available = true;
2143 } else if (kvm_enabled()) {
2144 smm_available = kvm_has_smm();
2147 if (smm_available) {
2148 return true;
2151 if (pcms->smm == ON_OFF_AUTO_ON) {
2152 error_report("System Management Mode not supported by this hypervisor.");
2153 exit(1);
2155 return false;
2158 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2159 void *opaque, Error **errp)
2161 PCMachineState *pcms = PC_MACHINE(obj);
2162 OnOffAuto smm = pcms->smm;
2164 visit_type_OnOffAuto(v, name, &smm, errp);
2167 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2168 void *opaque, Error **errp)
2170 PCMachineState *pcms = PC_MACHINE(obj);
2172 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2175 static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2177 PCMachineState *pcms = PC_MACHINE(obj);
2179 return pcms->acpi_nvdimm_state.is_enabled;
2182 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2184 PCMachineState *pcms = PC_MACHINE(obj);
2186 pcms->acpi_nvdimm_state.is_enabled = value;
2189 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2191 PCMachineState *pcms = PC_MACHINE(obj);
2193 return pcms->smbus;
2196 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2198 PCMachineState *pcms = PC_MACHINE(obj);
2200 pcms->smbus = value;
2203 static bool pc_machine_get_sata(Object *obj, Error **errp)
2205 PCMachineState *pcms = PC_MACHINE(obj);
2207 return pcms->sata;
2210 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2212 PCMachineState *pcms = PC_MACHINE(obj);
2214 pcms->sata = value;
2217 static bool pc_machine_get_pit(Object *obj, Error **errp)
2219 PCMachineState *pcms = PC_MACHINE(obj);
2221 return pcms->pit;
2224 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2226 PCMachineState *pcms = PC_MACHINE(obj);
2228 pcms->pit = value;
2231 static void pc_machine_initfn(Object *obj)
2233 PCMachineState *pcms = PC_MACHINE(obj);
2235 pcms->max_ram_below_4g = 0; /* use default */
2236 pcms->smm = ON_OFF_AUTO_AUTO;
2237 pcms->vmport = ON_OFF_AUTO_AUTO;
2238 /* nvdimm is disabled on default. */
2239 pcms->acpi_nvdimm_state.is_enabled = false;
2240 /* acpi build is enabled by default if machine supports it */
2241 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2242 pcms->smbus = true;
2243 pcms->sata = true;
2244 pcms->pit = true;
2247 static void pc_machine_reset(void)
2249 CPUState *cs;
2250 X86CPU *cpu;
2252 qemu_devices_reset();
2254 /* Reset APIC after devices have been reset to cancel
2255 * any changes that qemu_devices_reset() might have done.
2257 CPU_FOREACH(cs) {
2258 cpu = X86_CPU(cs);
2260 if (cpu->apic_state) {
2261 device_reset(cpu->apic_state);
2266 static CpuInstanceProperties
2267 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2269 MachineClass *mc = MACHINE_GET_CLASS(ms);
2270 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2272 assert(cpu_index < possible_cpus->len);
2273 return possible_cpus->cpus[cpu_index].props;
2276 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2278 X86CPUTopoInfo topo;
2280 assert(idx < ms->possible_cpus->len);
2281 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2282 smp_cores, smp_threads, &topo);
2283 return topo.pkg_id % nb_numa_nodes;
2286 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2288 int i;
2290 if (ms->possible_cpus) {
2292 * make sure that max_cpus hasn't changed since the first use, i.e.
2293 * -smp hasn't been parsed after it
2295 assert(ms->possible_cpus->len == max_cpus);
2296 return ms->possible_cpus;
2299 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2300 sizeof(CPUArchId) * max_cpus);
2301 ms->possible_cpus->len = max_cpus;
2302 for (i = 0; i < ms->possible_cpus->len; i++) {
2303 X86CPUTopoInfo topo;
2305 ms->possible_cpus->cpus[i].type = ms->cpu_type;
2306 ms->possible_cpus->cpus[i].vcpus_count = 1;
2307 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
2308 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2309 smp_cores, smp_threads, &topo);
2310 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2311 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2312 ms->possible_cpus->cpus[i].props.has_core_id = true;
2313 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2314 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2315 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2317 return ms->possible_cpus;
2320 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2322 /* cpu index isn't used */
2323 CPUState *cs;
2325 CPU_FOREACH(cs) {
2326 X86CPU *cpu = X86_CPU(cs);
2328 if (!cpu->apic_state) {
2329 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2330 } else {
2331 apic_deliver_nmi(cpu->apic_state);
2336 static void pc_machine_class_init(ObjectClass *oc, void *data)
2338 MachineClass *mc = MACHINE_CLASS(oc);
2339 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2340 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2341 NMIClass *nc = NMI_CLASS(oc);
2343 pcmc->get_hotplug_handler = mc->get_hotplug_handler;
2344 pcmc->pci_enabled = true;
2345 pcmc->has_acpi_build = true;
2346 pcmc->rsdp_in_ram = true;
2347 pcmc->smbios_defaults = true;
2348 pcmc->smbios_uuid_encoded = true;
2349 pcmc->gigabyte_align = true;
2350 pcmc->has_reserved_memory = true;
2351 pcmc->kvmclock_enabled = true;
2352 pcmc->enforce_aligned_dimm = true;
2353 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2354 * to be used at the moment, 32K should be enough for a while. */
2355 pcmc->acpi_data_size = 0x20000 + 0x8000;
2356 pcmc->save_tsc_khz = true;
2357 pcmc->linuxboot_dma_enabled = true;
2358 mc->get_hotplug_handler = pc_get_hotpug_handler;
2359 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2360 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2361 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2362 mc->auto_enable_numa_with_memhp = true;
2363 mc->has_hotpluggable_cpus = true;
2364 mc->default_boot_order = "cad";
2365 mc->hot_add_cpu = pc_hot_add_cpu;
2366 mc->block_default_type = IF_IDE;
2367 mc->max_cpus = 255;
2368 mc->reset = pc_machine_reset;
2369 hc->pre_plug = pc_machine_device_pre_plug_cb;
2370 hc->plug = pc_machine_device_plug_cb;
2371 hc->unplug_request = pc_machine_device_unplug_request_cb;
2372 hc->unplug = pc_machine_device_unplug_cb;
2373 nc->nmi_monitor_handler = x86_nmi;
2374 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2376 object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int",
2377 pc_machine_get_hotplug_memory_region_size, NULL,
2378 NULL, NULL, &error_abort);
2380 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2381 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2382 NULL, NULL, &error_abort);
2384 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2385 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2387 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2388 pc_machine_get_smm, pc_machine_set_smm,
2389 NULL, NULL, &error_abort);
2390 object_class_property_set_description(oc, PC_MACHINE_SMM,
2391 "Enable SMM (pc & q35)", &error_abort);
2393 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2394 pc_machine_get_vmport, pc_machine_set_vmport,
2395 NULL, NULL, &error_abort);
2396 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2397 "Enable vmport (pc & q35)", &error_abort);
2399 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2400 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2402 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2403 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2405 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2406 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2408 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2409 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2412 static const TypeInfo pc_machine_info = {
2413 .name = TYPE_PC_MACHINE,
2414 .parent = TYPE_MACHINE,
2415 .abstract = true,
2416 .instance_size = sizeof(PCMachineState),
2417 .instance_init = pc_machine_initfn,
2418 .class_size = sizeof(PCMachineClass),
2419 .class_init = pc_machine_class_init,
2420 .interfaces = (InterfaceInfo[]) {
2421 { TYPE_HOTPLUG_HANDLER },
2422 { TYPE_NMI },
2427 static void pc_machine_register_types(void)
2429 type_register_static(&pc_machine_info);
2432 type_init(pc_machine_register_types)