pc-dimm: pass in the machine and to the MemoryHotplugState
[qemu.git] / hw / acpi / pcihp.c
blob91c82fdc7a1b872c7327c899f13cace3f27447e3
1 /*
2 * QEMU<->ACPI BIOS PCI hotplug interface
4 * QEMU supports PCI hotplug via ACPI. This module
5 * implements the interface between QEMU and the ACPI BIOS.
6 * Interface specification - see docs/specs/acpi_pci_hotplug.txt
8 * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
9 * Copyright (c) 2006 Fabrice Bellard
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License version 2 as published by the Free Software Foundation.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>
23 * Contributions after 2012-01-13 are licensed under the terms of the
24 * GNU GPL, version 2 or (at your option) any later version.
27 #include "qemu/osdep.h"
28 #include "hw/acpi/pcihp.h"
30 #include "hw/hw.h"
31 #include "hw/i386/pc.h"
32 #include "hw/pci/pci.h"
33 #include "hw/acpi/acpi.h"
34 #include "sysemu/sysemu.h"
35 #include "exec/ioport.h"
36 #include "exec/address-spaces.h"
37 #include "hw/pci/pci_bus.h"
38 #include "qapi/error.h"
39 #include "qom/qom-qobject.h"
41 //#define DEBUG
43 #ifdef DEBUG
44 # define ACPI_PCIHP_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
45 #else
46 # define ACPI_PCIHP_DPRINTF(format, ...) do { } while (0)
47 #endif
49 #define ACPI_PCIHP_ADDR 0xae00
50 #define ACPI_PCIHP_SIZE 0x0014
51 #define PCI_UP_BASE 0x0000
52 #define PCI_DOWN_BASE 0x0004
53 #define PCI_EJ_BASE 0x0008
54 #define PCI_RMV_BASE 0x000c
55 #define PCI_SEL_BASE 0x0010
57 typedef struct AcpiPciHpFind {
58 int bsel;
59 PCIBus *bus;
60 } AcpiPciHpFind;
62 static int acpi_pcihp_get_bsel(PCIBus *bus)
64 Error *local_err = NULL;
65 uint64_t bsel = object_property_get_uint(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
66 &local_err);
68 if (local_err || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
69 if (local_err) {
70 error_free(local_err);
72 return -1;
73 } else {
74 return bsel;
78 /* Assign BSEL property to all buses. In the future, this can be changed
79 * to only assign to buses that support hotplug.
81 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
83 unsigned *bsel_alloc = opaque;
84 unsigned *bus_bsel;
86 if (qbus_is_hotpluggable(BUS(bus))) {
87 bus_bsel = g_malloc(sizeof *bus_bsel);
89 *bus_bsel = (*bsel_alloc)++;
90 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
91 bus_bsel, &error_abort);
94 return bsel_alloc;
97 static void acpi_set_pci_info(void)
99 static bool bsel_is_set;
100 PCIBus *bus;
101 unsigned bsel_alloc = ACPI_PCIHP_BSEL_DEFAULT;
103 if (bsel_is_set) {
104 return;
106 bsel_is_set = true;
108 bus = find_i440fx(); /* TODO: Q35 support */
109 if (bus) {
110 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
111 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
115 static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
117 AcpiPciHpFind *find = opaque;
118 if (find->bsel == acpi_pcihp_get_bsel(bus)) {
119 find->bus = bus;
123 static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
125 AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
127 if (bsel < 0) {
128 return NULL;
131 pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
133 /* Make bsel 0 eject root bus if bsel property is not set,
134 * for compatibility with non acpi setups.
135 * TODO: really needed?
137 if (!bsel && !find.bus) {
138 find.bus = s->root;
140 return find.bus;
143 static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
145 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
146 DeviceClass *dc = DEVICE_GET_CLASS(dev);
148 * ACPI doesn't allow hotplug of bridge devices. Don't allow
149 * hot-unplug of bridge devices unless they were added by hotplug
150 * (and so, not described by acpi).
152 return (pc->is_bridge && !dev->qdev.hotplugged) || !dc->hotpluggable;
155 static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
157 BusChild *kid, *next;
158 int slot = ctz32(slots);
159 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
161 if (!bus) {
162 return;
165 /* Mark request as complete */
166 s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
167 s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot);
169 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
170 DeviceState *qdev = kid->child;
171 PCIDevice *dev = PCI_DEVICE(qdev);
172 if (PCI_SLOT(dev->devfn) == slot) {
173 if (!acpi_pcihp_pc_no_hotplug(s, dev)) {
174 object_unparent(OBJECT(qdev));
180 static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
182 BusChild *kid, *next;
183 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
185 /* Execute any pending removes during reset */
186 while (s->acpi_pcihp_pci_status[bsel].down) {
187 acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
190 s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
192 if (!bus) {
193 return;
195 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
196 DeviceState *qdev = kid->child;
197 PCIDevice *pdev = PCI_DEVICE(qdev);
198 int slot = PCI_SLOT(pdev->devfn);
200 if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
201 s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
206 static void acpi_pcihp_update(AcpiPciHpState *s)
208 int i;
210 for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
211 acpi_pcihp_update_hotplug_bus(s, i);
215 void acpi_pcihp_reset(AcpiPciHpState *s)
217 acpi_set_pci_info();
218 acpi_pcihp_update(s);
221 void acpi_pcihp_device_plug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
222 DeviceState *dev, Error **errp)
224 PCIDevice *pdev = PCI_DEVICE(dev);
225 int slot = PCI_SLOT(pdev->devfn);
226 int bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev));
227 if (bsel < 0) {
228 error_setg(errp, "Unsupported bus. Bus doesn't have property '"
229 ACPI_PCIHP_PROP_BSEL "' set");
230 return;
233 /* Don't send event when device is enabled during qemu machine creation:
234 * it is present on boot, no hotplug event is necessary. We do send an
235 * event when the device is disabled later. */
236 if (!dev->hotplugged) {
237 return;
240 s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
241 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
244 void acpi_pcihp_device_unplug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
245 DeviceState *dev, Error **errp)
247 PCIDevice *pdev = PCI_DEVICE(dev);
248 int slot = PCI_SLOT(pdev->devfn);
249 int bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev));
250 if (bsel < 0) {
251 error_setg(errp, "Unsupported bus. Bus doesn't have property '"
252 ACPI_PCIHP_PROP_BSEL "' set");
253 return;
256 s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
257 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
260 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
262 AcpiPciHpState *s = opaque;
263 uint32_t val = 0;
264 int bsel = s->hotplug_select;
266 if (bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
267 return 0;
270 switch (addr) {
271 case PCI_UP_BASE:
272 val = s->acpi_pcihp_pci_status[bsel].up;
273 if (!s->legacy_piix) {
274 s->acpi_pcihp_pci_status[bsel].up = 0;
276 ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
277 break;
278 case PCI_DOWN_BASE:
279 val = s->acpi_pcihp_pci_status[bsel].down;
280 ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
281 break;
282 case PCI_EJ_BASE:
283 /* No feature defined yet */
284 ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
285 break;
286 case PCI_RMV_BASE:
287 val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
288 ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
289 break;
290 case PCI_SEL_BASE:
291 val = s->hotplug_select;
292 ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
293 default:
294 break;
297 return val;
300 static void pci_write(void *opaque, hwaddr addr, uint64_t data,
301 unsigned int size)
303 AcpiPciHpState *s = opaque;
304 switch (addr) {
305 case PCI_EJ_BASE:
306 if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
307 break;
309 acpi_pcihp_eject_slot(s, s->hotplug_select, data);
310 ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
311 addr, data);
312 break;
313 case PCI_SEL_BASE:
314 s->hotplug_select = s->legacy_piix ? ACPI_PCIHP_BSEL_DEFAULT : data;
315 ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
316 addr, data);
317 default:
318 break;
322 static const MemoryRegionOps acpi_pcihp_io_ops = {
323 .read = pci_read,
324 .write = pci_write,
325 .endianness = DEVICE_LITTLE_ENDIAN,
326 .valid = {
327 .min_access_size = 4,
328 .max_access_size = 4,
332 void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
333 MemoryRegion *address_space_io, bool bridges_enabled)
335 s->io_len = ACPI_PCIHP_SIZE;
336 s->io_base = ACPI_PCIHP_ADDR;
338 s->root= root_bus;
339 s->legacy_piix = !bridges_enabled;
341 memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
342 "acpi-pci-hotplug", s->io_len);
343 memory_region_add_subregion(address_space_io, s->io_base, &s->io);
345 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
346 &error_abort);
347 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
348 &error_abort);
351 const VMStateDescription vmstate_acpi_pcihp_pci_status = {
352 .name = "acpi_pcihp_pci_status",
353 .version_id = 1,
354 .minimum_version_id = 1,
355 .fields = (VMStateField[]) {
356 VMSTATE_UINT32(up, AcpiPciHpPciStatus),
357 VMSTATE_UINT32(down, AcpiPciHpPciStatus),
358 VMSTATE_END_OF_LIST()