hw/riscv/spike.c

   1 /*
   2  * QEMU RISC-V Spike Board
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This provides a RISC-V Board with the following devices:
   8  *
   9  * 0) HTIF Console and Poweroff
  10  * 1) CLINT (Timer and IPI)
  11  * 2) PLIC (Platform Level Interrupt Controller)
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under the terms and conditions of the GNU General Public License,
  15  * version 2 or later, as published by the Free Software Foundation.
  16  *
  17  * This program is distributed in the hope it will be useful, but WITHOUT
  18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20  * more details.
  21  *
  22  * You should have received a copy of the GNU General Public License along with
  23  * this program.  If not, see <http://www.gnu.org/licenses/>.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu/log.h"
  28 #include "qemu/error-report.h"
  29 #include "qapi/error.h"
  30 #include "hw/boards.h"
  31 #include "hw/loader.h"
  32 #include "hw/sysbus.h"
  33 #include "target/riscv/cpu.h"
  34 #include "hw/riscv/riscv_htif.h"
  35 #include "hw/riscv/riscv_hart.h"
  36 #include "hw/riscv/sifive_clint.h"
  37 #include "hw/riscv/spike.h"
  38 #include "hw/riscv/boot.h"
  39 #include "chardev/char.h"
  40 #include "sysemu/arch_init.h"
  41 #include "sysemu/device_tree.h"
  42 #include "sysemu/qtest.h"
  43 #include "sysemu/sysemu.h"
  44
  45 /*
  46  * Not like other RISC-V machines that use plain binary bios images,
  47  * keeping ELF files here was intentional because BIN files don't work
  48  * for the Spike machine as HTIF emulation depends on ELF parsing.
  49  */
  50 #if defined(TARGET_RISCV32)
  51 # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.elf"
  52 #else
  53 # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.elf"
  54 #endif
  55
  56 static const struct MemmapEntry {
  57     hwaddr base;
  58     hwaddr size;
  59 } spike_memmap[] = {
  60     [SPIKE_MROM] =     {     0x1000,     0xf000 },
  61     [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
  62     [SPIKE_DRAM] =     { 0x80000000,        0x0 },
  63 };
  64
  65 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
  66     uint64_t mem_size, const char *cmdline)
  67 {
  68     void *fdt;
  69     int cpu;
  70     uint32_t *cells;
  71     char *nodename;
  72
  73     fdt = s->fdt = create_device_tree(&s->fdt_size);
  74     if (!fdt) {
  75         error_report("create_device_tree() failed");
  76         exit(1);
  77     }
  78
  79     qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
  80     qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
  81     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
  82     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
  83
  84     qemu_fdt_add_subnode(fdt, "/htif");
  85     qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
  86
  87     qemu_fdt_add_subnode(fdt, "/soc");
  88     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
  89     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
  90     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
  91     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
  92
  93     nodename = g_strdup_printf("/memory@%lx",
  94         (long)memmap[SPIKE_DRAM].base);
  95     qemu_fdt_add_subnode(fdt, nodename);
  96     qemu_fdt_setprop_cells(fdt, nodename, "reg",
  97         memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
  98         mem_size >> 32, mem_size);
  99     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 100     g_free(nodename);
 101
 102     qemu_fdt_add_subnode(fdt, "/cpus");
 103     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 104         SIFIVE_CLINT_TIMEBASE_FREQ);
 105     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 106     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 107
 108     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 109         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 110         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 111         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 112         qemu_fdt_add_subnode(fdt, nodename);
 113 #if defined(TARGET_RISCV32)
 114         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
 115 #else
 116         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 117 #endif
 118         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 119         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 120         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 121         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 122         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 123         qemu_fdt_add_subnode(fdt, intc);
 124         qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
 125         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 126         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 127         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 128         g_free(isa);
 129         g_free(intc);
 130         g_free(nodename);
 131     }
 132
 133     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 134     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 135         nodename =
 136             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 137         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 138         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 139         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 140         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 141         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 142         g_free(nodename);
 143     }
 144     nodename = g_strdup_printf("/soc/clint@%lx",
 145         (long)memmap[SPIKE_CLINT].base);
 146     qemu_fdt_add_subnode(fdt, nodename);
 147     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 148     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 149         0x0, memmap[SPIKE_CLINT].base,
 150         0x0, memmap[SPIKE_CLINT].size);
 151     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 152         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 153     g_free(cells);
 154     g_free(nodename);
 155
 156     if (cmdline) {
 157         qemu_fdt_add_subnode(fdt, "/chosen");
 158         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 159     }
 160 }
 161
 162 static void spike_board_init(MachineState *machine)
 163 {
 164     const struct MemmapEntry *memmap = spike_memmap;
 165
 166     SpikeState *s = g_new0(SpikeState, 1);
 167     MemoryRegion *system_memory = get_system_memory();
 168     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 169     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 170     unsigned int smp_cpus = machine->smp.cpus;
 171     uint32_t fdt_load_addr;
 172     uint64_t kernel_entry;
 173
 174     /* Initialize SOC */
 175     object_initialize_child(OBJECT(machine), "soc", &s->soc,
 176                             TYPE_RISCV_HART_ARRAY);
 177     object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
 178                             &error_abort);
 179     object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
 180                             &error_abort);
 181     sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
 182
 183     /* register system main memory (actual RAM) */
 184     memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
 185                            machine->ram_size, &error_fatal);
 186     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
 187         main_mem);
 188
 189     /* create device tree */
 190     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 191
 192     /* boot rom */
 193     memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
 194                            memmap[SPIKE_MROM].size, &error_fatal);
 195     memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
 196                                 mask_rom);
 197
 198     riscv_find_and_load_firmware(machine, BIOS_FILENAME,
 199                                  memmap[SPIKE_DRAM].base,
 200                                  htif_symbol_callback);
 201
 202     if (machine->kernel_filename) {
 203         kernel_entry = riscv_load_kernel(machine->kernel_filename,
 204                                          htif_symbol_callback);
 205
 206         if (machine->initrd_filename) {
 207             hwaddr start;
 208             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 209                                            machine->ram_size, kernel_entry,
 210                                            &start);
 211             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 212                                   "linux,initrd-start", start);
 213             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 214                                   end);
 215         }
 216     } else {
 217        /*
 218         * If dynamic firmware is used, it doesn't know where is the next mode
 219         * if kernel argument is not set.
 220         */
 221         kernel_entry = 0;
 222     }
 223
 224     /* Compute the fdt load address in dram */
 225     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
 226                                    machine->ram_size, s->fdt);
 227     /* load the reset vector */
 228     riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
 229                               memmap[SPIKE_MROM].size, kernel_entry,
 230                               fdt_load_addr, s->fdt);
 231
 232     /* initialize HTIF using symbols found in load_kernel */
 233     htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
 234
 235     /* Core Local Interruptor (timer and IPI) */
 236     sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
 237         smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 238         false);
 239 }
 240
 241 static void spike_machine_init(MachineClass *mc)
 242 {
 243     mc->desc = "RISC-V Spike Board";
 244     mc->init = spike_board_init;
 245     mc->max_cpus = 8;
 246     mc->is_default = true;
 247     mc->default_cpu_type = SPIKE_V1_10_0_CPU;
 248 }
 249
 250 DEFINE_MACHINE("spike", spike_machine_init)