target-xtensa/translate.c

   1 /*
   2  * Xtensa ISA:
   3  * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
   4  *
   5  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in the
  14  *       documentation and/or other materials provided with the distribution.
  15  *     * Neither the name of the Open Source and Linux Lab nor the
  16  *       names of its contributors may be used to endorse or promote products
  17  *       derived from this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <stdio.h>
  32
  33 #include "cpu.h"
  34 #include "exec-all.h"
  35 #include "disas.h"
  36 #include "tcg-op.h"
  37 #include "qemu-log.h"
  38
  39 #include "helpers.h"
  40 #define GEN_HELPER 1
  41 #include "helpers.h"
  42
  43 typedef struct DisasContext {
  44     const XtensaConfig *config;
  45     TranslationBlock *tb;
  46     uint32_t pc;
  47     uint32_t next_pc;
  48     int is_jmp;
  49     int singlestep_enabled;
  50 } DisasContext;
  51
  52 static TCGv_ptr cpu_env;
  53 static TCGv_i32 cpu_pc;
  54 static TCGv_i32 cpu_R[16];
  55
  56 #include "gen-icount.h"
  57
  58 void xtensa_translate_init(void)
  59 {
  60     static const char * const regnames[] = {
  61         "ar0", "ar1", "ar2", "ar3",
  62         "ar4", "ar5", "ar6", "ar7",
  63         "ar8", "ar9", "ar10", "ar11",
  64         "ar12", "ar13", "ar14", "ar15",
  65     };
  66     int i;
  67
  68     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
  69     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
  70             offsetof(CPUState, pc), "pc");
  71
  72     for (i = 0; i < 16; i++) {
  73         cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
  74                 offsetof(CPUState, regs[i]),
  75                 regnames[i]);
  76     }
  77 #define GEN_HELPER 2
  78 #include "helpers.h"
  79 }
  80
  81 static inline bool option_enabled(DisasContext *dc, int opt)
  82 {
  83     return xtensa_option_enabled(dc->config, opt);
  84 }
  85
  86 static void gen_exception(int excp)
  87 {
  88     TCGv_i32 tmp = tcg_const_i32(excp);
  89     gen_helper_exception(tmp);
  90     tcg_temp_free(tmp);
  91 }
  92
  93 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
  94 {
  95     tcg_gen_mov_i32(cpu_pc, dest);
  96     if (dc->singlestep_enabled) {
  97         gen_exception(EXCP_DEBUG);
  98     } else {
  99         if (slot >= 0) {
 100             tcg_gen_goto_tb(slot);
 101             tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
 102         } else {
 103             tcg_gen_exit_tb(0);
 104         }
 105     }
 106     dc->is_jmp = DISAS_UPDATE;
 107 }
 108
 109 static void gen_jump(DisasContext *dc, TCGv dest)
 110 {
 111     gen_jump_slot(dc, dest, -1);
 112 }
 113
 114 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
 115 {
 116     TCGv_i32 tmp = tcg_const_i32(dest);
 117     if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
 118         slot = -1;
 119     }
 120     gen_jump_slot(dc, tmp, slot);
 121     tcg_temp_free(tmp);
 122 }
 123
 124 static void gen_brcond(DisasContext *dc, TCGCond cond,
 125         TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
 126 {
 127     int label = gen_new_label();
 128
 129     tcg_gen_brcond_i32(cond, t0, t1, label);
 130     gen_jumpi(dc, dc->next_pc, 0);
 131     gen_set_label(label);
 132     gen_jumpi(dc, dc->pc + offset, 1);
 133 }
 134
 135 static void gen_brcondi(DisasContext *dc, TCGCond cond,
 136         TCGv_i32 t0, uint32_t t1, uint32_t offset)
 137 {
 138     TCGv_i32 tmp = tcg_const_i32(t1);
 139     gen_brcond(dc, cond, t0, tmp, offset);
 140     tcg_temp_free(tmp);
 141 }
 142
 143 static void disas_xtensa_insn(DisasContext *dc)
 144 {
 145 #define HAS_OPTION(opt) do { \
 146         if (!option_enabled(dc, opt)) { \
 147             qemu_log("Option %d is not enabled %s:%d\n", \
 148                     (opt), __FILE__, __LINE__); \
 149             goto invalid_opcode; \
 150         } \
 151     } while (0)
 152
 153 #ifdef TARGET_WORDS_BIGENDIAN
 154 #define OP0 (((b0) & 0xf0) >> 4)
 155 #define OP1 (((b2) & 0xf0) >> 4)
 156 #define OP2 ((b2) & 0xf)
 157 #define RRR_R ((b1) & 0xf)
 158 #define RRR_S (((b1) & 0xf0) >> 4)
 159 #define RRR_T ((b0) & 0xf)
 160 #else
 161 #define OP0 (((b0) & 0xf))
 162 #define OP1 (((b2) & 0xf))
 163 #define OP2 (((b2) & 0xf0) >> 4)
 164 #define RRR_R (((b1) & 0xf0) >> 4)
 165 #define RRR_S (((b1) & 0xf))
 166 #define RRR_T (((b0) & 0xf0) >> 4)
 167 #endif
 168
 169 #define RRRN_R RRR_R
 170 #define RRRN_S RRR_S
 171 #define RRRN_T RRR_T
 172
 173 #define RRI8_R RRR_R
 174 #define RRI8_S RRR_S
 175 #define RRI8_T RRR_T
 176 #define RRI8_IMM8 (b2)
 177 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
 178
 179 #ifdef TARGET_WORDS_BIGENDIAN
 180 #define RI16_IMM16 (((b1) << 8) | (b2))
 181 #else
 182 #define RI16_IMM16 (((b2) << 8) | (b1))
 183 #endif
 184
 185 #ifdef TARGET_WORDS_BIGENDIAN
 186 #define CALL_N (((b0) & 0xc) >> 2)
 187 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
 188 #else
 189 #define CALL_N (((b0) & 0x30) >> 4)
 190 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
 191 #endif
 192 #define CALL_OFFSET_SE \
 193     (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
 194
 195 #define CALLX_N CALL_N
 196 #ifdef TARGET_WORDS_BIGENDIAN
 197 #define CALLX_M ((b0) & 0x3)
 198 #else
 199 #define CALLX_M (((b0) & 0xc0) >> 6)
 200 #endif
 201 #define CALLX_S RRR_S
 202
 203 #define BRI12_M CALLX_M
 204 #define BRI12_S RRR_S
 205 #ifdef TARGET_WORDS_BIGENDIAN
 206 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
 207 #else
 208 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
 209 #endif
 210 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
 211
 212 #define BRI8_M BRI12_M
 213 #define BRI8_R RRI8_R
 214 #define BRI8_S RRI8_S
 215 #define BRI8_IMM8 RRI8_IMM8
 216 #define BRI8_IMM8_SE RRI8_IMM8_SE
 217
 218 #define RSR_SR (b1)
 219
 220     uint8_t b0 = ldub_code(dc->pc);
 221     uint8_t b1 = ldub_code(dc->pc + 1);
 222     uint8_t b2 = ldub_code(dc->pc + 2);
 223
 224     static const uint32_t B4CONST[] = {
 225         0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
 226     };
 227
 228     static const uint32_t B4CONSTU[] = {
 229         32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
 230     };
 231
 232     if (OP0 >= 8) {
 233         dc->next_pc = dc->pc + 2;
 234         HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
 235     } else {
 236         dc->next_pc = dc->pc + 3;
 237     }
 238
 239     switch (OP0) {
 240     case 0: /*QRST*/
 241         switch (OP1) {
 242         case 0: /*RST0*/
 243             switch (OP2) {
 244             case 0: /*ST0*/
 245                 if ((RRR_R & 0xc) == 0x8) {
 246                     HAS_OPTION(XTENSA_OPTION_BOOLEAN);
 247                 }
 248
 249                 switch (RRR_R) {
 250                 case 0: /*SNM0*/
 251                     break;
 252
 253                 case 1: /*MOVSPw*/
 254                     HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
 255                     break;
 256
 257                 case 2: /*SYNC*/
 258                     break;
 259
 260                 case 3:
 261                     break;
 262
 263                 }
 264                 break;
 265
 266             case 1: /*AND*/
 267                 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
 268                 break;
 269
 270             case 2: /*OR*/
 271                 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
 272                 break;
 273
 274             case 3: /*XOR*/
 275                 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
 276                 break;
 277
 278             case 4: /*ST1*/
 279                 break;
 280
 281             case 5: /*TLB*/
 282                 break;
 283
 284             case 6: /*RT0*/
 285                 switch (RRR_S) {
 286                 case 0: /*NEG*/
 287                     tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
 288                     break;
 289
 290                 case 1: /*ABS*/
 291                     {
 292                         int label = gen_new_label();
 293                         tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
 294                         tcg_gen_brcondi_i32(
 295                                 TCG_COND_GE, cpu_R[RRR_R], 0, label);
 296                         tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
 297                         gen_set_label(label);
 298                     }
 299                     break;
 300
 301                 default: /*reserved*/
 302                     break;
 303                 }
 304                 break;
 305
 306             case 7: /*reserved*/
 307                 break;
 308
 309             case 8: /*ADD*/
 310                 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
 311                 break;
 312
 313             case 9: /*ADD**/
 314             case 10:
 315             case 11:
 316                 {
 317                     TCGv_i32 tmp = tcg_temp_new_i32();
 318                     tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
 319                     tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
 320                     tcg_temp_free(tmp);
 321                 }
 322                 break;
 323
 324             case 12: /*SUB*/
 325                 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
 326                 break;
 327
 328             case 13: /*SUB**/
 329             case 14:
 330             case 15:
 331                 {
 332                     TCGv_i32 tmp = tcg_temp_new_i32();
 333                     tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
 334                     tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
 335                     tcg_temp_free(tmp);
 336                 }
 337                 break;
 338             }
 339             break;
 340
 341         case 1: /*RST1*/
 342             break;
 343
 344         case 2: /*RST2*/
 345             break;
 346
 347         case 3: /*RST3*/
 348             break;
 349
 350         case 4: /*EXTUI*/
 351         case 5:
 352             break;
 353
 354         case 6: /*CUST0*/
 355             break;
 356
 357         case 7: /*CUST1*/
 358             break;
 359
 360         case 8: /*LSCXp*/
 361             HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
 362             break;
 363
 364         case 9: /*LSC4*/
 365             break;
 366
 367         case 10: /*FP0*/
 368             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
 369             break;
 370
 371         case 11: /*FP1*/
 372             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
 373             break;
 374
 375         default: /*reserved*/
 376             break;
 377         }
 378         break;
 379
 380     case 1: /*L32R*/
 381         {
 382             TCGv_i32 tmp = tcg_const_i32(
 383                     (0xfffc0000 | (RI16_IMM16 << 2)) +
 384                     ((dc->pc + 3) & ~3));
 385
 386             /* no ext L32R */
 387
 388             tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0);
 389             tcg_temp_free(tmp);
 390         }
 391         break;
 392
 393     case 2: /*LSAI*/
 394         break;
 395
 396     case 3: /*LSCIp*/
 397         HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
 398         break;
 399
 400     case 4: /*MAC16d*/
 401         HAS_OPTION(XTENSA_OPTION_MAC16);
 402         break;
 403
 404     case 5: /*CALLN*/
 405         switch (CALL_N) {
 406         case 0: /*CALL0*/
 407             tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
 408             gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
 409             break;
 410
 411         case 1: /*CALL4w*/
 412         case 2: /*CALL8w*/
 413         case 3: /*CALL12w*/
 414             HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
 415             break;
 416         }
 417         break;
 418
 419     case 6: /*SI*/
 420         switch (CALL_N) {
 421         case 0: /*J*/
 422             gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
 423             break;
 424
 425         case 1: /*BZ*/
 426             {
 427                 static const TCGCond cond[] = {
 428                     TCG_COND_EQ, /*BEQZ*/
 429                     TCG_COND_NE, /*BNEZ*/
 430                     TCG_COND_LT, /*BLTZ*/
 431                     TCG_COND_GE, /*BGEZ*/
 432                 };
 433
 434                 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
 435                         4 + BRI12_IMM12_SE);
 436             }
 437             break;
 438
 439         case 2: /*BI0*/
 440             {
 441                 static const TCGCond cond[] = {
 442                     TCG_COND_EQ, /*BEQI*/
 443                     TCG_COND_NE, /*BNEI*/
 444                     TCG_COND_LT, /*BLTI*/
 445                     TCG_COND_GE, /*BGEI*/
 446                 };
 447
 448                 gen_brcondi(dc, cond[BRI8_M & 3],
 449                         cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
 450             }
 451             break;
 452
 453         case 3: /*BI1*/
 454             switch (BRI8_M) {
 455             case 0: /*ENTRYw*/
 456                 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
 457                 break;
 458
 459             case 1: /*B1*/
 460                 switch (BRI8_R) {
 461                 case 0: /*BFp*/
 462                     HAS_OPTION(XTENSA_OPTION_BOOLEAN);
 463                     break;
 464
 465                 case 1: /*BTp*/
 466                     HAS_OPTION(XTENSA_OPTION_BOOLEAN);
 467                     break;
 468
 469                 case 8: /*LOOP*/
 470                     break;
 471
 472                 case 9: /*LOOPNEZ*/
 473                     break;
 474
 475                 case 10: /*LOOPGTZ*/
 476                     break;
 477
 478                 default: /*reserved*/
 479                     break;
 480
 481                 }
 482                 break;
 483
 484             case 2: /*BLTUI*/
 485             case 3: /*BGEUI*/
 486                 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
 487                         cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
 488                 break;
 489             }
 490             break;
 491
 492         }
 493         break;
 494
 495     case 7: /*B*/
 496         {
 497             TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
 498
 499             switch (RRI8_R & 7) {
 500             case 0: /*BNONE*/ /*BANY*/
 501                 {
 502                     TCGv_i32 tmp = tcg_temp_new_i32();
 503                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
 504                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
 505                     tcg_temp_free(tmp);
 506                 }
 507                 break;
 508
 509             case 1: /*BEQ*/ /*BNE*/
 510             case 2: /*BLT*/ /*BGE*/
 511             case 3: /*BLTU*/ /*BGEU*/
 512                 {
 513                     static const TCGCond cond[] = {
 514                         [1] = TCG_COND_EQ,
 515                         [2] = TCG_COND_LT,
 516                         [3] = TCG_COND_LTU,
 517                         [9] = TCG_COND_NE,
 518                         [10] = TCG_COND_GE,
 519                         [11] = TCG_COND_GEU,
 520                     };
 521                     gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
 522                             4 + RRI8_IMM8_SE);
 523                 }
 524                 break;
 525
 526             case 4: /*BALL*/ /*BNALL*/
 527                 {
 528                     TCGv_i32 tmp = tcg_temp_new_i32();
 529                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
 530                     gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
 531                             4 + RRI8_IMM8_SE);
 532                     tcg_temp_free(tmp);
 533                 }
 534                 break;
 535
 536             case 5: /*BBC*/ /*BBS*/
 537                 {
 538                     TCGv_i32 bit = tcg_const_i32(1);
 539                     TCGv_i32 tmp = tcg_temp_new_i32();
 540                     tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
 541                     tcg_gen_shl_i32(bit, bit, tmp);
 542                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
 543                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
 544                     tcg_temp_free(tmp);
 545                     tcg_temp_free(bit);
 546                 }
 547                 break;
 548
 549             case 6: /*BBCI*/ /*BBSI*/
 550             case 7:
 551                 {
 552                     TCGv_i32 tmp = tcg_temp_new_i32();
 553                     tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
 554                             1 << (((RRI8_R & 1) << 4) | RRI8_T));
 555                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
 556                     tcg_temp_free(tmp);
 557                 }
 558                 break;
 559
 560             }
 561         }
 562         break;
 563
 564 #define gen_narrow_load_store(type) do { \
 565             TCGv_i32 addr = tcg_temp_new_i32(); \
 566             tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
 567             tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
 568             tcg_temp_free(addr); \
 569         } while (0)
 570
 571     case 8: /*L32I.Nn*/
 572         gen_narrow_load_store(ld32u);
 573         break;
 574
 575     case 9: /*S32I.Nn*/
 576         gen_narrow_load_store(st32);
 577         break;
 578 #undef gen_narrow_load_store
 579
 580     case 10: /*ADD.Nn*/
 581         tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
 582         break;
 583
 584     case 11: /*ADDI.Nn*/
 585         tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
 586         break;
 587
 588     case 12: /*ST2n*/
 589         if (RRRN_T < 8) { /*MOVI.Nn*/
 590             tcg_gen_movi_i32(cpu_R[RRRN_S],
 591                     RRRN_R | (RRRN_T << 4) |
 592                     ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
 593         } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
 594             TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
 595
 596             gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
 597                     4 + (RRRN_R | ((RRRN_T & 3) << 4)));
 598         }
 599         break;
 600
 601     case 13: /*ST3n*/
 602         switch (RRRN_R) {
 603         case 0: /*MOV.Nn*/
 604             tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
 605             break;
 606
 607         case 15: /*S3*/
 608             switch (RRRN_T) {
 609             case 0: /*RET.Nn*/
 610                 gen_jump(dc, cpu_R[0]);
 611                 break;
 612
 613             case 1: /*RETW.Nn*/
 614                 break;
 615
 616             case 2: /*BREAK.Nn*/
 617                 break;
 618
 619             case 3: /*NOP.Nn*/
 620                 break;
 621
 622             case 6: /*ILL.Nn*/
 623                 break;
 624
 625             default: /*reserved*/
 626                 break;
 627             }
 628             break;
 629
 630         default: /*reserved*/
 631             break;
 632         }
 633         break;
 634
 635     default: /*reserved*/
 636         break;
 637     }
 638
 639     dc->pc = dc->next_pc;
 640     return;
 641
 642 invalid_opcode:
 643     qemu_log("INVALID(pc = %08x)\n", dc->pc);
 644     dc->pc = dc->next_pc;
 645 #undef HAS_OPTION
 646 }
 647
 648 static void check_breakpoint(CPUState *env, DisasContext *dc)
 649 {
 650     CPUBreakpoint *bp;
 651
 652     if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
 653         QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
 654             if (bp->pc == dc->pc) {
 655                 tcg_gen_movi_i32(cpu_pc, dc->pc);
 656                 gen_exception(EXCP_DEBUG);
 657                 dc->is_jmp = DISAS_UPDATE;
 658              }
 659         }
 660     }
 661 }
 662
 663 static void gen_intermediate_code_internal(
 664         CPUState *env, TranslationBlock *tb, int search_pc)
 665 {
 666     DisasContext dc;
 667     int insn_count = 0;
 668     int j, lj = -1;
 669     uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
 670     int max_insns = tb->cflags & CF_COUNT_MASK;
 671     uint32_t pc_start = tb->pc;
 672     uint32_t next_page_start =
 673         (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
 674
 675     if (max_insns == 0) {
 676         max_insns = CF_COUNT_MASK;
 677     }
 678
 679     dc.config = env->config;
 680     dc.singlestep_enabled = env->singlestep_enabled;
 681     dc.tb = tb;
 682     dc.pc = pc_start;
 683     dc.is_jmp = DISAS_NEXT;
 684
 685     gen_icount_start();
 686
 687     do {
 688         check_breakpoint(env, &dc);
 689
 690         if (search_pc) {
 691             j = gen_opc_ptr - gen_opc_buf;
 692             if (lj < j) {
 693                 lj++;
 694                 while (lj < j) {
 695                     gen_opc_instr_start[lj++] = 0;
 696                 }
 697             }
 698             gen_opc_pc[lj] = dc.pc;
 699             gen_opc_instr_start[lj] = 1;
 700             gen_opc_icount[lj] = insn_count;
 701         }
 702
 703         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
 704             tcg_gen_debug_insn_start(dc.pc);
 705         }
 706
 707         disas_xtensa_insn(&dc);
 708         ++insn_count;
 709         if (env->singlestep_enabled) {
 710             tcg_gen_movi_i32(cpu_pc, dc.pc);
 711             gen_exception(EXCP_DEBUG);
 712             break;
 713         }
 714     } while (dc.is_jmp == DISAS_NEXT &&
 715             insn_count < max_insns &&
 716             dc.pc < next_page_start &&
 717             gen_opc_ptr < gen_opc_end);
 718
 719     if (dc.is_jmp == DISAS_NEXT) {
 720         gen_jumpi(&dc, dc.pc, 0);
 721     }
 722     gen_icount_end(tb, insn_count);
 723     *gen_opc_ptr = INDEX_op_end;
 724
 725     if (!search_pc) {
 726         tb->size = dc.pc - pc_start;
 727         tb->icount = insn_count;
 728     }
 729 }
 730
 731 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
 732 {
 733     gen_intermediate_code_internal(env, tb, 0);
 734 }
 735
 736 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
 737 {
 738     gen_intermediate_code_internal(env, tb, 1);
 739 }
 740
 741 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
 742         int flags)
 743 {
 744     int i;
 745
 746     cpu_fprintf(f, "PC=%08x\n", env->pc);
 747
 748     for (i = 0; i < 16; ++i) {
 749         cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
 750                 (i % 4) == 3 ? '\n' : ' ');
 751     }
 752 }
 753
 754 void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
 755 {
 756     env->pc = gen_opc_pc[pc_pos];
 757 }