hw/intc/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/error-report.h"
  25 #include "monitor/monitor.h"
  26 #include "hw/hw.h"
  27 #include "hw/i386/pc.h"
  28 #include "hw/i386/apic.h"
  29 #include "hw/i386/ioapic.h"
  30 #include "hw/i386/ioapic_internal.h"
  31 #include "include/hw/pci/msi.h"
  32 #include "sysemu/kvm.h"
  33 #include "target/i386/cpu.h"
  34 #include "hw/i386/apic-msidef.h"
  35 #include "hw/i386/x86-iommu.h"
  36 #include "trace.h"
  37
  38 #define APIC_DELIVERY_MODE_SHIFT 8
  39 #define APIC_POLARITY_SHIFT 14
  40 #define APIC_TRIG_MODE_SHIFT 15
  41
  42 static IOAPICCommonState *ioapics[MAX_IOAPICS];
  43
  44 /* global variable from ioapic_common.c */
  45 extern int ioapic_no;
  46
  47 struct ioapic_entry_info {
  48     /* fields parsed from IOAPIC entries */
  49     uint8_t masked;
  50     uint8_t trig_mode;
  51     uint16_t dest_idx;
  52     uint8_t dest_mode;
  53     uint8_t delivery_mode;
  54     uint8_t vector;
  55
  56     /* MSI message generated from above parsed fields */
  57     uint32_t addr;
  58     uint32_t data;
  59 };
  60
  61 static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info)
  62 {
  63     memset(info, 0, sizeof(*info));
  64     info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1;
  65     info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
  66     /*
  67      * By default, this would be dest_id[8] + reserved[8]. When IR
  68      * is enabled, this would be interrupt_index[15] +
  69      * interrupt_format[1]. This field never means anything, but
  70      * only used to generate corresponding MSI.
  71      */
  72     info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff;
  73     info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
  74     info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \
  75         & IOAPIC_DM_MASK;
  76     if (info->delivery_mode == IOAPIC_DM_EXTINT) {
  77         info->vector = pic_read_irq(isa_pic);
  78     } else {
  79         info->vector = entry & IOAPIC_VECTOR_MASK;
  80     }
  81
  82     info->addr = APIC_DEFAULT_ADDRESS | \
  83         (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \
  84         (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
  85     info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \
  86         (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \
  87         (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
  88 }
  89
  90 static void ioapic_service(IOAPICCommonState *s)
  91 {
  92     AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;
  93     struct ioapic_entry_info info;
  94     uint8_t i;
  95     uint32_t mask;
  96     uint64_t entry;
  97
  98     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  99         mask = 1 << i;
 100         if (s->irr & mask) {
 101             int coalesce = 0;
 102
 103             entry = s->ioredtbl[i];
 104             ioapic_entry_parse(entry, &info);
 105             if (!info.masked) {
 106                 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
 107                     s->irr &= ~mask;
 108                 } else {
 109                     coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
 110                     trace_ioapic_set_remote_irr(i);
 111                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
 112                 }
 113
 114                 if (coalesce) {
 115                     /* We are level triggered interrupts, and the
 116                      * guest should be still working on previous one,
 117                      * so skip it. */
 118                     continue;
 119                 }
 120
 121 #ifdef CONFIG_KVM
 122                 if (kvm_irqchip_is_split()) {
 123                     if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
 124                         kvm_set_irq(kvm_state, i, 1);
 125                         kvm_set_irq(kvm_state, i, 0);
 126                     } else {
 127                         kvm_set_irq(kvm_state, i, 1);
 128                     }
 129                     continue;
 130                 }
 131 #endif
 132
 133                 /* No matter whether IR is enabled, we translate
 134                  * the IOAPIC message into a MSI one, and its
 135                  * address space will decide whether we need a
 136                  * translation. */
 137                 stl_le_phys(ioapic_as, info.addr, info.data);
 138             }
 139         }
 140     }
 141 }
 142
 143 static void ioapic_set_irq(void *opaque, int vector, int level)
 144 {
 145     IOAPICCommonState *s = opaque;
 146
 147     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 148      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 149      * the cleanest way of doing it but it should work. */
 150
 151     trace_ioapic_set_irq(vector, level);
 152     if (vector == 0) {
 153         vector = 2;
 154     }
 155     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 156         uint32_t mask = 1 << vector;
 157         uint64_t entry = s->ioredtbl[vector];
 158
 159         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
 160             IOAPIC_TRIGGER_LEVEL) {
 161             /* level triggered */
 162             if (level) {
 163                 s->irr |= mask;
 164                 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
 165                     ioapic_service(s);
 166                 }
 167             } else {
 168                 s->irr &= ~mask;
 169             }
 170         } else {
 171             /* According to the 82093AA manual, we must ignore edge requests
 172              * if the input pin is masked. */
 173             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 174                 s->irr |= mask;
 175                 ioapic_service(s);
 176             }
 177         }
 178     }
 179 }
 180
 181 static void ioapic_update_kvm_routes(IOAPICCommonState *s)
 182 {
 183 #ifdef CONFIG_KVM
 184     int i;
 185
 186     if (kvm_irqchip_is_split()) {
 187         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 188             MSIMessage msg;
 189             struct ioapic_entry_info info;
 190             ioapic_entry_parse(s->ioredtbl[i], &info);
 191             msg.address = info.addr;
 192             msg.data = info.data;
 193             kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
 194         }
 195         kvm_irqchip_commit_routes(kvm_state);
 196     }
 197 #endif
 198 }
 199
 200 #ifdef CONFIG_KVM
 201 static void ioapic_iec_notifier(void *private, bool global,
 202                                 uint32_t index, uint32_t mask)
 203 {
 204     IOAPICCommonState *s = (IOAPICCommonState *)private;
 205     /* For simplicity, we just update all the routes */
 206     ioapic_update_kvm_routes(s);
 207 }
 208 #endif
 209
 210 void ioapic_eoi_broadcast(int vector)
 211 {
 212     IOAPICCommonState *s;
 213     uint64_t entry;
 214     int i, n;
 215
 216     trace_ioapic_eoi_broadcast(vector);
 217
 218     for (i = 0; i < MAX_IOAPICS; i++) {
 219         s = ioapics[i];
 220         if (!s) {
 221             continue;
 222         }
 223         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 224             entry = s->ioredtbl[n];
 225             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 226                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 227                 trace_ioapic_clear_remote_irr(n, vector);
 228                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 229                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 230                     ioapic_service(s);
 231                 }
 232             }
 233         }
 234     }
 235 }
 236
 237 void ioapic_dump_state(Monitor *mon, const QDict *qdict)
 238 {
 239     int i;
 240
 241     for (i = 0; i < MAX_IOAPICS; i++) {
 242         if (ioapics[i] != 0) {
 243             ioapic_print_redtbl(mon, ioapics[i]);
 244         }
 245     }
 246 }
 247
 248 static uint64_t
 249 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
 250 {
 251     IOAPICCommonState *s = opaque;
 252     int index;
 253     uint32_t val = 0;
 254
 255     addr &= 0xff;
 256
 257     switch (addr) {
 258     case IOAPIC_IOREGSEL:
 259         val = s->ioregsel;
 260         break;
 261     case IOAPIC_IOWIN:
 262         if (size != 4) {
 263             break;
 264         }
 265         switch (s->ioregsel) {
 266         case IOAPIC_REG_ID:
 267         case IOAPIC_REG_ARB:
 268             val = s->id << IOAPIC_ID_SHIFT;
 269             break;
 270         case IOAPIC_REG_VER:
 271             val = s->version |
 272                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 273             break;
 274         default:
 275             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 276             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 277                 if (s->ioregsel & 1) {
 278                     val = s->ioredtbl[index] >> 32;
 279                 } else {
 280                     val = s->ioredtbl[index] & 0xffffffff;
 281                 }
 282             }
 283         }
 284         break;
 285     }
 286
 287     trace_ioapic_mem_read(addr, s->ioregsel, size, val);
 288
 289     return val;
 290 }
 291
 292 /*
 293  * This is to satisfy the hack in Linux kernel. One hack of it is to
 294  * simulate clearing the Remote IRR bit of IOAPIC entry using the
 295  * following:
 296  *
 297  * "For IO-APIC's with EOI register, we use that to do an explicit EOI.
 298  * Otherwise, we simulate the EOI message manually by changing the trigger
 299  * mode to edge and then back to level, with RTE being masked during
 300  * this."
 301  *
 302  * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701)
 303  *
 304  * This is based on the assumption that, Remote IRR bit will be
 305  * cleared by IOAPIC hardware when configured as edge-triggered
 306  * interrupts.
 307  *
 308  * Without this, level-triggered interrupts in IR mode might fail to
 309  * work correctly.
 310  */
 311 static inline void
 312 ioapic_fix_edge_remote_irr(uint64_t *entry)
 313 {
 314     if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) {
 315         /* Edge-triggered interrupts, make sure remote IRR is zero */
 316         *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR);
 317     }
 318 }
 319
 320 static void
 321 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 322                  unsigned int size)
 323 {
 324     IOAPICCommonState *s = opaque;
 325     int index;
 326
 327     addr &= 0xff;
 328     trace_ioapic_mem_write(addr, s->ioregsel, size, val);
 329
 330     switch (addr) {
 331     case IOAPIC_IOREGSEL:
 332         s->ioregsel = val;
 333         break;
 334     case IOAPIC_IOWIN:
 335         if (size != 4) {
 336             break;
 337         }
 338         switch (s->ioregsel) {
 339         case IOAPIC_REG_ID:
 340             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 341             break;
 342         case IOAPIC_REG_VER:
 343         case IOAPIC_REG_ARB:
 344             break;
 345         default:
 346             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 347             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 348                 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
 349                 if (s->ioregsel & 1) {
 350                     s->ioredtbl[index] &= 0xffffffff;
 351                     s->ioredtbl[index] |= (uint64_t)val << 32;
 352                 } else {
 353                     s->ioredtbl[index] &= ~0xffffffffULL;
 354                     s->ioredtbl[index] |= val;
 355                 }
 356                 /* restore RO bits */
 357                 s->ioredtbl[index] &= IOAPIC_RW_BITS;
 358                 s->ioredtbl[index] |= ro_bits;
 359                 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]);
 360                 ioapic_service(s);
 361             }
 362         }
 363         break;
 364     case IOAPIC_EOI:
 365         /* Explicit EOI is only supported for IOAPIC version 0x20 */
 366         if (size != 4 || s->version != 0x20) {
 367             break;
 368         }
 369         ioapic_eoi_broadcast(val);
 370         break;
 371     }
 372
 373     ioapic_update_kvm_routes(s);
 374 }
 375
 376 static const MemoryRegionOps ioapic_io_ops = {
 377     .read = ioapic_mem_read,
 378     .write = ioapic_mem_write,
 379     .endianness = DEVICE_NATIVE_ENDIAN,
 380 };
 381
 382 static void ioapic_machine_done_notify(Notifier *notifier, void *data)
 383 {
 384 #ifdef CONFIG_KVM
 385     IOAPICCommonState *s = container_of(notifier, IOAPICCommonState,
 386                                         machine_done);
 387
 388     if (kvm_irqchip_is_split()) {
 389         X86IOMMUState *iommu = x86_iommu_get_default();
 390         if (iommu) {
 391             /* Register this IOAPIC with IOMMU IEC notifier, so that
 392              * when there are IR invalidates, we can be notified to
 393              * update kernel IR cache. */
 394             x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s);
 395         }
 396     }
 397 #endif
 398 }
 399
 400 #define IOAPIC_VER_DEF 0x20
 401
 402 static void ioapic_realize(DeviceState *dev, Error **errp)
 403 {
 404     IOAPICCommonState *s = IOAPIC_COMMON(dev);
 405
 406     if (s->version != 0x11 && s->version != 0x20) {
 407         error_report("IOAPIC only supports version 0x11 or 0x20 "
 408                      "(default: 0x%x).", IOAPIC_VER_DEF);
 409         exit(1);
 410     }
 411
 412     memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
 413                           "ioapic", 0x1000);
 414
 415     qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
 416
 417     ioapics[ioapic_no] = s;
 418     s->machine_done.notify = ioapic_machine_done_notify;
 419     qemu_add_machine_init_done_notifier(&s->machine_done);
 420 }
 421
 422 static Property ioapic_properties[] = {
 423     DEFINE_PROP_UINT8("version", IOAPICCommonState, version, IOAPIC_VER_DEF),
 424     DEFINE_PROP_END_OF_LIST(),
 425 };
 426
 427 static void ioapic_class_init(ObjectClass *klass, void *data)
 428 {
 429     IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
 430     DeviceClass *dc = DEVICE_CLASS(klass);
 431
 432     k->realize = ioapic_realize;
 433     /*
 434      * If APIC is in kernel, we need to update the kernel cache after
 435      * migration, otherwise first 24 gsi routes will be invalid.
 436      */
 437     k->post_load = ioapic_update_kvm_routes;
 438     dc->reset = ioapic_reset_common;
 439     dc->props = ioapic_properties;
 440 }
 441
 442 static const TypeInfo ioapic_info = {
 443     .name          = "ioapic",
 444     .parent        = TYPE_IOAPIC_COMMON,
 445     .instance_size = sizeof(IOAPICCommonState),
 446     .class_init    = ioapic_class_init,
 447 };
 448
 449 static void ioapic_register_types(void)
 450 {
 451     type_register_static(&ioapic_info);
 452 }
 453
 454 type_init(ioapic_register_types)