tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "tcg-mo.h"
  33 #include "tcg-target.h"
  34
  35 /* XXX: make safe guess about sizes */
  36 #define MAX_OP_PER_INSTR 266
  37
  38 #if HOST_LONG_BITS == 32
  39 #define MAX_OPC_PARAM_PER_ARG 2
  40 #else
  41 #define MAX_OPC_PARAM_PER_ARG 1
  42 #endif
  43 #define MAX_OPC_PARAM_IARGS 5
  44 #define MAX_OPC_PARAM_OARGS 1
  45 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  46
  47 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  48  * and up to 4 + N parameters on 64-bit archs
  49  * (N = number of input arguments + output arguments).  */
  50 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  51 #define OPC_BUF_SIZE 640
  52 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  53
  54 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  55
  56 #define CPU_TEMP_BUF_NLONGS 128
  57
  58 /* Default target word size to pointer size.  */
  59 #ifndef TCG_TARGET_REG_BITS
  60 # if UINTPTR_MAX == UINT32_MAX
  61 #  define TCG_TARGET_REG_BITS 32
  62 # elif UINTPTR_MAX == UINT64_MAX
  63 #  define TCG_TARGET_REG_BITS 64
  64 # else
  65 #  error Unknown pointer size for tcg target
  66 # endif
  67 #endif
  68
  69 #if TCG_TARGET_REG_BITS == 32
  70 typedef int32_t tcg_target_long;
  71 typedef uint32_t tcg_target_ulong;
  72 #define TCG_PRIlx PRIx32
  73 #define TCG_PRIld PRId32
  74 #elif TCG_TARGET_REG_BITS == 64
  75 typedef int64_t tcg_target_long;
  76 typedef uint64_t tcg_target_ulong;
  77 #define TCG_PRIlx PRIx64
  78 #define TCG_PRIld PRId64
  79 #else
  80 #error unsupported
  81 #endif
  82
  83 /* Oversized TCG guests make things like MTTCG hard
  84  * as we can't use atomics for cputlb updates.
  85  */
  86 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  87 #define TCG_OVERSIZED_GUEST 1
  88 #else
  89 #define TCG_OVERSIZED_GUEST 0
  90 #endif
  91
  92 #if TCG_TARGET_NB_REGS <= 32
  93 typedef uint32_t TCGRegSet;
  94 #elif TCG_TARGET_NB_REGS <= 64
  95 typedef uint64_t TCGRegSet;
  96 #else
  97 #error unsupported
  98 #endif
  99
 100 #if TCG_TARGET_REG_BITS == 32
 101 /* Turn some undef macros into false macros.  */
 102 #define TCG_TARGET_HAS_extrl_i64_i32    0
 103 #define TCG_TARGET_HAS_extrh_i64_i32    0
 104 #define TCG_TARGET_HAS_div_i64          0
 105 #define TCG_TARGET_HAS_rem_i64          0
 106 #define TCG_TARGET_HAS_div2_i64         0
 107 #define TCG_TARGET_HAS_rot_i64          0
 108 #define TCG_TARGET_HAS_ext8s_i64        0
 109 #define TCG_TARGET_HAS_ext16s_i64       0
 110 #define TCG_TARGET_HAS_ext32s_i64       0
 111 #define TCG_TARGET_HAS_ext8u_i64        0
 112 #define TCG_TARGET_HAS_ext16u_i64       0
 113 #define TCG_TARGET_HAS_ext32u_i64       0
 114 #define TCG_TARGET_HAS_bswap16_i64      0
 115 #define TCG_TARGET_HAS_bswap32_i64      0
 116 #define TCG_TARGET_HAS_bswap64_i64      0
 117 #define TCG_TARGET_HAS_neg_i64          0
 118 #define TCG_TARGET_HAS_not_i64          0
 119 #define TCG_TARGET_HAS_andc_i64         0
 120 #define TCG_TARGET_HAS_orc_i64          0
 121 #define TCG_TARGET_HAS_eqv_i64          0
 122 #define TCG_TARGET_HAS_nand_i64         0
 123 #define TCG_TARGET_HAS_nor_i64          0
 124 #define TCG_TARGET_HAS_clz_i64          0
 125 #define TCG_TARGET_HAS_ctz_i64          0
 126 #define TCG_TARGET_HAS_ctpop_i64        0
 127 #define TCG_TARGET_HAS_deposit_i64      0
 128 #define TCG_TARGET_HAS_extract_i64      0
 129 #define TCG_TARGET_HAS_sextract_i64     0
 130 #define TCG_TARGET_HAS_movcond_i64      0
 131 #define TCG_TARGET_HAS_add2_i64         0
 132 #define TCG_TARGET_HAS_sub2_i64         0
 133 #define TCG_TARGET_HAS_mulu2_i64        0
 134 #define TCG_TARGET_HAS_muls2_i64        0
 135 #define TCG_TARGET_HAS_muluh_i64        0
 136 #define TCG_TARGET_HAS_mulsh_i64        0
 137 /* Turn some undef macros into true macros.  */
 138 #define TCG_TARGET_HAS_add2_i32         1
 139 #define TCG_TARGET_HAS_sub2_i32         1
 140 #endif
 141
 142 #ifndef TCG_TARGET_deposit_i32_valid
 143 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 144 #endif
 145 #ifndef TCG_TARGET_deposit_i64_valid
 146 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 147 #endif
 148 #ifndef TCG_TARGET_extract_i32_valid
 149 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
 150 #endif
 151 #ifndef TCG_TARGET_extract_i64_valid
 152 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
 153 #endif
 154
 155 /* Only one of DIV or DIV2 should be defined.  */
 156 #if defined(TCG_TARGET_HAS_div_i32)
 157 #define TCG_TARGET_HAS_div2_i32         0
 158 #elif defined(TCG_TARGET_HAS_div2_i32)
 159 #define TCG_TARGET_HAS_div_i32          0
 160 #define TCG_TARGET_HAS_rem_i32          0
 161 #endif
 162 #if defined(TCG_TARGET_HAS_div_i64)
 163 #define TCG_TARGET_HAS_div2_i64         0
 164 #elif defined(TCG_TARGET_HAS_div2_i64)
 165 #define TCG_TARGET_HAS_div_i64          0
 166 #define TCG_TARGET_HAS_rem_i64          0
 167 #endif
 168
 169 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 170 #if TCG_TARGET_REG_BITS == 32 \
 171     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 172          || defined(TCG_TARGET_HAS_muluh_i32))
 173 # error "Missing unsigned widening multiply"
 174 #endif
 175
 176 #ifndef TARGET_INSN_START_EXTRA_WORDS
 177 # define TARGET_INSN_START_WORDS 1
 178 #else
 179 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 180 #endif
 181
 182 typedef enum TCGOpcode {
 183 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 184 #include "tcg-opc.h"
 185 #undef DEF
 186     NB_OPS,
 187 } TCGOpcode;
 188
 189 #define tcg_regset_set_reg(d, r)   ((d) |= (TCGRegSet)1 << (r))
 190 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
 191 #define tcg_regset_test_reg(d, r)  (((d) >> (r)) & 1)
 192
 193 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 194 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 195 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 196 typedef uint8_t tcg_insn_unit;
 197 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 198 typedef uint16_t tcg_insn_unit;
 199 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 200 typedef uint32_t tcg_insn_unit;
 201 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 202 typedef uint64_t tcg_insn_unit;
 203 #else
 204 /* The port better have done this.  */
 205 #endif
 206
 207
 208 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 209 # define tcg_debug_assert(X) do { assert(X); } while (0)
 210 #elif QEMU_GNUC_PREREQ(4, 5)
 211 # define tcg_debug_assert(X) \
 212     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 213 #else
 214 # define tcg_debug_assert(X) do { (void)(X); } while (0)
 215 #endif
 216
 217 typedef struct TCGRelocation {
 218     struct TCGRelocation *next;
 219     int type;
 220     tcg_insn_unit *ptr;
 221     intptr_t addend;
 222 } TCGRelocation;
 223
 224 typedef struct TCGLabel {
 225     unsigned has_value : 1;
 226     unsigned id : 31;
 227     union {
 228         uintptr_t value;
 229         tcg_insn_unit *value_ptr;
 230         TCGRelocation *first_reloc;
 231     } u;
 232 } TCGLabel;
 233
 234 typedef struct TCGPool {
 235     struct TCGPool *next;
 236     int size;
 237     uint8_t data[0] __attribute__ ((aligned));
 238 } TCGPool;
 239
 240 #define TCG_POOL_CHUNK_SIZE 32768
 241
 242 #define TCG_MAX_TEMPS 512
 243 #define TCG_MAX_INSNS 512
 244
 245 /* when the size of the arguments of a called function is smaller than
 246    this value, they are statically allocated in the TB stack frame */
 247 #define TCG_STATIC_CALL_ARGS_SIZE 128
 248
 249 typedef enum TCGType {
 250     TCG_TYPE_I32,
 251     TCG_TYPE_I64,
 252     TCG_TYPE_COUNT, /* number of different types */
 253
 254     /* An alias for the size of the host register.  */
 255 #if TCG_TARGET_REG_BITS == 32
 256     TCG_TYPE_REG = TCG_TYPE_I32,
 257 #else
 258     TCG_TYPE_REG = TCG_TYPE_I64,
 259 #endif
 260
 261     /* An alias for the size of the native pointer.  */
 262 #if UINTPTR_MAX == UINT32_MAX
 263     TCG_TYPE_PTR = TCG_TYPE_I32,
 264 #else
 265     TCG_TYPE_PTR = TCG_TYPE_I64,
 266 #endif
 267
 268     /* An alias for the size of the target "long", aka register.  */
 269 #if TARGET_LONG_BITS == 64
 270     TCG_TYPE_TL = TCG_TYPE_I64,
 271 #else
 272     TCG_TYPE_TL = TCG_TYPE_I32,
 273 #endif
 274 } TCGType;
 275
 276 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 277 typedef enum TCGMemOp {
 278     MO_8     = 0,
 279     MO_16    = 1,
 280     MO_32    = 2,
 281     MO_64    = 3,
 282     MO_SIZE  = 3,   /* Mask for the above.  */
 283
 284     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 285
 286     MO_BSWAP = 8,   /* Host reverse endian.  */
 287 #ifdef HOST_WORDS_BIGENDIAN
 288     MO_LE    = MO_BSWAP,
 289     MO_BE    = 0,
 290 #else
 291     MO_LE    = 0,
 292     MO_BE    = MO_BSWAP,
 293 #endif
 294 #ifdef TARGET_WORDS_BIGENDIAN
 295     MO_TE    = MO_BE,
 296 #else
 297     MO_TE    = MO_LE,
 298 #endif
 299
 300     /* MO_UNALN accesses are never checked for alignment.
 301      * MO_ALIGN accesses will result in a call to the CPU's
 302      * do_unaligned_access hook if the guest address is not aligned.
 303      * The default depends on whether the target CPU defines ALIGNED_ONLY.
 304      *
 305      * Some architectures (e.g. ARMv8) need the address which is aligned
 306      * to a size more than the size of the memory access.
 307      * Some architectures (e.g. SPARCv9) need an address which is aligned,
 308      * but less strictly than the natural alignment.
 309      *
 310      * MO_ALIGN supposes the alignment size is the size of a memory access.
 311      *
 312      * There are three options:
 313      * - unaligned access permitted (MO_UNALN).
 314      * - an alignment to the size of an access (MO_ALIGN);
 315      * - an alignment to a specified size, which may be more or less than
 316      *   the access size (MO_ALIGN_x where 'x' is a size in bytes);
 317      */
 318     MO_ASHIFT = 4,
 319     MO_AMASK = 7 << MO_ASHIFT,
 320 #ifdef ALIGNED_ONLY
 321     MO_ALIGN = 0,
 322     MO_UNALN = MO_AMASK,
 323 #else
 324     MO_ALIGN = MO_AMASK,
 325     MO_UNALN = 0,
 326 #endif
 327     MO_ALIGN_2  = 1 << MO_ASHIFT,
 328     MO_ALIGN_4  = 2 << MO_ASHIFT,
 329     MO_ALIGN_8  = 3 << MO_ASHIFT,
 330     MO_ALIGN_16 = 4 << MO_ASHIFT,
 331     MO_ALIGN_32 = 5 << MO_ASHIFT,
 332     MO_ALIGN_64 = 6 << MO_ASHIFT,
 333
 334     /* Combinations of the above, for ease of use.  */
 335     MO_UB    = MO_8,
 336     MO_UW    = MO_16,
 337     MO_UL    = MO_32,
 338     MO_SB    = MO_SIGN | MO_8,
 339     MO_SW    = MO_SIGN | MO_16,
 340     MO_SL    = MO_SIGN | MO_32,
 341     MO_Q     = MO_64,
 342
 343     MO_LEUW  = MO_LE | MO_UW,
 344     MO_LEUL  = MO_LE | MO_UL,
 345     MO_LESW  = MO_LE | MO_SW,
 346     MO_LESL  = MO_LE | MO_SL,
 347     MO_LEQ   = MO_LE | MO_Q,
 348
 349     MO_BEUW  = MO_BE | MO_UW,
 350     MO_BEUL  = MO_BE | MO_UL,
 351     MO_BESW  = MO_BE | MO_SW,
 352     MO_BESL  = MO_BE | MO_SL,
 353     MO_BEQ   = MO_BE | MO_Q,
 354
 355     MO_TEUW  = MO_TE | MO_UW,
 356     MO_TEUL  = MO_TE | MO_UL,
 357     MO_TESW  = MO_TE | MO_SW,
 358     MO_TESL  = MO_TE | MO_SL,
 359     MO_TEQ   = MO_TE | MO_Q,
 360
 361     MO_SSIZE = MO_SIZE | MO_SIGN,
 362 } TCGMemOp;
 363
 364 /**
 365  * get_alignment_bits
 366  * @memop: TCGMemOp value
 367  *
 368  * Extract the alignment size from the memop.
 369  */
 370 static inline unsigned get_alignment_bits(TCGMemOp memop)
 371 {
 372     unsigned a = memop & MO_AMASK;
 373
 374     if (a == MO_UNALN) {
 375         /* No alignment required.  */
 376         a = 0;
 377     } else if (a == MO_ALIGN) {
 378         /* A natural alignment requirement.  */
 379         a = memop & MO_SIZE;
 380     } else {
 381         /* A specific alignment requirement.  */
 382         a = a >> MO_ASHIFT;
 383     }
 384 #if defined(CONFIG_SOFTMMU)
 385     /* The requested alignment cannot overlap the TLB flags.  */
 386     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 387 #endif
 388     return a;
 389 }
 390
 391 typedef tcg_target_ulong TCGArg;
 392
 393 /* Define type and accessor macros for TCG variables.
 394
 395    TCG variables are the inputs and outputs of TCG ops, as described
 396    in tcg/README. Target CPU front-end code uses these types to deal
 397    with TCG variables as it emits TCG code via the tcg_gen_* functions.
 398    They come in several flavours:
 399     * TCGv_i32 : 32 bit integer type
 400     * TCGv_i64 : 64 bit integer type
 401     * TCGv_ptr : a host pointer type
 402     * TCGv : an integer type the same size as target_ulong
 403              (an alias for either TCGv_i32 or TCGv_i64)
 404    The compiler's type checking will complain if you mix them
 405    up and pass the wrong sized TCGv to a function.
 406
 407    Users of tcg_gen_* don't need to know about any of the internal
 408    details of these, and should treat them as opaque types.
 409    You won't be able to look inside them in a debugger either.
 410
 411    Internal implementation details follow:
 412
 413    Note that there is no definition of the structs TCGv_i32_d etc anywhere.
 414    This is deliberate, because the values we store in variables of type
 415    TCGv_i32 are not really pointers-to-structures. They're just small
 416    integers, but keeping them in pointer types like this means that the
 417    compiler will complain if you accidentally pass a TCGv_i32 to a
 418    function which takes a TCGv_i64, and so on. Only the internals of
 419    TCG need to care about the actual contents of the types, and they always
 420    box and unbox via the MAKE_TCGV_* and GET_TCGV_* functions.
 421    Converting to and from intptr_t rather than int reduces the number
 422    of sign-extension instructions that get implied on 64-bit hosts.  */
 423
 424 typedef struct TCGv_i32_d *TCGv_i32;
 425 typedef struct TCGv_i64_d *TCGv_i64;
 426 typedef struct TCGv_ptr_d *TCGv_ptr;
 427 typedef TCGv_ptr TCGv_env;
 428 #if TARGET_LONG_BITS == 32
 429 #define TCGv TCGv_i32
 430 #elif TARGET_LONG_BITS == 64
 431 #define TCGv TCGv_i64
 432 #else
 433 #error Unhandled TARGET_LONG_BITS value
 434 #endif
 435
 436 static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i)
 437 {
 438     return (TCGv_i32)i;
 439 }
 440
 441 static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i)
 442 {
 443     return (TCGv_i64)i;
 444 }
 445
 446 static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i)
 447 {
 448     return (TCGv_ptr)i;
 449 }
 450
 451 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t)
 452 {
 453     return (intptr_t)t;
 454 }
 455
 456 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t)
 457 {
 458     return (intptr_t)t;
 459 }
 460
 461 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
 462 {
 463     return (intptr_t)t;
 464 }
 465
 466 #if TCG_TARGET_REG_BITS == 32
 467 #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
 468 #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
 469 #endif
 470
 471 #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
 472 #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
 473 #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
 474
 475 /* Dummy definition to avoid compiler warnings.  */
 476 #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
 477 #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
 478 #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
 479
 480 #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
 481 #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
 482 #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
 483
 484 /* call flags */
 485 /* Helper does not read globals (either directly or through an exception). It
 486    implies TCG_CALL_NO_WRITE_GLOBALS. */
 487 #define TCG_CALL_NO_READ_GLOBALS    0x0010
 488 /* Helper does not write globals */
 489 #define TCG_CALL_NO_WRITE_GLOBALS   0x0020
 490 /* Helper can be safely suppressed if the return value is not used. */
 491 #define TCG_CALL_NO_SIDE_EFFECTS    0x0040
 492
 493 /* convenience version of most used call flags */
 494 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 495 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 496 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 497 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 498 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 499
 500 /* used to align parameters */
 501 #define TCG_CALL_DUMMY_TCGV     MAKE_TCGV_I32(-1)
 502 #define TCG_CALL_DUMMY_ARG      ((TCGArg)(-1))
 503
 504 /* Conditions.  Note that these are laid out for easy manipulation by
 505    the functions below:
 506      bit 0 is used for inverting;
 507      bit 1 is signed,
 508      bit 2 is unsigned,
 509      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 510 typedef enum {
 511     /* non-signed */
 512     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 513     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 514     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 515     TCG_COND_NE     = 8 | 0 | 0 | 1,
 516     /* signed */
 517     TCG_COND_LT     = 0 | 0 | 2 | 0,
 518     TCG_COND_GE     = 0 | 0 | 2 | 1,
 519     TCG_COND_LE     = 8 | 0 | 2 | 0,
 520     TCG_COND_GT     = 8 | 0 | 2 | 1,
 521     /* unsigned */
 522     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 523     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 524     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 525     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 526 } TCGCond;
 527
 528 /* Invert the sense of the comparison.  */
 529 static inline TCGCond tcg_invert_cond(TCGCond c)
 530 {
 531     return (TCGCond)(c ^ 1);
 532 }
 533
 534 /* Swap the operands in a comparison.  */
 535 static inline TCGCond tcg_swap_cond(TCGCond c)
 536 {
 537     return c & 6 ? (TCGCond)(c ^ 9) : c;
 538 }
 539
 540 /* Create an "unsigned" version of a "signed" comparison.  */
 541 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 542 {
 543     return c & 2 ? (TCGCond)(c ^ 6) : c;
 544 }
 545
 546 /* Must a comparison be considered unsigned?  */
 547 static inline bool is_unsigned_cond(TCGCond c)
 548 {
 549     return (c & 4) != 0;
 550 }
 551
 552 /* Create a "high" version of a double-word comparison.
 553    This removes equality from a LTE or GTE comparison.  */
 554 static inline TCGCond tcg_high_cond(TCGCond c)
 555 {
 556     switch (c) {
 557     case TCG_COND_GE:
 558     case TCG_COND_LE:
 559     case TCG_COND_GEU:
 560     case TCG_COND_LEU:
 561         return (TCGCond)(c ^ 8);
 562     default:
 563         return c;
 564     }
 565 }
 566
 567 typedef enum TCGTempVal {
 568     TEMP_VAL_DEAD,
 569     TEMP_VAL_REG,
 570     TEMP_VAL_MEM,
 571     TEMP_VAL_CONST,
 572 } TCGTempVal;
 573
 574 typedef struct TCGTemp {
 575     TCGReg reg:8;
 576     TCGTempVal val_type:8;
 577     TCGType base_type:8;
 578     TCGType type:8;
 579     unsigned int fixed_reg:1;
 580     unsigned int indirect_reg:1;
 581     unsigned int indirect_base:1;
 582     unsigned int mem_coherent:1;
 583     unsigned int mem_allocated:1;
 584     unsigned int temp_local:1; /* If true, the temp is saved across
 585                                   basic blocks. Otherwise, it is not
 586                                   preserved across basic blocks. */
 587     unsigned int temp_allocated:1; /* never used for code gen */
 588
 589     tcg_target_long val;
 590     struct TCGTemp *mem_base;
 591     intptr_t mem_offset;
 592     const char *name;
 593 } TCGTemp;
 594
 595 typedef struct TCGContext TCGContext;
 596
 597 typedef struct TCGTempSet {
 598     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 599 } TCGTempSet;
 600
 601 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 602    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 603    There are never more than 2 outputs, which means that we can store all
 604    dead + sync data within 16 bits.  */
 605 #define DEAD_ARG  4
 606 #define SYNC_ARG  1
 607 typedef uint16_t TCGLifeData;
 608
 609 /* The layout here is designed to avoid crossing of a 32-bit boundary.
 610    If we do so, gcc adds padding, expanding the size to 12.  */
 611 typedef struct TCGOp {
 612     TCGOpcode opc   : 8;        /*  8 */
 613
 614     /* Index of the prev/next op, or 0 for the end of the list.  */
 615     unsigned prev   : 10;       /* 18 */
 616     unsigned next   : 10;       /* 28 */
 617
 618     /* The number of out and in parameter for a call.  */
 619     unsigned calli  : 4;        /* 32 */
 620     unsigned callo  : 2;        /* 34 */
 621
 622     /* Index of the arguments for this op, or 0 for zero-operand ops.  */
 623     unsigned args   : 14;       /* 48 */
 624
 625     /* Lifetime data of the operands.  */
 626     unsigned life   : 16;       /* 64 */
 627 } TCGOp;
 628
 629 /* Make sure operands fit in the bitfields above.  */
 630 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 631 QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 10));
 632 QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14));
 633
 634 /* Make sure that we don't overflow 64 bits without noticing.  */
 635 QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8);
 636
 637 struct TCGContext {
 638     uint8_t *pool_cur, *pool_end;
 639     TCGPool *pool_first, *pool_current, *pool_first_large;
 640     int nb_labels;
 641     int nb_globals;
 642     int nb_temps;
 643     int nb_indirects;
 644
 645     /* goto_tb support */
 646     tcg_insn_unit *code_buf;
 647     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 648     uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
 649     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 650
 651     TCGRegSet reserved_regs;
 652     intptr_t current_frame_offset;
 653     intptr_t frame_start;
 654     intptr_t frame_end;
 655     TCGTemp *frame_temp;
 656
 657     tcg_insn_unit *code_ptr;
 658
 659     GHashTable *helpers;
 660
 661 #ifdef CONFIG_PROFILER
 662     /* profiling info */
 663     int64_t tb_count1;
 664     int64_t tb_count;
 665     int64_t op_count; /* total insn count */
 666     int op_count_max; /* max insn per TB */
 667     int64_t temp_count;
 668     int temp_count_max;
 669     int64_t del_op_count;
 670     int64_t code_in_len;
 671     int64_t code_out_len;
 672     int64_t search_out_len;
 673     int64_t interm_time;
 674     int64_t code_time;
 675     int64_t la_time;
 676     int64_t opt_time;
 677     int64_t restore_count;
 678     int64_t restore_time;
 679 #endif
 680
 681 #ifdef CONFIG_DEBUG_TCG
 682     int temps_in_use;
 683     int goto_tb_issue_mask;
 684 #endif
 685
 686     int gen_next_op_idx;
 687     int gen_next_parm_idx;
 688
 689     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 690        here, because there's too much arithmetic throughout that relies
 691        on addition and subtraction working on bytes.  Rely on the GCC
 692        extension that allows arithmetic on void*.  */
 693     void *code_gen_prologue;
 694     void *code_gen_epilogue;
 695     void *code_gen_buffer;
 696     size_t code_gen_buffer_size;
 697     void *code_gen_ptr;
 698     void *data_gen_ptr;
 699
 700     /* Threshold to flush the translated code buffer.  */
 701     void *code_gen_highwater;
 702
 703     TBContext tb_ctx;
 704
 705     /* Track which vCPU triggers events */
 706     CPUState *cpu;                      /* *_trans */
 707     TCGv_env tcg_env;                   /* *_exec  */
 708
 709     /* These structures are private to tcg-target.inc.c.  */
 710 #ifdef TCG_TARGET_NEED_LDST_LABELS
 711     struct TCGLabelQemuLdst *ldst_labels;
 712 #endif
 713 #ifdef TCG_TARGET_NEED_POOL_LABELS
 714     struct TCGLabelPoolData *pool_labels;
 715 #endif
 716
 717     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 718     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 719
 720     /* Tells which temporary holds a given register.
 721        It does not take into account fixed registers */
 722     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 723
 724     TCGOp gen_op_buf[OPC_BUF_SIZE];
 725     TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
 726
 727     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 728     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 729 };
 730
 731 extern TCGContext tcg_ctx;
 732 extern bool parallel_cpus;
 733
 734 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
 735 {
 736     int op_argi = tcg_ctx.gen_op_buf[op_idx].args;
 737     tcg_ctx.gen_opparam_buf[op_argi + arg] = v;
 738 }
 739
 740 /* The number of opcodes emitted so far.  */
 741 static inline int tcg_op_buf_count(void)
 742 {
 743     return tcg_ctx.gen_next_op_idx;
 744 }
 745
 746 /* Test for whether to terminate the TB for using too many opcodes.  */
 747 static inline bool tcg_op_buf_full(void)
 748 {
 749     return tcg_op_buf_count() >= OPC_MAX_SIZE;
 750 }
 751
 752 /* pool based memory allocation */
 753
 754 /* tb_lock must be held for tcg_malloc_internal. */
 755 void *tcg_malloc_internal(TCGContext *s, int size);
 756 void tcg_pool_reset(TCGContext *s);
 757 TranslationBlock *tcg_tb_alloc(TCGContext *s);
 758
 759 /* Called with tb_lock held.  */
 760 static inline void *tcg_malloc(int size)
 761 {
 762     TCGContext *s = &tcg_ctx;
 763     uint8_t *ptr, *ptr_end;
 764
 765     /* ??? This is a weak placeholder for minimum malloc alignment.  */
 766     size = QEMU_ALIGN_UP(size, 8);
 767
 768     ptr = s->pool_cur;
 769     ptr_end = ptr + size;
 770     if (unlikely(ptr_end > s->pool_end)) {
 771         return tcg_malloc_internal(&tcg_ctx, size);
 772     } else {
 773         s->pool_cur = ptr_end;
 774         return ptr;
 775     }
 776 }
 777
 778 void tcg_context_init(TCGContext *s);
 779 void tcg_prologue_init(TCGContext *s);
 780 void tcg_func_start(TCGContext *s);
 781
 782 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 783
 784 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 785
 786 int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *);
 787
 788 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name);
 789 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name);
 790
 791 TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
 792 TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
 793
 794 void tcg_temp_free_i32(TCGv_i32 arg);
 795 void tcg_temp_free_i64(TCGv_i64 arg);
 796
 797 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 798                                               const char *name)
 799 {
 800     int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 801     return MAKE_TCGV_I32(idx);
 802 }
 803
 804 static inline TCGv_i32 tcg_temp_new_i32(void)
 805 {
 806     return tcg_temp_new_internal_i32(0);
 807 }
 808
 809 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 810 {
 811     return tcg_temp_new_internal_i32(1);
 812 }
 813
 814 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 815                                               const char *name)
 816 {
 817     int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 818     return MAKE_TCGV_I64(idx);
 819 }
 820
 821 static inline TCGv_i64 tcg_temp_new_i64(void)
 822 {
 823     return tcg_temp_new_internal_i64(0);
 824 }
 825
 826 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 827 {
 828     return tcg_temp_new_internal_i64(1);
 829 }
 830
 831 #if defined(CONFIG_DEBUG_TCG)
 832 /* If you call tcg_clear_temp_count() at the start of a section of
 833  * code which is not supposed to leak any TCG temporaries, then
 834  * calling tcg_check_temp_count() at the end of the section will
 835  * return 1 if the section did in fact leak a temporary.
 836  */
 837 void tcg_clear_temp_count(void);
 838 int tcg_check_temp_count(void);
 839 #else
 840 #define tcg_clear_temp_count() do { } while (0)
 841 #define tcg_check_temp_count() 0
 842 #endif
 843
 844 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
 845 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
 846
 847 #define TCG_CT_ALIAS  0x80
 848 #define TCG_CT_IALIAS 0x40
 849 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
 850 #define TCG_CT_REG    0x01
 851 #define TCG_CT_CONST  0x02 /* any constant of register size */
 852
 853 typedef struct TCGArgConstraint {
 854     uint16_t ct;
 855     uint8_t alias_index;
 856     union {
 857         TCGRegSet regs;
 858     } u;
 859 } TCGArgConstraint;
 860
 861 #define TCG_MAX_OP_ARGS 16
 862
 863 /* Bits for TCGOpDef->flags, 8 bits available.  */
 864 enum {
 865     /* Instruction defines the end of a basic block.  */
 866     TCG_OPF_BB_END       = 0x01,
 867     /* Instruction clobbers call registers and potentially update globals.  */
 868     TCG_OPF_CALL_CLOBBER = 0x02,
 869     /* Instruction has side effects: it cannot be removed if its outputs
 870        are not used, and might trigger exceptions.  */
 871     TCG_OPF_SIDE_EFFECTS = 0x04,
 872     /* Instruction operands are 64-bits (otherwise 32-bits).  */
 873     TCG_OPF_64BIT        = 0x08,
 874     /* Instruction is optional and not implemented by the host, or insn
 875        is generic and should not be implemened by the host.  */
 876     TCG_OPF_NOT_PRESENT  = 0x10,
 877 };
 878
 879 typedef struct TCGOpDef {
 880     const char *name;
 881     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
 882     uint8_t flags;
 883     TCGArgConstraint *args_ct;
 884     int *sorted_args;
 885 #if defined(CONFIG_DEBUG_TCG)
 886     int used;
 887 #endif
 888 } TCGOpDef;
 889
 890 extern TCGOpDef tcg_op_defs[];
 891 extern const size_t tcg_op_defs_max;
 892
 893 typedef struct TCGTargetOpDef {
 894     TCGOpcode op;
 895     const char *args_ct_str[TCG_MAX_OP_ARGS];
 896 } TCGTargetOpDef;
 897
 898 #define tcg_abort() \
 899 do {\
 900     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
 901     abort();\
 902 } while (0)
 903
 904 #if UINTPTR_MAX == UINT32_MAX
 905 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
 906 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
 907
 908 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
 909 #define tcg_global_reg_new_ptr(R, N) \
 910     TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
 911 #define tcg_global_mem_new_ptr(R, O, N) \
 912     TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
 913 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
 914 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
 915 #else
 916 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
 917 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
 918
 919 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
 920 #define tcg_global_reg_new_ptr(R, N) \
 921     TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
 922 #define tcg_global_mem_new_ptr(R, O, N) \
 923     TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
 924 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
 925 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
 926 #endif
 927
 928 bool tcg_op_supported(TCGOpcode op);
 929
 930 void tcg_gen_callN(TCGContext *s, void *func,
 931                    TCGArg ret, int nargs, TCGArg *args);
 932
 933 void tcg_op_remove(TCGContext *s, TCGOp *op);
 934 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
 935 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
 936
 937 void tcg_optimize(TCGContext *s);
 938
 939 /* only used for debugging purposes */
 940 void tcg_dump_ops(TCGContext *s);
 941
 942 TCGv_i32 tcg_const_i32(int32_t val);
 943 TCGv_i64 tcg_const_i64(int64_t val);
 944 TCGv_i32 tcg_const_local_i32(int32_t val);
 945 TCGv_i64 tcg_const_local_i64(int64_t val);
 946
 947 TCGLabel *gen_new_label(void);
 948
 949 /**
 950  * label_arg
 951  * @l: label
 952  *
 953  * Encode a label for storage in the TCG opcode stream.
 954  */
 955
 956 static inline TCGArg label_arg(TCGLabel *l)
 957 {
 958     return (uintptr_t)l;
 959 }
 960
 961 /**
 962  * arg_label
 963  * @i: value
 964  *
 965  * The opposite of label_arg.  Retrieve a label from the
 966  * encoding of the TCG opcode stream.
 967  */
 968
 969 static inline TCGLabel *arg_label(TCGArg i)
 970 {
 971     return (TCGLabel *)(uintptr_t)i;
 972 }
 973
 974 /**
 975  * tcg_ptr_byte_diff
 976  * @a, @b: addresses to be differenced
 977  *
 978  * There are many places within the TCG backends where we need a byte
 979  * difference between two pointers.  While this can be accomplished
 980  * with local casting, it's easy to get wrong -- especially if one is
 981  * concerned with the signedness of the result.
 982  *
 983  * This version relies on GCC's void pointer arithmetic to get the
 984  * correct result.
 985  */
 986
 987 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
 988 {
 989     return a - b;
 990 }
 991
 992 /**
 993  * tcg_pcrel_diff
 994  * @s: the tcg context
 995  * @target: address of the target
 996  *
 997  * Produce a pc-relative difference, from the current code_ptr
 998  * to the destination address.
 999  */
1000
1001 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1002 {
1003     return tcg_ptr_byte_diff(target, s->code_ptr);
1004 }
1005
1006 /**
1007  * tcg_current_code_size
1008  * @s: the tcg context
1009  *
1010  * Compute the current code size within the translation block.
1011  * This is used to fill in qemu's data structures for goto_tb.
1012  */
1013
1014 static inline size_t tcg_current_code_size(TCGContext *s)
1015 {
1016     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1017 }
1018
1019 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
1020 typedef uint32_t TCGMemOpIdx;
1021
1022 /**
1023  * make_memop_idx
1024  * @op: memory operation
1025  * @idx: mmu index
1026  *
1027  * Encode these values into a single parameter.
1028  */
1029 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1030 {
1031     tcg_debug_assert(idx <= 15);
1032     return (op << 4) | idx;
1033 }
1034
1035 /**
1036  * get_memop
1037  * @oi: combined op/idx parameter
1038  *
1039  * Extract the memory operation from the combined value.
1040  */
1041 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1042 {
1043     return oi >> 4;
1044 }
1045
1046 /**
1047  * get_mmuidx
1048  * @oi: combined op/idx parameter
1049  *
1050  * Extract the mmu index from the combined value.
1051  */
1052 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1053 {
1054     return oi & 15;
1055 }
1056
1057 /**
1058  * tcg_qemu_tb_exec:
1059  * @env: pointer to CPUArchState for the CPU
1060  * @tb_ptr: address of generated code for the TB to execute
1061  *
1062  * Start executing code from a given translation block.
1063  * Where translation blocks have been linked, execution
1064  * may proceed from the given TB into successive ones.
1065  * Control eventually returns only when some action is needed
1066  * from the top-level loop: either control must pass to a TB
1067  * which has not yet been directly linked, or an asynchronous
1068  * event such as an interrupt needs handling.
1069  *
1070  * Return: The return value is the value passed to the corresponding
1071  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1072  * The value is either zero or a 4-byte aligned pointer to that TB combined
1073  * with additional information in its two least significant bits. The
1074  * additional information is encoded as follows:
1075  *  0, 1: the link between this TB and the next is via the specified
1076  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1077  *        of) "goto_tb <index>". The main loop uses this to determine
1078  *        how to link the TB just executed to the next.
1079  *  2:    we are using instruction counting code generation, and we
1080  *        did not start executing this TB because the instruction counter
1081  *        would hit zero midway through it. In this case the pointer
1082  *        returned is the TB we were about to execute, and the caller must
1083  *        arrange to execute the remaining count of instructions.
1084  *  3:    we stopped because the CPU's exit_request flag was set
1085  *        (usually meaning that there is an interrupt that needs to be
1086  *        handled). The pointer returned is the TB we were about to execute
1087  *        when we noticed the pending exit request.
1088  *
1089  * If the bottom two bits indicate an exit-via-index then the CPU
1090  * state is correctly synchronised and ready for execution of the next
1091  * TB (and in particular the guest PC is the address to execute next).
1092  * Otherwise, we gave up on execution of this TB before it started, and
1093  * the caller must fix up the CPU state by calling the CPU's
1094  * synchronize_from_tb() method with the TB pointer we return (falling
1095  * back to calling the CPU's set_pc method with tb->pb if no
1096  * synchronize_from_tb() method exists).
1097  *
1098  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1099  * to this default (which just calls the prologue.code emitted by
1100  * tcg_target_qemu_prologue()).
1101  */
1102 #define TB_EXIT_MASK 3
1103 #define TB_EXIT_IDX0 0
1104 #define TB_EXIT_IDX1 1
1105 #define TB_EXIT_REQUESTED 3
1106
1107 #ifdef HAVE_TCG_QEMU_TB_EXEC
1108 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1109 #else
1110 # define tcg_qemu_tb_exec(env, tb_ptr) \
1111     ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
1112 #endif
1113
1114 void tcg_register_jit(void *buf, size_t buf_size);
1115
1116 /*
1117  * Memory helpers that will be used by TCG generated code.
1118  */
1119 #ifdef CONFIG_SOFTMMU
1120 /* Value zero-extended to tcg register size.  */
1121 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1122                                      TCGMemOpIdx oi, uintptr_t retaddr);
1123 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1124                                     TCGMemOpIdx oi, uintptr_t retaddr);
1125 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1126                                     TCGMemOpIdx oi, uintptr_t retaddr);
1127 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1128                            TCGMemOpIdx oi, uintptr_t retaddr);
1129 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1130                                     TCGMemOpIdx oi, uintptr_t retaddr);
1131 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1132                                     TCGMemOpIdx oi, uintptr_t retaddr);
1133 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1134                            TCGMemOpIdx oi, uintptr_t retaddr);
1135
1136 /* Value sign-extended to tcg register size.  */
1137 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1138                                      TCGMemOpIdx oi, uintptr_t retaddr);
1139 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1140                                     TCGMemOpIdx oi, uintptr_t retaddr);
1141 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1142                                     TCGMemOpIdx oi, uintptr_t retaddr);
1143 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1144                                     TCGMemOpIdx oi, uintptr_t retaddr);
1145 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1146                                     TCGMemOpIdx oi, uintptr_t retaddr);
1147
1148 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1149                         TCGMemOpIdx oi, uintptr_t retaddr);
1150 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1151                        TCGMemOpIdx oi, uintptr_t retaddr);
1152 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1153                        TCGMemOpIdx oi, uintptr_t retaddr);
1154 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1155                        TCGMemOpIdx oi, uintptr_t retaddr);
1156 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1157                        TCGMemOpIdx oi, uintptr_t retaddr);
1158 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1159                        TCGMemOpIdx oi, uintptr_t retaddr);
1160 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1161                        TCGMemOpIdx oi, uintptr_t retaddr);
1162
1163 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1164                             TCGMemOpIdx oi, uintptr_t retaddr);
1165 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1166                             TCGMemOpIdx oi, uintptr_t retaddr);
1167 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1168                             TCGMemOpIdx oi, uintptr_t retaddr);
1169 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1170                             TCGMemOpIdx oi, uintptr_t retaddr);
1171 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1172                             TCGMemOpIdx oi, uintptr_t retaddr);
1173 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1174                             TCGMemOpIdx oi, uintptr_t retaddr);
1175 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1176                             TCGMemOpIdx oi, uintptr_t retaddr);
1177
1178 /* Temporary aliases until backends are converted.  */
1179 #ifdef TARGET_WORDS_BIGENDIAN
1180 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1181 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1182 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1183 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1184 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1185 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1186 # define helper_ret_stw_mmu   helper_be_stw_mmu
1187 # define helper_ret_stl_mmu   helper_be_stl_mmu
1188 # define helper_ret_stq_mmu   helper_be_stq_mmu
1189 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1190 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1191 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1192 #else
1193 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1194 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1195 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1196 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1197 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1198 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1199 # define helper_ret_stw_mmu   helper_le_stw_mmu
1200 # define helper_ret_stl_mmu   helper_le_stl_mmu
1201 # define helper_ret_stq_mmu   helper_le_stq_mmu
1202 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1203 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1204 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1205 #endif
1206
1207 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1208                                     uint32_t cmpv, uint32_t newv,
1209                                     TCGMemOpIdx oi, uintptr_t retaddr);
1210 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1211                                        uint32_t cmpv, uint32_t newv,
1212                                        TCGMemOpIdx oi, uintptr_t retaddr);
1213 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1214                                        uint32_t cmpv, uint32_t newv,
1215                                        TCGMemOpIdx oi, uintptr_t retaddr);
1216 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1217                                        uint64_t cmpv, uint64_t newv,
1218                                        TCGMemOpIdx oi, uintptr_t retaddr);
1219 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1220                                        uint32_t cmpv, uint32_t newv,
1221                                        TCGMemOpIdx oi, uintptr_t retaddr);
1222 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1223                                        uint32_t cmpv, uint32_t newv,
1224                                        TCGMemOpIdx oi, uintptr_t retaddr);
1225 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1226                                        uint64_t cmpv, uint64_t newv,
1227                                        TCGMemOpIdx oi, uintptr_t retaddr);
1228
1229 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1230 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1231     (CPUArchState *env, target_ulong addr, TYPE val,  \
1232      TCGMemOpIdx oi, uintptr_t retaddr);
1233
1234 #ifdef CONFIG_ATOMIC64
1235 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1236     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1237     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1238     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1239     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1240     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1241     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1242     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1243 #else
1244 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1245     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1246     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1247     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1248     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1249     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1250 #endif
1251
1252 GEN_ATOMIC_HELPER_ALL(fetch_add)
1253 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1254 GEN_ATOMIC_HELPER_ALL(fetch_and)
1255 GEN_ATOMIC_HELPER_ALL(fetch_or)
1256 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1257
1258 GEN_ATOMIC_HELPER_ALL(add_fetch)
1259 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1260 GEN_ATOMIC_HELPER_ALL(and_fetch)
1261 GEN_ATOMIC_HELPER_ALL(or_fetch)
1262 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1263
1264 GEN_ATOMIC_HELPER_ALL(xchg)
1265
1266 #undef GEN_ATOMIC_HELPER_ALL
1267 #undef GEN_ATOMIC_HELPER
1268 #endif /* CONFIG_SOFTMMU */
1269
1270 #ifdef CONFIG_ATOMIC128
1271 #include "qemu/int128.h"
1272
1273 /* These aren't really a "proper" helpers because TCG cannot manage Int128.
1274    However, use the same format as the others, for use by the backends. */
1275 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1276                                      Int128 cmpv, Int128 newv,
1277                                      TCGMemOpIdx oi, uintptr_t retaddr);
1278 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1279                                      Int128 cmpv, Int128 newv,
1280                                      TCGMemOpIdx oi, uintptr_t retaddr);
1281
1282 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1283                                 TCGMemOpIdx oi, uintptr_t retaddr);
1284 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1285                                 TCGMemOpIdx oi, uintptr_t retaddr);
1286 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1287                               TCGMemOpIdx oi, uintptr_t retaddr);
1288 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1289                               TCGMemOpIdx oi, uintptr_t retaddr);
1290
1291 #endif /* CONFIG_ATOMIC128 */
1292
1293 #endif /* TCG_H */