2 * OpenRISC virtual CPU header.
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef CPU_OPENRISC_H
21 #define CPU_OPENRISC_H
23 #define TARGET_LONG_BITS 32
25 #define CPUArchState struct CPUOpenRISCState
27 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
31 #include "qemu-common.h"
32 #include "exec/cpu-defs.h"
33 #include "fpu/softfloat.h"
36 #define TYPE_OPENRISC_CPU "or32-cpu"
38 #define OPENRISC_CPU_CLASS(klass) \
39 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
40 #define OPENRISC_CPU(obj) \
41 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
42 #define OPENRISC_CPU_GET_CLASS(obj) \
43 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
47 * @parent_realize: The parent class' realize handler.
48 * @parent_reset: The parent class' reset handler.
50 * A OpenRISC CPU model.
52 typedef struct OpenRISCCPUClass
{
54 CPUClass parent_class
;
57 DeviceRealize parent_realize
;
58 void (*parent_reset
)(CPUState
*cpu
);
61 #define NB_MMU_MODES 3
65 MMU_SUPERVISOR_IDX
= 1,
69 #define TARGET_PAGE_BITS 13
71 #define TARGET_PHYS_ADDR_SPACE_BITS 32
72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
74 #define SET_FP_CAUSE(reg, v) do {\
75 (reg) = ((reg) & ~(0x3f << 12)) | \
78 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
79 #define UPDATE_FP_FLAGS(reg, v) do {\
80 (reg) |= ((v & 0x1f) << 2);\
83 /* Version Register */
84 #define SPR_VR 0xFFFF003F
86 /* Internal flags, delay slot flag */
92 /* Unit presece register */
105 UPR_CUP
= (255 << 24),
108 /* CPU configure register */
110 CPUCFGR_NSGF
= (15 << 0),
111 CPUCFGR_CGF
= (1 << 4),
112 CPUCFGR_OB32S
= (1 << 5),
113 CPUCFGR_OB64S
= (1 << 6),
114 CPUCFGR_OF32S
= (1 << 7),
115 CPUCFGR_OF64S
= (1 << 8),
116 CPUCFGR_OV64S
= (1 << 9),
119 /* DMMU configure register */
121 DMMUCFGR_NTW
= (3 << 0),
122 DMMUCFGR_NTS
= (7 << 2),
123 DMMUCFGR_NAE
= (7 << 5),
124 DMMUCFGR_CRI
= (1 << 8),
125 DMMUCFGR_PRI
= (1 << 9),
126 DMMUCFGR_TEIRI
= (1 << 10),
127 DMMUCFGR_HTR
= (1 << 11),
130 /* IMMU configure register */
132 IMMUCFGR_NTW
= (3 << 0),
133 IMMUCFGR_NTS
= (7 << 2),
134 IMMUCFGR_NAE
= (7 << 5),
135 IMMUCFGR_CRI
= (1 << 8),
136 IMMUCFGR_PRI
= (1 << 9),
137 IMMUCFGR_TEIRI
= (1 << 10),
138 IMMUCFGR_HTR
= (1 << 11),
141 /* Float point control status register */
145 FPCSR_OVF
= (1 << 3),
146 FPCSR_UNF
= (1 << 4),
147 FPCSR_SNF
= (1 << 5),
148 FPCSR_QNF
= (1 << 6),
150 FPCSR_IXF
= (1 << 8),
151 FPCSR_IVF
= (1 << 9),
152 FPCSR_INF
= (1 << 10),
153 FPCSR_DZF
= (1 << 11),
156 /* Exceptions indices */
175 /* Supervisor register */
193 SR_SUMRA
= (1 << 16),
197 /* OpenRISC Hardware Capabilities */
199 OPENRISC_FEATURE_NSGF
= (15 << 0),
200 OPENRISC_FEATURE_CGF
= (1 << 4),
201 OPENRISC_FEATURE_OB32S
= (1 << 5),
202 OPENRISC_FEATURE_OB64S
= (1 << 6),
203 OPENRISC_FEATURE_OF32S
= (1 << 7),
204 OPENRISC_FEATURE_OF64S
= (1 << 8),
205 OPENRISC_FEATURE_OV64S
= (1 << 9),
208 /* Tick Timer Mode Register */
210 TTMR_TP
= (0xfffffff),
218 TIMER_NONE
= (0 << 30),
219 TIMER_INTR
= (1 << 30),
220 TIMER_SHOT
= (2 << 30),
221 TIMER_CONT
= (3 << 30),
228 DTLB_MASK
= (DTLB_SIZE
-1),
231 ITLB_MASK
= (ITLB_SIZE
-1),
245 /* check if tlb available */
253 typedef struct OpenRISCTLBEntry
{
258 #ifndef CONFIG_USER_ONLY
259 typedef struct CPUOpenRISCTLBContext
{
260 OpenRISCTLBEntry itlb
[ITLB_WAYS
][ITLB_SIZE
];
261 OpenRISCTLBEntry dtlb
[DTLB_WAYS
][DTLB_SIZE
];
263 int (*cpu_openrisc_map_address_code
)(struct OpenRISCCPU
*cpu
,
266 target_ulong address
, int rw
);
267 int (*cpu_openrisc_map_address_data
)(struct OpenRISCCPU
*cpu
,
270 target_ulong address
, int rw
);
271 } CPUOpenRISCTLBContext
;
274 typedef struct CPUOpenRISCState
{
275 target_ulong gpr
[32]; /* General registers */
276 target_ulong pc
; /* Program counter */
277 target_ulong npc
; /* Next PC */
278 target_ulong ppc
; /* Prev PC */
279 target_ulong jmp_pc
; /* Jump PC */
281 target_ulong machi
; /* Multiply register MACHI */
282 target_ulong maclo
; /* Multiply register MACLO */
284 target_ulong fpmaddhi
; /* Multiply and add float register FPMADDHI */
285 target_ulong fpmaddlo
; /* Multiply and add float register FPMADDLO */
287 target_ulong epcr
; /* Exception PC register */
288 target_ulong eear
; /* Exception EA register */
290 uint32_t sr
; /* Supervisor register */
291 uint32_t vr
; /* Version register */
292 uint32_t upr
; /* Unit presence register */
293 uint32_t cpucfgr
; /* CPU configure register */
294 uint32_t dmmucfgr
; /* DMMU configure register */
295 uint32_t immucfgr
; /* IMMU configure register */
296 uint32_t esr
; /* Exception supervisor register */
297 uint32_t fpcsr
; /* Float register */
298 float_status fp_status
;
300 uint32_t flags
; /* cpu_flags, we only use it for exception
302 uint32_t btaken
; /* the SR_F bit */
306 /* Fields from here on are preserved across CPU reset. */
307 #ifndef CONFIG_USER_ONLY
308 CPUOpenRISCTLBContext
* tlb
;
311 uint32_t ttmr
; /* Timer tick mode register */
312 uint32_t ttcr
; /* Timer tick count register */
314 uint32_t picmr
; /* Interrupt mask register */
315 uint32_t picsr
; /* Interrupt contrl register*/
317 void *irq
[32]; /* Interrupt irq input */
322 * @env: #CPUOpenRISCState
326 typedef struct OpenRISCCPU
{
331 CPUOpenRISCState env
;
333 uint32_t feature
; /* CPU Capabilities */
336 static inline OpenRISCCPU
*openrisc_env_get_cpu(CPUOpenRISCState
*env
)
338 return container_of(env
, OpenRISCCPU
, env
);
341 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
343 #define ENV_OFFSET offsetof(OpenRISCCPU, env)
345 OpenRISCCPU
*cpu_openrisc_init(const char *cpu_model
);
347 void cpu_openrisc_list(FILE *f
, fprintf_function cpu_fprintf
);
348 int cpu_openrisc_exec(CPUState
*cpu
);
349 void openrisc_cpu_do_interrupt(CPUState
*cpu
);
350 bool openrisc_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
351 void openrisc_cpu_dump_state(CPUState
*cpu
, FILE *f
,
352 fprintf_function cpu_fprintf
, int flags
);
353 hwaddr
openrisc_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
354 int openrisc_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
355 int openrisc_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
356 void openrisc_translate_init(void);
357 int openrisc_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
,
358 int rw
, int mmu_idx
);
359 int cpu_openrisc_signal_handler(int host_signum
, void *pinfo
, void *puc
);
361 #define cpu_list cpu_openrisc_list
362 #define cpu_exec cpu_openrisc_exec
363 #define cpu_signal_handler cpu_openrisc_signal_handler
365 #ifndef CONFIG_USER_ONLY
366 extern const struct VMStateDescription vmstate_openrisc_cpu
;
368 /* hw/openrisc_pic.c */
369 void cpu_openrisc_pic_init(OpenRISCCPU
*cpu
);
371 /* hw/openrisc_timer.c */
372 void cpu_openrisc_clock_init(OpenRISCCPU
*cpu
);
373 void cpu_openrisc_count_update(OpenRISCCPU
*cpu
);
374 void cpu_openrisc_timer_update(OpenRISCCPU
*cpu
);
375 void cpu_openrisc_count_start(OpenRISCCPU
*cpu
);
376 void cpu_openrisc_count_stop(OpenRISCCPU
*cpu
);
378 void cpu_openrisc_mmu_init(OpenRISCCPU
*cpu
);
379 int cpu_openrisc_get_phys_nommu(OpenRISCCPU
*cpu
,
381 int *prot
, target_ulong address
, int rw
);
382 int cpu_openrisc_get_phys_code(OpenRISCCPU
*cpu
,
384 int *prot
, target_ulong address
, int rw
);
385 int cpu_openrisc_get_phys_data(OpenRISCCPU
*cpu
,
387 int *prot
, target_ulong address
, int rw
);
390 #define cpu_init(cpu_model) CPU(cpu_openrisc_init(cpu_model))
392 #include "exec/cpu-all.h"
394 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState
*env
,
396 target_ulong
*cs_base
, int *flags
)
400 /* D_FLAG -- branch instruction exception */
401 *flags
= (env
->flags
& D_FLAG
);
404 static inline int cpu_mmu_index(CPUOpenRISCState
*env
, bool ifetch
)
406 if (!(env
->sr
& SR_IME
)) {
407 return MMU_NOMMU_IDX
;
409 return (env
->sr
& SR_SM
) == 0 ? MMU_USER_IDX
: MMU_SUPERVISOR_IDX
;
412 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
414 #include "exec/exec-all.h"
416 #endif /* CPU_OPENRISC_H */