hw/arm_gic.c

   1 /*
   2  * ARM Generic/Distributed Interrupt Controller
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 /* This file contains implementation code for the RealView EB interrupt
  11  * controller, MPCore distributed interrupt controller and ARMv7-M
  12  * Nested Vectored Interrupt Controller.
  13  * It is compiled in two ways:
  14  *  (1) as a standalone file to produce a sysbus device which is a GIC
  15  *  that can be used on the realview board and as one of the builtin
  16  *  private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
  17  *  (2) by being directly #included into armv7m_nvic.c to produce the
  18  *  armv7m_nvic device.
  19  */
  20
  21 #include "sysbus.h"
  22 #include "arm_gic_internal.h"
  23
  24 //#define DEBUG_GIC
  25
  26 #ifdef DEBUG_GIC
  27 #define DPRINTF(fmt, ...) \
  28 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
  29 #else
  30 #define DPRINTF(fmt, ...) do {} while(0)
  31 #endif
  32
  33 static const uint8_t gic_id[] = {
  34     0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
  35 };
  36
  37 #define NUM_CPU(s) ((s)->num_cpu)
  38
  39 static inline int gic_get_current_cpu(GICState *s)
  40 {
  41     if (s->num_cpu > 1) {
  42         return cpu_single_env->cpu_index;
  43     }
  44     return 0;
  45 }
  46
  47 /* TODO: Many places that call this routine could be optimized.  */
  48 /* Update interrupt status after enabled or pending bits have been changed.  */
  49 void gic_update(GICState *s)
  50 {
  51     int best_irq;
  52     int best_prio;
  53     int irq;
  54     int level;
  55     int cpu;
  56     int cm;
  57
  58     for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
  59         cm = 1 << cpu;
  60         s->current_pending[cpu] = 1023;
  61         if (!s->enabled || !s->cpu_enabled[cpu]) {
  62             qemu_irq_lower(s->parent_irq[cpu]);
  63             return;
  64         }
  65         best_prio = 0x100;
  66         best_irq = 1023;
  67         for (irq = 0; irq < s->num_irq; irq++) {
  68             if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
  69                 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
  70                     best_prio = GIC_GET_PRIORITY(irq, cpu);
  71                     best_irq = irq;
  72                 }
  73             }
  74         }
  75         level = 0;
  76         if (best_prio < s->priority_mask[cpu]) {
  77             s->current_pending[cpu] = best_irq;
  78             if (best_prio < s->running_priority[cpu]) {
  79                 DPRINTF("Raised pending IRQ %d\n", best_irq);
  80                 level = 1;
  81             }
  82         }
  83         qemu_set_irq(s->parent_irq[cpu], level);
  84     }
  85 }
  86
  87 void gic_set_pending_private(GICState *s, int cpu, int irq)
  88 {
  89     int cm = 1 << cpu;
  90
  91     if (GIC_TEST_PENDING(irq, cm))
  92         return;
  93
  94     DPRINTF("Set %d pending cpu %d\n", irq, cpu);
  95     GIC_SET_PENDING(irq, cm);
  96     gic_update(s);
  97 }
  98
  99 /* Process a change in an external IRQ input.  */
 100 static void gic_set_irq(void *opaque, int irq, int level)
 101 {
 102     /* Meaning of the 'irq' parameter:
 103      *  [0..N-1] : external interrupts
 104      *  [N..N+31] : PPI (internal) interrupts for CPU 0
 105      *  [N+32..N+63] : PPI (internal interrupts for CPU 1
 106      *  ...
 107      */
 108     GICState *s = (GICState *)opaque;
 109     int cm, target;
 110     if (irq < (s->num_irq - GIC_INTERNAL)) {
 111         /* The first external input line is internal interrupt 32.  */
 112         cm = ALL_CPU_MASK;
 113         irq += GIC_INTERNAL;
 114         target = GIC_TARGET(irq);
 115     } else {
 116         int cpu;
 117         irq -= (s->num_irq - GIC_INTERNAL);
 118         cpu = irq / GIC_INTERNAL;
 119         irq %= GIC_INTERNAL;
 120         cm = 1 << cpu;
 121         target = cm;
 122     }
 123
 124     if (level == GIC_TEST_LEVEL(irq, cm)) {
 125         return;
 126     }
 127
 128     if (level) {
 129         GIC_SET_LEVEL(irq, cm);
 130         if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
 131             DPRINTF("Set %d pending mask %x\n", irq, target);
 132             GIC_SET_PENDING(irq, target);
 133         }
 134     } else {
 135         GIC_CLEAR_LEVEL(irq, cm);
 136     }
 137     gic_update(s);
 138 }
 139
 140 static void gic_set_running_irq(GICState *s, int cpu, int irq)
 141 {
 142     s->running_irq[cpu] = irq;
 143     if (irq == 1023) {
 144         s->running_priority[cpu] = 0x100;
 145     } else {
 146         s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
 147     }
 148     gic_update(s);
 149 }
 150
 151 uint32_t gic_acknowledge_irq(GICState *s, int cpu)
 152 {
 153     int new_irq;
 154     int cm = 1 << cpu;
 155     new_irq = s->current_pending[cpu];
 156     if (new_irq == 1023
 157             || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
 158         DPRINTF("ACK no pending IRQ\n");
 159         return 1023;
 160     }
 161     s->last_active[new_irq][cpu] = s->running_irq[cpu];
 162     /* Clear pending flags for both level and edge triggered interrupts.
 163        Level triggered IRQs will be reasserted once they become inactive.  */
 164     GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
 165     gic_set_running_irq(s, cpu, new_irq);
 166     DPRINTF("ACK %d\n", new_irq);
 167     return new_irq;
 168 }
 169
 170 void gic_complete_irq(GICState *s, int cpu, int irq)
 171 {
 172     int update = 0;
 173     int cm = 1 << cpu;
 174     DPRINTF("EOI %d\n", irq);
 175     if (irq >= s->num_irq) {
 176         /* This handles two cases:
 177          * 1. If software writes the ID of a spurious interrupt [ie 1023]
 178          * to the GICC_EOIR, the GIC ignores that write.
 179          * 2. If software writes the number of a non-existent interrupt
 180          * this must be a subcase of "value written does not match the last
 181          * valid interrupt value read from the Interrupt Acknowledge
 182          * register" and so this is UNPREDICTABLE. We choose to ignore it.
 183          */
 184         return;
 185     }
 186     if (s->running_irq[cpu] == 1023)
 187         return; /* No active IRQ.  */
 188     /* Mark level triggered interrupts as pending if they are still
 189        raised.  */
 190     if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
 191         && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
 192         DPRINTF("Set %d pending mask %x\n", irq, cm);
 193         GIC_SET_PENDING(irq, cm);
 194         update = 1;
 195     }
 196     if (irq != s->running_irq[cpu]) {
 197         /* Complete an IRQ that is not currently running.  */
 198         int tmp = s->running_irq[cpu];
 199         while (s->last_active[tmp][cpu] != 1023) {
 200             if (s->last_active[tmp][cpu] == irq) {
 201                 s->last_active[tmp][cpu] = s->last_active[irq][cpu];
 202                 break;
 203             }
 204             tmp = s->last_active[tmp][cpu];
 205         }
 206         if (update) {
 207             gic_update(s);
 208         }
 209     } else {
 210         /* Complete the current running IRQ.  */
 211         gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
 212     }
 213 }
 214
 215 static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
 216 {
 217     GICState *s = (GICState *)opaque;
 218     uint32_t res;
 219     int irq;
 220     int i;
 221     int cpu;
 222     int cm;
 223     int mask;
 224
 225     cpu = gic_get_current_cpu(s);
 226     cm = 1 << cpu;
 227     if (offset < 0x100) {
 228         if (offset == 0)
 229             return s->enabled;
 230         if (offset == 4)
 231             return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
 232         if (offset < 0x08)
 233             return 0;
 234         if (offset >= 0x80) {
 235             /* Interrupt Security , RAZ/WI */
 236             return 0;
 237         }
 238         goto bad_reg;
 239     } else if (offset < 0x200) {
 240         /* Interrupt Set/Clear Enable.  */
 241         if (offset < 0x180)
 242             irq = (offset - 0x100) * 8;
 243         else
 244             irq = (offset - 0x180) * 8;
 245         irq += GIC_BASE_IRQ;
 246         if (irq >= s->num_irq)
 247             goto bad_reg;
 248         res = 0;
 249         for (i = 0; i < 8; i++) {
 250             if (GIC_TEST_ENABLED(irq + i, cm)) {
 251                 res |= (1 << i);
 252             }
 253         }
 254     } else if (offset < 0x300) {
 255         /* Interrupt Set/Clear Pending.  */
 256         if (offset < 0x280)
 257             irq = (offset - 0x200) * 8;
 258         else
 259             irq = (offset - 0x280) * 8;
 260         irq += GIC_BASE_IRQ;
 261         if (irq >= s->num_irq)
 262             goto bad_reg;
 263         res = 0;
 264         mask = (irq < GIC_INTERNAL) ?  cm : ALL_CPU_MASK;
 265         for (i = 0; i < 8; i++) {
 266             if (GIC_TEST_PENDING(irq + i, mask)) {
 267                 res |= (1 << i);
 268             }
 269         }
 270     } else if (offset < 0x400) {
 271         /* Interrupt Active.  */
 272         irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
 273         if (irq >= s->num_irq)
 274             goto bad_reg;
 275         res = 0;
 276         mask = (irq < GIC_INTERNAL) ?  cm : ALL_CPU_MASK;
 277         for (i = 0; i < 8; i++) {
 278             if (GIC_TEST_ACTIVE(irq + i, mask)) {
 279                 res |= (1 << i);
 280             }
 281         }
 282     } else if (offset < 0x800) {
 283         /* Interrupt Priority.  */
 284         irq = (offset - 0x400) + GIC_BASE_IRQ;
 285         if (irq >= s->num_irq)
 286             goto bad_reg;
 287         res = GIC_GET_PRIORITY(irq, cpu);
 288     } else if (offset < 0xc00) {
 289         /* Interrupt CPU Target.  */
 290         if (s->num_cpu == 1 && s->revision != REV_11MPCORE) {
 291             /* For uniprocessor GICs these RAZ/WI */
 292             res = 0;
 293         } else {
 294             irq = (offset - 0x800) + GIC_BASE_IRQ;
 295             if (irq >= s->num_irq) {
 296                 goto bad_reg;
 297             }
 298             if (irq >= 29 && irq <= 31) {
 299                 res = cm;
 300             } else {
 301                 res = GIC_TARGET(irq);
 302             }
 303         }
 304     } else if (offset < 0xf00) {
 305         /* Interrupt Configuration.  */
 306         irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
 307         if (irq >= s->num_irq)
 308             goto bad_reg;
 309         res = 0;
 310         for (i = 0; i < 4; i++) {
 311             if (GIC_TEST_MODEL(irq + i))
 312                 res |= (1 << (i * 2));
 313             if (GIC_TEST_TRIGGER(irq + i))
 314                 res |= (2 << (i * 2));
 315         }
 316     } else if (offset < 0xfe0) {
 317         goto bad_reg;
 318     } else /* offset >= 0xfe0 */ {
 319         if (offset & 3) {
 320             res = 0;
 321         } else {
 322             res = gic_id[(offset - 0xfe0) >> 2];
 323         }
 324     }
 325     return res;
 326 bad_reg:
 327     qemu_log_mask(LOG_GUEST_ERROR,
 328                   "gic_dist_readb: Bad offset %x\n", (int)offset);
 329     return 0;
 330 }
 331
 332 static uint32_t gic_dist_readw(void *opaque, hwaddr offset)
 333 {
 334     uint32_t val;
 335     val = gic_dist_readb(opaque, offset);
 336     val |= gic_dist_readb(opaque, offset + 1) << 8;
 337     return val;
 338 }
 339
 340 static uint32_t gic_dist_readl(void *opaque, hwaddr offset)
 341 {
 342     uint32_t val;
 343     val = gic_dist_readw(opaque, offset);
 344     val |= gic_dist_readw(opaque, offset + 2) << 16;
 345     return val;
 346 }
 347
 348 static void gic_dist_writeb(void *opaque, hwaddr offset,
 349                             uint32_t value)
 350 {
 351     GICState *s = (GICState *)opaque;
 352     int irq;
 353     int i;
 354     int cpu;
 355
 356     cpu = gic_get_current_cpu(s);
 357     if (offset < 0x100) {
 358         if (offset == 0) {
 359             s->enabled = (value & 1);
 360             DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
 361         } else if (offset < 4) {
 362             /* ignored.  */
 363         } else if (offset >= 0x80) {
 364             /* Interrupt Security Registers, RAZ/WI */
 365         } else {
 366             goto bad_reg;
 367         }
 368     } else if (offset < 0x180) {
 369         /* Interrupt Set Enable.  */
 370         irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
 371         if (irq >= s->num_irq)
 372             goto bad_reg;
 373         if (irq < 16)
 374           value = 0xff;
 375         for (i = 0; i < 8; i++) {
 376             if (value & (1 << i)) {
 377                 int mask =
 378                     (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i);
 379                 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 380
 381                 if (!GIC_TEST_ENABLED(irq + i, cm)) {
 382                     DPRINTF("Enabled IRQ %d\n", irq + i);
 383                 }
 384                 GIC_SET_ENABLED(irq + i, cm);
 385                 /* If a raised level triggered IRQ enabled then mark
 386                    is as pending.  */
 387                 if (GIC_TEST_LEVEL(irq + i, mask)
 388                         && !GIC_TEST_TRIGGER(irq + i)) {
 389                     DPRINTF("Set %d pending mask %x\n", irq + i, mask);
 390                     GIC_SET_PENDING(irq + i, mask);
 391                 }
 392             }
 393         }
 394     } else if (offset < 0x200) {
 395         /* Interrupt Clear Enable.  */
 396         irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
 397         if (irq >= s->num_irq)
 398             goto bad_reg;
 399         if (irq < 16)
 400           value = 0;
 401         for (i = 0; i < 8; i++) {
 402             if (value & (1 << i)) {
 403                 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 404
 405                 if (GIC_TEST_ENABLED(irq + i, cm)) {
 406                     DPRINTF("Disabled IRQ %d\n", irq + i);
 407                 }
 408                 GIC_CLEAR_ENABLED(irq + i, cm);
 409             }
 410         }
 411     } else if (offset < 0x280) {
 412         /* Interrupt Set Pending.  */
 413         irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
 414         if (irq >= s->num_irq)
 415             goto bad_reg;
 416         if (irq < 16)
 417           irq = 0;
 418
 419         for (i = 0; i < 8; i++) {
 420             if (value & (1 << i)) {
 421                 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i));
 422             }
 423         }
 424     } else if (offset < 0x300) {
 425         /* Interrupt Clear Pending.  */
 426         irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
 427         if (irq >= s->num_irq)
 428             goto bad_reg;
 429         for (i = 0; i < 8; i++) {
 430             /* ??? This currently clears the pending bit for all CPUs, even
 431                for per-CPU interrupts.  It's unclear whether this is the
 432                corect behavior.  */
 433             if (value & (1 << i)) {
 434                 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
 435             }
 436         }
 437     } else if (offset < 0x400) {
 438         /* Interrupt Active.  */
 439         goto bad_reg;
 440     } else if (offset < 0x800) {
 441         /* Interrupt Priority.  */
 442         irq = (offset - 0x400) + GIC_BASE_IRQ;
 443         if (irq >= s->num_irq)
 444             goto bad_reg;
 445         if (irq < GIC_INTERNAL) {
 446             s->priority1[irq][cpu] = value;
 447         } else {
 448             s->priority2[irq - GIC_INTERNAL] = value;
 449         }
 450     } else if (offset < 0xc00) {
 451         /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
 452          * annoying exception of the 11MPCore's GIC.
 453          */
 454         if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
 455             irq = (offset - 0x800) + GIC_BASE_IRQ;
 456             if (irq >= s->num_irq) {
 457                 goto bad_reg;
 458             }
 459             if (irq < 29) {
 460                 value = 0;
 461             } else if (irq < GIC_INTERNAL) {
 462                 value = ALL_CPU_MASK;
 463             }
 464             s->irq_target[irq] = value & ALL_CPU_MASK;
 465         }
 466     } else if (offset < 0xf00) {
 467         /* Interrupt Configuration.  */
 468         irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
 469         if (irq >= s->num_irq)
 470             goto bad_reg;
 471         if (irq < GIC_INTERNAL)
 472             value |= 0xaa;
 473         for (i = 0; i < 4; i++) {
 474             if (value & (1 << (i * 2))) {
 475                 GIC_SET_MODEL(irq + i);
 476             } else {
 477                 GIC_CLEAR_MODEL(irq + i);
 478             }
 479             if (value & (2 << (i * 2))) {
 480                 GIC_SET_TRIGGER(irq + i);
 481             } else {
 482                 GIC_CLEAR_TRIGGER(irq + i);
 483             }
 484         }
 485     } else {
 486         /* 0xf00 is only handled for 32-bit writes.  */
 487         goto bad_reg;
 488     }
 489     gic_update(s);
 490     return;
 491 bad_reg:
 492     qemu_log_mask(LOG_GUEST_ERROR,
 493                   "gic_dist_writeb: Bad offset %x\n", (int)offset);
 494 }
 495
 496 static void gic_dist_writew(void *opaque, hwaddr offset,
 497                             uint32_t value)
 498 {
 499     gic_dist_writeb(opaque, offset, value & 0xff);
 500     gic_dist_writeb(opaque, offset + 1, value >> 8);
 501 }
 502
 503 static void gic_dist_writel(void *opaque, hwaddr offset,
 504                             uint32_t value)
 505 {
 506     GICState *s = (GICState *)opaque;
 507     if (offset == 0xf00) {
 508         int cpu;
 509         int irq;
 510         int mask;
 511
 512         cpu = gic_get_current_cpu(s);
 513         irq = value & 0x3ff;
 514         switch ((value >> 24) & 3) {
 515         case 0:
 516             mask = (value >> 16) & ALL_CPU_MASK;
 517             break;
 518         case 1:
 519             mask = ALL_CPU_MASK ^ (1 << cpu);
 520             break;
 521         case 2:
 522             mask = 1 << cpu;
 523             break;
 524         default:
 525             DPRINTF("Bad Soft Int target filter\n");
 526             mask = ALL_CPU_MASK;
 527             break;
 528         }
 529         GIC_SET_PENDING(irq, mask);
 530         gic_update(s);
 531         return;
 532     }
 533     gic_dist_writew(opaque, offset, value & 0xffff);
 534     gic_dist_writew(opaque, offset + 2, value >> 16);
 535 }
 536
 537 static const MemoryRegionOps gic_dist_ops = {
 538     .old_mmio = {
 539         .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
 540         .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
 541     },
 542     .endianness = DEVICE_NATIVE_ENDIAN,
 543 };
 544
 545 static uint32_t gic_cpu_read(GICState *s, int cpu, int offset)
 546 {
 547     switch (offset) {
 548     case 0x00: /* Control */
 549         return s->cpu_enabled[cpu];
 550     case 0x04: /* Priority mask */
 551         return s->priority_mask[cpu];
 552     case 0x08: /* Binary Point */
 553         /* ??? Not implemented.  */
 554         return 0;
 555     case 0x0c: /* Acknowledge */
 556         return gic_acknowledge_irq(s, cpu);
 557     case 0x14: /* Running Priority */
 558         return s->running_priority[cpu];
 559     case 0x18: /* Highest Pending Interrupt */
 560         return s->current_pending[cpu];
 561     default:
 562         qemu_log_mask(LOG_GUEST_ERROR,
 563                       "gic_cpu_read: Bad offset %x\n", (int)offset);
 564         return 0;
 565     }
 566 }
 567
 568 static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value)
 569 {
 570     switch (offset) {
 571     case 0x00: /* Control */
 572         s->cpu_enabled[cpu] = (value & 1);
 573         DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled[cpu] ? "En" : "Dis");
 574         break;
 575     case 0x04: /* Priority mask */
 576         s->priority_mask[cpu] = (value & 0xff);
 577         break;
 578     case 0x08: /* Binary Point */
 579         /* ??? Not implemented.  */
 580         break;
 581     case 0x10: /* End Of Interrupt */
 582         return gic_complete_irq(s, cpu, value & 0x3ff);
 583     default:
 584         qemu_log_mask(LOG_GUEST_ERROR,
 585                       "gic_cpu_write: Bad offset %x\n", (int)offset);
 586         return;
 587     }
 588     gic_update(s);
 589 }
 590
 591 /* Wrappers to read/write the GIC CPU interface for the current CPU */
 592 static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr,
 593                                  unsigned size)
 594 {
 595     GICState *s = (GICState *)opaque;
 596     return gic_cpu_read(s, gic_get_current_cpu(s), addr);
 597 }
 598
 599 static void gic_thiscpu_write(void *opaque, hwaddr addr,
 600                               uint64_t value, unsigned size)
 601 {
 602     GICState *s = (GICState *)opaque;
 603     gic_cpu_write(s, gic_get_current_cpu(s), addr, value);
 604 }
 605
 606 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
 607  * These just decode the opaque pointer into GICState* + cpu id.
 608  */
 609 static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr,
 610                                 unsigned size)
 611 {
 612     GICState **backref = (GICState **)opaque;
 613     GICState *s = *backref;
 614     int id = (backref - s->backref);
 615     return gic_cpu_read(s, id, addr);
 616 }
 617
 618 static void gic_do_cpu_write(void *opaque, hwaddr addr,
 619                              uint64_t value, unsigned size)
 620 {
 621     GICState **backref = (GICState **)opaque;
 622     GICState *s = *backref;
 623     int id = (backref - s->backref);
 624     gic_cpu_write(s, id, addr, value);
 625 }
 626
 627 static const MemoryRegionOps gic_thiscpu_ops = {
 628     .read = gic_thiscpu_read,
 629     .write = gic_thiscpu_write,
 630     .endianness = DEVICE_NATIVE_ENDIAN,
 631 };
 632
 633 static const MemoryRegionOps gic_cpu_ops = {
 634     .read = gic_do_cpu_read,
 635     .write = gic_do_cpu_write,
 636     .endianness = DEVICE_NATIVE_ENDIAN,
 637 };
 638
 639 void gic_init_irqs_and_distributor(GICState *s, int num_irq)
 640 {
 641     int i;
 642
 643     i = s->num_irq - GIC_INTERNAL;
 644     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
 645      * GPIO array layout is thus:
 646      *  [0..N-1] SPIs
 647      *  [N..N+31] PPIs for CPU 0
 648      *  [N+32..N+63] PPIs for CPU 1
 649      *   ...
 650      */
 651     if (s->revision != REV_NVIC) {
 652         i += (GIC_INTERNAL * s->num_cpu);
 653     }
 654     qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i);
 655     for (i = 0; i < NUM_CPU(s); i++) {
 656         sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
 657     }
 658     memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
 659 }
 660
 661 static int arm_gic_init(SysBusDevice *dev)
 662 {
 663     /* Device instance init function for the GIC sysbus device */
 664     int i;
 665     GICState *s = FROM_SYSBUS(GICState, dev);
 666     ARMGICClass *agc = ARM_GIC_GET_CLASS(s);
 667
 668     agc->parent_init(dev);
 669
 670     gic_init_irqs_and_distributor(s, s->num_irq);
 671
 672     /* Memory regions for the CPU interfaces (NVIC doesn't have these):
 673      * a region for "CPU interface for this core", then a region for
 674      * "CPU interface for core 0", "for core 1", ...
 675      * NB that the memory region size of 0x100 applies for the 11MPCore
 676      * and also cores following the GIC v1 spec (ie A9).
 677      * GIC v2 defines a larger memory region (0x1000) so this will need
 678      * to be extended when we implement A15.
 679      */
 680     memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s,
 681                           "gic_cpu", 0x100);
 682     for (i = 0; i < NUM_CPU(s); i++) {
 683         s->backref[i] = s;
 684         memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
 685                               "gic_cpu", 0x100);
 686     }
 687     /* Distributor */
 688     sysbus_init_mmio(dev, &s->iomem);
 689     /* cpu interfaces (one for "current cpu" plus one per cpu) */
 690     for (i = 0; i <= NUM_CPU(s); i++) {
 691         sysbus_init_mmio(dev, &s->cpuiomem[i]);
 692     }
 693     return 0;
 694 }
 695
 696 static void arm_gic_class_init(ObjectClass *klass, void *data)
 697 {
 698     DeviceClass *dc = DEVICE_CLASS(klass);
 699     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 700     ARMGICClass *agc = ARM_GIC_CLASS(klass);
 701     agc->parent_init = sbc->init;
 702     sbc->init = arm_gic_init;
 703     dc->no_user = 1;
 704 }
 705
 706 static TypeInfo arm_gic_info = {
 707     .name = TYPE_ARM_GIC,
 708     .parent = TYPE_ARM_GIC_COMMON,
 709     .instance_size = sizeof(GICState),
 710     .class_init = arm_gic_class_init,
 711     .class_size = sizeof(ARMGICClass),
 712 };
 713
 714 static void arm_gic_register_types(void)
 715 {
 716     type_register_static(&arm_gic_info);
 717 }
 718
 719 type_init(arm_gic_register_types)