hw/openrisc_sim.c

   1 /*
   2  * OpenRISC simulator for use as an IIS.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Feng Gao <gf91597@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw.h"
  22 #include "boards.h"
  23 #include "elf.h"
  24 #include "pc.h"
  25 #include "loader.h"
  26 #include "exec-memory.h"
  27 #include "sysemu.h"
  28 #include "sysbus.h"
  29 #include "qtest.h"
  30
  31 #define KERNEL_LOAD_ADDR 0x100
  32
  33 static void main_cpu_reset(void *opaque)
  34 {
  35     OpenRISCCPU *cpu = opaque;
  36
  37     cpu_reset(CPU(cpu));
  38 }
  39
  40 static void openrisc_sim_net_init(MemoryRegion *address_space,
  41                                   target_phys_addr_t base,
  42                                   target_phys_addr_t descriptors,
  43                                   qemu_irq irq, NICInfo *nd)
  44 {
  45     DeviceState *dev;
  46     SysBusDevice *s;
  47
  48     dev = qdev_create(NULL, "open_eth");
  49     qdev_set_nic_properties(dev, nd);
  50     qdev_init_nofail(dev);
  51
  52     s = sysbus_from_qdev(dev);
  53     sysbus_connect_irq(s, 0, irq);
  54     memory_region_add_subregion(address_space, base,
  55                                 sysbus_mmio_get_region(s, 0));
  56     memory_region_add_subregion(address_space, descriptors,
  57                                 sysbus_mmio_get_region(s, 1));
  58 }
  59
  60 static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
  61                                      const char *kernel_filename,
  62                                      OpenRISCCPU *cpu)
  63 {
  64     long kernel_size;
  65     uint64_t elf_entry;
  66     target_phys_addr_t entry;
  67
  68     if (kernel_filename && !qtest_enabled()) {
  69         kernel_size = load_elf(kernel_filename, NULL, NULL,
  70                                &elf_entry, NULL, NULL, 1, ELF_MACHINE, 1);
  71         entry = elf_entry;
  72         if (kernel_size < 0) {
  73             kernel_size = load_uimage(kernel_filename,
  74                                       &entry, NULL, NULL);
  75         }
  76         if (kernel_size < 0) {
  77             kernel_size = load_image_targphys(kernel_filename,
  78                                               KERNEL_LOAD_ADDR,
  79                                               ram_size - KERNEL_LOAD_ADDR);
  80             entry = KERNEL_LOAD_ADDR;
  81         }
  82
  83         if (kernel_size < 0) {
  84             qemu_log("QEMU: couldn't load the kernel '%s'\n",
  85                     kernel_filename);
  86             exit(1);
  87         }
  88     }
  89
  90     cpu->env.pc = entry;
  91 }
  92
  93 static void openrisc_sim_init(ram_addr_t ram_size,
  94                               const char *boot_device,
  95                               const char *kernel_filename,
  96                               const char *kernel_cmdline,
  97                               const char *initrd_filename,
  98                               const char *cpu_model)
  99 {
 100    OpenRISCCPU *cpu = NULL;
 101     MemoryRegion *ram;
 102     int n;
 103
 104     if (!cpu_model) {
 105         cpu_model = "or1200";
 106     }
 107
 108     for (n = 0; n < smp_cpus; n++) {
 109         cpu = cpu_openrisc_init(cpu_model);
 110         if (cpu == NULL) {
 111             qemu_log("Unable to find CPU defineition!\n");
 112             exit(1);
 113         }
 114         qemu_register_reset(main_cpu_reset, cpu);
 115         main_cpu_reset(cpu);
 116     }
 117
 118     ram = g_malloc(sizeof(*ram));
 119     memory_region_init_ram(ram, "openrisc.ram", ram_size);
 120     vmstate_register_ram_global(ram);
 121     memory_region_add_subregion(get_system_memory(), 0, ram);
 122
 123     cpu_openrisc_pic_init(cpu);
 124     cpu_openrisc_clock_init(cpu);
 125
 126     serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2],
 127                    115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
 128
 129     if (nd_table[0].used) {
 130         openrisc_sim_net_init(get_system_memory(), 0x92000000,
 131                               0x92000400, cpu->env.irq[4], nd_table);
 132     }
 133
 134     cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
 135 }
 136
 137 static QEMUMachine openrisc_sim_machine = {
 138     .name = "or32-sim",
 139     .desc = "or32 simulation",
 140     .init = openrisc_sim_init,
 141     .max_cpus = 1,
 142     .is_default = 1,
 143 };
 144
 145 static void openrisc_sim_machine_init(void)
 146 {
 147     qemu_register_machine(&openrisc_sim_machine);
 148 }
 149
 150 machine_init(openrisc_sim_machine_init);