hw/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "sysbus.h"
  21 #include "arm-misc.h"
  22 #include "devices.h"
  23 #include "loader.h"
  24 #include "net.h"
  25 #include "sysemu.h"
  26 #include "boards.h"
  27 #include "sysbus.h"
  28 #include "blockdev.h"
  29 #include "exec-memory.h"
  30
  31 #define SMP_BOOT_ADDR 0x100
  32 #define SMP_BOOT_REG  0x40
  33 #define GIC_BASE_ADDR 0xfff10000
  34
  35 #define NIRQ_GIC      160
  36
  37 /* Board init.  */
  38
  39 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  40 {
  41     int n;
  42     uint32_t smpboot[] = {
  43         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  44         0xe210000f, /* ands r0, r0, #0x0f */
  45         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  46         0xe0830200, /* add r0, r3, r0, lsl #4 */
  47         0xe59f2018, /* ldr r2, privbase */
  48         0xe3a01001, /* mov r1, #1 */
  49         0xe5821100, /* str r1, [r2, #256] */
  50         0xe320f003, /* wfi */
  51         0xe5901000, /* ldr     r1, [r0] */
  52         0xe1110001, /* tst     r1, r1 */
  53         0x0afffffb, /* beq     <wfi> */
  54         0xe12fff11, /* bx      r1 */
  55         GIC_BASE_ADDR      /* privbase: gic address.  */
  56     };
  57     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  58         smpboot[n] = tswap32(smpboot[n]);
  59     }
  60     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  61 }
  62
  63 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  64 {
  65     CPUARMState *env = &cpu->env;
  66
  67     switch (info->nb_cpus) {
  68     case 4:
  69         stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
  70     case 3:
  71         stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
  72     case 2:
  73         stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
  74         env->regs[15] = SMP_BOOT_ADDR;
  75         break;
  76     default:
  77         break;
  78     }
  79 }
  80
  81 #define NUM_REGS      0x200
  82 static void hb_regs_write(void *opaque, target_phys_addr_t offset,
  83                           uint64_t value, unsigned size)
  84 {
  85     uint32_t *regs = opaque;
  86
  87     if (offset == 0xf00) {
  88         if (value == 1 || value == 2) {
  89             qemu_system_reset_request();
  90         } else if (value == 3) {
  91             qemu_system_shutdown_request();
  92         }
  93     }
  94
  95     regs[offset/4] = value;
  96 }
  97
  98 static uint64_t hb_regs_read(void *opaque, target_phys_addr_t offset,
  99                              unsigned size)
 100 {
 101     uint32_t *regs = opaque;
 102     uint32_t value = regs[offset/4];
 103
 104     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 105         value |= 0x30000000;
 106     }
 107
 108     return value;
 109 }
 110
 111 static const MemoryRegionOps hb_mem_ops = {
 112     .read = hb_regs_read,
 113     .write = hb_regs_write,
 114     .endianness = DEVICE_NATIVE_ENDIAN,
 115 };
 116
 117 typedef struct {
 118     SysBusDevice busdev;
 119     MemoryRegion *iomem;
 120     uint32_t regs[NUM_REGS];
 121 } HighbankRegsState;
 122
 123 static VMStateDescription vmstate_highbank_regs = {
 124     .name = "highbank-regs",
 125     .version_id = 0,
 126     .minimum_version_id = 0,
 127     .minimum_version_id_old = 0,
 128     .fields = (VMStateField[]) {
 129         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 130         VMSTATE_END_OF_LIST(),
 131     },
 132 };
 133
 134 static void highbank_regs_reset(DeviceState *dev)
 135 {
 136     SysBusDevice *sys_dev = sysbus_from_qdev(dev);
 137     HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev);
 138
 139     s->regs[0x40] = 0x05F20121;
 140     s->regs[0x41] = 0x2;
 141     s->regs[0x42] = 0x05F30121;
 142     s->regs[0x43] = 0x05F40121;
 143 }
 144
 145 static int highbank_regs_init(SysBusDevice *dev)
 146 {
 147     HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);
 148
 149     s->iomem = g_new(MemoryRegion, 1);
 150     memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
 151                           0x1000);
 152     sysbus_init_mmio(dev, s->iomem);
 153
 154     return 0;
 155 }
 156
 157 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 158 {
 159     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 160     DeviceClass *dc = DEVICE_CLASS(klass);
 161
 162     sbc->init = highbank_regs_init;
 163     dc->desc = "Calxeda Highbank registers";
 164     dc->vmsd = &vmstate_highbank_regs;
 165     dc->reset = highbank_regs_reset;
 166 }
 167
 168 static TypeInfo highbank_regs_info = {
 169     .name          = "highbank-regs",
 170     .parent        = TYPE_SYS_BUS_DEVICE,
 171     .instance_size = sizeof(HighbankRegsState),
 172     .class_init    = highbank_regs_class_init,
 173 };
 174
 175 static void highbank_regs_register_types(void)
 176 {
 177     type_register_static(&highbank_regs_info);
 178 }
 179
 180 type_init(highbank_regs_register_types)
 181
 182 static struct arm_boot_info highbank_binfo;
 183
 184 /* ram_size must be set to match the upper bound of memory in the
 185  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 186  * normally 0xff900000 or -m 4089. When running this board on a
 187  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 188  * device tree and pass -m 2047 to QEMU.
 189  */
 190 static void highbank_init(ram_addr_t ram_size,
 191                      const char *boot_device,
 192                      const char *kernel_filename, const char *kernel_cmdline,
 193                      const char *initrd_filename, const char *cpu_model)
 194 {
 195     DeviceState *dev;
 196     SysBusDevice *busdev;
 197     qemu_irq *irqp;
 198     qemu_irq pic[128];
 199     int n;
 200     qemu_irq cpu_irq[4];
 201     MemoryRegion *sysram;
 202     MemoryRegion *dram;
 203     MemoryRegion *sysmem;
 204     char *sysboot_filename;
 205
 206     if (!cpu_model) {
 207         cpu_model = "cortex-a9";
 208     }
 209
 210     for (n = 0; n < smp_cpus; n++) {
 211         ARMCPU *cpu;
 212         cpu = cpu_arm_init(cpu_model);
 213         if (cpu == NULL) {
 214             fprintf(stderr, "Unable to find CPU definition\n");
 215             exit(1);
 216         }
 217
 218         /* This will become a QOM property eventually */
 219         cpu->reset_cbar = GIC_BASE_ADDR;
 220         irqp = arm_pic_init_cpu(cpu);
 221         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 222     }
 223
 224     sysmem = get_system_memory();
 225     dram = g_new(MemoryRegion, 1);
 226     memory_region_init_ram(dram, "highbank.dram", ram_size);
 227     /* SDRAM at address zero.  */
 228     memory_region_add_subregion(sysmem, 0, dram);
 229
 230     sysram = g_new(MemoryRegion, 1);
 231     memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
 232     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 233     if (bios_name != NULL) {
 234         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 235         if (sysboot_filename != NULL) {
 236             uint32_t filesize = get_image_size(sysboot_filename);
 237             if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
 238                 hw_error("Unable to load %s\n", bios_name);
 239             }
 240         } else {
 241            hw_error("Unable to find %s\n", bios_name);
 242         }
 243     }
 244
 245     dev = qdev_create(NULL, "a9mpcore_priv");
 246     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 247     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 248     qdev_init_nofail(dev);
 249     busdev = sysbus_from_qdev(dev);
 250     sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
 251     for (n = 0; n < smp_cpus; n++) {
 252         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 253     }
 254
 255     for (n = 0; n < 128; n++) {
 256         pic[n] = qdev_get_gpio_in(dev, n);
 257     }
 258
 259     dev = qdev_create(NULL, "l2x0");
 260     qdev_init_nofail(dev);
 261     busdev = sysbus_from_qdev(dev);
 262     sysbus_mmio_map(busdev, 0, 0xfff12000);
 263
 264     dev = qdev_create(NULL, "sp804");
 265     qdev_prop_set_uint32(dev, "freq0", 150000000);
 266     qdev_prop_set_uint32(dev, "freq1", 150000000);
 267     qdev_init_nofail(dev);
 268     busdev = sysbus_from_qdev(dev);
 269     sysbus_mmio_map(busdev, 0, 0xfff34000);
 270     sysbus_connect_irq(busdev, 0, pic[18]);
 271     sysbus_create_simple("pl011", 0xfff36000, pic[20]);
 272
 273     dev = qdev_create(NULL, "highbank-regs");
 274     qdev_init_nofail(dev);
 275     busdev = sysbus_from_qdev(dev);
 276     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 277
 278     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 279     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 280     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 281     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 282     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 283     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 284
 285     sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
 286
 287     if (nd_table[0].used) {
 288         qemu_check_nic_model(&nd_table[0], "xgmac");
 289         dev = qdev_create(NULL, "xgmac");
 290         qdev_set_nic_properties(dev, &nd_table[0]);
 291         qdev_init_nofail(dev);
 292         sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff50000);
 293         sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[77]);
 294         sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[78]);
 295         sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[79]);
 296
 297         qemu_check_nic_model(&nd_table[1], "xgmac");
 298         dev = qdev_create(NULL, "xgmac");
 299         qdev_set_nic_properties(dev, &nd_table[1]);
 300         qdev_init_nofail(dev);
 301         sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff51000);
 302         sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[80]);
 303         sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[81]);
 304         sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[82]);
 305     }
 306
 307     highbank_binfo.ram_size = ram_size;
 308     highbank_binfo.kernel_filename = kernel_filename;
 309     highbank_binfo.kernel_cmdline = kernel_cmdline;
 310     highbank_binfo.initrd_filename = initrd_filename;
 311     /* highbank requires a dtb in order to boot, and the dtb will override
 312      * the board ID. The following value is ignored, so set it to -1 to be
 313      * clear that the value is meaningless.
 314      */
 315     highbank_binfo.board_id = -1;
 316     highbank_binfo.nb_cpus = smp_cpus;
 317     highbank_binfo.loader_start = 0;
 318     highbank_binfo.write_secondary_boot = hb_write_secondary;
 319     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 320     arm_load_kernel(arm_env_get_cpu(first_cpu), &highbank_binfo);
 321 }
 322
 323 static QEMUMachine highbank_machine = {
 324     .name = "highbank",
 325     .desc = "Calxeda Highbank (ECX-1000)",
 326     .init = highbank_init,
 327     .use_scsi = 1,
 328     .max_cpus = 4,
 329 };
 330
 331 static void highbank_machine_init(void)
 332 {
 333     qemu_register_machine(&highbank_machine);
 334 }
 335
 336 machine_init(highbank_machine_init);