hw/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "sysbus.h"
  27 #include "esp.h"
  28 #include "trace.h"
  29 #include "qemu-log.h"
  30
  31 /*
  32  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  33  * also produced as NCR89C100. See
  34  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  35  * and
  36  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  37  */
  38
  39 static void esp_raise_irq(ESPState *s)
  40 {
  41     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
  42         s->rregs[ESP_RSTAT] |= STAT_INT;
  43         qemu_irq_raise(s->irq);
  44         trace_esp_raise_irq();
  45     }
  46 }
  47
  48 static void esp_lower_irq(ESPState *s)
  49 {
  50     if (s->rregs[ESP_RSTAT] & STAT_INT) {
  51         s->rregs[ESP_RSTAT] &= ~STAT_INT;
  52         qemu_irq_lower(s->irq);
  53         trace_esp_lower_irq();
  54     }
  55 }
  56
  57 void esp_dma_enable(ESPState *s, int irq, int level)
  58 {
  59     if (level) {
  60         s->dma_enabled = 1;
  61         trace_esp_dma_enable();
  62         if (s->dma_cb) {
  63             s->dma_cb(s);
  64             s->dma_cb = NULL;
  65         }
  66     } else {
  67         trace_esp_dma_disable();
  68         s->dma_enabled = 0;
  69     }
  70 }
  71
  72 void esp_request_cancelled(SCSIRequest *req)
  73 {
  74     ESPState *s = req->hba_private;
  75
  76     if (req == s->current_req) {
  77         scsi_req_unref(s->current_req);
  78         s->current_req = NULL;
  79         s->current_dev = NULL;
  80     }
  81 }
  82
  83 static uint32_t get_cmd(ESPState *s, uint8_t *buf)
  84 {
  85     uint32_t dmalen;
  86     int target;
  87
  88     target = s->wregs[ESP_WBUSID] & BUSID_DID;
  89     if (s->dma) {
  90         dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
  91         s->dma_memory_read(s->dma_opaque, buf, dmalen);
  92     } else {
  93         dmalen = s->ti_size;
  94         memcpy(buf, s->ti_buf, dmalen);
  95         buf[0] = buf[2] >> 5;
  96     }
  97     trace_esp_get_cmd(dmalen, target);
  98
  99     s->ti_size = 0;
 100     s->ti_rptr = 0;
 101     s->ti_wptr = 0;
 102
 103     if (s->current_req) {
 104         /* Started a new command before the old one finished.  Cancel it.  */
 105         scsi_req_cancel(s->current_req);
 106         s->async_len = 0;
 107     }
 108
 109     s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
 110     if (!s->current_dev) {
 111         // No such drive
 112         s->rregs[ESP_RSTAT] = 0;
 113         s->rregs[ESP_RINTR] = INTR_DC;
 114         s->rregs[ESP_RSEQ] = SEQ_0;
 115         esp_raise_irq(s);
 116         return 0;
 117     }
 118     return dmalen;
 119 }
 120
 121 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
 122 {
 123     int32_t datalen;
 124     int lun;
 125     SCSIDevice *current_lun;
 126
 127     trace_esp_do_busid_cmd(busid);
 128     lun = busid & 7;
 129     current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
 130     s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
 131     datalen = scsi_req_enqueue(s->current_req);
 132     s->ti_size = datalen;
 133     if (datalen != 0) {
 134         s->rregs[ESP_RSTAT] = STAT_TC;
 135         s->dma_left = 0;
 136         s->dma_counter = 0;
 137         if (datalen > 0) {
 138             s->rregs[ESP_RSTAT] |= STAT_DI;
 139         } else {
 140             s->rregs[ESP_RSTAT] |= STAT_DO;
 141         }
 142         scsi_req_continue(s->current_req);
 143     }
 144     s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 145     s->rregs[ESP_RSEQ] = SEQ_CD;
 146     esp_raise_irq(s);
 147 }
 148
 149 static void do_cmd(ESPState *s, uint8_t *buf)
 150 {
 151     uint8_t busid = buf[0];
 152
 153     do_busid_cmd(s, &buf[1], busid);
 154 }
 155
 156 static void handle_satn(ESPState *s)
 157 {
 158     uint8_t buf[32];
 159     int len;
 160
 161     if (s->dma && !s->dma_enabled) {
 162         s->dma_cb = handle_satn;
 163         return;
 164     }
 165     len = get_cmd(s, buf);
 166     if (len)
 167         do_cmd(s, buf);
 168 }
 169
 170 static void handle_s_without_atn(ESPState *s)
 171 {
 172     uint8_t buf[32];
 173     int len;
 174
 175     if (s->dma && !s->dma_enabled) {
 176         s->dma_cb = handle_s_without_atn;
 177         return;
 178     }
 179     len = get_cmd(s, buf);
 180     if (len) {
 181         do_busid_cmd(s, buf, 0);
 182     }
 183 }
 184
 185 static void handle_satn_stop(ESPState *s)
 186 {
 187     if (s->dma && !s->dma_enabled) {
 188         s->dma_cb = handle_satn_stop;
 189         return;
 190     }
 191     s->cmdlen = get_cmd(s, s->cmdbuf);
 192     if (s->cmdlen) {
 193         trace_esp_handle_satn_stop(s->cmdlen);
 194         s->do_cmd = 1;
 195         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 196         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 197         s->rregs[ESP_RSEQ] = SEQ_CD;
 198         esp_raise_irq(s);
 199     }
 200 }
 201
 202 static void write_response(ESPState *s)
 203 {
 204     trace_esp_write_response(s->status);
 205     s->ti_buf[0] = s->status;
 206     s->ti_buf[1] = 0;
 207     if (s->dma) {
 208         s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
 209         s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 210         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 211         s->rregs[ESP_RSEQ] = SEQ_CD;
 212     } else {
 213         s->ti_size = 2;
 214         s->ti_rptr = 0;
 215         s->ti_wptr = 0;
 216         s->rregs[ESP_RFLAGS] = 2;
 217     }
 218     esp_raise_irq(s);
 219 }
 220
 221 static void esp_dma_done(ESPState *s)
 222 {
 223     s->rregs[ESP_RSTAT] |= STAT_TC;
 224     s->rregs[ESP_RINTR] = INTR_BS;
 225     s->rregs[ESP_RSEQ] = 0;
 226     s->rregs[ESP_RFLAGS] = 0;
 227     s->rregs[ESP_TCLO] = 0;
 228     s->rregs[ESP_TCMID] = 0;
 229     esp_raise_irq(s);
 230 }
 231
 232 static void esp_do_dma(ESPState *s)
 233 {
 234     uint32_t len;
 235     int to_device;
 236
 237     to_device = (s->ti_size < 0);
 238     len = s->dma_left;
 239     if (s->do_cmd) {
 240         trace_esp_do_dma(s->cmdlen, len);
 241         s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 242         s->ti_size = 0;
 243         s->cmdlen = 0;
 244         s->do_cmd = 0;
 245         do_cmd(s, s->cmdbuf);
 246         return;
 247     }
 248     if (s->async_len == 0) {
 249         /* Defer until data is available.  */
 250         return;
 251     }
 252     if (len > s->async_len) {
 253         len = s->async_len;
 254     }
 255     if (to_device) {
 256         s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 257     } else {
 258         s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 259     }
 260     s->dma_left -= len;
 261     s->async_buf += len;
 262     s->async_len -= len;
 263     if (to_device)
 264         s->ti_size += len;
 265     else
 266         s->ti_size -= len;
 267     if (s->async_len == 0) {
 268         scsi_req_continue(s->current_req);
 269         /* If there is still data to be read from the device then
 270            complete the DMA operation immediately.  Otherwise defer
 271            until the scsi layer has completed.  */
 272         if (to_device || s->dma_left != 0 || s->ti_size == 0) {
 273             return;
 274         }
 275     }
 276
 277     /* Partially filled a scsi buffer. Complete immediately.  */
 278     esp_dma_done(s);
 279 }
 280
 281 void esp_command_complete(SCSIRequest *req, uint32_t status,
 282                                  size_t resid)
 283 {
 284     ESPState *s = req->hba_private;
 285
 286     trace_esp_command_complete();
 287     if (s->ti_size != 0) {
 288         trace_esp_command_complete_unexpected();
 289     }
 290     s->ti_size = 0;
 291     s->dma_left = 0;
 292     s->async_len = 0;
 293     if (status) {
 294         trace_esp_command_complete_fail();
 295     }
 296     s->status = status;
 297     s->rregs[ESP_RSTAT] = STAT_ST;
 298     esp_dma_done(s);
 299     if (s->current_req) {
 300         scsi_req_unref(s->current_req);
 301         s->current_req = NULL;
 302         s->current_dev = NULL;
 303     }
 304 }
 305
 306 void esp_transfer_data(SCSIRequest *req, uint32_t len)
 307 {
 308     ESPState *s = req->hba_private;
 309
 310     trace_esp_transfer_data(s->dma_left, s->ti_size);
 311     s->async_len = len;
 312     s->async_buf = scsi_req_get_buf(req);
 313     if (s->dma_left) {
 314         esp_do_dma(s);
 315     } else if (s->dma_counter != 0 && s->ti_size <= 0) {
 316         /* If this was the last part of a DMA transfer then the
 317            completion interrupt is deferred to here.  */
 318         esp_dma_done(s);
 319     }
 320 }
 321
 322 static void handle_ti(ESPState *s)
 323 {
 324     uint32_t dmalen, minlen;
 325
 326     if (s->dma && !s->dma_enabled) {
 327         s->dma_cb = handle_ti;
 328         return;
 329     }
 330
 331     dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 332     if (dmalen==0) {
 333       dmalen=0x10000;
 334     }
 335     s->dma_counter = dmalen;
 336
 337     if (s->do_cmd)
 338         minlen = (dmalen < 32) ? dmalen : 32;
 339     else if (s->ti_size < 0)
 340         minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 341     else
 342         minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
 343     trace_esp_handle_ti(minlen);
 344     if (s->dma) {
 345         s->dma_left = minlen;
 346         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 347         esp_do_dma(s);
 348     } else if (s->do_cmd) {
 349         trace_esp_handle_ti_cmd(s->cmdlen);
 350         s->ti_size = 0;
 351         s->cmdlen = 0;
 352         s->do_cmd = 0;
 353         do_cmd(s, s->cmdbuf);
 354         return;
 355     }
 356 }
 357
 358 void esp_hard_reset(ESPState *s)
 359 {
 360     memset(s->rregs, 0, ESP_REGS);
 361     memset(s->wregs, 0, ESP_REGS);
 362     s->rregs[ESP_TCHI] = s->chip_id;
 363     s->ti_size = 0;
 364     s->ti_rptr = 0;
 365     s->ti_wptr = 0;
 366     s->dma = 0;
 367     s->do_cmd = 0;
 368     s->dma_cb = NULL;
 369
 370     s->rregs[ESP_CFG1] = 7;
 371 }
 372
 373 static void esp_soft_reset(ESPState *s)
 374 {
 375     qemu_irq_lower(s->irq);
 376     esp_hard_reset(s);
 377 }
 378
 379 static void parent_esp_reset(ESPState *s, int irq, int level)
 380 {
 381     if (level) {
 382         esp_soft_reset(s);
 383     }
 384 }
 385
 386 uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
 387 {
 388     uint32_t old_val;
 389
 390     trace_esp_mem_readb(saddr, s->rregs[saddr]);
 391     switch (saddr) {
 392     case ESP_FIFO:
 393         if (s->ti_size > 0) {
 394             s->ti_size--;
 395             if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 396                 /* Data out.  */
 397                 qemu_log_mask(LOG_UNIMP,
 398                               "esp: PIO data read not implemented\n");
 399                 s->rregs[ESP_FIFO] = 0;
 400             } else {
 401                 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
 402             }
 403             esp_raise_irq(s);
 404         }
 405         if (s->ti_size == 0) {
 406             s->ti_rptr = 0;
 407             s->ti_wptr = 0;
 408         }
 409         break;
 410     case ESP_RINTR:
 411         /* Clear sequence step, interrupt register and all status bits
 412            except TC */
 413         old_val = s->rregs[ESP_RINTR];
 414         s->rregs[ESP_RINTR] = 0;
 415         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 416         s->rregs[ESP_RSEQ] = SEQ_CD;
 417         esp_lower_irq(s);
 418
 419         return old_val;
 420     default:
 421         break;
 422     }
 423     return s->rregs[saddr];
 424 }
 425
 426 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 427 {
 428     trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
 429     switch (saddr) {
 430     case ESP_TCLO:
 431     case ESP_TCMID:
 432         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 433         break;
 434     case ESP_FIFO:
 435         if (s->do_cmd) {
 436             s->cmdbuf[s->cmdlen++] = val & 0xff;
 437         } else if (s->ti_size == TI_BUFSZ - 1) {
 438             trace_esp_error_fifo_overrun();
 439         } else {
 440             s->ti_size++;
 441             s->ti_buf[s->ti_wptr++] = val & 0xff;
 442         }
 443         break;
 444     case ESP_CMD:
 445         s->rregs[saddr] = val;
 446         if (val & CMD_DMA) {
 447             s->dma = 1;
 448             /* Reload DMA counter.  */
 449             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
 450             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
 451         } else {
 452             s->dma = 0;
 453         }
 454         switch(val & CMD_CMD) {
 455         case CMD_NOP:
 456             trace_esp_mem_writeb_cmd_nop(val);
 457             break;
 458         case CMD_FLUSH:
 459             trace_esp_mem_writeb_cmd_flush(val);
 460             //s->ti_size = 0;
 461             s->rregs[ESP_RINTR] = INTR_FC;
 462             s->rregs[ESP_RSEQ] = 0;
 463             s->rregs[ESP_RFLAGS] = 0;
 464             break;
 465         case CMD_RESET:
 466             trace_esp_mem_writeb_cmd_reset(val);
 467             esp_soft_reset(s);
 468             break;
 469         case CMD_BUSRESET:
 470             trace_esp_mem_writeb_cmd_bus_reset(val);
 471             s->rregs[ESP_RINTR] = INTR_RST;
 472             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 473                 esp_raise_irq(s);
 474             }
 475             break;
 476         case CMD_TI:
 477             handle_ti(s);
 478             break;
 479         case CMD_ICCS:
 480             trace_esp_mem_writeb_cmd_iccs(val);
 481             write_response(s);
 482             s->rregs[ESP_RINTR] = INTR_FC;
 483             s->rregs[ESP_RSTAT] |= STAT_MI;
 484             break;
 485         case CMD_MSGACC:
 486             trace_esp_mem_writeb_cmd_msgacc(val);
 487             s->rregs[ESP_RINTR] = INTR_DC;
 488             s->rregs[ESP_RSEQ] = 0;
 489             s->rregs[ESP_RFLAGS] = 0;
 490             esp_raise_irq(s);
 491             break;
 492         case CMD_PAD:
 493             trace_esp_mem_writeb_cmd_pad(val);
 494             s->rregs[ESP_RSTAT] = STAT_TC;
 495             s->rregs[ESP_RINTR] = INTR_FC;
 496             s->rregs[ESP_RSEQ] = 0;
 497             break;
 498         case CMD_SATN:
 499             trace_esp_mem_writeb_cmd_satn(val);
 500             break;
 501         case CMD_RSTATN:
 502             trace_esp_mem_writeb_cmd_rstatn(val);
 503             break;
 504         case CMD_SEL:
 505             trace_esp_mem_writeb_cmd_sel(val);
 506             handle_s_without_atn(s);
 507             break;
 508         case CMD_SELATN:
 509             trace_esp_mem_writeb_cmd_selatn(val);
 510             handle_satn(s);
 511             break;
 512         case CMD_SELATNS:
 513             trace_esp_mem_writeb_cmd_selatns(val);
 514             handle_satn_stop(s);
 515             break;
 516         case CMD_ENSEL:
 517             trace_esp_mem_writeb_cmd_ensel(val);
 518             s->rregs[ESP_RINTR] = 0;
 519             break;
 520         case CMD_DISSEL:
 521             trace_esp_mem_writeb_cmd_dissel(val);
 522             s->rregs[ESP_RINTR] = 0;
 523             esp_raise_irq(s);
 524             break;
 525         default:
 526             trace_esp_error_unhandled_command(val);
 527             break;
 528         }
 529         break;
 530     case ESP_WBUSID ... ESP_WSYNO:
 531         break;
 532     case ESP_CFG1:
 533         s->rregs[saddr] = val;
 534         break;
 535     case ESP_WCCF ... ESP_WTEST:
 536         break;
 537     case ESP_CFG2 ... ESP_RES4:
 538         s->rregs[saddr] = val;
 539         break;
 540     default:
 541         trace_esp_error_invalid_write(val, saddr);
 542         return;
 543     }
 544     s->wregs[saddr] = val;
 545 }
 546
 547 static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
 548                             unsigned size, bool is_write)
 549 {
 550     return (size == 1) || (is_write && size == 4);
 551 }
 552
 553 const VMStateDescription vmstate_esp = {
 554     .name ="esp",
 555     .version_id = 3,
 556     .minimum_version_id = 3,
 557     .minimum_version_id_old = 3,
 558     .fields      = (VMStateField []) {
 559         VMSTATE_BUFFER(rregs, ESPState),
 560         VMSTATE_BUFFER(wregs, ESPState),
 561         VMSTATE_INT32(ti_size, ESPState),
 562         VMSTATE_UINT32(ti_rptr, ESPState),
 563         VMSTATE_UINT32(ti_wptr, ESPState),
 564         VMSTATE_BUFFER(ti_buf, ESPState),
 565         VMSTATE_UINT32(status, ESPState),
 566         VMSTATE_UINT32(dma, ESPState),
 567         VMSTATE_BUFFER(cmdbuf, ESPState),
 568         VMSTATE_UINT32(cmdlen, ESPState),
 569         VMSTATE_UINT32(do_cmd, ESPState),
 570         VMSTATE_UINT32(dma_left, ESPState),
 571         VMSTATE_END_OF_LIST()
 572     }
 573 };
 574
 575 typedef struct {
 576     SysBusDevice busdev;
 577     MemoryRegion iomem;
 578     uint32_t it_shift;
 579     ESPState esp;
 580 } SysBusESPState;
 581
 582 static void sysbus_esp_mem_write(void *opaque, target_phys_addr_t addr,
 583                                  uint64_t val, unsigned int size)
 584 {
 585     SysBusESPState *sysbus = opaque;
 586     uint32_t saddr;
 587
 588     saddr = addr >> sysbus->it_shift;
 589     esp_reg_write(&sysbus->esp, saddr, val);
 590 }
 591
 592 static uint64_t sysbus_esp_mem_read(void *opaque, target_phys_addr_t addr,
 593                                     unsigned int size)
 594 {
 595     SysBusESPState *sysbus = opaque;
 596     uint32_t saddr;
 597
 598     saddr = addr >> sysbus->it_shift;
 599     return esp_reg_read(&sysbus->esp, saddr);
 600 }
 601
 602 static const MemoryRegionOps sysbus_esp_mem_ops = {
 603     .read = sysbus_esp_mem_read,
 604     .write = sysbus_esp_mem_write,
 605     .endianness = DEVICE_NATIVE_ENDIAN,
 606     .valid.accepts = esp_mem_accepts,
 607 };
 608
 609 void esp_init(target_phys_addr_t espaddr, int it_shift,
 610               ESPDMAMemoryReadWriteFunc dma_memory_read,
 611               ESPDMAMemoryReadWriteFunc dma_memory_write,
 612               void *dma_opaque, qemu_irq irq, qemu_irq *reset,
 613               qemu_irq *dma_enable)
 614 {
 615     DeviceState *dev;
 616     SysBusDevice *s;
 617     SysBusESPState *sysbus;
 618     ESPState *esp;
 619
 620     dev = qdev_create(NULL, "esp");
 621     sysbus = DO_UPCAST(SysBusESPState, busdev.qdev, dev);
 622     esp = &sysbus->esp;
 623     esp->dma_memory_read = dma_memory_read;
 624     esp->dma_memory_write = dma_memory_write;
 625     esp->dma_opaque = dma_opaque;
 626     sysbus->it_shift = it_shift;
 627     /* XXX for now until rc4030 has been changed to use DMA enable signal */
 628     esp->dma_enabled = 1;
 629     qdev_init_nofail(dev);
 630     s = sysbus_from_qdev(dev);
 631     sysbus_connect_irq(s, 0, irq);
 632     sysbus_mmio_map(s, 0, espaddr);
 633     *reset = qdev_get_gpio_in(dev, 0);
 634     *dma_enable = qdev_get_gpio_in(dev, 1);
 635 }
 636
 637 static const struct SCSIBusInfo esp_scsi_info = {
 638     .tcq = false,
 639     .max_target = ESP_MAX_DEVS,
 640     .max_lun = 7,
 641
 642     .transfer_data = esp_transfer_data,
 643     .complete = esp_command_complete,
 644     .cancel = esp_request_cancelled
 645 };
 646
 647 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
 648 {
 649     DeviceState *d = opaque;
 650     SysBusESPState *sysbus = container_of(d, SysBusESPState, busdev.qdev);
 651     ESPState *s = &sysbus->esp;
 652
 653     switch (irq) {
 654     case 0:
 655         parent_esp_reset(s, irq, level);
 656         break;
 657     case 1:
 658         esp_dma_enable(opaque, irq, level);
 659         break;
 660     }
 661 }
 662
 663 static int sysbus_esp_init(SysBusDevice *dev)
 664 {
 665     SysBusESPState *sysbus = FROM_SYSBUS(SysBusESPState, dev);
 666     ESPState *s = &sysbus->esp;
 667
 668     sysbus_init_irq(dev, &s->irq);
 669     assert(sysbus->it_shift != -1);
 670
 671     s->chip_id = TCHI_FAS100A;
 672     memory_region_init_io(&sysbus->iomem, &sysbus_esp_mem_ops, sysbus,
 673                           "esp", ESP_REGS << sysbus->it_shift);
 674     sysbus_init_mmio(dev, &sysbus->iomem);
 675
 676     qdev_init_gpio_in(&dev->qdev, sysbus_esp_gpio_demux, 2);
 677
 678     scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info);
 679     return scsi_bus_legacy_handle_cmdline(&s->bus);
 680 }
 681
 682 static void sysbus_esp_hard_reset(DeviceState *dev)
 683 {
 684     SysBusESPState *sysbus = DO_UPCAST(SysBusESPState, busdev.qdev, dev);
 685     esp_hard_reset(&sysbus->esp);
 686 }
 687
 688 static const VMStateDescription vmstate_sysbus_esp_scsi = {
 689     .name = "sysbusespscsi",
 690     .version_id = 0,
 691     .minimum_version_id = 0,
 692     .minimum_version_id_old = 0,
 693     .fields = (VMStateField[]) {
 694         VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
 695         VMSTATE_END_OF_LIST()
 696     }
 697 };
 698
 699 static void sysbus_esp_class_init(ObjectClass *klass, void *data)
 700 {
 701     DeviceClass *dc = DEVICE_CLASS(klass);
 702     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 703
 704     k->init = sysbus_esp_init;
 705     dc->reset = sysbus_esp_hard_reset;
 706     dc->vmsd = &vmstate_sysbus_esp_scsi;
 707 }
 708
 709 static const TypeInfo sysbus_esp_info = {
 710     .name          = "esp",
 711     .parent        = TYPE_SYS_BUS_DEVICE,
 712     .instance_size = sizeof(SysBusESPState),
 713     .class_init    = sysbus_esp_class_init,
 714 };
 715
 716 static void esp_register_types(void)
 717 {
 718     type_register_static(&sysbus_esp_info);
 719 }
 720
 721 type_init(esp_register_types)