target-microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "cpu.h"
  26 #include "qemu-common.h"
  27 #include "hw/qdev-properties.h"
  28 #include "migration/vmstate.h"
  29
  30 static const struct {
  31     const char *name;
  32     uint8_t version_id;
  33 } mb_cpu_lookup[] = {
  34     /* These key value are as per MBV field in PVR0 */
  35     {"5.00.a", 0x01},
  36     {"5.00.b", 0x02},
  37     {"5.00.c", 0x03},
  38     {"6.00.a", 0x04},
  39     {"6.00.b", 0x06},
  40     {"7.00.a", 0x05},
  41     {"7.00.b", 0x07},
  42     {"7.10.a", 0x08},
  43     {"7.10.b", 0x09},
  44     {"7.10.c", 0x0a},
  45     {"7.10.d", 0x0b},
  46     {"7.20.a", 0x0c},
  47     {"7.20.b", 0x0d},
  48     {"7.20.c", 0x0e},
  49     {"7.20.d", 0x0f},
  50     {"7.30.a", 0x10},
  51     {"7.30.b", 0x11},
  52     {"8.00.a", 0x12},
  53     {"8.00.b", 0x13},
  54     {"8.10.a", 0x14},
  55     {"8.20.a", 0x15},
  56     {"8.20.b", 0x16},
  57     {"8.30.a", 0x17},
  58     {"8.40.a", 0x18},
  59     {"8.40.b", 0x19},
  60     {"8.50.a", 0x1A},
  61     {"9.0", 0x1B},
  62     {"9.1", 0x1D},
  63     {"9.2", 0x1F},
  64     {"9.3", 0x20},
  65     {NULL, 0},
  66 };
  67
  68 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  69 {
  70     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  71
  72     cpu->env.sregs[SR_PC] = value;
  73 }
  74
  75 static bool mb_cpu_has_work(CPUState *cs)
  76 {
  77     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  78 }
  79
  80 #ifndef CONFIG_USER_ONLY
  81 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
  82 {
  83     MicroBlazeCPU *cpu = opaque;
  84     CPUState *cs = CPU(cpu);
  85     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
  86
  87     if (level) {
  88         cpu_interrupt(cs, type);
  89     } else {
  90         cpu_reset_interrupt(cs, type);
  91     }
  92 }
  93 #endif
  94
  95 /* CPUClass::reset() */
  96 static void mb_cpu_reset(CPUState *s)
  97 {
  98     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
  99     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
 100     CPUMBState *env = &cpu->env;
 101
 102     mcc->parent_reset(s);
 103
 104     memset(env, 0, offsetof(CPUMBState, pvr));
 105     env->res_addr = RES_ADDR_NONE;
 106     tlb_flush(s, 1);
 107
 108     /* Disable stack protector.  */
 109     env->shr = ~0;
 110
 111     env->sregs[SR_PC] = cpu->cfg.base_vectors;
 112
 113 #if defined(CONFIG_USER_ONLY)
 114     /* start in user mode with interrupts enabled.  */
 115     env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
 116 #else
 117     env->sregs[SR_MSR] = 0;
 118     mmu_init(&env->mmu);
 119     env->mmu.c_mmu = 3;
 120     env->mmu.c_mmu_tlb_access = 3;
 121     env->mmu.c_mmu_zones = 16;
 122 #endif
 123 }
 124
 125 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
 126 {
 127     info->mach = bfd_arch_microblaze;
 128     info->print_insn = print_insn_microblaze;
 129 }
 130
 131 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 132 {
 133     CPUState *cs = CPU(dev);
 134     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 135     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 136     CPUMBState *env = &cpu->env;
 137     uint8_t version_code = 0;
 138     int i = 0;
 139
 140     qemu_init_vcpu(cs);
 141
 142     env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
 143                        | PVR0_USE_DIV_MASK \
 144                        | PVR0_USE_HW_MUL_MASK \
 145                        | PVR0_USE_EXC_MASK \
 146                        | PVR0_USE_ICACHE_MASK \
 147                        | PVR0_USE_DCACHE_MASK \
 148                        | (0xb << 8);
 149     env->pvr.regs[2] = PVR2_D_OPB_MASK \
 150                         | PVR2_D_LMB_MASK \
 151                         | PVR2_I_OPB_MASK \
 152                         | PVR2_I_LMB_MASK \
 153                         | PVR2_USE_MSR_INSTR \
 154                         | PVR2_USE_PCMP_INSTR \
 155                         | PVR2_USE_BARREL_MASK \
 156                         | PVR2_USE_DIV_MASK \
 157                         | PVR2_USE_HW_MUL_MASK \
 158                         | PVR2_USE_MUL64_MASK \
 159                         | PVR2_FPU_EXC_MASK \
 160                         | 0;
 161
 162     for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
 163         if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
 164             version_code = mb_cpu_lookup[i].version_id;
 165             break;
 166         }
 167     }
 168
 169     if (!version_code) {
 170         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
 171     }
 172
 173     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
 174                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
 175                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
 176                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
 177                         (version_code << 16) |
 178                         (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
 179
 180     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
 181                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
 182
 183     env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
 184                                         PVR5_DCACHE_WRITEBACK_MASK : 0;
 185
 186     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
 187     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
 188
 189     mcc->parent_realize(dev, errp);
 190 }
 191
 192 static void mb_cpu_initfn(Object *obj)
 193 {
 194     CPUState *cs = CPU(obj);
 195     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 196     CPUMBState *env = &cpu->env;
 197     static bool tcg_initialized;
 198
 199     cs->env_ptr = env;
 200     cpu_exec_init(cs, &error_abort);
 201
 202     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 203
 204 #ifndef CONFIG_USER_ONLY
 205     /* Inbound IRQ and FIR lines */
 206     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 207 #endif
 208
 209     if (tcg_enabled() && !tcg_initialized) {
 210         tcg_initialized = true;
 211         mb_tcg_init();
 212     }
 213 }
 214
 215 static const VMStateDescription vmstate_mb_cpu = {
 216     .name = "cpu",
 217     .unmigratable = 1,
 218 };
 219
 220 static Property mb_properties[] = {
 221     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 222     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
 223                      false),
 224     /* If use-fpu > 0 - FPU is enabled
 225      * If use-fpu = 2 - Floating point conversion and square root instructions
 226      *                  are enabled
 227      */
 228     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
 229     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
 230     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
 231                      false),
 232     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
 233     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
 234     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
 235     DEFINE_PROP_END_OF_LIST(),
 236 };
 237
 238 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 239 {
 240     DeviceClass *dc = DEVICE_CLASS(oc);
 241     CPUClass *cc = CPU_CLASS(oc);
 242     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 243
 244     mcc->parent_realize = dc->realize;
 245     dc->realize = mb_cpu_realizefn;
 246
 247     mcc->parent_reset = cc->reset;
 248     cc->reset = mb_cpu_reset;
 249
 250     cc->has_work = mb_cpu_has_work;
 251     cc->do_interrupt = mb_cpu_do_interrupt;
 252     cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
 253     cc->dump_state = mb_cpu_dump_state;
 254     cc->set_pc = mb_cpu_set_pc;
 255     cc->gdb_read_register = mb_cpu_gdb_read_register;
 256     cc->gdb_write_register = mb_cpu_gdb_write_register;
 257 #ifdef CONFIG_USER_ONLY
 258     cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
 259 #else
 260     cc->do_unassigned_access = mb_cpu_unassigned_access;
 261     cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
 262 #endif
 263     dc->vmsd = &vmstate_mb_cpu;
 264     dc->props = mb_properties;
 265     cc->gdb_num_core_regs = 32 + 5;
 266
 267     cc->disas_set_info = mb_disas_set_info;
 268
 269     /*
 270      * Reason: mb_cpu_initfn() calls cpu_exec_init(), which saves the
 271      * object in cpus -> dangling pointer after final object_unref().
 272      */
 273     dc->cannot_destroy_with_object_finalize_yet = true;
 274 }
 275
 276 static const TypeInfo mb_cpu_type_info = {
 277     .name = TYPE_MICROBLAZE_CPU,
 278     .parent = TYPE_CPU,
 279     .instance_size = sizeof(MicroBlazeCPU),
 280     .instance_init = mb_cpu_initfn,
 281     .class_size = sizeof(MicroBlazeCPUClass),
 282     .class_init = mb_cpu_class_init,
 283 };
 284
 285 static void mb_cpu_register_types(void)
 286 {
 287     type_register_static(&mb_cpu_type_info);
 288 }
 289
 290 type_init(mb_cpu_register_types)