cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #include "exec.h"
  22 #include "disas.h"
  23
  24 int tb_invalidated_flag;
  25
  26 //#define DEBUG_EXEC
  27 //#define DEBUG_SIGNAL
  28
  29 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
  30 /* XXX: unify with i386 target */
  31 void cpu_loop_exit(void)
  32 {
  33     longjmp(env->jmp_env, 1);
  34 }
  35 #endif
  36
  37 /* main execution loop */
  38
  39 int cpu_exec(CPUState *env1)
  40 {
  41     int saved_T0, saved_T1, saved_T2;
  42     CPUState *saved_env;
  43 #ifdef reg_EAX
  44     int saved_EAX;
  45 #endif
  46 #ifdef reg_ECX
  47     int saved_ECX;
  48 #endif
  49 #ifdef reg_EDX
  50     int saved_EDX;
  51 #endif
  52 #ifdef reg_EBX
  53     int saved_EBX;
  54 #endif
  55 #ifdef reg_ESP
  56     int saved_ESP;
  57 #endif
  58 #ifdef reg_EBP
  59     int saved_EBP;
  60 #endif
  61 #ifdef reg_ESI
  62     int saved_ESI;
  63 #endif
  64 #ifdef reg_EDI
  65     int saved_EDI;
  66 #endif
  67 #ifdef __sparc__
  68     int saved_i7, tmp_T0;
  69 #endif
  70     int code_gen_size, ret, interrupt_request;
  71     void (*gen_func)(void);
  72     TranslationBlock *tb, **ptb;
  73     uint8_t *tc_ptr, *cs_base, *pc;
  74     unsigned int flags;
  75
  76     /* first we save global registers */
  77     saved_T0 = T0;
  78     saved_T1 = T1;
  79     saved_T2 = T2;
  80     saved_env = env;
  81     env = env1;
  82 #ifdef __sparc__
  83     /* we also save i7 because longjmp may not restore it */
  84     asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
  85 #endif
  86
  87 #if defined(TARGET_I386)
  88 #ifdef reg_EAX
  89     saved_EAX = EAX;
  90     EAX = env->regs[R_EAX];
  91 #endif
  92 #ifdef reg_ECX
  93     saved_ECX = ECX;
  94     ECX = env->regs[R_ECX];
  95 #endif
  96 #ifdef reg_EDX
  97     saved_EDX = EDX;
  98     EDX = env->regs[R_EDX];
  99 #endif
 100 #ifdef reg_EBX
 101     saved_EBX = EBX;
 102     EBX = env->regs[R_EBX];
 103 #endif
 104 #ifdef reg_ESP
 105     saved_ESP = ESP;
 106     ESP = env->regs[R_ESP];
 107 #endif
 108 #ifdef reg_EBP
 109     saved_EBP = EBP;
 110     EBP = env->regs[R_EBP];
 111 #endif
 112 #ifdef reg_ESI
 113     saved_ESI = ESI;
 114     ESI = env->regs[R_ESI];
 115 #endif
 116 #ifdef reg_EDI
 117     saved_EDI = EDI;
 118     EDI = env->regs[R_EDI];
 119 #endif
 120
 121     /* put eflags in CPU temporary format */
 122     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 123     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 124     CC_OP = CC_OP_EFLAGS;
 125     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 126 #elif defined(TARGET_ARM)
 127     {
 128         unsigned int psr;
 129         psr = env->cpsr;
 130         env->CF = (psr >> 29) & 1;
 131         env->NZF = (psr & 0xc0000000) ^ 0x40000000;
 132         env->VF = (psr << 3) & 0x80000000;
 133         env->cpsr = psr & ~0xf0000000;
 134     }
 135 #elif defined(TARGET_SPARC)
 136 #elif defined(TARGET_PPC)
 137 #else
 138 #error unsupported target CPU
 139 #endif
 140     env->exception_index = -1;
 141
 142     /* prepare setjmp context for exception handling */
 143     for(;;) {
 144         if (setjmp(env->jmp_env) == 0) {
 145             env->current_tb = NULL;
 146             /* if an exception is pending, we execute it here */
 147             if (env->exception_index >= 0) {
 148                 if (env->exception_index >= EXCP_INTERRUPT) {
 149                     /* exit request from the cpu execution loop */
 150                     ret = env->exception_index;
 151                     break;
 152                 } else if (env->user_mode_only) {
 153                     /* if user mode only, we simulate a fake exception
 154                        which will be hanlded outside the cpu execution
 155                        loop */
 156 #if defined(TARGET_I386)
 157                     do_interrupt_user(env->exception_index,
 158                                       env->exception_is_int,
 159                                       env->error_code,
 160                                       env->exception_next_eip);
 161 #endif
 162                     ret = env->exception_index;
 163                     break;
 164                 } else {
 165 #if defined(TARGET_I386)
 166                     /* simulate a real cpu exception. On i386, it can
 167                        trigger new exceptions, but we do not handle
 168                        double or triple faults yet. */
 169                     do_interrupt(env->exception_index,
 170                                  env->exception_is_int,
 171                                  env->error_code,
 172                                  env->exception_next_eip, 0);
 173 #elif defined(TARGET_PPC)
 174                     do_interrupt(env);
 175 #endif
 176                 }
 177                 env->exception_index = -1;
 178             }
 179             T0 = 0; /* force lookup of first TB */
 180             for(;;) {
 181 #ifdef __sparc__
 182                 /* g1 can be modified by some libc? functions */
 183                 tmp_T0 = T0;
 184 #endif
 185                 interrupt_request = env->interrupt_request;
 186                 if (__builtin_expect(interrupt_request, 0)) {
 187 #if defined(TARGET_I386)
 188                     /* if hardware interrupt pending, we execute it */
 189                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 190                         (env->eflags & IF_MASK) &&
 191                         !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 192                         int intno;
 193                         intno = cpu_x86_get_pic_interrupt(env);
 194                         if (loglevel & CPU_LOG_TB_IN_ASM) {
 195                             fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
 196                         }
 197                         do_interrupt(intno, 0, 0, 0, 1);
 198                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 199                         /* ensure that no TB jump will be modified as
 200                            the program flow was changed */
 201 #ifdef __sparc__
 202                         tmp_T0 = 0;
 203 #else
 204                         T0 = 0;
 205 #endif
 206                     }
 207 #elif defined(TARGET_PPC)
 208                     if ((interrupt_request & CPU_INTERRUPT_HARD)) {
 209                         do_queue_exception(EXCP_EXTERNAL);
 210                         if (check_exception_state(env))
 211                             do_interrupt(env);
 212                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 213                     }
 214 #endif
 215                     if (interrupt_request & CPU_INTERRUPT_EXITTB) {
 216                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 217                         /* ensure that no TB jump will be modified as
 218                            the program flow was changed */
 219 #ifdef __sparc__
 220                         tmp_T0 = 0;
 221 #else
 222                         T0 = 0;
 223 #endif
 224                     }
 225                     if (interrupt_request & CPU_INTERRUPT_EXIT) {
 226                         env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
 227                         env->exception_index = EXCP_INTERRUPT;
 228                         cpu_loop_exit();
 229                     }
 230                 }
 231 #ifdef DEBUG_EXEC
 232                 if (loglevel & CPU_LOG_EXEC) {
 233 #if defined(TARGET_I386)
 234                     /* restore flags in standard format */
 235                     env->regs[R_EAX] = EAX;
 236                     env->regs[R_EBX] = EBX;
 237                     env->regs[R_ECX] = ECX;
 238                     env->regs[R_EDX] = EDX;
 239                     env->regs[R_ESI] = ESI;
 240                     env->regs[R_EDI] = EDI;
 241                     env->regs[R_EBP] = EBP;
 242                     env->regs[R_ESP] = ESP;
 243                     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 244                     cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
 245                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 246 #elif defined(TARGET_ARM)
 247                     env->cpsr = compute_cpsr();
 248                     cpu_arm_dump_state(env, logfile, 0);
 249                     env->cpsr &= ~0xf0000000;
 250 #elif defined(TARGET_SPARC)
 251                     cpu_sparc_dump_state (env, logfile, 0);
 252 #elif defined(TARGET_PPC)
 253                     cpu_ppc_dump_state(env, logfile, 0);
 254 #else
 255 #error unsupported target CPU
 256 #endif
 257                 }
 258 #endif
 259                 /* we record a subset of the CPU state. It will
 260                    always be the same before a given translated block
 261                    is executed. */
 262 #if defined(TARGET_I386)
 263                 flags = env->hflags;
 264                 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
 265                 cs_base = env->segs[R_CS].base;
 266                 pc = cs_base + env->eip;
 267 #elif defined(TARGET_ARM)
 268                 flags = 0;
 269                 cs_base = 0;
 270                 pc = (uint8_t *)env->regs[15];
 271 #elif defined(TARGET_SPARC)
 272                 flags = 0;
 273                 cs_base = (uint8_t *)env->npc;
 274                 pc = (uint8_t *) env->pc;
 275 #elif defined(TARGET_PPC)
 276                 flags = 0;
 277                 cs_base = 0;
 278                 pc = (uint8_t *)env->nip;
 279 #else
 280 #error unsupported CPU
 281 #endif
 282                 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
 283                              flags);
 284                 if (!tb) {
 285                     TranslationBlock **ptb1;
 286                     unsigned int h;
 287                     target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
 288
 289
 290                     spin_lock(&tb_lock);
 291
 292                     tb_invalidated_flag = 0;
 293
 294                     /* find translated block using physical mappings */
 295                     phys_pc = get_phys_addr_code(env, (unsigned long)pc);
 296                     phys_page1 = phys_pc & TARGET_PAGE_MASK;
 297                     phys_page2 = -1;
 298                     h = tb_phys_hash_func(phys_pc);
 299                     ptb1 = &tb_phys_hash[h];
 300                     for(;;) {
 301                         tb = *ptb1;
 302                         if (!tb)
 303                             goto not_found;
 304                         if (tb->pc == (unsigned long)pc &&
 305                             tb->page_addr[0] == phys_page1 &&
 306                             tb->cs_base == (unsigned long)cs_base &&
 307                             tb->flags == flags) {
 308                             /* check next page if needed */
 309                             if (tb->page_addr[1] != -1) {
 310                                 virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) +
 311                                     TARGET_PAGE_SIZE;
 312                                 phys_page2 = get_phys_addr_code(env, virt_page2);
 313                                 if (tb->page_addr[1] == phys_page2)
 314                                     goto found;
 315                             } else {
 316                                 goto found;
 317                             }
 318                         }
 319                         ptb1 = &tb->phys_hash_next;
 320                     }
 321                 not_found:
 322                     /* if no translated code available, then translate it now */
 323                     tb = tb_alloc((unsigned long)pc);
 324                     if (!tb) {
 325                         /* flush must be done */
 326                         tb_flush(env);
 327                         /* cannot fail at this point */
 328                         tb = tb_alloc((unsigned long)pc);
 329                         /* don't forget to invalidate previous TB info */
 330                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 331                         T0 = 0;
 332                     }
 333                     tc_ptr = code_gen_ptr;
 334                     tb->tc_ptr = tc_ptr;
 335                     tb->cs_base = (unsigned long)cs_base;
 336                     tb->flags = flags;
 337                     cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
 338                     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
 339
 340                     /* check next page if needed */
 341                     virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
 342                     phys_page2 = -1;
 343                     if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
 344                         phys_page2 = get_phys_addr_code(env, virt_page2);
 345                     }
 346                     tb_link_phys(tb, phys_pc, phys_page2);
 347
 348                 found:
 349                     if (tb_invalidated_flag) {
 350                         /* as some TB could have been invalidated because
 351                            of memory exceptions while generating the code, we
 352                            must recompute the hash index here */
 353                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 354                         while (*ptb != NULL)
 355                             ptb = &(*ptb)->hash_next;
 356                         T0 = 0;
 357                     }
 358                     /* we add the TB in the virtual pc hash table */
 359                     *ptb = tb;
 360                     tb->hash_next = NULL;
 361                     tb_link(tb);
 362                     spin_unlock(&tb_lock);
 363                 }
 364 #ifdef DEBUG_EXEC
 365                 if (loglevel & CPU_LOG_EXEC) {
 366                     fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
 367                             (long)tb->tc_ptr, (long)tb->pc,
 368                             lookup_symbol((void *)tb->pc));
 369                 }
 370 #endif
 371 #ifdef __sparc__
 372                 T0 = tmp_T0;
 373 #endif
 374                 /* see if we can patch the calling TB. */
 375                 if (T0 != 0
 376 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
 377                     && (tb->cflags & CF_CODE_COPY) ==
 378                     (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
 379 #endif
 380                     ) {
 381                     spin_lock(&tb_lock);
 382                     tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
 383 #if defined(USE_CODE_COPY)
 384                     /* propagates the FP use info */
 385                     ((TranslationBlock *)(T0 & ~3))->cflags |=
 386                         (tb->cflags & CF_FP_USED);
 387 #endif
 388                     spin_unlock(&tb_lock);
 389                 }
 390                 tc_ptr = tb->tc_ptr;
 391                 env->current_tb = tb;
 392                 /* execute the generated code */
 393                 gen_func = (void *)tc_ptr;
 394 #if defined(__sparc__)
 395                 __asm__ __volatile__("call      %0\n\t"
 396                                      "mov       %%o7,%%i0"
 397                                      : /* no outputs */
 398                                      : "r" (gen_func)
 399                                      : "i0", "i1", "i2", "i3", "i4", "i5");
 400 #elif defined(__arm__)
 401                 asm volatile ("mov pc, %0\n\t"
 402                               ".global exec_loop\n\t"
 403                               "exec_loop:\n\t"
 404                               : /* no outputs */
 405                               : "r" (gen_func)
 406                               : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
 407 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
 408 {
 409     if (!(tb->cflags & CF_CODE_COPY)) {
 410         if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
 411             save_native_fp_state(env);
 412         }
 413         gen_func();
 414     } else {
 415         if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
 416             restore_native_fp_state(env);
 417         }
 418         /* we work with native eflags */
 419         CC_SRC = cc_table[CC_OP].compute_all();
 420         CC_OP = CC_OP_EFLAGS;
 421         asm(".globl exec_loop\n"
 422             "\n"
 423             "debug1:\n"
 424             "    pushl %%ebp\n"
 425             "    fs movl %10, %9\n"
 426             "    fs movl %11, %%eax\n"
 427             "    andl $0x400, %%eax\n"
 428             "    fs orl %8, %%eax\n"
 429             "    pushl %%eax\n"
 430             "    popf\n"
 431             "    fs movl %%esp, %12\n"
 432             "    fs movl %0, %%eax\n"
 433             "    fs movl %1, %%ecx\n"
 434             "    fs movl %2, %%edx\n"
 435             "    fs movl %3, %%ebx\n"
 436             "    fs movl %4, %%esp\n"
 437             "    fs movl %5, %%ebp\n"
 438             "    fs movl %6, %%esi\n"
 439             "    fs movl %7, %%edi\n"
 440             "    fs jmp *%9\n"
 441             "exec_loop:\n"
 442             "    fs movl %%esp, %4\n"
 443             "    fs movl %12, %%esp\n"
 444             "    fs movl %%eax, %0\n"
 445             "    fs movl %%ecx, %1\n"
 446             "    fs movl %%edx, %2\n"
 447             "    fs movl %%ebx, %3\n"
 448             "    fs movl %%ebp, %5\n"
 449             "    fs movl %%esi, %6\n"
 450             "    fs movl %%edi, %7\n"
 451             "    pushf\n"
 452             "    popl %%eax\n"
 453             "    movl %%eax, %%ecx\n"
 454             "    andl $0x400, %%ecx\n"
 455             "    shrl $9, %%ecx\n"
 456             "    andl $0x8d5, %%eax\n"
 457             "    fs movl %%eax, %8\n"
 458             "    movl $1, %%eax\n"
 459             "    subl %%ecx, %%eax\n"
 460             "    fs movl %%eax, %11\n"
 461             "    fs movl %9, %%ebx\n" /* get T0 value */
 462             "    popl %%ebp\n"
 463             :
 464             : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
 465             "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
 466             "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
 467             "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
 468             "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
 469             "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
 470             "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
 471             "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
 472             "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
 473             "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
 474             "a" (gen_func),
 475             "m" (*(uint8_t *)offsetof(CPUState, df)),
 476             "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
 477             : "%ecx", "%edx"
 478             );
 479     }
 480 }
 481 #else
 482                 gen_func();
 483 #endif
 484                 env->current_tb = NULL;
 485                 /* reset soft MMU for next block (it can currently
 486                    only be set by a memory fault) */
 487 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
 488                 if (env->hflags & HF_SOFTMMU_MASK) {
 489                     env->hflags &= ~HF_SOFTMMU_MASK;
 490                     /* do not allow linking to another block */
 491                     T0 = 0;
 492                 }
 493 #endif
 494             }
 495         } else {
 496         }
 497     } /* for(;;) */
 498
 499
 500 #if defined(TARGET_I386)
 501 #if defined(USE_CODE_COPY)
 502     if (env->native_fp_regs) {
 503         save_native_fp_state(env);
 504     }
 505 #endif
 506     /* restore flags in standard format */
 507     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 508
 509     /* restore global registers */
 510 #ifdef reg_EAX
 511     EAX = saved_EAX;
 512 #endif
 513 #ifdef reg_ECX
 514     ECX = saved_ECX;
 515 #endif
 516 #ifdef reg_EDX
 517     EDX = saved_EDX;
 518 #endif
 519 #ifdef reg_EBX
 520     EBX = saved_EBX;
 521 #endif
 522 #ifdef reg_ESP
 523     ESP = saved_ESP;
 524 #endif
 525 #ifdef reg_EBP
 526     EBP = saved_EBP;
 527 #endif
 528 #ifdef reg_ESI
 529     ESI = saved_ESI;
 530 #endif
 531 #ifdef reg_EDI
 532     EDI = saved_EDI;
 533 #endif
 534 #elif defined(TARGET_ARM)
 535     env->cpsr = compute_cpsr();
 536 #elif defined(TARGET_SPARC)
 537 #elif defined(TARGET_PPC)
 538 #else
 539 #error unsupported target CPU
 540 #endif
 541 #ifdef __sparc__
 542     asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
 543 #endif
 544     T0 = saved_T0;
 545     T1 = saved_T1;
 546     T2 = saved_T2;
 547     env = saved_env;
 548     return ret;
 549 }
 550
 551 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
 552
 553 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 554 {
 555     CPUX86State *saved_env;
 556
 557     saved_env = env;
 558     env = s;
 559     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 560         selector &= 0xffff;
 561         cpu_x86_load_seg_cache(env, seg_reg, selector,
 562                                (uint8_t *)(selector << 4), 0xffff, 0);
 563     } else {
 564         load_seg(seg_reg, selector);
 565     }
 566     env = saved_env;
 567 }
 568
 569 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
 570 {
 571     CPUX86State *saved_env;
 572
 573     saved_env = env;
 574     env = s;
 575
 576     helper_fsave(ptr, data32);
 577
 578     env = saved_env;
 579 }
 580
 581 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
 582 {
 583     CPUX86State *saved_env;
 584
 585     saved_env = env;
 586     env = s;
 587
 588     helper_frstor(ptr, data32);
 589
 590     env = saved_env;
 591 }
 592
 593 #endif /* TARGET_I386 */
 594
 595 #undef EAX
 596 #undef ECX
 597 #undef EDX
 598 #undef EBX
 599 #undef ESP
 600 #undef EBP
 601 #undef ESI
 602 #undef EDI
 603 #undef EIP
 604 #include <signal.h>
 605 #include <sys/ucontext.h>
 606
 607 #if defined(TARGET_I386)
 608
 609 /* 'pc' is the host PC at which the exception was raised. 'address' is
 610    the effective address of the memory exception. 'is_write' is 1 if a
 611    write caused the exception and otherwise 0'. 'old_set' is the
 612    signal set which should be restored */
 613 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 614                                     int is_write, sigset_t *old_set,
 615                                     void *puc)
 616 {
 617     TranslationBlock *tb;
 618     int ret;
 619
 620     if (cpu_single_env)
 621         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 622 #if defined(DEBUG_SIGNAL)
 623     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 624                 pc, address, is_write, *(unsigned long *)old_set);
 625 #endif
 626     /* XXX: locking issue */
 627     if (is_write && page_unprotect(address)) {
 628         return 1;
 629     }
 630     /* see if it is an MMU fault */
 631     ret = cpu_x86_handle_mmu_fault(env, address, is_write,
 632                                    ((env->hflags & HF_CPL_MASK) == 3), 0);
 633     if (ret < 0)
 634         return 0; /* not an MMU fault */
 635     if (ret == 0)
 636         return 1; /* the MMU fault was handled without causing real CPU fault */
 637     /* now we have a real cpu fault */
 638     tb = tb_find_pc(pc);
 639     if (tb) {
 640         /* the PC is inside the translated code. It means that we have
 641            a virtual CPU fault */
 642         cpu_restore_state(tb, env, pc, puc);
 643     }
 644     if (ret == 1) {
 645 #if 0
 646         printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 647                env->eip, env->cr[2], env->error_code);
 648 #endif
 649         /* we restore the process signal mask as the sigreturn should
 650            do it (XXX: use sigsetjmp) */
 651         sigprocmask(SIG_SETMASK, old_set, NULL);
 652         raise_exception_err(EXCP0E_PAGE, env->error_code);
 653     } else {
 654         /* activate soft MMU for this block */
 655         env->hflags |= HF_SOFTMMU_MASK;
 656         sigprocmask(SIG_SETMASK, old_set, NULL);
 657         cpu_loop_exit();
 658     }
 659     /* never comes here */
 660     return 1;
 661 }
 662
 663 #elif defined(TARGET_ARM)
 664 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 665                                     int is_write, sigset_t *old_set,
 666                                     void *puc)
 667 {
 668     /* XXX: do more */
 669     return 0;
 670 }
 671 #elif defined(TARGET_SPARC)
 672 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 673                                     int is_write, sigset_t *old_set,
 674                                     void *puc)
 675 {
 676     /* XXX: locking issue */
 677     if (is_write && page_unprotect(address)) {
 678         return 1;
 679     }
 680     return 0;
 681 }
 682 #elif defined (TARGET_PPC)
 683 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 684                                     int is_write, sigset_t *old_set,
 685                                     void *puc)
 686 {
 687     TranslationBlock *tb;
 688     int ret;
 689
 690 #if 1
 691     if (cpu_single_env)
 692         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 693 #endif
 694 #if defined(DEBUG_SIGNAL)
 695     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 696            pc, address, is_write, *(unsigned long *)old_set);
 697 #endif
 698     /* XXX: locking issue */
 699     if (is_write && page_unprotect(address)) {
 700         return 1;
 701     }
 702
 703     /* see if it is an MMU fault */
 704     ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
 705     if (ret < 0)
 706         return 0; /* not an MMU fault */
 707     if (ret == 0)
 708         return 1; /* the MMU fault was handled without causing real CPU fault */
 709
 710     /* now we have a real cpu fault */
 711     tb = tb_find_pc(pc);
 712     if (tb) {
 713         /* the PC is inside the translated code. It means that we have
 714            a virtual CPU fault */
 715         cpu_restore_state(tb, env, pc, puc);
 716     }
 717     if (ret == 1) {
 718 #if 0
 719         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
 720                env->nip, env->error_code, tb);
 721 #endif
 722     /* we restore the process signal mask as the sigreturn should
 723        do it (XXX: use sigsetjmp) */
 724         sigprocmask(SIG_SETMASK, old_set, NULL);
 725         do_queue_exception_err(env->exception_index, env->error_code);
 726     } else {
 727         /* activate soft MMU for this block */
 728         sigprocmask(SIG_SETMASK, old_set, NULL);
 729         cpu_loop_exit();
 730     }
 731     /* never comes here */
 732     return 1;
 733 }
 734 #else
 735 #error unsupported target CPU
 736 #endif
 737
 738 #if defined(__i386__)
 739
 740 #if defined(USE_CODE_COPY)
 741 static void cpu_send_trap(unsigned long pc, int trap,
 742                           struct ucontext *uc)
 743 {
 744     TranslationBlock *tb;
 745
 746     if (cpu_single_env)
 747         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 748     /* now we have a real cpu fault */
 749     tb = tb_find_pc(pc);
 750     if (tb) {
 751         /* the PC is inside the translated code. It means that we have
 752            a virtual CPU fault */
 753         cpu_restore_state(tb, env, pc, uc);
 754     }
 755     sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
 756     raise_exception_err(trap, env->error_code);
 757 }
 758 #endif
 759
 760 int cpu_signal_handler(int host_signum, struct siginfo *info,
 761                        void *puc)
 762 {
 763     struct ucontext *uc = puc;
 764     unsigned long pc;
 765     int trapno;
 766
 767 #ifndef REG_EIP
 768 /* for glibc 2.1 */
 769 #define REG_EIP    EIP
 770 #define REG_ERR    ERR
 771 #define REG_TRAPNO TRAPNO
 772 #endif
 773     pc = uc->uc_mcontext.gregs[REG_EIP];
 774     trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
 775 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
 776     if (trapno == 0x00 || trapno == 0x05) {
 777         /* send division by zero or bound exception */
 778         cpu_send_trap(pc, trapno, uc);
 779         return 1;
 780     } else
 781 #endif
 782         return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 783                                  trapno == 0xe ?
 784                                  (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 785                                  &uc->uc_sigmask, puc);
 786 }
 787
 788 #elif defined(__x86_64__)
 789
 790 int cpu_signal_handler(int host_signum, struct siginfo *info,
 791                        void *puc)
 792 {
 793     struct ucontext *uc = puc;
 794     unsigned long pc;
 795
 796     pc = uc->uc_mcontext.gregs[REG_RIP];
 797     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 798                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
 799                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 800                              &uc->uc_sigmask, puc);
 801 }
 802
 803 #elif defined(__powerpc)
 804
 805 int cpu_signal_handler(int host_signum, struct siginfo *info,
 806                        void *puc)
 807 {
 808     struct ucontext *uc = puc;
 809     struct pt_regs *regs = uc->uc_mcontext.regs;
 810     unsigned long pc;
 811     int is_write;
 812
 813     pc = regs->nip;
 814     is_write = 0;
 815 #if 0
 816     /* ppc 4xx case */
 817     if (regs->dsisr & 0x00800000)
 818         is_write = 1;
 819 #else
 820     if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
 821         is_write = 1;
 822 #endif
 823     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 824                              is_write, &uc->uc_sigmask, puc);
 825 }
 826
 827 #elif defined(__alpha__)
 828
 829 int cpu_signal_handler(int host_signum, struct siginfo *info,
 830                            void *puc)
 831 {
 832     struct ucontext *uc = puc;
 833     uint32_t *pc = uc->uc_mcontext.sc_pc;
 834     uint32_t insn = *pc;
 835     int is_write = 0;
 836
 837     /* XXX: need kernel patch to get write flag faster */
 838     switch (insn >> 26) {
 839     case 0x0d: // stw
 840     case 0x0e: // stb
 841     case 0x0f: // stq_u
 842     case 0x24: // stf
 843     case 0x25: // stg
 844     case 0x26: // sts
 845     case 0x27: // stt
 846     case 0x2c: // stl
 847     case 0x2d: // stq
 848     case 0x2e: // stl_c
 849     case 0x2f: // stq_c
 850         is_write = 1;
 851     }
 852
 853     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 854                              is_write, &uc->uc_sigmask, puc);
 855 }
 856 #elif defined(__sparc__)
 857
 858 int cpu_signal_handler(int host_signum, struct siginfo *info,
 859                        void *puc)
 860 {
 861     uint32_t *regs = (uint32_t *)(info + 1);
 862     void *sigmask = (regs + 20);
 863     unsigned long pc;
 864     int is_write;
 865     uint32_t insn;
 866
 867     /* XXX: is there a standard glibc define ? */
 868     pc = regs[1];
 869     /* XXX: need kernel patch to get write flag faster */
 870     is_write = 0;
 871     insn = *(uint32_t *)pc;
 872     if ((insn >> 30) == 3) {
 873       switch((insn >> 19) & 0x3f) {
 874       case 0x05: // stb
 875       case 0x06: // sth
 876       case 0x04: // st
 877       case 0x07: // std
 878       case 0x24: // stf
 879       case 0x27: // stdf
 880       case 0x25: // stfsr
 881         is_write = 1;
 882         break;
 883       }
 884     }
 885     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 886                              is_write, sigmask, NULL);
 887 }
 888
 889 #elif defined(__arm__)
 890
 891 int cpu_signal_handler(int host_signum, struct siginfo *info,
 892                        void *puc)
 893 {
 894     struct ucontext *uc = puc;
 895     unsigned long pc;
 896     int is_write;
 897
 898     pc = uc->uc_mcontext.gregs[R15];
 899     /* XXX: compute is_write */
 900     is_write = 0;
 901     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 902                              is_write,
 903                              &uc->uc_sigmask);
 904 }
 905
 906 #elif defined(__mc68000)
 907
 908 int cpu_signal_handler(int host_signum, struct siginfo *info,
 909                        void *puc)
 910 {
 911     struct ucontext *uc = puc;
 912     unsigned long pc;
 913     int is_write;
 914
 915     pc = uc->uc_mcontext.gregs[16];
 916     /* XXX: compute is_write */
 917     is_write = 0;
 918     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 919                              is_write,
 920                              &uc->uc_sigmask, puc);
 921 }
 922
 923 #else
 924
 925 #error host CPU specific signal handler needed
 926
 927 #endif