include/hw/arm/omap.h

   1 /*
   2  * Texas Instruments OMAP processors.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HW_ARM_OMAP_H
  21 #define HW_ARM_OMAP_H
  22
  23 #include "exec/memory.h"
  24 #include "hw/input/tsc2xxx.h"
  25 #include "target/arm/cpu-qom.h"
  26 #include "qemu/log.h"
  27
  28 # define OMAP_EMIFS_BASE        0x00000000
  29 # define OMAP2_Q0_BASE          0x00000000
  30 # define OMAP_CS0_BASE          0x00000000
  31 # define OMAP_CS1_BASE          0x04000000
  32 # define OMAP_CS2_BASE          0x08000000
  33 # define OMAP_CS3_BASE          0x0c000000
  34 # define OMAP_EMIFF_BASE        0x10000000
  35 # define OMAP_IMIF_BASE         0x20000000
  36 # define OMAP_LOCALBUS_BASE     0x30000000
  37 # define OMAP2_Q1_BASE          0x40000000
  38 # define OMAP2_L4_BASE          0x48000000
  39 # define OMAP2_SRAM_BASE        0x40200000
  40 # define OMAP2_L3_BASE          0x68000000
  41 # define OMAP2_Q2_BASE          0x80000000
  42 # define OMAP2_Q3_BASE          0xc0000000
  43 # define OMAP_MPUI_BASE         0xe1000000
  44
  45 # define OMAP730_SRAM_SIZE      0x00032000
  46 # define OMAP15XX_SRAM_SIZE     0x00030000
  47 # define OMAP16XX_SRAM_SIZE     0x00004000
  48 # define OMAP1611_SRAM_SIZE     0x0003e800
  49 # define OMAP242X_SRAM_SIZE     0x000a0000
  50 # define OMAP243X_SRAM_SIZE     0x00010000
  51 # define OMAP_CS0_SIZE          0x04000000
  52 # define OMAP_CS1_SIZE          0x04000000
  53 # define OMAP_CS2_SIZE          0x04000000
  54 # define OMAP_CS3_SIZE          0x04000000
  55
  56 /* omap_clk.c */
  57 struct omap_mpu_state_s;
  58 typedef struct clk *omap_clk;
  59 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
  60 void omap_clk_init(struct omap_mpu_state_s *mpu);
  61 void omap_clk_adduser(struct clk *clk, qemu_irq user);
  62 void omap_clk_get(omap_clk clk);
  63 void omap_clk_put(omap_clk clk);
  64 void omap_clk_onoff(omap_clk clk, int on);
  65 void omap_clk_canidle(omap_clk clk, int can);
  66 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
  67 int64_t omap_clk_getrate(omap_clk clk);
  68 void omap_clk_reparent(omap_clk clk, omap_clk parent);
  69
  70 /* omap_intc.c */
  71 #define TYPE_OMAP_INTC "common-omap-intc"
  72 #define OMAP_INTC(obj)                                              \
  73     OBJECT_CHECK(omap_intr_handler, (obj), TYPE_OMAP_INTC)
  74
  75 typedef struct omap_intr_handler_s omap_intr_handler;
  76
  77 /*
  78  * TODO: Ideally we should have a clock framework that
  79  * let us wire these clocks up with QOM properties or links.
  80  */
  81 void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk);
  82 void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
  83
  84 /* OMAP2 l4 Interconnect */
  85 struct omap_l4_s;
  86 struct omap_l4_region_s {
  87     hwaddr offset;
  88     size_t size;
  89     int access;
  90 };
  91 struct omap_l4_agent_info_s {
  92     int ta;
  93     int region;
  94     int regions;
  95     int ta_region;
  96 };
  97 struct omap_target_agent_s {
  98     MemoryRegion iomem;
  99     struct omap_l4_s *bus;
 100     int regions;
 101     const struct omap_l4_region_s *start;
 102     hwaddr base;
 103     uint32_t component;
 104     uint32_t control;
 105     uint32_t status;
 106 };
 107 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
 108                                hwaddr base, int ta_num);
 109
 110 struct omap_target_agent_s;
 111 struct omap_target_agent_s *omap_l4ta_get(
 112     struct omap_l4_s *bus,
 113     const struct omap_l4_region_s *regions,
 114     const struct omap_l4_agent_info_s *agents,
 115     int cs);
 116 hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
 117                                          int region, MemoryRegion *mr);
 118 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
 119                                        int region);
 120 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
 121                                        int region);
 122
 123 /* OMAP2 SDRAM controller */
 124 struct omap_sdrc_s;
 125 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
 126                                    hwaddr base);
 127 void omap_sdrc_reset(struct omap_sdrc_s *s);
 128
 129 /* OMAP2 general purpose memory controller */
 130 struct omap_gpmc_s;
 131 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
 132                                    hwaddr base,
 133                                    qemu_irq irq, qemu_irq drq);
 134 void omap_gpmc_reset(struct omap_gpmc_s *s);
 135 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
 136 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
 137
 138 /*
 139  * Common IRQ numbers for level 1 interrupt handler
 140  * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
 141  */
 142 # define OMAP_INT_CAMERA                1
 143 # define OMAP_INT_FIQ                   3
 144 # define OMAP_INT_RTDX                  6
 145 # define OMAP_INT_DSP_MMU_ABORT         7
 146 # define OMAP_INT_HOST                  8
 147 # define OMAP_INT_ABORT                 9
 148 # define OMAP_INT_BRIDGE_PRIV           13
 149 # define OMAP_INT_GPIO_BANK1            14
 150 # define OMAP_INT_UART3                 15
 151 # define OMAP_INT_TIMER3                16
 152 # define OMAP_INT_DMA_CH0_6             19
 153 # define OMAP_INT_DMA_CH1_7             20
 154 # define OMAP_INT_DMA_CH2_8             21
 155 # define OMAP_INT_DMA_CH3               22
 156 # define OMAP_INT_DMA_CH4               23
 157 # define OMAP_INT_DMA_CH5               24
 158 # define OMAP_INT_DMA_LCD               25
 159 # define OMAP_INT_TIMER1                26
 160 # define OMAP_INT_WD_TIMER              27
 161 # define OMAP_INT_BRIDGE_PUB            28
 162 # define OMAP_INT_TIMER2                30
 163 # define OMAP_INT_LCD_CTRL              31
 164
 165 /*
 166  * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
 167  */
 168 # define OMAP_INT_15XX_IH2_IRQ          0
 169 # define OMAP_INT_15XX_LB_MMU           17
 170 # define OMAP_INT_15XX_LOCAL_BUS        29
 171
 172 /*
 173  * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
 174  */
 175 # define OMAP_INT_1510_SPI_TX           4
 176 # define OMAP_INT_1510_SPI_RX           5
 177 # define OMAP_INT_1510_DSP_MAILBOX1     10
 178 # define OMAP_INT_1510_DSP_MAILBOX2     11
 179
 180 /*
 181  * OMAP-310 specific IRQ numbers for level 1 interrupt handler
 182  */
 183 # define OMAP_INT_310_McBSP2_TX         4
 184 # define OMAP_INT_310_McBSP2_RX         5
 185 # define OMAP_INT_310_HSB_MAILBOX1      12
 186 # define OMAP_INT_310_HSAB_MMU          18
 187
 188 /*
 189  * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
 190  */
 191 # define OMAP_INT_1610_IH2_IRQ          0
 192 # define OMAP_INT_1610_IH2_FIQ          2
 193 # define OMAP_INT_1610_McBSP2_TX        4
 194 # define OMAP_INT_1610_McBSP2_RX        5
 195 # define OMAP_INT_1610_DSP_MAILBOX1     10
 196 # define OMAP_INT_1610_DSP_MAILBOX2     11
 197 # define OMAP_INT_1610_LCD_LINE         12
 198 # define OMAP_INT_1610_GPTIMER1         17
 199 # define OMAP_INT_1610_GPTIMER2         18
 200 # define OMAP_INT_1610_SSR_FIFO_0       29
 201
 202 /*
 203  * OMAP-730 specific IRQ numbers for level 1 interrupt handler
 204  */
 205 # define OMAP_INT_730_IH2_FIQ           0
 206 # define OMAP_INT_730_IH2_IRQ           1
 207 # define OMAP_INT_730_USB_NON_ISO       2
 208 # define OMAP_INT_730_USB_ISO           3
 209 # define OMAP_INT_730_ICR               4
 210 # define OMAP_INT_730_EAC               5
 211 # define OMAP_INT_730_GPIO_BANK1        6
 212 # define OMAP_INT_730_GPIO_BANK2        7
 213 # define OMAP_INT_730_GPIO_BANK3        8
 214 # define OMAP_INT_730_McBSP2TX          10
 215 # define OMAP_INT_730_McBSP2RX          11
 216 # define OMAP_INT_730_McBSP2RX_OVF      12
 217 # define OMAP_INT_730_LCD_LINE          14
 218 # define OMAP_INT_730_GSM_PROTECT       15
 219 # define OMAP_INT_730_TIMER3            16
 220 # define OMAP_INT_730_GPIO_BANK5        17
 221 # define OMAP_INT_730_GPIO_BANK6        18
 222 # define OMAP_INT_730_SPGIO_WR          29
 223
 224 /*
 225  * Common IRQ numbers for level 2 interrupt handler
 226  */
 227 # define OMAP_INT_KEYBOARD              1
 228 # define OMAP_INT_uWireTX               2
 229 # define OMAP_INT_uWireRX               3
 230 # define OMAP_INT_I2C                   4
 231 # define OMAP_INT_MPUIO                 5
 232 # define OMAP_INT_USB_HHC_1             6
 233 # define OMAP_INT_McBSP3TX              10
 234 # define OMAP_INT_McBSP3RX              11
 235 # define OMAP_INT_McBSP1TX              12
 236 # define OMAP_INT_McBSP1RX              13
 237 # define OMAP_INT_UART1                 14
 238 # define OMAP_INT_UART2                 15
 239 # define OMAP_INT_USB_W2FC              20
 240 # define OMAP_INT_1WIRE                 21
 241 # define OMAP_INT_OS_TIMER              22
 242 # define OMAP_INT_OQN                   23
 243 # define OMAP_INT_GAUGE_32K             24
 244 # define OMAP_INT_RTC_TIMER             25
 245 # define OMAP_INT_RTC_ALARM             26
 246 # define OMAP_INT_DSP_MMU               28
 247
 248 /*
 249  * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
 250  */
 251 # define OMAP_INT_1510_BT_MCSI1TX       16
 252 # define OMAP_INT_1510_BT_MCSI1RX       17
 253 # define OMAP_INT_1510_SoSSI_MATCH      19
 254 # define OMAP_INT_1510_MEM_STICK        27
 255 # define OMAP_INT_1510_COM_SPI_RO       31
 256
 257 /*
 258  * OMAP-310 specific IRQ numbers for level 2 interrupt handler
 259  */
 260 # define OMAP_INT_310_FAC               0
 261 # define OMAP_INT_310_USB_HHC_2         7
 262 # define OMAP_INT_310_MCSI1_FE          16
 263 # define OMAP_INT_310_MCSI2_FE          17
 264 # define OMAP_INT_310_USB_W2FC_ISO      29
 265 # define OMAP_INT_310_USB_W2FC_NON_ISO  30
 266 # define OMAP_INT_310_McBSP2RX_OF       31
 267
 268 /*
 269  * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
 270  */
 271 # define OMAP_INT_1610_FAC              0
 272 # define OMAP_INT_1610_USB_HHC_2        7
 273 # define OMAP_INT_1610_USB_OTG          8
 274 # define OMAP_INT_1610_SoSSI            9
 275 # define OMAP_INT_1610_BT_MCSI1TX       16
 276 # define OMAP_INT_1610_BT_MCSI1RX       17
 277 # define OMAP_INT_1610_SoSSI_MATCH      19
 278 # define OMAP_INT_1610_MEM_STICK        27
 279 # define OMAP_INT_1610_McBSP2RX_OF      31
 280 # define OMAP_INT_1610_STI              32
 281 # define OMAP_INT_1610_STI_WAKEUP       33
 282 # define OMAP_INT_1610_GPTIMER3         34
 283 # define OMAP_INT_1610_GPTIMER4         35
 284 # define OMAP_INT_1610_GPTIMER5         36
 285 # define OMAP_INT_1610_GPTIMER6         37
 286 # define OMAP_INT_1610_GPTIMER7         38
 287 # define OMAP_INT_1610_GPTIMER8         39
 288 # define OMAP_INT_1610_GPIO_BANK2       40
 289 # define OMAP_INT_1610_GPIO_BANK3       41
 290 # define OMAP_INT_1610_MMC2             42
 291 # define OMAP_INT_1610_CF               43
 292 # define OMAP_INT_1610_WAKE_UP_REQ      46
 293 # define OMAP_INT_1610_GPIO_BANK4       48
 294 # define OMAP_INT_1610_SPI              49
 295 # define OMAP_INT_1610_DMA_CH6          53
 296 # define OMAP_INT_1610_DMA_CH7          54
 297 # define OMAP_INT_1610_DMA_CH8          55
 298 # define OMAP_INT_1610_DMA_CH9          56
 299 # define OMAP_INT_1610_DMA_CH10         57
 300 # define OMAP_INT_1610_DMA_CH11         58
 301 # define OMAP_INT_1610_DMA_CH12         59
 302 # define OMAP_INT_1610_DMA_CH13         60
 303 # define OMAP_INT_1610_DMA_CH14         61
 304 # define OMAP_INT_1610_DMA_CH15         62
 305 # define OMAP_INT_1610_NAND             63
 306
 307 /*
 308  * OMAP-730 specific IRQ numbers for level 2 interrupt handler
 309  */
 310 # define OMAP_INT_730_HW_ERRORS         0
 311 # define OMAP_INT_730_NFIQ_PWR_FAIL     1
 312 # define OMAP_INT_730_CFCD              2
 313 # define OMAP_INT_730_CFIREQ            3
 314 # define OMAP_INT_730_I2C               4
 315 # define OMAP_INT_730_PCC               5
 316 # define OMAP_INT_730_MPU_EXT_NIRQ      6
 317 # define OMAP_INT_730_SPI_100K_1        7
 318 # define OMAP_INT_730_SYREN_SPI         8
 319 # define OMAP_INT_730_VLYNQ             9
 320 # define OMAP_INT_730_GPIO_BANK4        10
 321 # define OMAP_INT_730_McBSP1TX          11
 322 # define OMAP_INT_730_McBSP1RX          12
 323 # define OMAP_INT_730_McBSP1RX_OF       13
 324 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
 325 # define OMAP_INT_730_UART_MODEM_1      15
 326 # define OMAP_INT_730_MCSI              16
 327 # define OMAP_INT_730_uWireTX           17
 328 # define OMAP_INT_730_uWireRX           18
 329 # define OMAP_INT_730_SMC_CD            19
 330 # define OMAP_INT_730_SMC_IREQ          20
 331 # define OMAP_INT_730_HDQ_1WIRE         21
 332 # define OMAP_INT_730_TIMER32K          22
 333 # define OMAP_INT_730_MMC_SDIO          23
 334 # define OMAP_INT_730_UPLD              24
 335 # define OMAP_INT_730_USB_HHC_1         27
 336 # define OMAP_INT_730_USB_HHC_2         28
 337 # define OMAP_INT_730_USB_GENI          29
 338 # define OMAP_INT_730_USB_OTG           30
 339 # define OMAP_INT_730_CAMERA_IF         31
 340 # define OMAP_INT_730_RNG               32
 341 # define OMAP_INT_730_DUAL_MODE_TIMER   33
 342 # define OMAP_INT_730_DBB_RF_EN         34
 343 # define OMAP_INT_730_MPUIO_KEYPAD      35
 344 # define OMAP_INT_730_SHA1_MD5          36
 345 # define OMAP_INT_730_SPI_100K_2        37
 346 # define OMAP_INT_730_RNG_IDLE          38
 347 # define OMAP_INT_730_MPUIO             39
 348 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
 349 # define OMAP_INT_730_LLPC_OE_FALLING   41
 350 # define OMAP_INT_730_LLPC_OE_RISING    42
 351 # define OMAP_INT_730_LLPC_VSYNC        43
 352 # define OMAP_INT_730_WAKE_UP_REQ       46
 353 # define OMAP_INT_730_DMA_CH6           53
 354 # define OMAP_INT_730_DMA_CH7           54
 355 # define OMAP_INT_730_DMA_CH8           55
 356 # define OMAP_INT_730_DMA_CH9           56
 357 # define OMAP_INT_730_DMA_CH10          57
 358 # define OMAP_INT_730_DMA_CH11          58
 359 # define OMAP_INT_730_DMA_CH12          59
 360 # define OMAP_INT_730_DMA_CH13          60
 361 # define OMAP_INT_730_DMA_CH14          61
 362 # define OMAP_INT_730_DMA_CH15          62
 363 # define OMAP_INT_730_NAND              63
 364
 365 /*
 366  * OMAP-24xx common IRQ numbers
 367  */
 368 # define OMAP_INT_24XX_STI              4
 369 # define OMAP_INT_24XX_SYS_NIRQ         7
 370 # define OMAP_INT_24XX_L3_IRQ           10
 371 # define OMAP_INT_24XX_PRCM_MPU_IRQ     11
 372 # define OMAP_INT_24XX_SDMA_IRQ0        12
 373 # define OMAP_INT_24XX_SDMA_IRQ1        13
 374 # define OMAP_INT_24XX_SDMA_IRQ2        14
 375 # define OMAP_INT_24XX_SDMA_IRQ3        15
 376 # define OMAP_INT_243X_MCBSP2_IRQ       16
 377 # define OMAP_INT_243X_MCBSP3_IRQ       17
 378 # define OMAP_INT_243X_MCBSP4_IRQ       18
 379 # define OMAP_INT_243X_MCBSP5_IRQ       19
 380 # define OMAP_INT_24XX_GPMC_IRQ         20
 381 # define OMAP_INT_24XX_GUFFAW_IRQ       21
 382 # define OMAP_INT_24XX_IVA_IRQ          22
 383 # define OMAP_INT_24XX_EAC_IRQ          23
 384 # define OMAP_INT_24XX_CAM_IRQ          24
 385 # define OMAP_INT_24XX_DSS_IRQ          25
 386 # define OMAP_INT_24XX_MAIL_U0_MPU      26
 387 # define OMAP_INT_24XX_DSP_UMA          27
 388 # define OMAP_INT_24XX_DSP_MMU          28
 389 # define OMAP_INT_24XX_GPIO_BANK1       29
 390 # define OMAP_INT_24XX_GPIO_BANK2       30
 391 # define OMAP_INT_24XX_GPIO_BANK3       31
 392 # define OMAP_INT_24XX_GPIO_BANK4       32
 393 # define OMAP_INT_243X_GPIO_BANK5       33
 394 # define OMAP_INT_24XX_MAIL_U3_MPU      34
 395 # define OMAP_INT_24XX_WDT3             35
 396 # define OMAP_INT_24XX_WDT4             36
 397 # define OMAP_INT_24XX_GPTIMER1         37
 398 # define OMAP_INT_24XX_GPTIMER2         38
 399 # define OMAP_INT_24XX_GPTIMER3         39
 400 # define OMAP_INT_24XX_GPTIMER4         40
 401 # define OMAP_INT_24XX_GPTIMER5         41
 402 # define OMAP_INT_24XX_GPTIMER6         42
 403 # define OMAP_INT_24XX_GPTIMER7         43
 404 # define OMAP_INT_24XX_GPTIMER8         44
 405 # define OMAP_INT_24XX_GPTIMER9         45
 406 # define OMAP_INT_24XX_GPTIMER10        46
 407 # define OMAP_INT_24XX_GPTIMER11        47
 408 # define OMAP_INT_24XX_GPTIMER12        48
 409 # define OMAP_INT_24XX_PKA_IRQ          50
 410 # define OMAP_INT_24XX_SHA1MD5_IRQ      51
 411 # define OMAP_INT_24XX_RNG_IRQ          52
 412 # define OMAP_INT_24XX_MG_IRQ           53
 413 # define OMAP_INT_24XX_I2C1_IRQ         56
 414 # define OMAP_INT_24XX_I2C2_IRQ         57
 415 # define OMAP_INT_24XX_MCBSP1_IRQ_TX    59
 416 # define OMAP_INT_24XX_MCBSP1_IRQ_RX    60
 417 # define OMAP_INT_24XX_MCBSP2_IRQ_TX    62
 418 # define OMAP_INT_24XX_MCBSP2_IRQ_RX    63
 419 # define OMAP_INT_243X_MCBSP1_IRQ       64
 420 # define OMAP_INT_24XX_MCSPI1_IRQ       65
 421 # define OMAP_INT_24XX_MCSPI2_IRQ       66
 422 # define OMAP_INT_24XX_SSI1_IRQ0        67
 423 # define OMAP_INT_24XX_SSI1_IRQ1        68
 424 # define OMAP_INT_24XX_SSI2_IRQ0        69
 425 # define OMAP_INT_24XX_SSI2_IRQ1        70
 426 # define OMAP_INT_24XX_SSI_GDD_IRQ      71
 427 # define OMAP_INT_24XX_UART1_IRQ        72
 428 # define OMAP_INT_24XX_UART2_IRQ        73
 429 # define OMAP_INT_24XX_UART3_IRQ        74
 430 # define OMAP_INT_24XX_USB_IRQ_GEN      75
 431 # define OMAP_INT_24XX_USB_IRQ_NISO     76
 432 # define OMAP_INT_24XX_USB_IRQ_ISO      77
 433 # define OMAP_INT_24XX_USB_IRQ_HGEN     78
 434 # define OMAP_INT_24XX_USB_IRQ_HSOF     79
 435 # define OMAP_INT_24XX_USB_IRQ_OTG      80
 436 # define OMAP_INT_24XX_VLYNQ_IRQ        81
 437 # define OMAP_INT_24XX_MMC_IRQ          83
 438 # define OMAP_INT_24XX_MS_IRQ           84
 439 # define OMAP_INT_24XX_FAC_IRQ          85
 440 # define OMAP_INT_24XX_MCSPI3_IRQ       91
 441 # define OMAP_INT_243X_HS_USB_MC        92
 442 # define OMAP_INT_243X_HS_USB_DMA       93
 443 # define OMAP_INT_243X_CARKIT           94
 444 # define OMAP_INT_34XX_GPTIMER12        95
 445
 446 /* omap_dma.c */
 447 enum omap_dma_model {
 448     omap_dma_3_0,
 449     omap_dma_3_1,
 450     omap_dma_3_2,
 451     omap_dma_4,
 452 };
 453
 454 struct soc_dma_s;
 455 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
 456                 MemoryRegion *sysmem,
 457                 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
 458                 enum omap_dma_model model);
 459 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
 460                 MemoryRegion *sysmem,
 461                 struct omap_mpu_state_s *mpu, int fifo,
 462                 int chans, omap_clk iclk, omap_clk fclk);
 463 void omap_dma_reset(struct soc_dma_s *s);
 464
 465 struct dma_irq_map {
 466     int ih;
 467     int intr;
 468 };
 469
 470 /* Only used in OMAP DMA 3.x gigacells */
 471 enum omap_dma_port {
 472     emiff = 0,
 473     emifs,
 474     imif,       /* omap16xx: ocp_t1 */
 475     tipb,
 476     local,      /* omap16xx: ocp_t2 */
 477     tipb_mpui,
 478     __omap_dma_port_last,
 479 };
 480
 481 typedef enum {
 482     constant = 0,
 483     post_incremented,
 484     single_index,
 485     double_index,
 486 } omap_dma_addressing_t;
 487
 488 /* Only used in OMAP DMA 3.x gigacells */
 489 struct omap_dma_lcd_channel_s {
 490     enum omap_dma_port src;
 491     hwaddr src_f1_top;
 492     hwaddr src_f1_bottom;
 493     hwaddr src_f2_top;
 494     hwaddr src_f2_bottom;
 495
 496     /* Used in OMAP DMA 3.2 gigacell */
 497     unsigned char brust_f1;
 498     unsigned char pack_f1;
 499     unsigned char data_type_f1;
 500     unsigned char brust_f2;
 501     unsigned char pack_f2;
 502     unsigned char data_type_f2;
 503     unsigned char end_prog;
 504     unsigned char repeat;
 505     unsigned char auto_init;
 506     unsigned char priority;
 507     unsigned char fs;
 508     unsigned char running;
 509     unsigned char bs;
 510     unsigned char omap_3_1_compatible_disable;
 511     unsigned char dst;
 512     unsigned char lch_type;
 513     int16_t element_index_f1;
 514     int16_t element_index_f2;
 515     int32_t frame_index_f1;
 516     int32_t frame_index_f2;
 517     uint16_t elements_f1;
 518     uint16_t frames_f1;
 519     uint16_t elements_f2;
 520     uint16_t frames_f2;
 521     omap_dma_addressing_t mode_f1;
 522     omap_dma_addressing_t mode_f2;
 523
 524     /* Destination port is fixed.  */
 525     int interrupts;
 526     int condition;
 527     int dual;
 528
 529     int current_frame;
 530     hwaddr phys_framebuffer[2];
 531     qemu_irq irq;
 532     struct omap_mpu_state_s *mpu;
 533 } *omap_dma_get_lcdch(struct soc_dma_s *s);
 534
 535 /*
 536  * DMA request numbers for OMAP1
 537  * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
 538  */
 539 # define OMAP_DMA_NO_DEVICE             0
 540 # define OMAP_DMA_MCSI1_TX              1
 541 # define OMAP_DMA_MCSI1_RX              2
 542 # define OMAP_DMA_I2C_RX                3
 543 # define OMAP_DMA_I2C_TX                4
 544 # define OMAP_DMA_EXT_NDMA_REQ0         5
 545 # define OMAP_DMA_EXT_NDMA_REQ1         6
 546 # define OMAP_DMA_UWIRE_TX              7
 547 # define OMAP_DMA_MCBSP1_TX             8
 548 # define OMAP_DMA_MCBSP1_RX             9
 549 # define OMAP_DMA_MCBSP3_TX             10
 550 # define OMAP_DMA_MCBSP3_RX             11
 551 # define OMAP_DMA_UART1_TX              12
 552 # define OMAP_DMA_UART1_RX              13
 553 # define OMAP_DMA_UART2_TX              14
 554 # define OMAP_DMA_UART2_RX              15
 555 # define OMAP_DMA_MCBSP2_TX             16
 556 # define OMAP_DMA_MCBSP2_RX             17
 557 # define OMAP_DMA_UART3_TX              18
 558 # define OMAP_DMA_UART3_RX              19
 559 # define OMAP_DMA_CAMERA_IF_RX          20
 560 # define OMAP_DMA_MMC_TX                21
 561 # define OMAP_DMA_MMC_RX                22
 562 # define OMAP_DMA_NAND                  23      /* Not in OMAP310 */
 563 # define OMAP_DMA_IRQ_LCD_LINE          24      /* Not in OMAP310 */
 564 # define OMAP_DMA_MEMORY_STICK          25      /* Not in OMAP310 */
 565 # define OMAP_DMA_USB_W2FC_RX0          26
 566 # define OMAP_DMA_USB_W2FC_RX1          27
 567 # define OMAP_DMA_USB_W2FC_RX2          28
 568 # define OMAP_DMA_USB_W2FC_TX0          29
 569 # define OMAP_DMA_USB_W2FC_TX1          30
 570 # define OMAP_DMA_USB_W2FC_TX2          31
 571
 572 /* These are only for 1610 */
 573 # define OMAP_DMA_CRYPTO_DES_IN         32
 574 # define OMAP_DMA_SPI_TX                33
 575 # define OMAP_DMA_SPI_RX                34
 576 # define OMAP_DMA_CRYPTO_HASH           35
 577 # define OMAP_DMA_CCP_ATTN              36
 578 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY    37
 579 # define OMAP_DMA_CMT_APE_TX_CHAN_0     38
 580 # define OMAP_DMA_CMT_APE_RV_CHAN_0     39
 581 # define OMAP_DMA_CMT_APE_TX_CHAN_1     40
 582 # define OMAP_DMA_CMT_APE_RV_CHAN_1     41
 583 # define OMAP_DMA_CMT_APE_TX_CHAN_2     42
 584 # define OMAP_DMA_CMT_APE_RV_CHAN_2     43
 585 # define OMAP_DMA_CMT_APE_TX_CHAN_3     44
 586 # define OMAP_DMA_CMT_APE_RV_CHAN_3     45
 587 # define OMAP_DMA_CMT_APE_TX_CHAN_4     46
 588 # define OMAP_DMA_CMT_APE_RV_CHAN_4     47
 589 # define OMAP_DMA_CMT_APE_TX_CHAN_5     48
 590 # define OMAP_DMA_CMT_APE_RV_CHAN_5     49
 591 # define OMAP_DMA_CMT_APE_TX_CHAN_6     50
 592 # define OMAP_DMA_CMT_APE_RV_CHAN_6     51
 593 # define OMAP_DMA_CMT_APE_TX_CHAN_7     52
 594 # define OMAP_DMA_CMT_APE_RV_CHAN_7     53
 595 # define OMAP_DMA_MMC2_TX               54
 596 # define OMAP_DMA_MMC2_RX               55
 597 # define OMAP_DMA_CRYPTO_DES_OUT        56
 598
 599 /*
 600  * DMA request numbers for the OMAP2
 601  */
 602 # define OMAP24XX_DMA_NO_DEVICE         0
 603 # define OMAP24XX_DMA_XTI_DMA           1       /* Not in OMAP2420 */
 604 # define OMAP24XX_DMA_EXT_DMAREQ0       2
 605 # define OMAP24XX_DMA_EXT_DMAREQ1       3
 606 # define OMAP24XX_DMA_GPMC              4
 607 # define OMAP24XX_DMA_GFX               5       /* Not in OMAP2420 */
 608 # define OMAP24XX_DMA_DSS               6
 609 # define OMAP24XX_DMA_VLYNQ_TX          7       /* Not in OMAP2420 */
 610 # define OMAP24XX_DMA_CWT               8       /* Not in OMAP2420 */
 611 # define OMAP24XX_DMA_AES_TX            9       /* Not in OMAP2420 */
 612 # define OMAP24XX_DMA_AES_RX            10      /* Not in OMAP2420 */
 613 # define OMAP24XX_DMA_DES_TX            11      /* Not in OMAP2420 */
 614 # define OMAP24XX_DMA_DES_RX            12      /* Not in OMAP2420 */
 615 # define OMAP24XX_DMA_SHA1MD5_RX        13      /* Not in OMAP2420 */
 616 # define OMAP24XX_DMA_EXT_DMAREQ2       14
 617 # define OMAP24XX_DMA_EXT_DMAREQ3       15
 618 # define OMAP24XX_DMA_EXT_DMAREQ4       16
 619 # define OMAP24XX_DMA_EAC_AC_RD         17
 620 # define OMAP24XX_DMA_EAC_AC_WR         18
 621 # define OMAP24XX_DMA_EAC_MD_UL_RD      19
 622 # define OMAP24XX_DMA_EAC_MD_UL_WR      20
 623 # define OMAP24XX_DMA_EAC_MD_DL_RD      21
 624 # define OMAP24XX_DMA_EAC_MD_DL_WR      22
 625 # define OMAP24XX_DMA_EAC_BT_UL_RD      23
 626 # define OMAP24XX_DMA_EAC_BT_UL_WR      24
 627 # define OMAP24XX_DMA_EAC_BT_DL_RD      25
 628 # define OMAP24XX_DMA_EAC_BT_DL_WR      26
 629 # define OMAP24XX_DMA_I2C1_TX           27
 630 # define OMAP24XX_DMA_I2C1_RX           28
 631 # define OMAP24XX_DMA_I2C2_TX           29
 632 # define OMAP24XX_DMA_I2C2_RX           30
 633 # define OMAP24XX_DMA_MCBSP1_TX         31
 634 # define OMAP24XX_DMA_MCBSP1_RX         32
 635 # define OMAP24XX_DMA_MCBSP2_TX         33
 636 # define OMAP24XX_DMA_MCBSP2_RX         34
 637 # define OMAP24XX_DMA_SPI1_TX0          35
 638 # define OMAP24XX_DMA_SPI1_RX0          36
 639 # define OMAP24XX_DMA_SPI1_TX1          37
 640 # define OMAP24XX_DMA_SPI1_RX1          38
 641 # define OMAP24XX_DMA_SPI1_TX2          39
 642 # define OMAP24XX_DMA_SPI1_RX2          40
 643 # define OMAP24XX_DMA_SPI1_TX3          41
 644 # define OMAP24XX_DMA_SPI1_RX3          42
 645 # define OMAP24XX_DMA_SPI2_TX0          43
 646 # define OMAP24XX_DMA_SPI2_RX0          44
 647 # define OMAP24XX_DMA_SPI2_TX1          45
 648 # define OMAP24XX_DMA_SPI2_RX1          46
 649
 650 # define OMAP24XX_DMA_UART1_TX          49
 651 # define OMAP24XX_DMA_UART1_RX          50
 652 # define OMAP24XX_DMA_UART2_TX          51
 653 # define OMAP24XX_DMA_UART2_RX          52
 654 # define OMAP24XX_DMA_UART3_TX          53
 655 # define OMAP24XX_DMA_UART3_RX          54
 656 # define OMAP24XX_DMA_USB_W2FC_TX0      55
 657 # define OMAP24XX_DMA_USB_W2FC_RX0      56
 658 # define OMAP24XX_DMA_USB_W2FC_TX1      57
 659 # define OMAP24XX_DMA_USB_W2FC_RX1      58
 660 # define OMAP24XX_DMA_USB_W2FC_TX2      59
 661 # define OMAP24XX_DMA_USB_W2FC_RX2      60
 662 # define OMAP24XX_DMA_MMC1_TX           61
 663 # define OMAP24XX_DMA_MMC1_RX           62
 664 # define OMAP24XX_DMA_MS                63      /* Not in OMAP2420 */
 665 # define OMAP24XX_DMA_EXT_DMAREQ5       64
 666
 667 /* omap[123].c */
 668 /* OMAP2 gp timer */
 669 struct omap_gp_timer_s;
 670 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
 671                 qemu_irq irq, omap_clk fclk, omap_clk iclk);
 672 void omap_gp_timer_reset(struct omap_gp_timer_s *s);
 673
 674 /* OMAP2 sysctimer */
 675 struct omap_synctimer_s;
 676 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
 677                 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
 678 void omap_synctimer_reset(struct omap_synctimer_s *s);
 679
 680 struct omap_uart_s;
 681 struct omap_uart_s *omap_uart_init(hwaddr base,
 682                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 683                 qemu_irq txdma, qemu_irq rxdma,
 684                 const char *label, Chardev *chr);
 685 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
 686                 struct omap_target_agent_s *ta,
 687                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 688                 qemu_irq txdma, qemu_irq rxdma,
 689                 const char *label, Chardev *chr);
 690 void omap_uart_reset(struct omap_uart_s *s);
 691 void omap_uart_attach(struct omap_uart_s *s, Chardev *chr);
 692
 693 struct omap_mpuio_s;
 694 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
 695 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
 696 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
 697
 698 struct omap_uwire_s;
 699 void omap_uwire_attach(struct omap_uwire_s *s,
 700                 uWireSlave *slave, int chipselect);
 701
 702 /* OMAP2 spi */
 703 struct omap_mcspi_s;
 704 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
 705                 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
 706 void omap_mcspi_attach(struct omap_mcspi_s *s,
 707                 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
 708                 int chipselect);
 709 void omap_mcspi_reset(struct omap_mcspi_s *s);
 710
 711 struct I2SCodec {
 712     void *opaque;
 713
 714     /* The CPU can call this if it is generating the clock signal on the
 715      * i2s port.  The CODEC can ignore it if it is set up as a clock
 716      * master and generates its own clock.  */
 717     void (*set_rate)(void *opaque, int in, int out);
 718
 719     void (*tx_swallow)(void *opaque);
 720     qemu_irq rx_swallow;
 721     qemu_irq tx_start;
 722
 723     int tx_rate;
 724     int cts;
 725     int rx_rate;
 726     int rts;
 727
 728     struct i2s_fifo_s {
 729         uint8_t *fifo;
 730         int len;
 731         int start;
 732         int size;
 733     } in, out;
 734 };
 735 struct omap_mcbsp_s;
 736 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
 737
 738 void omap_tap_init(struct omap_target_agent_s *ta,
 739                 struct omap_mpu_state_s *mpu);
 740
 741 /* omap_lcdc.c */
 742 struct omap_lcd_panel_s;
 743 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
 744 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
 745                                         hwaddr base,
 746                                         qemu_irq irq,
 747                                         struct omap_dma_lcd_channel_s *dma,
 748                                         omap_clk clk);
 749
 750 /* omap_dss.c */
 751 struct rfbi_chip_s {
 752     void *opaque;
 753     void (*write)(void *opaque, int dc, uint16_t value);
 754     void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
 755     uint16_t (*read)(void *opaque, int dc);
 756 };
 757 struct omap_dss_s;
 758 void omap_dss_reset(struct omap_dss_s *s);
 759 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
 760                 MemoryRegion *sysmem,
 761                 hwaddr l3_base,
 762                 qemu_irq irq, qemu_irq drq,
 763                 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
 764                 omap_clk ick1, omap_clk ick2);
 765 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
 766
 767 /* omap_mmc.c */
 768 struct omap_mmc_s;
 769 struct omap_mmc_s *omap_mmc_init(hwaddr base,
 770                 MemoryRegion *sysmem,
 771                 BlockBackend *blk,
 772                 qemu_irq irq, qemu_irq dma[], omap_clk clk);
 773 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 774                 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
 775                 omap_clk fclk, omap_clk iclk);
 776 void omap_mmc_reset(struct omap_mmc_s *s);
 777 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
 778 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
 779
 780 /* omap_i2c.c */
 781 I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
 782
 783 # define cpu_is_omap310(cpu)            (cpu->mpu_model == omap310)
 784 # define cpu_is_omap1510(cpu)           (cpu->mpu_model == omap1510)
 785 # define cpu_is_omap1610(cpu)           (cpu->mpu_model == omap1610)
 786 # define cpu_is_omap1710(cpu)           (cpu->mpu_model == omap1710)
 787 # define cpu_is_omap2410(cpu)           (cpu->mpu_model == omap2410)
 788 # define cpu_is_omap2420(cpu)           (cpu->mpu_model == omap2420)
 789 # define cpu_is_omap2430(cpu)           (cpu->mpu_model == omap2430)
 790 # define cpu_is_omap3430(cpu)           (cpu->mpu_model == omap3430)
 791 # define cpu_is_omap3630(cpu)           (cpu->mpu_model == omap3630)
 792
 793 # define cpu_is_omap15xx(cpu)           \
 794         (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
 795 # define cpu_is_omap16xx(cpu)           \
 796         (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
 797 # define cpu_is_omap24xx(cpu)           \
 798         (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
 799
 800 # define cpu_class_omap1(cpu)           \
 801         (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
 802 # define cpu_class_omap2(cpu)           cpu_is_omap24xx(cpu)
 803 # define cpu_class_omap3(cpu) \
 804         (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
 805
 806 struct omap_mpu_state_s {
 807     enum omap_mpu_model {
 808         omap310,
 809         omap1510,
 810         omap1610,
 811         omap1710,
 812         omap2410,
 813         omap2420,
 814         omap2422,
 815         omap2423,
 816         omap2430,
 817         omap3430,
 818         omap3630,
 819     } mpu_model;
 820
 821     ARMCPU *cpu;
 822
 823     qemu_irq *drq;
 824
 825     qemu_irq wakeup;
 826
 827     MemoryRegion ulpd_pm_iomem;
 828     MemoryRegion pin_cfg_iomem;
 829     MemoryRegion id_iomem;
 830     MemoryRegion id_iomem_e18;
 831     MemoryRegion id_iomem_ed4;
 832     MemoryRegion id_iomem_e20;
 833     MemoryRegion mpui_iomem;
 834     MemoryRegion tcmi_iomem;
 835     MemoryRegion clkm_iomem;
 836     MemoryRegion clkdsp_iomem;
 837     MemoryRegion mpui_io_iomem;
 838     MemoryRegion tap_iomem;
 839     MemoryRegion imif_ram;
 840     MemoryRegion sram;
 841
 842     struct omap_dma_port_if_s {
 843         uint32_t (*read[3])(struct omap_mpu_state_s *s,
 844                         hwaddr offset);
 845         void (*write[3])(struct omap_mpu_state_s *s,
 846                         hwaddr offset, uint32_t value);
 847         int (*addr_valid)(struct omap_mpu_state_s *s,
 848                         hwaddr addr);
 849     } port[__omap_dma_port_last];
 850
 851     uint64_t sdram_size;
 852     unsigned long sram_size;
 853
 854     /* MPUI-TIPB peripherals */
 855     struct omap_uart_s *uart[3];
 856
 857     DeviceState *gpio;
 858
 859     struct omap_mcbsp_s *mcbsp1;
 860     struct omap_mcbsp_s *mcbsp3;
 861
 862     /* MPU public TIPB peripherals */
 863     struct omap_32khz_timer_s *os_timer;
 864
 865     struct omap_mmc_s *mmc;
 866
 867     struct omap_mpuio_s *mpuio;
 868
 869     struct omap_uwire_s *microwire;
 870
 871     struct omap_pwl_s *pwl;
 872     struct omap_pwt_s *pwt;
 873     DeviceState *i2c[2];
 874
 875     struct omap_rtc_s *rtc;
 876
 877     struct omap_mcbsp_s *mcbsp2;
 878
 879     struct omap_lpg_s *led[2];
 880
 881     /* MPU private TIPB peripherals */
 882     DeviceState *ih[2];
 883
 884     struct soc_dma_s *dma;
 885
 886     struct omap_mpu_timer_s *timer[3];
 887     struct omap_watchdog_timer_s *wdt;
 888
 889     struct omap_lcd_panel_s *lcd;
 890
 891     uint32_t ulpd_pm_regs[21];
 892     int64_t ulpd_gauge_start;
 893
 894     uint32_t func_mux_ctrl[14];
 895     uint32_t comp_mode_ctrl[1];
 896     uint32_t pull_dwn_ctrl[4];
 897     uint32_t gate_inh_ctrl[1];
 898     uint32_t voltage_ctrl[1];
 899     uint32_t test_dbg_ctrl[1];
 900     uint32_t mod_conf_ctrl[1];
 901     int compat1509;
 902
 903     uint32_t mpui_ctrl;
 904
 905     struct omap_tipb_bridge_s *private_tipb;
 906     struct omap_tipb_bridge_s *public_tipb;
 907
 908     uint32_t tcmi_regs[17];
 909
 910     struct dpll_ctl_s *dpll[3];
 911
 912     omap_clk clks;
 913     struct {
 914         int cold_start;
 915         int clocking_scheme;
 916         uint16_t arm_ckctl;
 917         uint16_t arm_idlect1;
 918         uint16_t arm_idlect2;
 919         uint16_t arm_ewupct;
 920         uint16_t arm_rstct1;
 921         uint16_t arm_rstct2;
 922         uint16_t arm_ckout1;
 923         int dpll1_mode;
 924         uint16_t dsp_idlect1;
 925         uint16_t dsp_idlect2;
 926         uint16_t dsp_rstct2;
 927     } clkm;
 928
 929     /* OMAP2-only peripherals */
 930     struct omap_l4_s *l4;
 931
 932     struct omap_gp_timer_s *gptimer[12];
 933     struct omap_synctimer_s *synctimer;
 934
 935     struct omap_prcm_s *prcm;
 936     struct omap_sdrc_s *sdrc;
 937     struct omap_gpmc_s *gpmc;
 938     struct omap_sysctl_s *sysc;
 939
 940     struct omap_mcspi_s *mcspi[2];
 941
 942     struct omap_dss_s *dss;
 943
 944     struct omap_eac_s *eac;
 945 };
 946
 947 /* omap1.c */
 948 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram,
 949                 const char *core);
 950
 951 /* omap2.c */
 952 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
 953                 const char *core);
 954
 955 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
 956 void omap_badwidth_write8(void *opaque, hwaddr addr,
 957                 uint32_t value);
 958 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
 959 void omap_badwidth_write16(void *opaque, hwaddr addr,
 960                 uint32_t value);
 961 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
 962 void omap_badwidth_write32(void *opaque, hwaddr addr,
 963                 uint32_t value);
 964
 965 void omap_mpu_wakeup(void *opaque, int irq, int req);
 966
 967 # define OMAP_BAD_REG(paddr)            \
 968         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
 969                       __func__, paddr)
 970 # define OMAP_RO_REG(paddr)             \
 971         qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
 972                                        HWADDR_PRIx "\n", \
 973                       __func__, paddr)
 974
 975 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
 976    (Board-specifc tags are not here)  */
 977 #define OMAP_TAG_CLOCK          0x4f01
 978 #define OMAP_TAG_MMC            0x4f02
 979 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
 980 #define OMAP_TAG_USB            0x4f04
 981 #define OMAP_TAG_LCD            0x4f05
 982 #define OMAP_TAG_GPIO_SWITCH    0x4f06
 983 #define OMAP_TAG_UART           0x4f07
 984 #define OMAP_TAG_FBMEM          0x4f08
 985 #define OMAP_TAG_STI_CONSOLE    0x4f09
 986 #define OMAP_TAG_CAMERA_SENSOR  0x4f0a
 987 #define OMAP_TAG_PARTITION      0x4f0b
 988 #define OMAP_TAG_TEA5761        0x4f10
 989 #define OMAP_TAG_TMP105         0x4f11
 990 #define OMAP_TAG_BOOT_REASON    0x4f80
 991 #define OMAP_TAG_FLASH_PART_STR 0x4f81
 992 #define OMAP_TAG_VERSION_STR    0x4f82
 993
 994 enum {
 995     OMAP_GPIOSW_TYPE_COVER      = 0 << 4,
 996     OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
 997     OMAP_GPIOSW_TYPE_ACTIVITY   = 2 << 4,
 998 };
 999
1000 #define OMAP_GPIOSW_INVERTED    0x0001
1001 #define OMAP_GPIOSW_OUTPUT      0x0002
1002
1003 # define OMAP_MPUI_REG_MASK             0x000007ff
1004
1005 #endif