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xen: cleanup IOREQ server on exit
[qemu.git] / hw / ppc / pnv.c
blobd95086fbbd1e0cfc9ee9d67389895c73894e5e8d
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/units.h"
23 #include "qapi/error.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/numa.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/cpus.h"
29 #include "sysemu/device_tree.h"
30 #include "target/ppc/cpu.h"
31 #include "qemu/log.h"
32 #include "hw/ppc/fdt.h"
33 #include "hw/ppc/ppc.h"
34 #include "hw/ppc/pnv.h"
35 #include "hw/ppc/pnv_core.h"
36 #include "hw/loader.h"
37 #include "exec/address-spaces.h"
38 #include "qapi/visitor.h"
39 #include "monitor/monitor.h"
40 #include "hw/intc/intc.h"
41 #include "hw/ipmi/ipmi.h"
42 #include "target/ppc/mmu-hash64.h"
43
44 #include "hw/ppc/xics.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/ppc/pnv_xscom.h"
47
48 #include "hw/isa/isa.h"
49 #include "hw/boards.h"
50 #include "hw/char/serial.h"
51 #include "hw/timer/mc146818rtc.h"
52
53 #include <libfdt.h>
54
55 #define FDT_MAX_SIZE (1 * MiB)
56
57 #define FW_FILE_NAME "skiboot.lid"
58 #define FW_LOAD_ADDR 0x0
59 #define FW_MAX_SIZE (4 * MiB)
60
61 #define KERNEL_LOAD_ADDR 0x20000000
62 #define KERNEL_MAX_SIZE (256 * MiB)
63 #define INITRD_LOAD_ADDR 0x60000000
64 #define INITRD_MAX_SIZE (256 * MiB)
65
66 static const char *pnv_chip_core_typename(const PnvChip *o)
67 {
68 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
69 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
70 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
71 const char *core_type = object_class_get_name(object_class_by_name(s));
72 g_free(s);
73 return core_type;
74 }
75
76 /*
77 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
78 * 4 * 4 sockets * 12 cores * 8 threads = 1536
79 * Let's make it 2^11
80 */
81 #define MAX_CPUS 2048
82
83 /*
84 * Memory nodes are created by hostboot, one for each range of memory
85 * that has a different "affinity". In practice, it means one range
86 * per chip.
87 */
88 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
89 {
90 char *mem_name;
91 uint64_t mem_reg_property[2];
92 int off;
93
94 mem_reg_property[0] = cpu_to_be64(start);
95 mem_reg_property[1] = cpu_to_be64(size);
96
97 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
98 off = fdt_add_subnode(fdt, 0, mem_name);
99 g_free(mem_name);
100
101 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
102 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
103 sizeof(mem_reg_property))));
104 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
105 }
106
107 static int get_cpus_node(void *fdt)
108 {
109 int cpus_offset = fdt_path_offset(fdt, "/cpus");
110
111 if (cpus_offset < 0) {
112 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
113 if (cpus_offset) {
114 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
116 }
117 }
118 _FDT(cpus_offset);
119 return cpus_offset;
120 }
121
122 /*
123 * The PowerNV cores (and threads) need to use real HW ids and not an
124 * incremental index like it has been done on other platforms. This HW
125 * id is stored in the CPU PIR, it is used to create cpu nodes in the
126 * device tree, used in XSCOM to address cores and in interrupt
127 * servers.
128 */
129 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
130 {
131 PowerPCCPU *cpu = pc->threads[0];
132 CPUState *cs = CPU(cpu);
133 DeviceClass *dc = DEVICE_GET_CLASS(cs);
134 int smt_threads = CPU_CORE(pc)->nr_threads;
135 CPUPPCState *env = &cpu->env;
136 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
137 uint32_t servers_prop[smt_threads];
138 int i;
139 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
140 0xffffffff, 0xffffffff};
141 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
142 uint32_t cpufreq = 1000000000;
143 uint32_t page_sizes_prop[64];
144 size_t page_sizes_prop_size;
145 const uint8_t pa_features[] = { 24, 0,
146 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
147 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
148 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
149 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
150 int offset;
151 char *nodename;
152 int cpus_offset = get_cpus_node(fdt);
153
154 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
155 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
156 _FDT(offset);
157 g_free(nodename);
158
159 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
160
161 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
162 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
163 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
166 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
167 env->dcache_line_size)));
168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
169 env->dcache_line_size)));
170 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
171 env->icache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
173 env->icache_line_size)));
174
175 if (pcc->l1_dcache_size) {
176 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
177 pcc->l1_dcache_size)));
178 } else {
179 warn_report("Unknown L1 dcache size for cpu");
180 }
181 if (pcc->l1_icache_size) {
182 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
183 pcc->l1_icache_size)));
184 } else {
185 warn_report("Unknown L1 icache size for cpu");
186 }
187
188 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
189 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
190 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
191 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
192 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
193
194 if (env->spr_cb[SPR_PURR].oea_read) {
195 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
196 }
197
198 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
199 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
200 segs, sizeof(segs))));
201 }
202
203 /* Advertise VMX/VSX (vector extensions) if available
204 * 0 / no property == no vector extensions
205 * 1 == VMX / Altivec available
206 * 2 == VSX available */
207 if (env->insns_flags & PPC_ALTIVEC) {
208 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
209
210 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
211 }
212
213 /* Advertise DFP (Decimal Floating Point) if available
214 * 0 / no property == no DFP
215 * 1 == DFP available */
216 if (env->insns_flags2 & PPC2_DFP) {
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
218 }
219
220 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
221 sizeof(page_sizes_prop));
222 if (page_sizes_prop_size) {
223 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
224 page_sizes_prop, page_sizes_prop_size)));
225 }
226
227 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
228 pa_features, sizeof(pa_features))));
229
230 /* Build interrupt servers properties */
231 for (i = 0; i < smt_threads; i++) {
232 servers_prop[i] = cpu_to_be32(pc->pir + i);
233 }
234 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
235 servers_prop, sizeof(servers_prop))));
236 }
237
238 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
239 uint32_t nr_threads)
240 {
241 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
242 char *name;
243 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
244 uint32_t irange[2], i, rsize;
245 uint64_t *reg;
246 int offset;
247
248 irange[0] = cpu_to_be32(pir);
249 irange[1] = cpu_to_be32(nr_threads);
250
251 rsize = sizeof(uint64_t) * 2 * nr_threads;
252 reg = g_malloc(rsize);
253 for (i = 0; i < nr_threads; i++) {
254 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
255 reg[i * 2 + 1] = cpu_to_be64(0x1000);
256 }
257
258 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
259 offset = fdt_add_subnode(fdt, 0, name);
260 _FDT(offset);
261 g_free(name);
262
263 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
264 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
265 _FDT((fdt_setprop_string(fdt, offset, "device_type",
266 "PowerPC-External-Interrupt-Presentation")));
267 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
268 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
269 irange, sizeof(irange))));
270 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
271 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
272 g_free(reg);
273 }
274
275 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
276 {
277 const char *typename = pnv_chip_core_typename(chip);
278 size_t typesize = object_type_get_instance_size(typename);
279 int i;
280
281 pnv_dt_xscom(chip, fdt, 0);
282
283 for (i = 0; i < chip->nr_cores; i++) {
284 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
285
286 pnv_dt_core(chip, pnv_core, fdt);
287
288 /* Interrupt Control Presenters (ICP). One per core. */
289 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
290 }
291
292 if (chip->ram_size) {
293 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
294 }
295 }
296
297 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
298 {
299 const char *typename = pnv_chip_core_typename(chip);
300 size_t typesize = object_type_get_instance_size(typename);
301 int i;
302
303 pnv_dt_xscom(chip, fdt, 0);
304
305 for (i = 0; i < chip->nr_cores; i++) {
306 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
307
308 pnv_dt_core(chip, pnv_core, fdt);
309 }
310
311 if (chip->ram_size) {
312 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
313 }
314
315 pnv_dt_lpc(chip, fdt, 0);
316 }
317
318 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
319 {
320 uint32_t io_base = d->ioport_id;
321 uint32_t io_regs[] = {
322 cpu_to_be32(1),
323 cpu_to_be32(io_base),
324 cpu_to_be32(2)
325 };
326 char *name;
327 int node;
328
329 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
330 node = fdt_add_subnode(fdt, lpc_off, name);
331 _FDT(node);
332 g_free(name);
333
334 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
335 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
336 }
337
338 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
339 {
340 const char compatible[] = "ns16550\0pnpPNP,501";
341 uint32_t io_base = d->ioport_id;
342 uint32_t io_regs[] = {
343 cpu_to_be32(1),
344 cpu_to_be32(io_base),
345 cpu_to_be32(8)
346 };
347 char *name;
348 int node;
349
350 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
351 node = fdt_add_subnode(fdt, lpc_off, name);
352 _FDT(node);
353 g_free(name);
354
355 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
356 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
357 sizeof(compatible))));
358
359 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
360 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
361 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
362 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
363 fdt_get_phandle(fdt, lpc_off))));
364
365 /* This is needed by Linux */
366 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
367 }
368
369 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
370 {
371 const char compatible[] = "bt\0ipmi-bt";
372 uint32_t io_base;
373 uint32_t io_regs[] = {
374 cpu_to_be32(1),
375 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
376 cpu_to_be32(3)
377 };
378 uint32_t irq;
379 char *name;
380 int node;
381
382 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
383 io_regs[1] = cpu_to_be32(io_base);
384
385 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
386
387 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
388 node = fdt_add_subnode(fdt, lpc_off, name);
389 _FDT(node);
390 g_free(name);
391
392 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
393 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
394 sizeof(compatible))));
395
396 /* Mark it as reserved to avoid Linux trying to claim it */
397 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
398 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
399 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
400 fdt_get_phandle(fdt, lpc_off))));
401 }
402
403 typedef struct ForeachPopulateArgs {
404 void *fdt;
405 int offset;
406 } ForeachPopulateArgs;
407
408 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
409 {
410 ForeachPopulateArgs *args = opaque;
411 ISADevice *d = ISA_DEVICE(dev);
412
413 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
414 pnv_dt_rtc(d, args->fdt, args->offset);
415 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
416 pnv_dt_serial(d, args->fdt, args->offset);
417 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
418 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
419 } else {
420 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
421 d->ioport_id);
422 }
423
424 return 0;
425 }
426
427 /* The default LPC bus of a multichip system is on chip 0. It's
428 * recognized by the firmware (skiboot) using a "primary" property.
429 */
430 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
431 {
432 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
433 ForeachPopulateArgs args = {
434 .fdt = fdt,
435 .offset = isa_offset,
436 };
437
438 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
439
440 /* ISA devices are not necessarily parented to the ISA bus so we
441 * can not use object_child_foreach() */
442 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
443 &args);
444 }
445
446 static void pnv_dt_power_mgt(void *fdt)
447 {
448 int off;
449
450 off = fdt_add_subnode(fdt, 0, "ibm,opal");
451 off = fdt_add_subnode(fdt, off, "power-mgt");
452
453 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
454 }
455
456 static void *pnv_dt_create(MachineState *machine)
457 {
458 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
459 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv";
460 PnvMachineState *pnv = PNV_MACHINE(machine);
461 void *fdt;
462 char *buf;
463 int off;
464 int i;
465
466 fdt = g_malloc0(FDT_MAX_SIZE);
467 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
468
469 /* Root node */
470 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
471 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
472 _FDT((fdt_setprop_string(fdt, 0, "model",
473 "IBM PowerNV (emulated by qemu)")));
474 if (pnv_is_power9(pnv)) {
475 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9,
476 sizeof(plat_compat9))));
477 } else {
478 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8,
479 sizeof(plat_compat8))));
480 }
481
482
483 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
484 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
485 if (qemu_uuid_set) {
486 _FDT((fdt_property_string(fdt, "system-id", buf)));
487 }
488 g_free(buf);
489
490 off = fdt_add_subnode(fdt, 0, "chosen");
491 if (machine->kernel_cmdline) {
492 _FDT((fdt_setprop_string(fdt, off, "bootargs",
493 machine->kernel_cmdline)));
494 }
495
496 if (pnv->initrd_size) {
497 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
498 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
499
500 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
501 &start_prop, sizeof(start_prop))));
502 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
503 &end_prop, sizeof(end_prop))));
504 }
505
506 /* Populate device tree for each chip */
507 for (i = 0; i < pnv->num_chips; i++) {
508 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
509 }
510
511 /* Populate ISA devices on chip 0 */
512 pnv_dt_isa(pnv, fdt);
513
514 if (pnv->bmc) {
515 pnv_dt_bmc_sensors(pnv->bmc, fdt);
516 }
517
518 /* Create an extra node for power management on Power9 */
519 if (pnv_is_power9(pnv)) {
520 pnv_dt_power_mgt(fdt);
521 }
522
523 return fdt;
524 }
525
526 static void pnv_powerdown_notify(Notifier *n, void *opaque)
527 {
528 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
529
530 if (pnv->bmc) {
531 pnv_bmc_powerdown(pnv->bmc);
532 }
533 }
534
535 static void pnv_reset(MachineState *machine)
536 {
537 PnvMachineState *pnv = PNV_MACHINE(machine);
538 void *fdt;
539 Object *obj;
540
541 qemu_devices_reset();
542
543 /* OpenPOWER systems have a BMC, which can be defined on the
544 * command line with:
545 *
546 * -device ipmi-bmc-sim,id=bmc0
547 *
548 * This is the internal simulator but it could also be an external
549 * BMC.
550 */
551 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL);
552 if (obj) {
553 pnv->bmc = IPMI_BMC(obj);
554 }
555
556 fdt = pnv_dt_create(machine);
557
558 /* Pack resulting tree */
559 _FDT((fdt_pack(fdt)));
560
561 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
562 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
563 }
564
565 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
566 {
567 Pnv8Chip *chip8 = PNV8_CHIP(chip);
568 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
569 }
570
571 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
572 {
573 Pnv8Chip *chip8 = PNV8_CHIP(chip);
574 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
575 }
576
577 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
578 {
579 Pnv9Chip *chip9 = PNV9_CHIP(chip);
580 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
581 }
582
583 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
584 {
585 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
586 }
587
588 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
589 {
590 Pnv8Chip *chip8 = PNV8_CHIP(chip);
591
592 ics_pic_print_info(&chip8->psi.ics, mon);
593 }
594
595 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
596 {
597 Pnv9Chip *chip9 = PNV9_CHIP(chip);
598
599 pnv_xive_pic_print_info(&chip9->xive, mon);
600 pnv_psi_pic_print_info(&chip9->psi, mon);
601 }
602
603 static void pnv_init(MachineState *machine)
604 {
605 PnvMachineState *pnv = PNV_MACHINE(machine);
606 MemoryRegion *ram;
607 char *fw_filename;
608 long fw_size;
609 int i;
610 char *chip_typename;
611
612 /* allocate RAM */
613 if (machine->ram_size < (1 * GiB)) {
614 warn_report("skiboot may not work with < 1GB of RAM");
615 }
616
617 ram = g_new(MemoryRegion, 1);
618 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
619 machine->ram_size);
620 memory_region_add_subregion(get_system_memory(), 0, ram);
621
622 /* load skiboot firmware */
623 if (bios_name == NULL) {
624 bios_name = FW_FILE_NAME;
625 }
626
627 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
628 if (!fw_filename) {
629 error_report("Could not find OPAL firmware '%s'", bios_name);
630 exit(1);
631 }
632
633 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
634 if (fw_size < 0) {
635 error_report("Could not load OPAL firmware '%s'", fw_filename);
636 exit(1);
637 }
638 g_free(fw_filename);
639
640 /* load kernel */
641 if (machine->kernel_filename) {
642 long kernel_size;
643
644 kernel_size = load_image_targphys(machine->kernel_filename,
645 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
646 if (kernel_size < 0) {
647 error_report("Could not load kernel '%s'",
648 machine->kernel_filename);
649 exit(1);
650 }
651 }
652
653 /* load initrd */
654 if (machine->initrd_filename) {
655 pnv->initrd_base = INITRD_LOAD_ADDR;
656 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
657 pnv->initrd_base, INITRD_MAX_SIZE);
658 if (pnv->initrd_size < 0) {
659 error_report("Could not load initial ram disk '%s'",
660 machine->initrd_filename);
661 exit(1);
662 }
663 }
664
665 /* Create the processor chips */
666 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
667 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
668 i, machine->cpu_type);
669 if (!object_class_by_name(chip_typename)) {
670 error_report("invalid CPU model '%.*s' for %s machine",
671 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name);
672 exit(1);
673 }
674
675 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
676 for (i = 0; i < pnv->num_chips; i++) {
677 char chip_name[32];
678 Object *chip = object_new(chip_typename);
679
680 pnv->chips[i] = PNV_CHIP(chip);
681
682 /* TODO: put all the memory in one node on chip 0 until we find a
683 * way to specify different ranges for each chip
684 */
685 if (i == 0) {
686 object_property_set_int(chip, machine->ram_size, "ram-size",
687 &error_fatal);
688 }
689
690 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
691 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
692 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
693 &error_fatal);
694 object_property_set_int(chip, machine->smp.cores,
695 "nr-cores", &error_fatal);
696 object_property_set_bool(chip, true, "realized", &error_fatal);
697 }
698 g_free(chip_typename);
699
700 /* Instantiate ISA bus on chip 0 */
701 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
702
703 /* Create serial port */
704 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
705
706 /* Create an RTC ISA device too */
707 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
708
709 /* OpenPOWER systems use a IPMI SEL Event message to notify the
710 * host to powerdown */
711 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
712 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
713 }
714
715 /*
716 * 0:21 Reserved - Read as zeros
717 * 22:24 Chip ID
718 * 25:28 Core number
719 * 29:31 Thread ID
720 */
721 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
722 {
723 return (chip->chip_id << 7) | (core_id << 3);
724 }
725
726 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
727 Error **errp)
728 {
729 Error *local_err = NULL;
730 Object *obj;
731 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
732
733 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
734 &local_err);
735 if (local_err) {
736 error_propagate(errp, local_err);
737 return;
738 }
739
740 pnv_cpu->intc = obj;
741 }
742
743 /*
744 * 0:48 Reserved - Read as zeroes
745 * 49:52 Node ID
746 * 53:55 Chip ID
747 * 56 Reserved - Read as zero
748 * 57:61 Core number
749 * 62:63 Thread ID
750 *
751 * We only care about the lower bits. uint32_t is fine for the moment.
752 */
753 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
754 {
755 return (chip->chip_id << 8) | (core_id << 2);
756 }
757
758 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
759 Error **errp)
760 {
761 Pnv9Chip *chip9 = PNV9_CHIP(chip);
762 Error *local_err = NULL;
763 Object *obj;
764 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
765
766 /*
767 * The core creates its interrupt presenter but the XIVE interrupt
768 * controller object is initialized afterwards. Hopefully, it's
769 * only used at runtime.
770 */
771 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err);
772 if (local_err) {
773 error_propagate(errp, local_err);
774 return;
775 }
776
777 pnv_cpu->intc = obj;
778 }
779
780 /* Allowed core identifiers on a POWER8 Processor Chip :
781 *
782 * <EX0 reserved>
783 * EX1 - Venice only
784 * EX2 - Venice only
785 * EX3 - Venice only
786 * EX4
787 * EX5
788 * EX6
789 * <EX7,8 reserved> <reserved>
790 * EX9 - Venice only
791 * EX10 - Venice only
792 * EX11 - Venice only
793 * EX12
794 * EX13
795 * EX14
796 * <EX15 reserved>
797 */
798 #define POWER8E_CORE_MASK (0x7070ull)
799 #define POWER8_CORE_MASK (0x7e7eull)
800
801 /*
802 * POWER9 has 24 cores, ids starting at 0x0
803 */
804 #define POWER9_CORE_MASK (0xffffffffffffffull)
805
806 static void pnv_chip_power8_instance_init(Object *obj)
807 {
808 Pnv8Chip *chip8 = PNV8_CHIP(obj);
809
810 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
811 TYPE_PNV8_PSI, &error_abort, NULL);
812 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
813 OBJECT(qdev_get_machine()), &error_abort);
814
815 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
816 TYPE_PNV8_LPC, &error_abort, NULL);
817 object_property_add_const_link(OBJECT(&chip8->lpc), "psi",
818 OBJECT(&chip8->psi), &error_abort);
819
820 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
821 TYPE_PNV8_OCC, &error_abort, NULL);
822 object_property_add_const_link(OBJECT(&chip8->occ), "psi",
823 OBJECT(&chip8->psi), &error_abort);
824 }
825
826 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
827 {
828 PnvChip *chip = PNV_CHIP(chip8);
829 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
830 const char *typename = pnv_chip_core_typename(chip);
831 size_t typesize = object_type_get_instance_size(typename);
832 int i, j;
833 char *name;
834 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
835
836 name = g_strdup_printf("icp-%x", chip->chip_id);
837 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
838 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
839 g_free(name);
840
841 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
842
843 /* Map the ICP registers for each thread */
844 for (i = 0; i < chip->nr_cores; i++) {
845 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
846 int core_hwid = CPU_CORE(pnv_core)->core_id;
847
848 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
849 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
850 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
851
852 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
853 &icp->mmio);
854 }
855 }
856 }
857
858 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
859 {
860 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
861 PnvChip *chip = PNV_CHIP(dev);
862 Pnv8Chip *chip8 = PNV8_CHIP(dev);
863 Pnv8Psi *psi8 = &chip8->psi;
864 Error *local_err = NULL;
865
866 /* XSCOM bridge is first */
867 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
868 if (local_err) {
869 error_propagate(errp, local_err);
870 return;
871 }
872 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
873
874 pcc->parent_realize(dev, &local_err);
875 if (local_err) {
876 error_propagate(errp, local_err);
877 return;
878 }
879
880 /* Processor Service Interface (PSI) Host Bridge */
881 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
882 "bar", &error_fatal);
883 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
884 if (local_err) {
885 error_propagate(errp, local_err);
886 return;
887 }
888 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
889 &PNV_PSI(psi8)->xscom_regs);
890
891 /* Create LPC controller */
892 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
893 &error_fatal);
894 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
895
896 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
897 (uint64_t) PNV_XSCOM_BASE(chip),
898 PNV_XSCOM_LPC_BASE);
899
900 /* Interrupt Management Area. This is the memory region holding
901 * all the Interrupt Control Presenter (ICP) registers */
902 pnv_chip_icp_realize(chip8, &local_err);
903 if (local_err) {
904 error_propagate(errp, local_err);
905 return;
906 }
907
908 /* Create the simplified OCC model */
909 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
910 if (local_err) {
911 error_propagate(errp, local_err);
912 return;
913 }
914 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
915 }
916
917 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
918 {
919 DeviceClass *dc = DEVICE_CLASS(klass);
920 PnvChipClass *k = PNV_CHIP_CLASS(klass);
921
922 k->chip_type = PNV_CHIP_POWER8E;
923 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
924 k->cores_mask = POWER8E_CORE_MASK;
925 k->core_pir = pnv_chip_core_pir_p8;
926 k->intc_create = pnv_chip_power8_intc_create;
927 k->isa_create = pnv_chip_power8_isa_create;
928 k->dt_populate = pnv_chip_power8_dt_populate;
929 k->pic_print_info = pnv_chip_power8_pic_print_info;
930 dc->desc = "PowerNV Chip POWER8E";
931
932 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
933 &k->parent_realize);
934 }
935
936 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
937 {
938 DeviceClass *dc = DEVICE_CLASS(klass);
939 PnvChipClass *k = PNV_CHIP_CLASS(klass);
940
941 k->chip_type = PNV_CHIP_POWER8;
942 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
943 k->cores_mask = POWER8_CORE_MASK;
944 k->core_pir = pnv_chip_core_pir_p8;
945 k->intc_create = pnv_chip_power8_intc_create;
946 k->isa_create = pnv_chip_power8_isa_create;
947 k->dt_populate = pnv_chip_power8_dt_populate;
948 k->pic_print_info = pnv_chip_power8_pic_print_info;
949 dc->desc = "PowerNV Chip POWER8";
950
951 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
952 &k->parent_realize);
953 }
954
955 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
956 {
957 DeviceClass *dc = DEVICE_CLASS(klass);
958 PnvChipClass *k = PNV_CHIP_CLASS(klass);
959
960 k->chip_type = PNV_CHIP_POWER8NVL;
961 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
962 k->cores_mask = POWER8_CORE_MASK;
963 k->core_pir = pnv_chip_core_pir_p8;
964 k->intc_create = pnv_chip_power8_intc_create;
965 k->isa_create = pnv_chip_power8nvl_isa_create;
966 k->dt_populate = pnv_chip_power8_dt_populate;
967 k->pic_print_info = pnv_chip_power8_pic_print_info;
968 dc->desc = "PowerNV Chip POWER8NVL";
969
970 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
971 &k->parent_realize);
972 }
973
974 static void pnv_chip_power9_instance_init(Object *obj)
975 {
976 Pnv9Chip *chip9 = PNV9_CHIP(obj);
977
978 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
979 TYPE_PNV_XIVE, &error_abort, NULL);
980 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj,
981 &error_abort);
982
983 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
984 TYPE_PNV9_PSI, &error_abort, NULL);
985 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj,
986 &error_abort);
987
988 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
989 TYPE_PNV9_LPC, &error_abort, NULL);
990 object_property_add_const_link(OBJECT(&chip9->lpc), "psi",
991 OBJECT(&chip9->psi), &error_abort);
992
993 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
994 TYPE_PNV9_OCC, &error_abort, NULL);
995 object_property_add_const_link(OBJECT(&chip9->occ), "psi",
996 OBJECT(&chip9->psi), &error_abort);
997 }
998
999 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1000 {
1001 PnvChip *chip = PNV_CHIP(chip9);
1002 const char *typename = pnv_chip_core_typename(chip);
1003 size_t typesize = object_type_get_instance_size(typename);
1004 int i;
1005
1006 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1007 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1008
1009 for (i = 0; i < chip9->nr_quads; i++) {
1010 char eq_name[32];
1011 PnvQuad *eq = &chip9->quads[i];
1012 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize);
1013 int core_id = CPU_CORE(pnv_core)->core_id;
1014
1015 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1016 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
1017 TYPE_PNV_QUAD, &error_fatal, NULL);
1018
1019 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1020 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
1021
1022 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1023 &eq->xscom_regs);
1024 }
1025 }
1026
1027 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1028 {
1029 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1030 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1031 PnvChip *chip = PNV_CHIP(dev);
1032 Pnv9Psi *psi9 = &chip9->psi;
1033 Error *local_err = NULL;
1034
1035 /* XSCOM bridge is first */
1036 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1037 if (local_err) {
1038 error_propagate(errp, local_err);
1039 return;
1040 }
1041 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1042
1043 pcc->parent_realize(dev, &local_err);
1044 if (local_err) {
1045 error_propagate(errp, local_err);
1046 return;
1047 }
1048
1049 pnv_chip_quad_realize(chip9, &local_err);
1050 if (local_err) {
1051 error_propagate(errp, local_err);
1052 return;
1053 }
1054
1055 /* XIVE interrupt controller (POWER9) */
1056 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1057 "ic-bar", &error_fatal);
1058 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1059 "vc-bar", &error_fatal);
1060 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1061 "pc-bar", &error_fatal);
1062 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1063 "tm-bar", &error_fatal);
1064 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1065 &local_err);
1066 if (local_err) {
1067 error_propagate(errp, local_err);
1068 return;
1069 }
1070 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1071 &chip9->xive.xscom_regs);
1072
1073 /* Processor Service Interface (PSI) Host Bridge */
1074 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1075 "bar", &error_fatal);
1076 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1077 if (local_err) {
1078 error_propagate(errp, local_err);
1079 return;
1080 }
1081 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1082 &PNV_PSI(psi9)->xscom_regs);
1083
1084 /* LPC */
1085 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1086 if (local_err) {
1087 error_propagate(errp, local_err);
1088 return;
1089 }
1090 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1091 &chip9->lpc.xscom_regs);
1092
1093 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1094 (uint64_t) PNV9_LPCM_BASE(chip));
1095
1096 /* Create the simplified OCC model */
1097 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1098 if (local_err) {
1099 error_propagate(errp, local_err);
1100 return;
1101 }
1102 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1103 }
1104
1105 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1106 {
1107 DeviceClass *dc = DEVICE_CLASS(klass);
1108 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1109
1110 k->chip_type = PNV_CHIP_POWER9;
1111 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1112 k->cores_mask = POWER9_CORE_MASK;
1113 k->core_pir = pnv_chip_core_pir_p9;
1114 k->intc_create = pnv_chip_power9_intc_create;
1115 k->isa_create = pnv_chip_power9_isa_create;
1116 k->dt_populate = pnv_chip_power9_dt_populate;
1117 k->pic_print_info = pnv_chip_power9_pic_print_info;
1118 dc->desc = "PowerNV Chip POWER9";
1119
1120 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1121 &k->parent_realize);
1122 }
1123
1124 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1125 {
1126 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1127 int cores_max;
1128
1129 /*
1130 * No custom mask for this chip, let's use the default one from *
1131 * the chip class
1132 */
1133 if (!chip->cores_mask) {
1134 chip->cores_mask = pcc->cores_mask;
1135 }
1136
1137 /* filter alien core ids ! some are reserved */
1138 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1139 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1140 chip->cores_mask);
1141 return;
1142 }
1143 chip->cores_mask &= pcc->cores_mask;
1144
1145 /* now that we have a sane layout, let check the number of cores */
1146 cores_max = ctpop64(chip->cores_mask);
1147 if (chip->nr_cores > cores_max) {
1148 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1149 cores_max);
1150 return;
1151 }
1152 }
1153
1154 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1155 {
1156 MachineState *ms = MACHINE(qdev_get_machine());
1157 Error *error = NULL;
1158 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1159 const char *typename = pnv_chip_core_typename(chip);
1160 size_t typesize = object_type_get_instance_size(typename);
1161 int i, core_hwid;
1162
1163 if (!object_class_by_name(typename)) {
1164 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1165 return;
1166 }
1167
1168 /* Cores */
1169 pnv_chip_core_sanitize(chip, &error);
1170 if (error) {
1171 error_propagate(errp, error);
1172 return;
1173 }
1174
1175 chip->cores = g_malloc0(typesize * chip->nr_cores);
1176
1177 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1178 && (i < chip->nr_cores); core_hwid++) {
1179 char core_name[32];
1180 void *pnv_core = chip->cores + i * typesize;
1181 uint64_t xscom_core_base;
1182
1183 if (!(chip->cores_mask & (1ull << core_hwid))) {
1184 continue;
1185 }
1186
1187 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1188 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize,
1189 typename, &error_fatal, NULL);
1190 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
1191 &error_fatal);
1192 object_property_set_int(OBJECT(pnv_core), core_hwid,
1193 CPU_CORE_PROP_CORE_ID, &error_fatal);
1194 object_property_set_int(OBJECT(pnv_core),
1195 pcc->core_pir(chip, core_hwid),
1196 "pir", &error_fatal);
1197 object_property_add_const_link(OBJECT(pnv_core), "chip",
1198 OBJECT(chip), &error_fatal);
1199 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1200 &error_fatal);
1201
1202 /* Each core has an XSCOM MMIO region */
1203 if (!pnv_chip_is_power9(chip)) {
1204 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
1205 } else {
1206 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid);
1207 }
1208
1209 pnv_xscom_add_subregion(chip, xscom_core_base,
1210 &PNV_CORE(pnv_core)->xscom_regs);
1211 i++;
1212 }
1213 }
1214
1215 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1216 {
1217 PnvChip *chip = PNV_CHIP(dev);
1218 Error *error = NULL;
1219
1220 /* Cores */
1221 pnv_chip_core_realize(chip, &error);
1222 if (error) {
1223 error_propagate(errp, error);
1224 return;
1225 }
1226 }
1227
1228 static Property pnv_chip_properties[] = {
1229 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1230 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1231 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1232 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1233 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1234 DEFINE_PROP_END_OF_LIST(),
1235 };
1236
1237 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1238 {
1239 DeviceClass *dc = DEVICE_CLASS(klass);
1240
1241 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1242 dc->realize = pnv_chip_realize;
1243 dc->props = pnv_chip_properties;
1244 dc->desc = "PowerNV Chip";
1245 }
1246
1247 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1248 {
1249 PnvMachineState *pnv = PNV_MACHINE(xi);
1250 int i;
1251
1252 for (i = 0; i < pnv->num_chips; i++) {
1253 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1254
1255 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1256 return &chip8->psi.ics;
1257 }
1258 }
1259 return NULL;
1260 }
1261
1262 static void pnv_ics_resend(XICSFabric *xi)
1263 {
1264 PnvMachineState *pnv = PNV_MACHINE(xi);
1265 int i;
1266
1267 for (i = 0; i < pnv->num_chips; i++) {
1268 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1269 ics_resend(&chip8->psi.ics);
1270 }
1271 }
1272
1273 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1274 {
1275 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1276
1277 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1278 }
1279
1280 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1281 Monitor *mon)
1282 {
1283 PnvMachineState *pnv = PNV_MACHINE(obj);
1284 int i;
1285 CPUState *cs;
1286
1287 CPU_FOREACH(cs) {
1288 PowerPCCPU *cpu = POWERPC_CPU(cs);
1289
1290 if (pnv_chip_is_power9(pnv->chips[0])) {
1291 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1292 } else {
1293 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1294 }
1295 }
1296
1297 for (i = 0; i < pnv->num_chips; i++) {
1298 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1299 }
1300 }
1301
1302 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1303 void *opaque, Error **errp)
1304 {
1305 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
1306 }
1307
1308 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1309 void *opaque, Error **errp)
1310 {
1311 PnvMachineState *pnv = PNV_MACHINE(obj);
1312 uint32_t num_chips;
1313 Error *local_err = NULL;
1314
1315 visit_type_uint32(v, name, &num_chips, &local_err);
1316 if (local_err) {
1317 error_propagate(errp, local_err);
1318 return;
1319 }
1320
1321 /*
1322 * TODO: should we decide on how many chips we can create based
1323 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1324 */
1325 if (!is_power_of_2(num_chips) || num_chips > 4) {
1326 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1327 return;
1328 }
1329
1330 pnv->num_chips = num_chips;
1331 }
1332
1333 static void pnv_machine_instance_init(Object *obj)
1334 {
1335 PnvMachineState *pnv = PNV_MACHINE(obj);
1336 pnv->num_chips = 1;
1337 }
1338
1339 static void pnv_machine_class_props_init(ObjectClass *oc)
1340 {
1341 object_class_property_add(oc, "num-chips", "uint32",
1342 pnv_get_num_chips, pnv_set_num_chips,
1343 NULL, NULL, NULL);
1344 object_class_property_set_description(oc, "num-chips",
1345 "Specifies the number of processor chips",
1346 NULL);
1347 }
1348
1349 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1350 {
1351 MachineClass *mc = MACHINE_CLASS(oc);
1352 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1353 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1354
1355 mc->desc = "IBM PowerNV (Non-Virtualized)";
1356 mc->init = pnv_init;
1357 mc->reset = pnv_reset;
1358 mc->max_cpus = MAX_CPUS;
1359 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1360 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
1361 * storage */
1362 mc->no_parallel = 1;
1363 mc->default_boot_order = NULL;
1364 mc->default_ram_size = 1 * GiB;
1365 xic->icp_get = pnv_icp_get;
1366 xic->ics_get = pnv_ics_get;
1367 xic->ics_resend = pnv_ics_resend;
1368 ispc->print_info = pnv_pic_print_info;
1369
1370 pnv_machine_class_props_init(oc);
1371 }
1372
1373 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1374 { \
1375 .name = type, \
1376 .class_init = class_initfn, \
1377 .parent = TYPE_PNV8_CHIP, \
1378 }
1379
1380 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1381 { \
1382 .name = type, \
1383 .class_init = class_initfn, \
1384 .parent = TYPE_PNV9_CHIP, \
1385 }
1386
1387 static const TypeInfo types[] = {
1388 {
1389 .name = TYPE_PNV_MACHINE,
1390 .parent = TYPE_MACHINE,
1391 .instance_size = sizeof(PnvMachineState),
1392 .instance_init = pnv_machine_instance_init,
1393 .class_init = pnv_machine_class_init,
1394 .interfaces = (InterfaceInfo[]) {
1395 { TYPE_XICS_FABRIC },
1396 { TYPE_INTERRUPT_STATS_PROVIDER },
1397 { },
1398 },
1399 },
1400 {
1401 .name = TYPE_PNV_CHIP,
1402 .parent = TYPE_SYS_BUS_DEVICE,
1403 .class_init = pnv_chip_class_init,
1404 .instance_size = sizeof(PnvChip),
1405 .class_size = sizeof(PnvChipClass),
1406 .abstract = true,
1407 },
1408
1409 /*
1410 * P9 chip and variants
1411 */
1412 {
1413 .name = TYPE_PNV9_CHIP,
1414 .parent = TYPE_PNV_CHIP,
1415 .instance_init = pnv_chip_power9_instance_init,
1416 .instance_size = sizeof(Pnv9Chip),
1417 },
1418 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1419
1420 /*
1421 * P8 chip and variants
1422 */
1423 {
1424 .name = TYPE_PNV8_CHIP,
1425 .parent = TYPE_PNV_CHIP,
1426 .instance_init = pnv_chip_power8_instance_init,
1427 .instance_size = sizeof(Pnv8Chip),
1428 },
1429 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1430 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1431 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1432 pnv_chip_power8nvl_class_init),
1433 };
1434
1435 DEFINE_TYPES(types)
QEmu