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usb-ehci: fix offset writeback in ehci_buffer_rw
[qemu.git] / hw / usb-ehci.c
blob5de0cdad9e34536637c0070aa3b889ac00eb664f
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 *
24 * TODO:
25 * o Downstream port handoff
26 */
27
28 #include "hw.h"
29 #include "qemu-timer.h"
30 #include "usb.h"
31 #include "pci.h"
32 #include "monitor.h"
33 #include "trace.h"
34
35 #define EHCI_DEBUG 0
36
37 #if EHCI_DEBUG
38 #define DPRINTF printf
39 #else
40 #define DPRINTF(...)
41 #endif
42
43 /* internal processing - reset HC to try and recover */
44 #define USB_RET_PROCERR (-99)
45
46 #define MMIO_SIZE 0x1000
47
48 /* Capability Registers Base Address - section 2.2 */
49 #define CAPREGBASE 0x0000
50 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54 #define EECP HCCPARAMS + 1
55 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
57
58 #define OPREGBASE 0x0020 // Operational Registers Base Address
59
60 #define USBCMD OPREGBASE + 0x0000
61 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
62 #define USBCMD_HCRESET (1 << 1) // HC Reset
63 #define USBCMD_FLS (3 << 2) // Frame List Size
64 #define USBCMD_FLS_SH 2 // Frame List Size Shift
65 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
73
74 #define USBSTS OPREGBASE + 0x0004
75 #define USBSTS_RO_MASK 0x0000003f
76 #define USBSTS_INT (1 << 0) // USB Interrupt
77 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
78 #define USBSTS_PCD (1 << 2) // Port Change Detect
79 #define USBSTS_FLR (1 << 3) // Frame List Rollover
80 #define USBSTS_HSE (1 << 4) // Host System Error
81 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82 #define USBSTS_HALT (1 << 12) // HC Halted
83 #define USBSTS_REC (1 << 13) // Reclamation
84 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86
87 /*
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
90 */
91 #define USBINTR OPREGBASE + 0x0008
92 #define USBINTR_MASK 0x0000003f
93
94 #define FRINDEX OPREGBASE + 0x000c
95 #define CTRLDSSEGMENT OPREGBASE + 0x0010
96 #define PERIODICLISTBASE OPREGBASE + 0x0014
97 #define ASYNCLISTADDR OPREGBASE + 0x0018
98 #define ASYNCLISTADDR_MASK 0xffffffe0
99
100 #define CONFIGFLAG OPREGBASE + 0x0040
101
102 #define PORTSC (OPREGBASE + 0x0044)
103 #define PORTSC_BEGIN PORTSC
104 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
105 /*
106 * Bits that are reserverd or are read-only are masked out of values
107 * written to us by software
108 */
109 #define PORTSC_RO_MASK 0x007021c5
110 #define PORTSC_RWC_MASK 0x0000002a
111 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114 #define PORTSC_PTC (15 << 16) // Port Test Control
115 #define PORTSC_PTC_SH 16 // Port Test Control shift
116 #define PORTSC_PIC (3 << 14) // Port Indicator Control
117 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118 #define PORTSC_POWNER (1 << 13) // Port Owner
119 #define PORTSC_PPOWER (1 << 12) // Port Power
120 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
121 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122 #define PORTSC_PRESET (1 << 8) // Port Reset
123 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
124 #define PORTSC_FPRES (1 << 6) // Force Port Resume
125 #define PORTSC_OCC (1 << 5) // Over Current Change
126 #define PORTSC_OCA (1 << 4) // Over Current Active
127 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128 #define PORTSC_PED (1 << 2) // Port Enable/Disable
129 #define PORTSC_CSC (1 << 1) // Connect Status Change
130 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
131
132 #define FRAME_TIMER_FREQ 1000
133 #define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
134
135 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136 #define NB_PORTS 4 // Number of downstream ports
137 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139 #define MAX_QH 100 // Max allowable queue heads in a chain
140
141 /* Internal periodic / asynchronous schedule state machine states
142 */
143 typedef enum {
144 EST_INACTIVE = 1000,
145 EST_ACTIVE,
146 EST_EXECUTING,
147 EST_SLEEPING,
148 /* The following states are internal to the state machine function
149 */
150 EST_WAITLISTHEAD,
151 EST_FETCHENTRY,
152 EST_FETCHQH,
153 EST_FETCHITD,
154 EST_ADVANCEQUEUE,
155 EST_FETCHQTD,
156 EST_EXECUTE,
157 EST_WRITEBACK,
158 EST_HORIZONTALQH
159 } EHCI_STATES;
160
161 /* macros for accessing fields within next link pointer entry */
162 #define NLPTR_GET(x) ((x) & 0xffffffe0)
163 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
165
166 /* link pointer types */
167 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168 #define NLPTR_TYPE_QH 1 // queue head
169 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
171
172
173 /* EHCI spec version 1.0 Section 3.3
174 */
175 typedef struct EHCIitd {
176 uint32_t next;
177
178 uint32_t transact[8];
179 #define ITD_XACT_ACTIVE (1 << 31)
180 #define ITD_XACT_DBERROR (1 << 30)
181 #define ITD_XACT_BABBLE (1 << 29)
182 #define ITD_XACT_XACTERR (1 << 28)
183 #define ITD_XACT_LENGTH_MASK 0x0fff0000
184 #define ITD_XACT_LENGTH_SH 16
185 #define ITD_XACT_IOC (1 << 15)
186 #define ITD_XACT_PGSEL_MASK 0x00007000
187 #define ITD_XACT_PGSEL_SH 12
188 #define ITD_XACT_OFFSET_MASK 0x00000fff
189
190 uint32_t bufptr[7];
191 #define ITD_BUFPTR_MASK 0xfffff000
192 #define ITD_BUFPTR_SH 12
193 #define ITD_BUFPTR_EP_MASK 0x00000f00
194 #define ITD_BUFPTR_EP_SH 8
195 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196 #define ITD_BUFPTR_DEVADDR_SH 0
197 #define ITD_BUFPTR_DIRECTION (1 << 11)
198 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199 #define ITD_BUFPTR_MAXPKT_SH 0
200 #define ITD_BUFPTR_MULT_MASK 0x00000003
201 } EHCIitd;
202
203 /* EHCI spec version 1.0 Section 3.4
204 */
205 typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208 #define SITD_EPCHAR_IO (1 << 31)
209 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210 #define SITD_EPCHAR_PORTNUM_SH 24
211 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212 #define SITD_EPCHAR_HUBADDR_SH 16
213 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214 #define SITD_EPCHAR_EPNUM_SH 8
215 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
219 #define SITD_UFRAME_CMASK_SH 8
220 #define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223 #define SITD_RESULTS_IOC (1 << 31)
224 #define SITD_RESULTS_PGSEL (1 << 30)
225 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226 #define SITD_RESULTS_TYBYTES_SH 16
227 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228 #define SITD_RESULTS_CPROGMASK_SH 8
229 #define SITD_RESULTS_ACTIVE (1 << 7)
230 #define SITD_RESULTS_ERR (1 << 6)
231 #define SITD_RESULTS_DBERR (1 << 5)
232 #define SITD_RESULTS_BABBLE (1 << 4)
233 #define SITD_RESULTS_XACTERR (1 << 3)
234 #define SITD_RESULTS_MISSEDUF (1 << 2)
235 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238 #define SITD_BUFPTR_MASK 0xfffff000
239 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240 #define SITD_BUFPTR_TPOS_MASK 0x00000018
241 #define SITD_BUFPTR_TPOS_SH 3
242 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245 } EHCIsitd;
246
247 /* EHCI spec version 1.0 Section 3.5
248 */
249 typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253 #define QTD_TOKEN_DTOGGLE (1 << 31)
254 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255 #define QTD_TOKEN_TBYTES_SH 16
256 #define QTD_TOKEN_IOC (1 << 15)
257 #define QTD_TOKEN_CPAGE_MASK 0x00007000
258 #define QTD_TOKEN_CPAGE_SH 12
259 #define QTD_TOKEN_CERR_MASK 0x00000c00
260 #define QTD_TOKEN_CERR_SH 10
261 #define QTD_TOKEN_PID_MASK 0x00000300
262 #define QTD_TOKEN_PID_SH 8
263 #define QTD_TOKEN_ACTIVE (1 << 7)
264 #define QTD_TOKEN_HALT (1 << 6)
265 #define QTD_TOKEN_DBERR (1 << 5)
266 #define QTD_TOKEN_BABBLE (1 << 4)
267 #define QTD_TOKEN_XACTERR (1 << 3)
268 #define QTD_TOKEN_MISSEDUF (1 << 2)
269 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
270 #define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273 #define QTD_BUFPTR_MASK 0xfffff000
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIQueue EHCIQueue;
338 typedef struct EHCIState EHCIState;
339
340 enum async_state {
341 EHCI_ASYNC_NONE = 0,
342 EHCI_ASYNC_INFLIGHT,
343 EHCI_ASYNC_FINISHED,
344 };
345
346 struct EHCIQueue {
347 EHCIState *ehci;
348 QTAILQ_ENTRY(EHCIQueue) next;
349 bool async_schedule;
350 uint32_t seen, ts;
351
352 /* cached data from guest - needs to be flushed
353 * when guest removes an entry (doorbell, handshake sequence)
354 */
355 EHCIqh qh; // copy of current QH (being worked on)
356 uint32_t qhaddr; // address QH read from
357 EHCIqtd qtd; // copy of current QTD (being worked on)
358 uint32_t qtdaddr; // address QTD read from
359
360 USBPacket packet;
361 uint8_t buffer[BUFF_SIZE];
362 int pid;
363 uint32_t tbytes;
364 enum async_state async;
365 int usb_status;
366 };
367
368 struct EHCIState {
369 PCIDevice dev;
370 USBBus bus;
371 qemu_irq irq;
372 target_phys_addr_t mem_base;
373 int mem;
374 int num_ports;
375 /*
376 * EHCI spec version 1.0 Section 2.3
377 * Host Controller Operational Registers
378 */
379 union {
380 uint8_t mmio[MMIO_SIZE];
381 struct {
382 uint8_t cap[OPREGBASE];
383 uint32_t usbcmd;
384 uint32_t usbsts;
385 uint32_t usbintr;
386 uint32_t frindex;
387 uint32_t ctrldssegment;
388 uint32_t periodiclistbase;
389 uint32_t asynclistaddr;
390 uint32_t notused[9];
391 uint32_t configflag;
392 uint32_t portsc[NB_PORTS];
393 };
394 };
395
396 /*
397 * Internal states, shadow registers, etc
398 */
399 uint32_t sofv;
400 QEMUTimer *frame_timer;
401 int attach_poll_counter;
402 int astate; // Current state in asynchronous schedule
403 int pstate; // Current state in periodic schedule
404 USBPort ports[NB_PORTS];
405 uint32_t usbsts_pending;
406 QTAILQ_HEAD(, EHCIQueue) queues;
407
408 uint32_t a_fetch_addr; // which address to look at next
409 uint32_t p_fetch_addr; // which address to look at next
410
411 USBPacket ipacket;
412 uint8_t ibuffer[BUFF_SIZE];
413 int isoch_pause;
414
415 uint32_t last_run_usec;
416 uint32_t frame_end_usec;
417 };
418
419 #define SET_LAST_RUN_CLOCK(s) \
420 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
421
422 /* nifty macros from Arnon's EHCI version */
423 #define get_field(data, field) \
424 (((data) & field##_MASK) >> field##_SH)
425
426 #define set_field(data, newval, field) do { \
427 uint32_t val = *data; \
428 val &= ~ field##_MASK; \
429 val |= ((newval) << field##_SH) & field##_MASK; \
430 *data = val; \
431 } while(0)
432
433 static const char *ehci_state_names[] = {
434 [ EST_INACTIVE ] = "INACTIVE",
435 [ EST_ACTIVE ] = "ACTIVE",
436 [ EST_EXECUTING ] = "EXECUTING",
437 [ EST_SLEEPING ] = "SLEEPING",
438 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
439 [ EST_FETCHENTRY ] = "FETCH ENTRY",
440 [ EST_FETCHQH ] = "FETCH QH",
441 [ EST_FETCHITD ] = "FETCH ITD",
442 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
443 [ EST_FETCHQTD ] = "FETCH QTD",
444 [ EST_EXECUTE ] = "EXECUTE",
445 [ EST_WRITEBACK ] = "WRITEBACK",
446 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
447 };
448
449 static const char *ehci_mmio_names[] = {
450 [ CAPLENGTH ] = "CAPLENGTH",
451 [ HCIVERSION ] = "HCIVERSION",
452 [ HCSPARAMS ] = "HCSPARAMS",
453 [ HCCPARAMS ] = "HCCPARAMS",
454 [ USBCMD ] = "USBCMD",
455 [ USBSTS ] = "USBSTS",
456 [ USBINTR ] = "USBINTR",
457 [ FRINDEX ] = "FRINDEX",
458 [ PERIODICLISTBASE ] = "P-LIST BASE",
459 [ ASYNCLISTADDR ] = "A-LIST ADDR",
460 [ PORTSC_BEGIN ] = "PORTSC #0",
461 [ PORTSC_BEGIN + 4] = "PORTSC #1",
462 [ PORTSC_BEGIN + 8] = "PORTSC #2",
463 [ PORTSC_BEGIN + 12] = "PORTSC #3",
464 [ CONFIGFLAG ] = "CONFIGFLAG",
465 };
466
467 static const char *nr2str(const char **n, size_t len, uint32_t nr)
468 {
469 if (nr < len && n[nr] != NULL) {
470 return n[nr];
471 } else {
472 return "unknown";
473 }
474 }
475
476 static const char *state2str(uint32_t state)
477 {
478 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
479 }
480
481 static const char *addr2str(target_phys_addr_t addr)
482 {
483 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
484 }
485
486 static void ehci_trace_usbsts(uint32_t mask, int state)
487 {
488 /* interrupts */
489 if (mask & USBSTS_INT) {
490 trace_usb_ehci_usbsts("INT", state);
491 }
492 if (mask & USBSTS_ERRINT) {
493 trace_usb_ehci_usbsts("ERRINT", state);
494 }
495 if (mask & USBSTS_PCD) {
496 trace_usb_ehci_usbsts("PCD", state);
497 }
498 if (mask & USBSTS_FLR) {
499 trace_usb_ehci_usbsts("FLR", state);
500 }
501 if (mask & USBSTS_HSE) {
502 trace_usb_ehci_usbsts("HSE", state);
503 }
504 if (mask & USBSTS_IAA) {
505 trace_usb_ehci_usbsts("IAA", state);
506 }
507
508 /* status */
509 if (mask & USBSTS_HALT) {
510 trace_usb_ehci_usbsts("HALT", state);
511 }
512 if (mask & USBSTS_REC) {
513 trace_usb_ehci_usbsts("REC", state);
514 }
515 if (mask & USBSTS_PSS) {
516 trace_usb_ehci_usbsts("PSS", state);
517 }
518 if (mask & USBSTS_ASS) {
519 trace_usb_ehci_usbsts("ASS", state);
520 }
521 }
522
523 static inline void ehci_set_usbsts(EHCIState *s, int mask)
524 {
525 if ((s->usbsts & mask) == mask) {
526 return;
527 }
528 ehci_trace_usbsts(mask, 1);
529 s->usbsts |= mask;
530 }
531
532 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
533 {
534 if ((s->usbsts & mask) == 0) {
535 return;
536 }
537 ehci_trace_usbsts(mask, 0);
538 s->usbsts &= ~mask;
539 }
540
541 static inline void ehci_set_interrupt(EHCIState *s, int intr)
542 {
543 int level = 0;
544
545 // TODO honour interrupt threshold requests
546
547 ehci_set_usbsts(s, intr);
548
549 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
550 level = 1;
551 }
552
553 qemu_set_irq(s->irq, level);
554 }
555
556 static inline void ehci_record_interrupt(EHCIState *s, int intr)
557 {
558 s->usbsts_pending |= intr;
559 }
560
561 static inline void ehci_commit_interrupt(EHCIState *s)
562 {
563 if (!s->usbsts_pending) {
564 return;
565 }
566 ehci_set_interrupt(s, s->usbsts_pending);
567 s->usbsts_pending = 0;
568 }
569
570 static void ehci_set_state(EHCIState *s, int async, int state)
571 {
572 if (async) {
573 trace_usb_ehci_state("async", state2str(state));
574 s->astate = state;
575 } else {
576 trace_usb_ehci_state("periodic", state2str(state));
577 s->pstate = state;
578 }
579 }
580
581 static int ehci_get_state(EHCIState *s, int async)
582 {
583 return async ? s->astate : s->pstate;
584 }
585
586 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
587 {
588 if (async) {
589 s->a_fetch_addr = addr;
590 } else {
591 s->p_fetch_addr = addr;
592 }
593 }
594
595 static int ehci_get_fetch_addr(EHCIState *s, int async)
596 {
597 return async ? s->a_fetch_addr : s->p_fetch_addr;
598 }
599
600 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
601 {
602 trace_usb_ehci_qh(q, addr, qh->next,
603 qh->current_qtd, qh->next_qtd, qh->altnext_qtd,
604 get_field(qh->epchar, QH_EPCHAR_RL),
605 get_field(qh->epchar, QH_EPCHAR_MPLEN),
606 get_field(qh->epchar, QH_EPCHAR_EPS),
607 get_field(qh->epchar, QH_EPCHAR_EP),
608 get_field(qh->epchar, QH_EPCHAR_DEVADDR),
609 (bool)(qh->epchar & QH_EPCHAR_C),
610 (bool)(qh->epchar & QH_EPCHAR_H),
611 (bool)(qh->epchar & QH_EPCHAR_DTC),
612 (bool)(qh->epchar & QH_EPCHAR_I));
613 }
614
615 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
616 {
617 trace_usb_ehci_qtd(q, addr, qtd->next, qtd->altnext,
618 get_field(qtd->token, QTD_TOKEN_TBYTES),
619 get_field(qtd->token, QTD_TOKEN_CPAGE),
620 get_field(qtd->token, QTD_TOKEN_CERR),
621 get_field(qtd->token, QTD_TOKEN_PID),
622 (bool)(qtd->token & QTD_TOKEN_IOC),
623 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
624 (bool)(qtd->token & QTD_TOKEN_HALT),
625 (bool)(qtd->token & QTD_TOKEN_BABBLE),
626 (bool)(qtd->token & QTD_TOKEN_XACTERR));
627 }
628
629 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
630 {
631 trace_usb_ehci_itd(addr, itd->next);
632 }
633
634 /* queue management */
635
636 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
637 {
638 EHCIQueue *q;
639
640 q = qemu_mallocz(sizeof(*q));
641 q->ehci = ehci;
642 q->async_schedule = async;
643 QTAILQ_INSERT_HEAD(&ehci->queues, q, next);
644 trace_usb_ehci_queue_action(q, "alloc");
645 return q;
646 }
647
648 static void ehci_free_queue(EHCIQueue *q)
649 {
650 trace_usb_ehci_queue_action(q, "free");
651 if (q->async == EHCI_ASYNC_INFLIGHT) {
652 usb_cancel_packet(&q->packet);
653 }
654 QTAILQ_REMOVE(&q->ehci->queues, q, next);
655 qemu_free(q);
656 }
657
658 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr)
659 {
660 EHCIQueue *q;
661
662 QTAILQ_FOREACH(q, &ehci->queues, next) {
663 if (addr == q->qhaddr) {
664 return q;
665 }
666 }
667 return NULL;
668 }
669
670 static void ehci_queues_rip_unused(EHCIState *ehci)
671 {
672 EHCIQueue *q, *tmp;
673
674 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
675 if (q->seen) {
676 q->seen = 0;
677 q->ts = ehci->last_run_usec;
678 continue;
679 }
680 if (ehci->last_run_usec < q->ts + 250000) {
681 /* allow 0.25 sec idle */
682 continue;
683 }
684 ehci_free_queue(q);
685 }
686 }
687
688 static void ehci_queues_rip_all(EHCIState *ehci)
689 {
690 EHCIQueue *q, *tmp;
691
692 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
693 ehci_free_queue(q);
694 }
695 }
696
697 /* Attach or detach a device on root hub */
698
699 static void ehci_attach(USBPort *port)
700 {
701 EHCIState *s = port->opaque;
702 uint32_t *portsc = &s->portsc[port->index];
703
704 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
705
706 *portsc |= PORTSC_CONNECT;
707 *portsc |= PORTSC_CSC;
708
709 /*
710 * If a high speed device is attached then we own this port(indicated
711 * by zero in the PORTSC_POWNER bit field) so set the status bit
712 * and set an interrupt if enabled.
713 */
714 if ( !(*portsc & PORTSC_POWNER)) {
715 ehci_set_interrupt(s, USBSTS_PCD);
716 }
717 }
718
719 static void ehci_detach(USBPort *port)
720 {
721 EHCIState *s = port->opaque;
722 uint32_t *portsc = &s->portsc[port->index];
723
724 trace_usb_ehci_port_detach(port->index);
725
726 *portsc &= ~PORTSC_CONNECT;
727 *portsc |= PORTSC_CSC;
728
729 /*
730 * If a high speed device is attached then we own this port(indicated
731 * by zero in the PORTSC_POWNER bit field) so set the status bit
732 * and set an interrupt if enabled.
733 */
734 if ( !(*portsc & PORTSC_POWNER)) {
735 ehci_set_interrupt(s, USBSTS_PCD);
736 }
737 }
738
739 /* 4.1 host controller initialization */
740 static void ehci_reset(void *opaque)
741 {
742 EHCIState *s = opaque;
743 uint8_t *pci_conf;
744 int i;
745
746 trace_usb_ehci_reset();
747 pci_conf = s->dev.config;
748
749 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
750
751 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
752 s->usbsts = USBSTS_HALT;
753
754 s->astate = EST_INACTIVE;
755 s->pstate = EST_INACTIVE;
756 s->isoch_pause = -1;
757 s->attach_poll_counter = 0;
758
759 for(i = 0; i < NB_PORTS; i++) {
760 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
761
762 if (s->ports[i].dev) {
763 usb_attach(&s->ports[i], s->ports[i].dev);
764 }
765 }
766 ehci_queues_rip_all(s);
767 }
768
769 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
770 {
771 EHCIState *s = ptr;
772 uint32_t val;
773
774 val = s->mmio[addr];
775
776 return val;
777 }
778
779 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
780 {
781 EHCIState *s = ptr;
782 uint32_t val;
783
784 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
785
786 return val;
787 }
788
789 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
790 {
791 EHCIState *s = ptr;
792 uint32_t val;
793
794 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
795 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
796
797 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
798 return val;
799 }
800
801 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
802 {
803 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
804 exit(1);
805 }
806
807 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
808 {
809 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
810 exit(1);
811 }
812
813 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
814 {
815 uint32_t *portsc = &s->portsc[port];
816 int rwc;
817 USBDevice *dev = s->ports[port].dev;
818
819 rwc = val & PORTSC_RWC_MASK;
820 val &= PORTSC_RO_MASK;
821
822 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
823
824 *portsc &= ~rwc;
825
826 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
827 trace_usb_ehci_port_reset(port, 1);
828 }
829
830 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
831 trace_usb_ehci_port_reset(port, 0);
832 usb_attach(&s->ports[port], dev);
833
834 // TODO how to handle reset of ports with no device
835 if (dev) {
836 usb_send_msg(dev, USB_MSG_RESET);
837 }
838
839 if (s->ports[port].dev) {
840 *portsc &= ~PORTSC_CSC;
841 }
842
843 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
844 * to SW that this port has a high speed device attached
845 *
846 * TODO - when to disable?
847 */
848 val |= PORTSC_PED;
849 val |= PORTSC_PEDC;
850 }
851
852 *portsc &= ~PORTSC_RO_MASK;
853 *portsc |= val;
854 }
855
856 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
857 {
858 EHCIState *s = ptr;
859 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
860 uint32_t old = *mmio;
861 int i;
862
863 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
864
865 /* Only aligned reads are allowed on OHCI */
866 if (addr & 3) {
867 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
868 TARGET_FMT_plx "\n", addr);
869 return;
870 }
871
872 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
873 handle_port_status_write(s, (addr-PORTSC)/4, val);
874 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
875 return;
876 }
877
878 if (addr < OPREGBASE) {
879 fprintf(stderr, "usb-ehci: write attempt to read-only register"
880 TARGET_FMT_plx "\n", addr);
881 return;
882 }
883
884
885 /* Do any register specific pre-write processing here. */
886 switch(addr) {
887 case USBCMD:
888 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
889 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
890 SET_LAST_RUN_CLOCK(s);
891 ehci_clear_usbsts(s, USBSTS_HALT);
892 }
893
894 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
895 qemu_del_timer(s->frame_timer);
896 // TODO - should finish out some stuff before setting halt
897 ehci_set_usbsts(s, USBSTS_HALT);
898 }
899
900 if (val & USBCMD_HCRESET) {
901 ehci_reset(s);
902 val &= ~USBCMD_HCRESET;
903 }
904
905 /* not supporting dynamic frame list size at the moment */
906 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
907 fprintf(stderr, "attempt to set frame list size -- value %d\n",
908 val & USBCMD_FLS);
909 val &= ~USBCMD_FLS;
910 }
911 break;
912
913 case USBSTS:
914 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
915 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
916 val = s->usbsts;
917 ehci_set_interrupt(s, 0);
918 break;
919
920 case USBINTR:
921 val &= USBINTR_MASK;
922 break;
923
924 case FRINDEX:
925 s->sofv = val >> 3;
926 break;
927
928 case CONFIGFLAG:
929 val &= 0x1;
930 if (val) {
931 for(i = 0; i < NB_PORTS; i++)
932 s->portsc[i] &= ~PORTSC_POWNER;
933 }
934 break;
935
936 case PERIODICLISTBASE:
937 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
938 fprintf(stderr,
939 "ehci: PERIODIC list base register set while periodic schedule\n"
940 " is enabled and HC is enabled\n");
941 }
942 break;
943
944 case ASYNCLISTADDR:
945 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
946 fprintf(stderr,
947 "ehci: ASYNC list address register set while async schedule\n"
948 " is enabled and HC is enabled\n");
949 }
950 break;
951 }
952
953 *mmio = val;
954 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
955 }
956
957
958 // TODO : Put in common header file, duplication from usb-ohci.c
959
960 /* Get an array of dwords from main memory */
961 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
962 {
963 int i;
964
965 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
966 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
967 *buf = le32_to_cpu(*buf);
968 }
969
970 return 1;
971 }
972
973 /* Put an array of dwords in to main memory */
974 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
975 {
976 int i;
977
978 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
979 uint32_t tmp = cpu_to_le32(*buf);
980 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
981 }
982
983 return 1;
984 }
985
986 // 4.10.2
987
988 static int ehci_qh_do_overlay(EHCIQueue *q)
989 {
990 int i;
991 int dtoggle;
992 int ping;
993 int eps;
994 int reload;
995
996 // remember values in fields to preserve in qh after overlay
997
998 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
999 ping = q->qh.token & QTD_TOKEN_PING;
1000
1001 q->qh.current_qtd = q->qtdaddr;
1002 q->qh.next_qtd = q->qtd.next;
1003 q->qh.altnext_qtd = q->qtd.altnext;
1004 q->qh.token = q->qtd.token;
1005
1006
1007 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1008 if (eps == EHCI_QH_EPS_HIGH) {
1009 q->qh.token &= ~QTD_TOKEN_PING;
1010 q->qh.token |= ping;
1011 }
1012
1013 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1014 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1015
1016 for (i = 0; i < 5; i++) {
1017 q->qh.bufptr[i] = q->qtd.bufptr[i];
1018 }
1019
1020 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1021 // preserve QH DT bit
1022 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1023 q->qh.token |= dtoggle;
1024 }
1025
1026 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1027 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1028
1029 put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1030
1031 return 0;
1032 }
1033
1034 static int ehci_buffer_rw(EHCIQueue *q, int bytes, int rw)
1035 {
1036 int bufpos = 0;
1037 int cpage, offset;
1038 uint32_t head;
1039 uint32_t tail;
1040
1041
1042 if (!bytes) {
1043 return 0;
1044 }
1045
1046 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1047 if (cpage > 4) {
1048 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1049 return USB_RET_PROCERR;
1050 }
1051
1052 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1053
1054 do {
1055 /* start and end of this page */
1056 head = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1057 tail = head + ~QTD_BUFPTR_MASK + 1;
1058 /* add offset into page */
1059 head |= offset;
1060
1061 if (bytes <= (tail - head)) {
1062 tail = head + bytes;
1063 }
1064
1065 trace_usb_ehci_data(rw, cpage, offset, head, tail-head, bufpos);
1066 cpu_physical_memory_rw(head, q->buffer + bufpos, tail - head, rw);
1067
1068 bufpos += (tail - head);
1069 offset += (tail - head);
1070 bytes -= (tail - head);
1071
1072 if (bytes > 0) {
1073 cpage++;
1074 offset = 0;
1075 }
1076 } while (bytes > 0);
1077
1078 /* save cpage */
1079 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1080
1081 /* save offset into cpage */
1082 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1083 q->qh.bufptr[0] |= offset;
1084
1085 return 0;
1086 }
1087
1088 static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
1089 {
1090 EHCIQueue *q = container_of(packet, EHCIQueue, packet);
1091
1092 trace_usb_ehci_queue_action(q, "wakeup");
1093 assert(q->async == EHCI_ASYNC_INFLIGHT);
1094 q->async = EHCI_ASYNC_FINISHED;
1095 q->usb_status = packet->len;
1096 }
1097
1098 static void ehci_execute_complete(EHCIQueue *q)
1099 {
1100 int c_err, reload;
1101
1102 assert(q->async != EHCI_ASYNC_INFLIGHT);
1103 q->async = EHCI_ASYNC_NONE;
1104
1105 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1106 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1107
1108 if (q->usb_status < 0) {
1109 err:
1110 /* TO-DO: put this is in a function that can be invoked below as well */
1111 c_err = get_field(q->qh.token, QTD_TOKEN_CERR);
1112 c_err--;
1113 set_field(&q->qh.token, c_err, QTD_TOKEN_CERR);
1114
1115 switch(q->usb_status) {
1116 case USB_RET_NODEV:
1117 fprintf(stderr, "USB no device\n");
1118 break;
1119 case USB_RET_STALL:
1120 fprintf(stderr, "USB stall\n");
1121 q->qh.token |= QTD_TOKEN_HALT;
1122 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1123 break;
1124 case USB_RET_NAK:
1125 /* 4.10.3 */
1126 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1127 if ((q->pid == USB_TOKEN_IN) && reload) {
1128 int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1129 nakcnt--;
1130 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1131 } else if (!reload) {
1132 return;
1133 }
1134 break;
1135 case USB_RET_BABBLE:
1136 fprintf(stderr, "USB babble TODO\n");
1137 q->qh.token |= QTD_TOKEN_BABBLE;
1138 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1139 break;
1140 default:
1141 /* should not be triggerable */
1142 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1143 assert(0);
1144 break;
1145 }
1146 } else {
1147 // DPRINTF("Short packet condition\n");
1148 // TODO check 4.12 for splits
1149
1150 if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1151 q->usb_status = USB_RET_BABBLE;
1152 goto err;
1153 }
1154
1155 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1156 if (ehci_buffer_rw(q, q->usb_status, 1) != 0) {
1157 q->usb_status = USB_RET_PROCERR;
1158 return;
1159 }
1160 q->tbytes -= q->usb_status;
1161 } else {
1162 q->tbytes = 0;
1163 }
1164
1165 DPRINTF("updating tbytes to %d\n", q->tbytes);
1166 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1167 }
1168
1169 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1170 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1171
1172 if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) {
1173 ehci_record_interrupt(q->ehci, USBSTS_INT);
1174 }
1175 }
1176
1177 // 4.10.3
1178
1179 static int ehci_execute(EHCIQueue *q)
1180 {
1181 USBPort *port;
1182 USBDevice *dev;
1183 int ret;
1184 int i;
1185 int endp;
1186 int devadr;
1187
1188 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1189 fprintf(stderr, "Attempting to execute inactive QH\n");
1190 return USB_RET_PROCERR;
1191 }
1192
1193 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1194 if (q->tbytes > BUFF_SIZE) {
1195 fprintf(stderr, "Request for more bytes than allowed\n");
1196 return USB_RET_PROCERR;
1197 }
1198
1199 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1200 switch(q->pid) {
1201 case 0: q->pid = USB_TOKEN_OUT; break;
1202 case 1: q->pid = USB_TOKEN_IN; break;
1203 case 2: q->pid = USB_TOKEN_SETUP; break;
1204 default: fprintf(stderr, "bad token\n"); break;
1205 }
1206
1207 if ((q->tbytes && q->pid != USB_TOKEN_IN) &&
1208 (ehci_buffer_rw(q, q->tbytes, 0) != 0)) {
1209 return USB_RET_PROCERR;
1210 }
1211
1212 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1213 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1214
1215 ret = USB_RET_NODEV;
1216
1217 // TO-DO: associating device with ehci port
1218 for(i = 0; i < NB_PORTS; i++) {
1219 port = &q->ehci->ports[i];
1220 dev = port->dev;
1221
1222 // TODO sometime we will also need to check if we are the port owner
1223
1224 if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) {
1225 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1226 i, q->ehci->portsc[i]);
1227 continue;
1228 }
1229
1230 q->packet.pid = q->pid;
1231 q->packet.devaddr = devadr;
1232 q->packet.devep = endp;
1233 q->packet.data = q->buffer;
1234 q->packet.len = q->tbytes;
1235
1236 ret = usb_handle_packet(dev, &q->packet);
1237
1238 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1239 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1240 q->packet.len, q->tbytes, endp, ret);
1241
1242 if (ret != USB_RET_NODEV) {
1243 break;
1244 }
1245 }
1246
1247 if (ret > BUFF_SIZE) {
1248 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1249 return USB_RET_PROCERR;
1250 }
1251
1252 return ret;
1253 }
1254
1255 /* 4.7.2
1256 */
1257
1258 static int ehci_process_itd(EHCIState *ehci,
1259 EHCIitd *itd)
1260 {
1261 USBPort *port;
1262 USBDevice *dev;
1263 int ret;
1264 int i, j;
1265 int ptr;
1266 int pid;
1267 int pg;
1268 int len;
1269 int dir;
1270 int devadr;
1271 int endp;
1272 int maxpkt;
1273
1274 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1275 devadr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1276 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1277 maxpkt = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1278
1279 for(i = 0; i < 8; i++) {
1280 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1281 DPRINTF("ISOCHRONOUS active for frame %d, interval %d\n",
1282 ehci->frindex >> 3, i);
1283
1284 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1285 ptr = (itd->bufptr[pg] & ITD_BUFPTR_MASK) |
1286 (itd->transact[i] & ITD_XACT_OFFSET_MASK);
1287 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1288
1289 if (len > BUFF_SIZE) {
1290 return USB_RET_PROCERR;
1291 }
1292
1293 DPRINTF("ISOCH: buffer %08X len %d\n", ptr, len);
1294
1295 if (!dir) {
1296 cpu_physical_memory_rw(ptr, &ehci->ibuffer[0], len, 0);
1297 pid = USB_TOKEN_OUT;
1298 } else
1299 pid = USB_TOKEN_IN;
1300
1301 ret = USB_RET_NODEV;
1302
1303 for (j = 0; j < NB_PORTS; j++) {
1304 port = &ehci->ports[j];
1305 dev = port->dev;
1306
1307 // TODO sometime we will also need to check if we are the port owner
1308
1309 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1310 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1311 j, ehci->portsc[j]);
1312 continue;
1313 }
1314
1315 ehci->ipacket.pid = pid;
1316 ehci->ipacket.devaddr = devadr;
1317 ehci->ipacket.devep = endp;
1318 ehci->ipacket.data = ehci->ibuffer;
1319 ehci->ipacket.len = len;
1320
1321 DPRINTF("calling usb_handle_packet\n");
1322 ret = usb_handle_packet(dev, &ehci->ipacket);
1323
1324 if (ret != USB_RET_NODEV) {
1325 break;
1326 }
1327 }
1328
1329 /* In isoch, there is no facility to indicate a NAK so let's
1330 * instead just complete a zero-byte transaction. Setting
1331 * DBERR seems too draconian.
1332 */
1333
1334 if (ret == USB_RET_NAK) {
1335 if (ehci->isoch_pause > 0) {
1336 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1337 ehci->isoch_pause--;
1338 return 0;
1339 } else if (ehci->isoch_pause == -1) {
1340 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1341 // Pause frindex for up to 50 msec waiting for data from
1342 // remote
1343 ehci->isoch_pause = 50;
1344 return 0;
1345 } else {
1346 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1347 ret = 0;
1348 }
1349 } else {
1350 DPRINTF("ISOCH: received ACK, clearing pause\n");
1351 ehci->isoch_pause = -1;
1352 }
1353
1354 if (ret >= 0) {
1355 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1356
1357 if (itd->transact[i] & ITD_XACT_IOC) {
1358 ehci_record_interrupt(ehci, USBSTS_INT);
1359 }
1360 }
1361
1362 if (ret >= 0 && dir) {
1363 cpu_physical_memory_rw(ptr, &ehci->ibuffer[0], len, 1);
1364
1365 if (ret != len) {
1366 DPRINTF("ISOCH IN expected %d, got %d\n",
1367 len, ret);
1368 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1369 }
1370 }
1371 }
1372 }
1373 return 0;
1374 }
1375
1376 /* This state is the entry point for asynchronous schedule
1377 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1378 */
1379 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1380 {
1381 EHCIqh qh;
1382 int i = 0;
1383 int again = 0;
1384 uint32_t entry = ehci->asynclistaddr;
1385
1386 /* set reclamation flag at start event (4.8.6) */
1387 if (async) {
1388 ehci_set_usbsts(ehci, USBSTS_REC);
1389 }
1390
1391 ehci_queues_rip_unused(ehci);
1392
1393 /* Find the head of the list (4.9.1.1) */
1394 for(i = 0; i < MAX_QH; i++) {
1395 get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1396 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1397
1398 if (qh.epchar & QH_EPCHAR_H) {
1399 if (async) {
1400 entry |= (NLPTR_TYPE_QH << 1);
1401 }
1402
1403 ehci_set_fetch_addr(ehci, async, entry);
1404 ehci_set_state(ehci, async, EST_FETCHENTRY);
1405 again = 1;
1406 goto out;
1407 }
1408
1409 entry = qh.next;
1410 if (entry == ehci->asynclistaddr) {
1411 break;
1412 }
1413 }
1414
1415 /* no head found for list. */
1416
1417 ehci_set_state(ehci, async, EST_ACTIVE);
1418
1419 out:
1420 return again;
1421 }
1422
1423
1424 /* This state is the entry point for periodic schedule processing as
1425 * well as being a continuation state for async processing.
1426 */
1427 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1428 {
1429 int again = 0;
1430 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1431
1432 #if EHCI_DEBUG == 0
1433 if (qemu_get_clock_ns(vm_clock) / 1000 >= ehci->frame_end_usec) {
1434 if (async) {
1435 DPRINTF("FETCHENTRY: FRAME timer elapsed, exit state machine\n");
1436 goto out;
1437 } else {
1438 DPRINTF("FETCHENTRY: WARNING "
1439 "- frame timer elapsed during periodic\n");
1440 }
1441 }
1442 #endif
1443 if (entry < 0x1000) {
1444 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1445 ehci_set_state(ehci, async, EST_ACTIVE);
1446 goto out;
1447 }
1448
1449 /* section 4.8, only QH in async schedule */
1450 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1451 fprintf(stderr, "non queue head request in async schedule\n");
1452 return -1;
1453 }
1454
1455 switch (NLPTR_TYPE_GET(entry)) {
1456 case NLPTR_TYPE_QH:
1457 ehci_set_state(ehci, async, EST_FETCHQH);
1458 again = 1;
1459 break;
1460
1461 case NLPTR_TYPE_ITD:
1462 ehci_set_state(ehci, async, EST_FETCHITD);
1463 again = 1;
1464 break;
1465
1466 default:
1467 // TODO: handle siTD and FSTN types
1468 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1469 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1470 return -1;
1471 }
1472
1473 out:
1474 return again;
1475 }
1476
1477 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1478 {
1479 uint32_t entry;
1480 EHCIQueue *q;
1481 int reload;
1482
1483 entry = ehci_get_fetch_addr(ehci, async);
1484 q = ehci_find_queue_by_qh(ehci, entry);
1485 if (NULL == q) {
1486 q = ehci_alloc_queue(ehci, async);
1487 }
1488 q->qhaddr = entry;
1489 q->seen++;
1490
1491 if (q->seen > 1) {
1492 /* we are going in circles -- stop processing */
1493 ehci_set_state(ehci, async, EST_ACTIVE);
1494 q = NULL;
1495 goto out;
1496 }
1497
1498 get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1499 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1500
1501 if (q->async == EHCI_ASYNC_INFLIGHT) {
1502 /* I/O still in progress -- skip queue */
1503 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1504 goto out;
1505 }
1506 if (q->async == EHCI_ASYNC_FINISHED) {
1507 /* I/O finished -- continue processing queue */
1508 trace_usb_ehci_queue_action(q, "resume");
1509 ehci_set_state(ehci, async, EST_EXECUTING);
1510 goto out;
1511 }
1512
1513 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1514
1515 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1516 if (ehci->usbsts & USBSTS_REC) {
1517 ehci_clear_usbsts(ehci, USBSTS_REC);
1518 } else {
1519 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1520 " - done processing\n", q->qhaddr);
1521 ehci_set_state(ehci, async, EST_ACTIVE);
1522 q = NULL;
1523 goto out;
1524 }
1525 }
1526
1527 #if EHCI_DEBUG
1528 if (q->qhaddr != q->qh.next) {
1529 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1530 q->qhaddr,
1531 q->qh.epchar & QH_EPCHAR_H,
1532 q->qh.token & QTD_TOKEN_HALT,
1533 q->qh.token & QTD_TOKEN_ACTIVE,
1534 q->qh.next);
1535 }
1536 #endif
1537
1538 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1539 if (reload) {
1540 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1541 }
1542
1543 if (q->qh.token & QTD_TOKEN_HALT) {
1544 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1545
1546 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) {
1547 q->qtdaddr = q->qh.current_qtd;
1548 ehci_set_state(ehci, async, EST_FETCHQTD);
1549
1550 } else {
1551 /* EHCI spec version 1.0 Section 4.10.2 */
1552 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1553 }
1554
1555 out:
1556 return q;
1557 }
1558
1559 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1560 {
1561 uint32_t entry;
1562 EHCIitd itd;
1563
1564 assert(!async);
1565 entry = ehci_get_fetch_addr(ehci, async);
1566
1567 get_dwords(NLPTR_GET(entry),(uint32_t *) &itd,
1568 sizeof(EHCIitd) >> 2);
1569 ehci_trace_itd(ehci, entry, &itd);
1570
1571 if (ehci_process_itd(ehci, &itd) != 0) {
1572 return -1;
1573 }
1574
1575 put_dwords(NLPTR_GET(entry), (uint32_t *) &itd,
1576 sizeof(EHCIitd) >> 2);
1577 ehci_set_fetch_addr(ehci, async, itd.next);
1578 ehci_set_state(ehci, async, EST_FETCHENTRY);
1579
1580 return 1;
1581 }
1582
1583 /* Section 4.10.2 - paragraph 3 */
1584 static int ehci_state_advqueue(EHCIQueue *q, int async)
1585 {
1586 #if 0
1587 /* TO-DO: 4.10.2 - paragraph 2
1588 * if I-bit is set to 1 and QH is not active
1589 * go to horizontal QH
1590 */
1591 if (I-bit set) {
1592 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1593 goto out;
1594 }
1595 #endif
1596
1597 /*
1598 * want data and alt-next qTD is valid
1599 */
1600 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1601 (q->qh.altnext_qtd > 0x1000) &&
1602 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1603 q->qtdaddr = q->qh.altnext_qtd;
1604 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1605
1606 /*
1607 * next qTD is valid
1608 */
1609 } else if ((q->qh.next_qtd > 0x1000) &&
1610 (NLPTR_TBIT(q->qh.next_qtd) == 0)) {
1611 q->qtdaddr = q->qh.next_qtd;
1612 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1613
1614 /*
1615 * no valid qTD, try next QH
1616 */
1617 } else {
1618 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1619 }
1620
1621 return 1;
1622 }
1623
1624 /* Section 4.10.2 - paragraph 4 */
1625 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1626 {
1627 int again = 0;
1628
1629 get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2);
1630 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1631
1632 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1633 ehci_set_state(q->ehci, async, EST_EXECUTE);
1634 again = 1;
1635 } else {
1636 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1637 again = 1;
1638 }
1639
1640 return again;
1641 }
1642
1643 static int ehci_state_horizqh(EHCIQueue *q, int async)
1644 {
1645 int again = 0;
1646
1647 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1648 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1649 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1650 again = 1;
1651 } else {
1652 ehci_set_state(q->ehci, async, EST_ACTIVE);
1653 }
1654
1655 return again;
1656 }
1657
1658 /*
1659 * Write the qh back to guest physical memory. This step isn't
1660 * in the EHCI spec but we need to do it since we don't share
1661 * physical memory with our guest VM.
1662 *
1663 * The first three dwords are read-only for the EHCI, so skip them
1664 * when writing back the qh.
1665 */
1666 static void ehci_flush_qh(EHCIQueue *q)
1667 {
1668 uint32_t *qh = (uint32_t *) &q->qh;
1669 uint32_t dwords = sizeof(EHCIqh) >> 2;
1670 uint32_t addr = NLPTR_GET(q->qhaddr);
1671
1672 put_dwords(addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1673 }
1674
1675 static int ehci_state_execute(EHCIQueue *q, int async)
1676 {
1677 int again = 0;
1678 int reload, nakcnt;
1679 int smask;
1680
1681 if (ehci_qh_do_overlay(q) != 0) {
1682 return -1;
1683 }
1684
1685 smask = get_field(q->qh.epcap, QH_EPCAP_SMASK);
1686
1687 if (!smask) {
1688 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1689 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1690 if (reload && !nakcnt) {
1691 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1692 again = 1;
1693 goto out;
1694 }
1695 }
1696
1697 // TODO verify enough time remains in the uframe as in 4.4.1.1
1698 // TODO write back ptr to async list when done or out of time
1699 // TODO Windows does not seem to ever set the MULT field
1700
1701 if (!async) {
1702 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1703 if (!transactCtr) {
1704 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1705 again = 1;
1706 goto out;
1707 }
1708 }
1709
1710 if (async) {
1711 ehci_set_usbsts(q->ehci, USBSTS_REC);
1712 }
1713
1714 q->usb_status = ehci_execute(q);
1715 if (q->usb_status == USB_RET_PROCERR) {
1716 again = -1;
1717 goto out;
1718 }
1719 if (q->usb_status == USB_RET_ASYNC) {
1720 ehci_flush_qh(q);
1721 trace_usb_ehci_queue_action(q, "suspend");
1722 q->async = EHCI_ASYNC_INFLIGHT;
1723 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1724 again = 1;
1725 goto out;
1726 }
1727
1728 ehci_set_state(q->ehci, async, EST_EXECUTING);
1729 again = 1;
1730
1731 out:
1732 return again;
1733 }
1734
1735 static int ehci_state_executing(EHCIQueue *q, int async)
1736 {
1737 int again = 0;
1738 int reload, nakcnt;
1739
1740 ehci_execute_complete(q);
1741 if (q->usb_status == USB_RET_ASYNC) {
1742 goto out;
1743 }
1744 if (q->usb_status == USB_RET_PROCERR) {
1745 again = -1;
1746 goto out;
1747 }
1748
1749 // 4.10.3
1750 if (!async) {
1751 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1752 transactCtr--;
1753 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1754 // 4.10.3, bottom of page 82, should exit this state when transaction
1755 // counter decrements to 0
1756 }
1757
1758 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1759 if (reload) {
1760 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1761 if (q->usb_status == USB_RET_NAK) {
1762 if (nakcnt) {
1763 nakcnt--;
1764 }
1765 } else {
1766 nakcnt = reload;
1767 }
1768 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1769 }
1770
1771 /* 4.10.5 */
1772 if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) {
1773 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1774 } else {
1775 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1776 }
1777
1778 again = 1;
1779
1780 out:
1781 ehci_flush_qh(q);
1782 return again;
1783 }
1784
1785
1786 static int ehci_state_writeback(EHCIQueue *q, int async)
1787 {
1788 int again = 0;
1789
1790 /* Write back the QTD from the QH area */
1791 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1792 put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd,
1793 sizeof(EHCIqtd) >> 2);
1794
1795 /* TODO confirm next state. For now, keep going if async
1796 * but stop after one qtd if periodic
1797 */
1798 //if (async) {
1799 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1800 again = 1;
1801 //} else {
1802 // ehci_set_state(ehci, async, EST_ACTIVE);
1803 //}
1804 return again;
1805 }
1806
1807 /*
1808 * This is the state machine that is common to both async and periodic
1809 */
1810
1811 static void ehci_advance_state(EHCIState *ehci,
1812 int async)
1813 {
1814 EHCIQueue *q = NULL;
1815 int again;
1816 int iter = 0;
1817
1818 do {
1819 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1820 iter++;
1821 /* if we are roaming a lot of QH without executing a qTD
1822 * something is wrong with the linked list. TO-DO: why is
1823 * this hack needed?
1824 */
1825 assert(iter < MAX_ITERATIONS);
1826 #if 0
1827 if (iter > MAX_ITERATIONS) {
1828 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1829 ehci_set_state(ehci, async, EST_ACTIVE);
1830 break;
1831 }
1832 #endif
1833 }
1834 switch(ehci_get_state(ehci, async)) {
1835 case EST_WAITLISTHEAD:
1836 again = ehci_state_waitlisthead(ehci, async);
1837 break;
1838
1839 case EST_FETCHENTRY:
1840 again = ehci_state_fetchentry(ehci, async);
1841 break;
1842
1843 case EST_FETCHQH:
1844 q = ehci_state_fetchqh(ehci, async);
1845 again = q ? 1 : 0;
1846 break;
1847
1848 case EST_FETCHITD:
1849 again = ehci_state_fetchitd(ehci, async);
1850 break;
1851
1852 case EST_ADVANCEQUEUE:
1853 again = ehci_state_advqueue(q, async);
1854 break;
1855
1856 case EST_FETCHQTD:
1857 again = ehci_state_fetchqtd(q, async);
1858 break;
1859
1860 case EST_HORIZONTALQH:
1861 again = ehci_state_horizqh(q, async);
1862 break;
1863
1864 case EST_EXECUTE:
1865 iter = 0;
1866 again = ehci_state_execute(q, async);
1867 break;
1868
1869 case EST_EXECUTING:
1870 assert(q != NULL);
1871 again = ehci_state_executing(q, async);
1872 break;
1873
1874 case EST_WRITEBACK:
1875 again = ehci_state_writeback(q, async);
1876 break;
1877
1878 default:
1879 fprintf(stderr, "Bad state!\n");
1880 again = -1;
1881 assert(0);
1882 break;
1883 }
1884
1885 if (again < 0) {
1886 fprintf(stderr, "processing error - resetting ehci HC\n");
1887 ehci_reset(ehci);
1888 again = 0;
1889 assert(0);
1890 }
1891 }
1892 while (again);
1893
1894 ehci_commit_interrupt(ehci);
1895 }
1896
1897 static void ehci_advance_async_state(EHCIState *ehci)
1898 {
1899 int async = 1;
1900
1901 switch(ehci_get_state(ehci, async)) {
1902 case EST_INACTIVE:
1903 if (!(ehci->usbcmd & USBCMD_ASE)) {
1904 break;
1905 }
1906 ehci_set_usbsts(ehci, USBSTS_ASS);
1907 ehci_set_state(ehci, async, EST_ACTIVE);
1908 // No break, fall through to ACTIVE
1909
1910 case EST_ACTIVE:
1911 if ( !(ehci->usbcmd & USBCMD_ASE)) {
1912 ehci_clear_usbsts(ehci, USBSTS_ASS);
1913 ehci_set_state(ehci, async, EST_INACTIVE);
1914 break;
1915 }
1916
1917 /* If the doorbell is set, the guest wants to make a change to the
1918 * schedule. The host controller needs to release cached data.
1919 * (section 4.8.2)
1920 */
1921 if (ehci->usbcmd & USBCMD_IAAD) {
1922 DPRINTF("ASYNC: doorbell request acknowledged\n");
1923 ehci->usbcmd &= ~USBCMD_IAAD;
1924 ehci_set_interrupt(ehci, USBSTS_IAA);
1925 break;
1926 }
1927
1928 /* make sure guest has acknowledged */
1929 /* TO-DO: is this really needed? */
1930 if (ehci->usbsts & USBSTS_IAA) {
1931 DPRINTF("IAA status bit still set.\n");
1932 break;
1933 }
1934
1935 /* check that address register has been set */
1936 if (ehci->asynclistaddr == 0) {
1937 break;
1938 }
1939
1940 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
1941 /* fall through */
1942
1943 case EST_FETCHENTRY:
1944 /* fall through */
1945
1946 case EST_EXECUTING:
1947 ehci_advance_state(ehci, async);
1948 break;
1949
1950 default:
1951 /* this should only be due to a developer mistake */
1952 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1953 "Resetting to active\n", ehci->astate);
1954 assert(0);
1955 }
1956 }
1957
1958 static void ehci_advance_periodic_state(EHCIState *ehci)
1959 {
1960 uint32_t entry;
1961 uint32_t list;
1962 int async = 0;
1963
1964 // 4.6
1965
1966 switch(ehci_get_state(ehci, async)) {
1967 case EST_INACTIVE:
1968 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
1969 ehci_set_usbsts(ehci, USBSTS_PSS);
1970 ehci_set_state(ehci, async, EST_ACTIVE);
1971 // No break, fall through to ACTIVE
1972 } else
1973 break;
1974
1975 case EST_ACTIVE:
1976 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
1977 ehci_clear_usbsts(ehci, USBSTS_PSS);
1978 ehci_set_state(ehci, async, EST_INACTIVE);
1979 break;
1980 }
1981
1982 list = ehci->periodiclistbase & 0xfffff000;
1983 /* check that register has been set */
1984 if (list == 0) {
1985 break;
1986 }
1987 list |= ((ehci->frindex & 0x1ff8) >> 1);
1988
1989 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
1990 entry = le32_to_cpu(entry);
1991
1992 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
1993 ehci->frindex / 8, list, entry);
1994 ehci_set_fetch_addr(ehci, async,entry);
1995 ehci_set_state(ehci, async, EST_FETCHENTRY);
1996 ehci_advance_state(ehci, async);
1997 break;
1998
1999 case EST_EXECUTING:
2000 DPRINTF("PERIODIC state adv for executing\n");
2001 ehci_advance_state(ehci, async);
2002 break;
2003
2004 default:
2005 /* this should only be due to a developer mistake */
2006 fprintf(stderr, "ehci: Bad periodic state %d. "
2007 "Resetting to active\n", ehci->pstate);
2008 assert(0);
2009 }
2010 }
2011
2012 static void ehci_frame_timer(void *opaque)
2013 {
2014 EHCIState *ehci = opaque;
2015 int64_t expire_time, t_now;
2016 int usec_elapsed;
2017 int frames;
2018 int usec_now;
2019 int i;
2020 int skipped_frames = 0;
2021
2022
2023 t_now = qemu_get_clock_ns(vm_clock);
2024 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
2025 if (expire_time == t_now) {
2026 expire_time++;
2027 }
2028
2029 usec_now = t_now / 1000;
2030 usec_elapsed = usec_now - ehci->last_run_usec;
2031 frames = usec_elapsed / FRAME_TIMER_USEC;
2032 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
2033
2034 for (i = 0; i < frames; i++) {
2035 if ( !(ehci->usbsts & USBSTS_HALT)) {
2036 if (ehci->isoch_pause <= 0) {
2037 ehci->frindex += 8;
2038 }
2039
2040 if (ehci->frindex > 0x00001fff) {
2041 ehci->frindex = 0;
2042 ehci_set_interrupt(ehci, USBSTS_FLR);
2043 }
2044
2045 ehci->sofv = (ehci->frindex - 1) >> 3;
2046 ehci->sofv &= 0x000003ff;
2047 }
2048
2049 if (frames - i > 10) {
2050 skipped_frames++;
2051 } else {
2052 // TODO could this cause periodic frames to get skipped if async
2053 // active?
2054 if (ehci_get_state(ehci, 1) != EST_EXECUTING) {
2055 ehci_advance_periodic_state(ehci);
2056 }
2057 }
2058
2059 ehci->last_run_usec += FRAME_TIMER_USEC;
2060 }
2061
2062 #if 0
2063 if (skipped_frames) {
2064 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2065 }
2066 #endif
2067
2068 /* Async is not inside loop since it executes everything it can once
2069 * called
2070 */
2071 if (ehci_get_state(ehci, 0) != EST_EXECUTING) {
2072 ehci_advance_async_state(ehci);
2073 }
2074
2075 qemu_mod_timer(ehci->frame_timer, expire_time);
2076 }
2077
2078 static CPUReadMemoryFunc *ehci_readfn[3]={
2079 ehci_mem_readb,
2080 ehci_mem_readw,
2081 ehci_mem_readl
2082 };
2083
2084 static CPUWriteMemoryFunc *ehci_writefn[3]={
2085 ehci_mem_writeb,
2086 ehci_mem_writew,
2087 ehci_mem_writel
2088 };
2089
2090 static void ehci_map(PCIDevice *pci_dev, int region_num,
2091 pcibus_t addr, pcibus_t size, int type)
2092 {
2093 EHCIState *s =(EHCIState *)pci_dev;
2094
2095 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
2096 region_num, addr, size, s->mem);
2097 s->mem_base = addr;
2098 cpu_register_physical_memory(addr, size, s->mem);
2099 }
2100
2101 static int usb_ehci_initfn(PCIDevice *dev);
2102
2103 static USBPortOps ehci_port_ops = {
2104 .attach = ehci_attach,
2105 .detach = ehci_detach,
2106 .complete = ehci_async_complete_packet,
2107 };
2108
2109 static PCIDeviceInfo ehci_info = {
2110 .qdev.name = "usb-ehci",
2111 .qdev.size = sizeof(EHCIState),
2112 .init = usb_ehci_initfn,
2113 };
2114
2115 static int usb_ehci_initfn(PCIDevice *dev)
2116 {
2117 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2118 uint8_t *pci_conf = s->dev.config;
2119 int i;
2120
2121 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
2122 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82801D);
2123 pci_set_byte(&pci_conf[PCI_REVISION_ID], 0x10);
2124 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2125 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
2126 pci_set_byte(&pci_conf[PCI_HEADER_TYPE], PCI_HEADER_TYPE_NORMAL);
2127
2128 /* capabilities pointer */
2129 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2130 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2131
2132 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2133 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2134 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2135
2136 // pci_conf[0x50] = 0x01; // power management caps
2137
2138 pci_set_byte(&pci_conf[0x60], 0x20); // spec release number (2.1.4)
2139 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2140 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2141
2142 pci_conf[0x64] = 0x00;
2143 pci_conf[0x65] = 0x00;
2144 pci_conf[0x66] = 0x00;
2145 pci_conf[0x67] = 0x00;
2146 pci_conf[0x68] = 0x01;
2147 pci_conf[0x69] = 0x00;
2148 pci_conf[0x6a] = 0x00;
2149 pci_conf[0x6b] = 0x00; // USBLEGSUP
2150 pci_conf[0x6c] = 0x00;
2151 pci_conf[0x6d] = 0x00;
2152 pci_conf[0x6e] = 0x00;
2153 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2154
2155 // 2.2 host controller interface version
2156 s->mmio[0x00] = (uint8_t) OPREGBASE;
2157 s->mmio[0x01] = 0x00;
2158 s->mmio[0x02] = 0x00;
2159 s->mmio[0x03] = 0x01; // HC version
2160 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2161 s->mmio[0x05] = 0x00; // No companion ports at present
2162 s->mmio[0x06] = 0x00;
2163 s->mmio[0x07] = 0x00;
2164 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2165 s->mmio[0x09] = 0x68; // EECP
2166 s->mmio[0x0a] = 0x00;
2167 s->mmio[0x0b] = 0x00;
2168
2169 s->irq = s->dev.irq[3];
2170
2171 usb_bus_new(&s->bus, &s->dev.qdev);
2172 for(i = 0; i < NB_PORTS; i++) {
2173 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2174 USB_SPEED_MASK_HIGH);
2175 usb_port_location(&s->ports[i], NULL, i+1);
2176 s->ports[i].dev = 0;
2177 }
2178
2179 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2180 QTAILQ_INIT(&s->queues);
2181
2182 qemu_register_reset(ehci_reset, s);
2183
2184 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2185 DEVICE_LITTLE_ENDIAN);
2186
2187 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2188 ehci_map);
2189
2190 fprintf(stderr, "*** EHCI support is under development ***\n");
2191
2192 return 0;
2193 }
2194
2195 static void ehci_register(void)
2196 {
2197 pci_qdev_register(&ehci_info);
2198 }
2199 device_init(ehci_register);
2200
2201 /*
2202 * vim: expandtab ts=4
2203 */
QEmu