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hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
[qemu.git] / hw / riscv / sifive_u.c
blob37f5087172e5dd3bff283f0749f84fe13ccadcfa
1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:
9 *
10 * 0) UART
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) GPIO (General Purpose Input/Output Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
16 * 6) GEM (Gigabit Ethernet Controller) and management block
17 * 7) DMA (Direct Memory Access Controller)
18 * 8) SPI0 connected to an SPI flash
19 * 9) SPI2 connected to an SD card
20 * 10) PWM0 and PWM1
21 *
22 * This board currently generates devicetree dynamically that indicates at least
23 * two harts and up to five harts.
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms and conditions of the GNU General Public License,
27 * version 2 or later, as published by the Free Software Foundation.
28 *
29 * This program is distributed in the hope it will be useful, but WITHOUT
30 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
31 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
32 * more details.
33 *
34 * You should have received a copy of the GNU General Public License along with
35 * this program. If not, see <http://www.gnu.org/licenses/>.
36 */
37
38 #include "qemu/osdep.h"
39 #include "qemu/error-report.h"
40 #include "qapi/error.h"
41 #include "qapi/visitor.h"
42 #include "hw/boards.h"
43 #include "hw/irq.h"
44 #include "hw/loader.h"
45 #include "hw/sysbus.h"
46 #include "hw/char/serial.h"
47 #include "hw/cpu/cluster.h"
48 #include "hw/misc/unimp.h"
49 #include "hw/sd/sd.h"
50 #include "hw/ssi/ssi.h"
51 #include "target/riscv/cpu.h"
52 #include "hw/riscv/riscv_hart.h"
53 #include "hw/riscv/sifive_u.h"
54 #include "hw/riscv/boot.h"
55 #include "hw/char/sifive_uart.h"
56 #include "hw/intc/riscv_aclint.h"
57 #include "hw/intc/sifive_plic.h"
58 #include "chardev/char.h"
59 #include "net/eth.h"
60 #include "sysemu/device_tree.h"
61 #include "sysemu/runstate.h"
62 #include "sysemu/sysemu.h"
63
64 #include <libfdt.h>
65
66 /* CLINT timebase frequency */
67 #define CLINT_TIMEBASE_FREQ 1000000
68
69 static const MemMapEntry sifive_u_memmap[] = {
70 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
71 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
72 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
73 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
74 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
75 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
76 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
77 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
78 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
79 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
80 [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 },
81 [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 },
82 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },
83 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 },
84 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
85 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
86 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
87 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
88 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
89 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
90 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
91 };
92
93 #define OTP_SERIAL 1
94 #define GEM_REVISION 0x10070109
95
96 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
97 uint64_t mem_size, const char *cmdline, bool is_32_bit)
98 {
99 MachineState *ms = MACHINE(qdev_get_machine());
100 void *fdt;
101 int cpu, fdt_size;
102 uint32_t *cells;
103 char *nodename;
104 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
105 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
106 static const char * const ethclk_names[2] = { "pclk", "hclk" };
107 static const char * const clint_compat[2] = {
108 "sifive,clint0", "riscv,clint0"
109 };
110 static const char * const plic_compat[2] = {
111 "sifive,plic-1.0.0", "riscv,plic0"
112 };
113
114 if (ms->dtb) {
115 fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size);
116 if (!fdt) {
117 error_report("load_device_tree() failed");
118 exit(1);
119 }
120 goto update_bootargs;
121 } else {
122 fdt = ms->fdt = create_device_tree(&fdt_size);
123 if (!fdt) {
124 error_report("create_device_tree() failed");
125 exit(1);
126 }
127 }
128
129 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
130 qemu_fdt_setprop_string(fdt, "/", "compatible",
131 "sifive,hifive-unleashed-a00");
132 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
133 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
134
135 qemu_fdt_add_subnode(fdt, "/soc");
136 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
137 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
138 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
139 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
140
141 hfclk_phandle = phandle++;
142 nodename = g_strdup_printf("/hfclk");
143 qemu_fdt_add_subnode(fdt, nodename);
144 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
145 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
146 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
147 SIFIVE_U_HFCLK_FREQ);
148 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
149 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
150 g_free(nodename);
151
152 rtcclk_phandle = phandle++;
153 nodename = g_strdup_printf("/rtcclk");
154 qemu_fdt_add_subnode(fdt, nodename);
155 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
156 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
157 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
158 SIFIVE_U_RTCCLK_FREQ);
159 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
160 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
161 g_free(nodename);
162
163 nodename = g_strdup_printf("/memory@%lx",
164 (long)memmap[SIFIVE_U_DEV_DRAM].base);
165 qemu_fdt_add_subnode(fdt, nodename);
166 qemu_fdt_setprop_cells(fdt, nodename, "reg",
167 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
168 mem_size >> 32, mem_size);
169 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
170 g_free(nodename);
171
172 qemu_fdt_add_subnode(fdt, "/cpus");
173 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
174 CLINT_TIMEBASE_FREQ);
175 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
176 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
177
178 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
179 int cpu_phandle = phandle++;
180 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
181 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
182 char *isa;
183 qemu_fdt_add_subnode(fdt, nodename);
184 /* cpu 0 is the management hart that does not have mmu */
185 if (cpu != 0) {
186 if (is_32_bit) {
187 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
188 } else {
189 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
190 }
191 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
192 } else {
193 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
194 }
195 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
196 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
197 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
198 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
199 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
200 qemu_fdt_add_subnode(fdt, intc);
201 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
202 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
203 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
204 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
205 g_free(isa);
206 g_free(intc);
207 g_free(nodename);
208 }
209
210 cells = g_new0(uint32_t, ms->smp.cpus * 4);
211 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
212 nodename =
213 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
214 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
215 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
216 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
217 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
218 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
219 g_free(nodename);
220 }
221 nodename = g_strdup_printf("/soc/clint@%lx",
222 (long)memmap[SIFIVE_U_DEV_CLINT].base);
223 qemu_fdt_add_subnode(fdt, nodename);
224 qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
225 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
226 qemu_fdt_setprop_cells(fdt, nodename, "reg",
227 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
228 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
229 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
230 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
231 g_free(cells);
232 g_free(nodename);
233
234 nodename = g_strdup_printf("/soc/otp@%lx",
235 (long)memmap[SIFIVE_U_DEV_OTP].base);
236 qemu_fdt_add_subnode(fdt, nodename);
237 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
238 qemu_fdt_setprop_cells(fdt, nodename, "reg",
239 0x0, memmap[SIFIVE_U_DEV_OTP].base,
240 0x0, memmap[SIFIVE_U_DEV_OTP].size);
241 qemu_fdt_setprop_string(fdt, nodename, "compatible",
242 "sifive,fu540-c000-otp");
243 g_free(nodename);
244
245 prci_phandle = phandle++;
246 nodename = g_strdup_printf("/soc/clock-controller@%lx",
247 (long)memmap[SIFIVE_U_DEV_PRCI].base);
248 qemu_fdt_add_subnode(fdt, nodename);
249 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
250 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
251 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
252 hfclk_phandle, rtcclk_phandle);
253 qemu_fdt_setprop_cells(fdt, nodename, "reg",
254 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
255 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
256 qemu_fdt_setprop_string(fdt, nodename, "compatible",
257 "sifive,fu540-c000-prci");
258 g_free(nodename);
259
260 plic_phandle = phandle++;
261 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
262 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
263 nodename =
264 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
265 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
266 /* cpu 0 is the management hart that does not have S-mode */
267 if (cpu == 0) {
268 cells[0] = cpu_to_be32(intc_phandle);
269 cells[1] = cpu_to_be32(IRQ_M_EXT);
270 } else {
271 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
272 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
273 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
274 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
275 }
276 g_free(nodename);
277 }
278 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
279 (long)memmap[SIFIVE_U_DEV_PLIC].base);
280 qemu_fdt_add_subnode(fdt, nodename);
281 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
282 qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
283 (char **)&plic_compat, ARRAY_SIZE(plic_compat));
284 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
285 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
286 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
287 qemu_fdt_setprop_cells(fdt, nodename, "reg",
288 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
289 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
290 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
291 SIFIVE_U_PLIC_NUM_SOURCES - 1);
292 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
293 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
294 g_free(cells);
295 g_free(nodename);
296
297 gpio_phandle = phandle++;
298 nodename = g_strdup_printf("/soc/gpio@%lx",
299 (long)memmap[SIFIVE_U_DEV_GPIO].base);
300 qemu_fdt_add_subnode(fdt, nodename);
301 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
302 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
303 prci_phandle, PRCI_CLK_TLCLK);
304 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
305 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
306 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
307 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
308 qemu_fdt_setprop_cells(fdt, nodename, "reg",
309 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
310 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
311 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
312 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
313 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
314 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
315 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
316 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
317 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
318 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
319 g_free(nodename);
320
321 nodename = g_strdup_printf("/gpio-restart");
322 qemu_fdt_add_subnode(fdt, nodename);
323 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
324 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
325 g_free(nodename);
326
327 nodename = g_strdup_printf("/soc/dma@%lx",
328 (long)memmap[SIFIVE_U_DEV_PDMA].base);
329 qemu_fdt_add_subnode(fdt, nodename);
330 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
331 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
332 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
333 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
334 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
335 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
336 qemu_fdt_setprop_cells(fdt, nodename, "reg",
337 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
338 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
339 qemu_fdt_setprop_string(fdt, nodename, "compatible",
340 "sifive,fu540-c000-pdma");
341 g_free(nodename);
342
343 nodename = g_strdup_printf("/soc/cache-controller@%lx",
344 (long)memmap[SIFIVE_U_DEV_L2CC].base);
345 qemu_fdt_add_subnode(fdt, nodename);
346 qemu_fdt_setprop_cells(fdt, nodename, "reg",
347 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
348 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
349 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
350 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
351 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
352 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
353 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
354 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
355 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
356 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
357 qemu_fdt_setprop_string(fdt, nodename, "compatible",
358 "sifive,fu540-c000-ccache");
359 g_free(nodename);
360
361 nodename = g_strdup_printf("/soc/spi@%lx",
362 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
363 qemu_fdt_add_subnode(fdt, nodename);
364 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
365 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
366 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
367 prci_phandle, PRCI_CLK_TLCLK);
368 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ);
369 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
370 qemu_fdt_setprop_cells(fdt, nodename, "reg",
371 0x0, memmap[SIFIVE_U_DEV_QSPI2].base,
372 0x0, memmap[SIFIVE_U_DEV_QSPI2].size);
373 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
374 g_free(nodename);
375
376 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0",
377 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
378 qemu_fdt_add_subnode(fdt, nodename);
379 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
380 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
381 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
382 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
383 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
384 g_free(nodename);
385
386 nodename = g_strdup_printf("/soc/spi@%lx",
387 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
388 qemu_fdt_add_subnode(fdt, nodename);
389 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
390 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
391 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
392 prci_phandle, PRCI_CLK_TLCLK);
393 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ);
394 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
395 qemu_fdt_setprop_cells(fdt, nodename, "reg",
396 0x0, memmap[SIFIVE_U_DEV_QSPI0].base,
397 0x0, memmap[SIFIVE_U_DEV_QSPI0].size);
398 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
399 g_free(nodename);
400
401 nodename = g_strdup_printf("/soc/spi@%lx/flash@0",
402 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
403 qemu_fdt_add_subnode(fdt, nodename);
404 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
405 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
406 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
407 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
408 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
409 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
410 g_free(nodename);
411
412 phy_phandle = phandle++;
413 nodename = g_strdup_printf("/soc/ethernet@%lx",
414 (long)memmap[SIFIVE_U_DEV_GEM].base);
415 qemu_fdt_add_subnode(fdt, nodename);
416 qemu_fdt_setprop_string(fdt, nodename, "compatible",
417 "sifive,fu540-c000-gem");
418 qemu_fdt_setprop_cells(fdt, nodename, "reg",
419 0x0, memmap[SIFIVE_U_DEV_GEM].base,
420 0x0, memmap[SIFIVE_U_DEV_GEM].size,
421 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
422 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
423 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
424 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
425 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
426 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
427 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
428 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
429 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
430 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
431 (char **)&ethclk_names, ARRAY_SIZE(ethclk_names));
432 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
433 s->soc.gem.conf.macaddr.a, ETH_ALEN);
434 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
435 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
436
437 qemu_fdt_add_subnode(fdt, "/aliases");
438 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
439
440 g_free(nodename);
441
442 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
443 (long)memmap[SIFIVE_U_DEV_GEM].base);
444 qemu_fdt_add_subnode(fdt, nodename);
445 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
446 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
447 g_free(nodename);
448
449 nodename = g_strdup_printf("/soc/pwm@%lx",
450 (long)memmap[SIFIVE_U_DEV_PWM0].base);
451 qemu_fdt_add_subnode(fdt, nodename);
452 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
453 qemu_fdt_setprop_cells(fdt, nodename, "reg",
454 0x0, memmap[SIFIVE_U_DEV_PWM0].base,
455 0x0, memmap[SIFIVE_U_DEV_PWM0].size);
456 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
457 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
458 SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1,
459 SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3);
460 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
461 prci_phandle, PRCI_CLK_TLCLK);
462 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
463 g_free(nodename);
464
465 nodename = g_strdup_printf("/soc/pwm@%lx",
466 (long)memmap[SIFIVE_U_DEV_PWM1].base);
467 qemu_fdt_add_subnode(fdt, nodename);
468 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
469 qemu_fdt_setprop_cells(fdt, nodename, "reg",
470 0x0, memmap[SIFIVE_U_DEV_PWM1].base,
471 0x0, memmap[SIFIVE_U_DEV_PWM1].size);
472 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
473 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
474 SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1,
475 SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3);
476 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
477 prci_phandle, PRCI_CLK_TLCLK);
478 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
479 g_free(nodename);
480
481 nodename = g_strdup_printf("/soc/serial@%lx",
482 (long)memmap[SIFIVE_U_DEV_UART1].base);
483 qemu_fdt_add_subnode(fdt, nodename);
484 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
485 qemu_fdt_setprop_cells(fdt, nodename, "reg",
486 0x0, memmap[SIFIVE_U_DEV_UART1].base,
487 0x0, memmap[SIFIVE_U_DEV_UART1].size);
488 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
489 prci_phandle, PRCI_CLK_TLCLK);
490 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
491 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
492
493 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
494 g_free(nodename);
495
496 nodename = g_strdup_printf("/soc/serial@%lx",
497 (long)memmap[SIFIVE_U_DEV_UART0].base);
498 qemu_fdt_add_subnode(fdt, nodename);
499 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
500 qemu_fdt_setprop_cells(fdt, nodename, "reg",
501 0x0, memmap[SIFIVE_U_DEV_UART0].base,
502 0x0, memmap[SIFIVE_U_DEV_UART0].size);
503 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
504 prci_phandle, PRCI_CLK_TLCLK);
505 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
506 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
507
508 qemu_fdt_add_subnode(fdt, "/chosen");
509 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
510 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
511
512 g_free(nodename);
513
514 update_bootargs:
515 if (cmdline && *cmdline) {
516 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
517 }
518 }
519
520 static void sifive_u_machine_reset(void *opaque, int n, int level)
521 {
522 /* gpio pin active low triggers reset */
523 if (!level) {
524 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
525 }
526 }
527
528 static void sifive_u_machine_init(MachineState *machine)
529 {
530 const MemMapEntry *memmap = sifive_u_memmap;
531 SiFiveUState *s = RISCV_U_MACHINE(machine);
532 MemoryRegion *system_memory = get_system_memory();
533 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
534 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
535 target_ulong firmware_end_addr, kernel_start_addr;
536 const char *firmware_name;
537 uint32_t start_addr_hi32 = 0x00000000;
538 int i;
539 uint32_t fdt_load_addr;
540 uint64_t kernel_entry;
541 DriveInfo *dinfo;
542 BlockBackend *blk;
543 DeviceState *flash_dev, *sd_dev, *card_dev;
544 qemu_irq flash_cs, sd_cs;
545
546 /* Initialize SoC */
547 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
548 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
549 &error_abort);
550 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
551 &error_abort);
552 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
553
554 /* register RAM */
555 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
556 machine->ram);
557
558 /* register QSPI0 Flash */
559 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
560 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
561 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
562 flash0);
563
564 /* register gpio-restart */
565 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
566 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
567
568 /* create device tree */
569 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
570 riscv_is_32bit(&s->soc.u_cpus));
571
572 if (s->start_in_flash) {
573 /*
574 * If start_in_flash property is given, assign s->msel to a value
575 * that representing booting from QSPI0 memory-mapped flash.
576 *
577 * This also means that when both start_in_flash and msel properties
578 * are given, start_in_flash takes the precedence over msel.
579 *
580 * Note this is to keep backward compatibility not to break existing
581 * users that use start_in_flash property.
582 */
583 s->msel = MSEL_MEMMAP_QSPI0_FLASH;
584 }
585
586 switch (s->msel) {
587 case MSEL_MEMMAP_QSPI0_FLASH:
588 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
589 break;
590 case MSEL_L2LIM_QSPI0_FLASH:
591 case MSEL_L2LIM_QSPI2_SD:
592 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
593 break;
594 default:
595 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
596 break;
597 }
598
599 firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
600 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
601 start_addr, NULL);
602
603 if (machine->kernel_filename) {
604 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
605 firmware_end_addr);
606
607 kernel_entry = riscv_load_kernel(machine->kernel_filename,
608 kernel_start_addr, NULL);
609
610 if (machine->initrd_filename) {
611 riscv_load_initrd(machine->initrd_filename, machine->ram_size,
612 kernel_entry, machine->fdt);
613 }
614 } else {
615 /*
616 * If dynamic firmware is used, it doesn't know where is the next mode
617 * if kernel argument is not set.
618 */
619 kernel_entry = 0;
620 }
621
622 /* Compute the fdt load address in dram */
623 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
624 machine->ram_size, machine->fdt);
625 if (!riscv_is_32bit(&s->soc.u_cpus)) {
626 start_addr_hi32 = (uint64_t)start_addr >> 32;
627 }
628
629 /* reset vector */
630 uint32_t reset_vec[12] = {
631 s->msel, /* MSEL pin state */
632 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
633 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */
634 0xf1402573, /* csrr a0, mhartid */
635 0,
636 0,
637 0x00028067, /* jr t0 */
638 start_addr, /* start: .dword */
639 start_addr_hi32,
640 fdt_load_addr, /* fdt_laddr: .dword */
641 0x00000000,
642 0x00000000,
643 /* fw_dyn: */
644 };
645 if (riscv_is_32bit(&s->soc.u_cpus)) {
646 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
647 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
648 } else {
649 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
650 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
651 }
652
653
654 /* copy in the reset vector in little_endian byte order */
655 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
656 reset_vec[i] = cpu_to_le32(reset_vec[i]);
657 }
658 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
659 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
660
661 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
662 memmap[SIFIVE_U_DEV_MROM].size,
663 sizeof(reset_vec), kernel_entry);
664
665 /* Connect an SPI flash to SPI0 */
666 flash_dev = qdev_new("is25wp256");
667 dinfo = drive_get(IF_MTD, 0, 0);
668 if (dinfo) {
669 qdev_prop_set_drive_err(flash_dev, "drive",
670 blk_by_legacy_dinfo(dinfo),
671 &error_fatal);
672 }
673 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);
674
675 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
676 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);
677
678 /* Connect an SD card to SPI2 */
679 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd");
680
681 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);
682 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);
683
684 dinfo = drive_get(IF_SD, 0, 0);
685 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
686 card_dev = qdev_new(TYPE_SD_CARD);
687 qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal);
688 qdev_prop_set_bit(card_dev, "spi", true);
689 qdev_realize_and_unref(card_dev,
690 qdev_get_child_bus(sd_dev, "sd-bus"),
691 &error_fatal);
692 }
693
694 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
695 {
696 SiFiveUState *s = RISCV_U_MACHINE(obj);
697
698 return s->start_in_flash;
699 }
700
701 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
702 {
703 SiFiveUState *s = RISCV_U_MACHINE(obj);
704
705 s->start_in_flash = value;
706 }
707
708 static void sifive_u_machine_instance_init(Object *obj)
709 {
710 SiFiveUState *s = RISCV_U_MACHINE(obj);
711
712 s->start_in_flash = false;
713 s->msel = 0;
714 object_property_add_uint32_ptr(obj, "msel", &s->msel,
715 OBJ_PROP_FLAG_READWRITE);
716 object_property_set_description(obj, "msel",
717 "Mode Select (MSEL[3:0]) pin state");
718
719 s->serial = OTP_SERIAL;
720 object_property_add_uint32_ptr(obj, "serial", &s->serial,
721 OBJ_PROP_FLAG_READWRITE);
722 object_property_set_description(obj, "serial", "Board serial number");
723 }
724
725 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
726 {
727 MachineClass *mc = MACHINE_CLASS(oc);
728
729 mc->desc = "RISC-V Board compatible with SiFive U SDK";
730 mc->init = sifive_u_machine_init;
731 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
732 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
733 mc->default_cpu_type = SIFIVE_U_CPU;
734 mc->default_cpus = mc->min_cpus;
735 mc->default_ram_id = "riscv.sifive.u.ram";
736
737 object_class_property_add_bool(oc, "start-in-flash",
738 sifive_u_machine_get_start_in_flash,
739 sifive_u_machine_set_start_in_flash);
740 object_class_property_set_description(oc, "start-in-flash",
741 "Set on to tell QEMU's ROM to jump to "
742 "flash. Otherwise QEMU will jump to DRAM "
743 "or L2LIM depending on the msel value");
744 }
745
746 static const TypeInfo sifive_u_machine_typeinfo = {
747 .name = MACHINE_TYPE_NAME("sifive_u"),
748 .parent = TYPE_MACHINE,
749 .class_init = sifive_u_machine_class_init,
750 .instance_init = sifive_u_machine_instance_init,
751 .instance_size = sizeof(SiFiveUState),
752 };
753
754 static void sifive_u_machine_init_register_types(void)
755 {
756 type_register_static(&sifive_u_machine_typeinfo);
757 }
758
759 type_init(sifive_u_machine_init_register_types)
760
761 static void sifive_u_soc_instance_init(Object *obj)
762 {
763 SiFiveUSoCState *s = RISCV_U_SOC(obj);
764
765 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
766 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
767
768 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
769 TYPE_RISCV_HART_ARRAY);
770 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
771 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
772 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
773 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
774
775 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
776 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
777
778 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
779 TYPE_RISCV_HART_ARRAY);
780
781 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
782 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
783 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
784 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
785 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
786 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
787 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
788 object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM);
789 object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM);
790 }
791
792 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
793 {
794 MachineState *ms = MACHINE(qdev_get_machine());
795 SiFiveUSoCState *s = RISCV_U_SOC(dev);
796 const MemMapEntry *memmap = sifive_u_memmap;
797 MemoryRegion *system_memory = get_system_memory();
798 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
799 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
800 char *plic_hart_config;
801 int i, j;
802 NICInfo *nd = &nd_table[0];
803
804 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
805 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
806 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
807 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
808
809 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
810 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
811 /*
812 * The cluster must be realized after the RISC-V hart array container,
813 * as the container's CPU object is only created on realize, and the
814 * CPU must exist and have been parented into the cluster before the
815 * cluster is realized.
816 */
817 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
818 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
819
820 /* boot rom */
821 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
822 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
823 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
824 mask_rom);
825
826 /*
827 * Add L2-LIM at reset size.
828 * This should be reduced in size as the L2 Cache Controller WayEnable
829 * register is incremented. Unfortunately I don't see a nice (or any) way
830 * to handle reducing or blocking out the L2 LIM while still allowing it
831 * be re returned to all enabled after a reset. For the time being, just
832 * leave it enabled all the time. This won't break anything, but will be
833 * too generous to misbehaving guests.
834 */
835 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
836 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
837 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
838 l2lim_mem);
839
840 /* create PLIC hart topology configuration string */
841 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
842
843 /* MMIO */
844 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
845 plic_hart_config, ms->smp.cpus, 0,
846 SIFIVE_U_PLIC_NUM_SOURCES,
847 SIFIVE_U_PLIC_NUM_PRIORITIES,
848 SIFIVE_U_PLIC_PRIORITY_BASE,
849 SIFIVE_U_PLIC_PENDING_BASE,
850 SIFIVE_U_PLIC_ENABLE_BASE,
851 SIFIVE_U_PLIC_ENABLE_STRIDE,
852 SIFIVE_U_PLIC_CONTEXT_BASE,
853 SIFIVE_U_PLIC_CONTEXT_STRIDE,
854 memmap[SIFIVE_U_DEV_PLIC].size);
855 g_free(plic_hart_config);
856 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
857 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
858 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
859 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
860 riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0,
861 ms->smp.cpus, false);
862 riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base +
863 RISCV_ACLINT_SWI_SIZE,
864 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
865 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
866 CLINT_TIMEBASE_FREQ, false);
867
868 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
869 return;
870 }
871 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
872
873 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
874 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
875 return;
876 }
877 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
878
879 /* Pass all GPIOs to the SOC layer so they are available to the board */
880 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
881
882 /* Connect GPIO interrupts to the PLIC */
883 for (i = 0; i < 16; i++) {
884 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
885 qdev_get_gpio_in(DEVICE(s->plic),
886 SIFIVE_U_GPIO_IRQ0 + i));
887 }
888
889 /* PDMA */
890 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
891 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
892
893 /* Connect PDMA interrupts to the PLIC */
894 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
895 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
896 qdev_get_gpio_in(DEVICE(s->plic),
897 SIFIVE_U_PDMA_IRQ0 + i));
898 }
899
900 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
901 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
902 return;
903 }
904 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
905
906 /* FIXME use qdev NIC properties instead of nd_table[] */
907 if (nd->used) {
908 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
909 qdev_set_nic_properties(DEVICE(&s->gem), nd);
910 }
911 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
912 &error_abort);
913 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
914 return;
915 }
916 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
917 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
918 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
919
920 /* PWM */
921 for (i = 0; i < 2; i++) {
922 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) {
923 return;
924 }
925 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0,
926 memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i));
927
928 /* Connect PWM interrupts to the PLIC */
929 for (j = 0; j < SIFIVE_PWM_IRQS; j++) {
930 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j,
931 qdev_get_gpio_in(DEVICE(s->plic),
932 SIFIVE_U_PWM0_IRQ0 + (i * 4) + j));
933 }
934 }
935
936 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
937 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
938
939 create_unimplemented_device("riscv.sifive.u.dmc",
940 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
941
942 create_unimplemented_device("riscv.sifive.u.l2cc",
943 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
944
945 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);
946 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,
947 memmap[SIFIVE_U_DEV_QSPI0].base);
948 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,
949 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));
950 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);
951 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,
952 memmap[SIFIVE_U_DEV_QSPI2].base);
953 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,
954 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
955 }
956
957 static Property sifive_u_soc_props[] = {
958 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
959 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
960 DEFINE_PROP_END_OF_LIST()
961 };
962
963 static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
964 {
965 DeviceClass *dc = DEVICE_CLASS(oc);
966
967 device_class_set_props(dc, sifive_u_soc_props);
968 dc->realize = sifive_u_soc_realize;
969 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
970 dc->user_creatable = false;
971 }
972
973 static const TypeInfo sifive_u_soc_type_info = {
974 .name = TYPE_RISCV_U_SOC,
975 .parent = TYPE_DEVICE,
976 .instance_size = sizeof(SiFiveUSoCState),
977 .instance_init = sifive_u_soc_instance_init,
978 .class_init = sifive_u_soc_class_init,
979 };
980
981 static void sifive_u_soc_register_types(void)
982 {
983 type_register_static(&sifive_u_soc_type_info);
984 }
985
986 type_init(sifive_u_soc_register_types)
QEmu