tests/libqos/virtio-pci.c

   1 /*
   2  * libqos virtio PCI driver
   3  *
   4  * Copyright (c) 2014 Marc Marí
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "libqtest.h"
  12 #include "libqos/virtio.h"
  13 #include "libqos/virtio-pci.h"
  14 #include "libqos/pci.h"
  15 #include "libqos/pci-pc.h"
  16 #include "libqos/malloc.h"
  17 #include "libqos/malloc-pc.h"
  18
  19 #include "hw/pci/pci_regs.h"
  20
  21 typedef struct QVirtioPCIForeachData {
  22     void (*func)(QVirtioDevice *d, void *data);
  23     uint16_t device_type;
  24     void *user_data;
  25 } QVirtioPCIForeachData;
  26
  27 static QVirtioPCIDevice *qpcidevice_to_qvirtiodevice(QPCIDevice *pdev)
  28 {
  29     QVirtioPCIDevice *vpcidev;
  30     vpcidev = g_malloc0(sizeof(*vpcidev));
  31
  32     if (pdev) {
  33         vpcidev->pdev = pdev;
  34         vpcidev->vdev.device_type =
  35                             qpci_config_readw(vpcidev->pdev, PCI_SUBSYSTEM_ID);
  36     }
  37
  38     vpcidev->config_msix_entry = -1;
  39
  40     return vpcidev;
  41 }
  42
  43 static void qvirtio_pci_foreach_callback(
  44                         QPCIDevice *dev, int devfn, void *data)
  45 {
  46     QVirtioPCIForeachData *d = data;
  47     QVirtioPCIDevice *vpcidev = qpcidevice_to_qvirtiodevice(dev);
  48
  49     if (vpcidev->vdev.device_type == d->device_type) {
  50         d->func(&vpcidev->vdev, d->user_data);
  51     } else {
  52         g_free(vpcidev);
  53     }
  54 }
  55
  56 static void qvirtio_pci_assign_device(QVirtioDevice *d, void *data)
  57 {
  58     QVirtioPCIDevice **vpcidev = data;
  59     *vpcidev = (QVirtioPCIDevice *)d;
  60 }
  61
  62 static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t addr)
  63 {
  64     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  65     return qpci_io_readb(dev->pdev, (void *)(uintptr_t)addr);
  66 }
  67
  68 static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t addr)
  69 {
  70     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  71     return qpci_io_readw(dev->pdev, (void *)(uintptr_t)addr);
  72 }
  73
  74 static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t addr)
  75 {
  76     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  77     return qpci_io_readl(dev->pdev, (void *)(uintptr_t)addr);
  78 }
  79
  80 static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t addr)
  81 {
  82     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  83     int i;
  84     uint64_t u64 = 0;
  85
  86     if (qtest_big_endian()) {
  87         for (i = 0; i < 8; ++i) {
  88             u64 |= (uint64_t)qpci_io_readb(dev->pdev,
  89                                 (void *)(uintptr_t)addr + i) << (7 - i) * 8;
  90         }
  91     } else {
  92         for (i = 0; i < 8; ++i) {
  93             u64 |= (uint64_t)qpci_io_readb(dev->pdev,
  94                                 (void *)(uintptr_t)addr + i) << i * 8;
  95         }
  96     }
  97
  98     return u64;
  99 }
 100
 101 static uint32_t qvirtio_pci_get_features(QVirtioDevice *d)
 102 {
 103     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 104     return qpci_io_readl(dev->pdev, dev->addr + QVIRTIO_PCI_DEVICE_FEATURES);
 105 }
 106
 107 static void qvirtio_pci_set_features(QVirtioDevice *d, uint32_t features)
 108 {
 109     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 110     qpci_io_writel(dev->pdev, dev->addr + QVIRTIO_PCI_GUEST_FEATURES, features);
 111 }
 112
 113 static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
 114 {
 115     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 116     return qpci_io_readl(dev->pdev, dev->addr + QVIRTIO_PCI_GUEST_FEATURES);
 117 }
 118
 119 static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
 120 {
 121     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 122     return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_DEVICE_STATUS);
 123 }
 124
 125 static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
 126 {
 127     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 128     qpci_io_writeb(dev->pdev, dev->addr + QVIRTIO_PCI_DEVICE_STATUS, status);
 129 }
 130
 131 static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
 132 {
 133     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 134     QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
 135     uint32_t data;
 136
 137     if (dev->pdev->msix_enabled) {
 138         g_assert_cmpint(vqpci->msix_entry, !=, -1);
 139         if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
 140             /* No ISR checking should be done if masked, but read anyway */
 141             return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
 142         } else {
 143             data = readl(vqpci->msix_addr);
 144             if (data == vqpci->msix_data) {
 145                 writel(vqpci->msix_addr, 0);
 146                 return true;
 147             } else {
 148                 return false;
 149             }
 150         }
 151     } else {
 152         return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STATUS) & 1;
 153     }
 154 }
 155
 156 static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
 157 {
 158     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 159     uint32_t data;
 160
 161     if (dev->pdev->msix_enabled) {
 162         g_assert_cmpint(dev->config_msix_entry, !=, -1);
 163         if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
 164             /* No ISR checking should be done if masked, but read anyway */
 165             return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
 166         } else {
 167             data = readl(dev->config_msix_addr);
 168             if (data == dev->config_msix_data) {
 169                 writel(dev->config_msix_addr, 0);
 170                 return true;
 171             } else {
 172                 return false;
 173             }
 174         }
 175     } else {
 176         return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STATUS) & 2;
 177     }
 178 }
 179
 180 static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
 181 {
 182     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 183     qpci_io_writeb(dev->pdev, dev->addr + QVIRTIO_PCI_QUEUE_SELECT, index);
 184 }
 185
 186 static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
 187 {
 188     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 189     return qpci_io_readw(dev->pdev, dev->addr + QVIRTIO_PCI_QUEUE_SIZE);
 190 }
 191
 192 static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn)
 193 {
 194     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 195     qpci_io_writel(dev->pdev, dev->addr + QVIRTIO_PCI_QUEUE_ADDRESS, pfn);
 196 }
 197
 198 static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d,
 199                                         QGuestAllocator *alloc, uint16_t index)
 200 {
 201     uint32_t feat;
 202     uint64_t addr;
 203     QVirtQueuePCI *vqpci;
 204
 205     vqpci = g_malloc0(sizeof(*vqpci));
 206     feat = qvirtio_pci_get_guest_features(d);
 207
 208     qvirtio_pci_queue_select(d, index);
 209     vqpci->vq.index = index;
 210     vqpci->vq.size = qvirtio_pci_get_queue_size(d);
 211     vqpci->vq.free_head = 0;
 212     vqpci->vq.num_free = vqpci->vq.size;
 213     vqpci->vq.align = QVIRTIO_PCI_ALIGN;
 214     vqpci->vq.indirect = (feat & QVIRTIO_F_RING_INDIRECT_DESC) != 0;
 215     vqpci->vq.event = (feat & QVIRTIO_F_RING_EVENT_IDX) != 0;
 216
 217     vqpci->msix_entry = -1;
 218     vqpci->msix_addr = 0;
 219     vqpci->msix_data = 0x12345678;
 220
 221     /* Check different than 0 */
 222     g_assert_cmpint(vqpci->vq.size, !=, 0);
 223
 224     /* Check power of 2 */
 225     g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);
 226
 227     addr = guest_alloc(alloc, qvring_size(vqpci->vq.size, QVIRTIO_PCI_ALIGN));
 228     qvring_init(alloc, &vqpci->vq, addr);
 229     qvirtio_pci_set_queue_address(d, vqpci->vq.desc / QVIRTIO_PCI_ALIGN);
 230
 231     return &vqpci->vq;
 232 }
 233
 234 static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
 235 {
 236     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 237     qpci_io_writew(dev->pdev, dev->addr + QVIRTIO_PCI_QUEUE_NOTIFY, vq->index);
 238 }
 239
 240 const QVirtioBus qvirtio_pci = {
 241     .config_readb = qvirtio_pci_config_readb,
 242     .config_readw = qvirtio_pci_config_readw,
 243     .config_readl = qvirtio_pci_config_readl,
 244     .config_readq = qvirtio_pci_config_readq,
 245     .get_features = qvirtio_pci_get_features,
 246     .set_features = qvirtio_pci_set_features,
 247     .get_guest_features = qvirtio_pci_get_guest_features,
 248     .get_status = qvirtio_pci_get_status,
 249     .set_status = qvirtio_pci_set_status,
 250     .get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
 251     .get_config_isr_status = qvirtio_pci_get_config_isr_status,
 252     .queue_select = qvirtio_pci_queue_select,
 253     .get_queue_size = qvirtio_pci_get_queue_size,
 254     .set_queue_address = qvirtio_pci_set_queue_address,
 255     .virtqueue_setup = qvirtio_pci_virtqueue_setup,
 256     .virtqueue_kick = qvirtio_pci_virtqueue_kick,
 257 };
 258
 259 void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type,
 260                 void (*func)(QVirtioDevice *d, void *data), void *data)
 261 {
 262     QVirtioPCIForeachData d = { .func = func,
 263                                 .device_type = device_type,
 264                                 .user_data = data };
 265
 266     qpci_device_foreach(bus, QVIRTIO_VENDOR_ID, -1,
 267                                 qvirtio_pci_foreach_callback, &d);
 268 }
 269
 270 QVirtioPCIDevice *qvirtio_pci_device_find(QPCIBus *bus, uint16_t device_type)
 271 {
 272     QVirtioPCIDevice *dev = NULL;
 273     qvirtio_pci_foreach(bus, device_type, qvirtio_pci_assign_device, &dev);
 274
 275     return dev;
 276 }
 277
 278 void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
 279 {
 280     qpci_device_enable(d->pdev);
 281     d->addr = qpci_iomap(d->pdev, 0, NULL);
 282     g_assert(d->addr != NULL);
 283 }
 284
 285 void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
 286 {
 287     qpci_iounmap(d->pdev, d->addr);
 288     d->addr = NULL;
 289 }
 290
 291 void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
 292                                         QGuestAllocator *alloc, uint16_t entry)
 293 {
 294     uint16_t vector;
 295     uint32_t control;
 296     void *addr;
 297
 298     g_assert(d->pdev->msix_enabled);
 299     addr = d->pdev->msix_table + (entry * 16);
 300
 301     g_assert_cmpint(entry, >=, 0);
 302     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 303     vqpci->msix_entry = entry;
 304
 305     vqpci->msix_addr = guest_alloc(alloc, 4);
 306     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
 307                                                     vqpci->msix_addr & ~0UL);
 308     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
 309                                             (vqpci->msix_addr >> 32) & ~0UL);
 310     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
 311
 312     control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
 313     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
 314                                         control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 315
 316     qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
 317     qpci_io_writew(d->pdev, d->addr + QVIRTIO_PCI_MSIX_QUEUE_VECTOR, entry);
 318     vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_PCI_MSIX_QUEUE_VECTOR);
 319     g_assert_cmphex(vector, !=, QVIRTIO_MSI_NO_VECTOR);
 320 }
 321
 322 void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
 323                                         QGuestAllocator *alloc, uint16_t entry)
 324 {
 325     uint16_t vector;
 326     uint32_t control;
 327     void *addr;
 328
 329     g_assert(d->pdev->msix_enabled);
 330     addr = d->pdev->msix_table + (entry * 16);
 331
 332     g_assert_cmpint(entry, >=, 0);
 333     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 334     d->config_msix_entry = entry;
 335
 336     d->config_msix_data = 0x12345678;
 337     d->config_msix_addr = guest_alloc(alloc, 4);
 338
 339     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
 340                                                     d->config_msix_addr & ~0UL);
 341     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
 342                                             (d->config_msix_addr >> 32) & ~0UL);
 343     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
 344
 345     control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
 346     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
 347                                         control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 348
 349     qpci_io_writew(d->pdev, d->addr + QVIRTIO_PCI_MSIX_CONF_VECTOR, entry);
 350     vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_PCI_MSIX_CONF_VECTOR);
 351     g_assert_cmphex(vector, !=, QVIRTIO_MSI_NO_VECTOR);
 352 }