target-moxie/translate.c

   1 /*
   2  *  Moxie emulation for qemu: main translation routines.
   3  *
   4  *  Copyright (c) 2009, 2013 Anthony Green
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public License
   8  * as published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /* For information on the Moxie architecture, see
  21  *    http://moxielogic.org/wiki
  22  */
  23
  24 #include <stdarg.h>
  25 #include <stdlib.h>
  26 #include <stdio.h>
  27 #include <string.h>
  28 #include <inttypes.h>
  29
  30 #include "cpu.h"
  31 #include "exec/exec-all.h"
  32 #include "disas/disas.h"
  33 #include "tcg-op.h"
  34 #include "exec/cpu_ldst.h"
  35
  36 #include "exec/helper-proto.h"
  37 #include "exec/helper-gen.h"
  38
  39 /* This is the state at translation time.  */
  40 typedef struct DisasContext {
  41     struct TranslationBlock *tb;
  42     target_ulong pc, saved_pc;
  43     uint32_t opcode;
  44     uint32_t fp_status;
  45     /* Routine used to access memory */
  46     int memidx;
  47     int bstate;
  48     target_ulong btarget;
  49     int singlestep_enabled;
  50 } DisasContext;
  51
  52 enum {
  53     BS_NONE     = 0, /* We go out of the TB without reaching a branch or an
  54                       * exception condition */
  55     BS_STOP     = 1, /* We want to stop translation for any reason */
  56     BS_BRANCH   = 2, /* We reached a branch condition     */
  57     BS_EXCP     = 3, /* We reached an exception condition */
  58 };
  59
  60 static TCGv cpu_pc;
  61 static TCGv cpu_gregs[16];
  62 static TCGv_ptr cpu_env;
  63 static TCGv cc_a, cc_b;
  64
  65 #include "exec/gen-icount.h"
  66
  67 #define REG(x) (cpu_gregs[x])
  68
  69 /* Extract the signed 10-bit offset from a 16-bit branch
  70    instruction.  */
  71 static int extract_branch_offset(int opcode)
  72 {
  73   return (((signed short)((opcode & ((1 << 10) - 1)) << 6)) >> 6) << 1;
  74 }
  75
  76 void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
  77                           int flags)
  78 {
  79     MoxieCPU *cpu = MOXIE_CPU(cs);
  80     CPUMoxieState *env = &cpu->env;
  81     int i;
  82     cpu_fprintf(f, "pc=0x%08x\n", env->pc);
  83     cpu_fprintf(f, "$fp=0x%08x $sp=0x%08x $r0=0x%08x $r1=0x%08x\n",
  84                 env->gregs[0], env->gregs[1], env->gregs[2], env->gregs[3]);
  85     for (i = 4; i < 16; i += 4) {
  86         cpu_fprintf(f, "$r%d=0x%08x $r%d=0x%08x $r%d=0x%08x $r%d=0x%08x\n",
  87                     i-2, env->gregs[i], i-1, env->gregs[i + 1],
  88                     i, env->gregs[i + 2], i+1, env->gregs[i + 3]);
  89     }
  90     for (i = 4; i < 16; i += 4) {
  91         cpu_fprintf(f, "sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x\n",
  92                     i-2, env->sregs[i], i-1, env->sregs[i + 1],
  93                     i, env->sregs[i + 2], i+1, env->sregs[i + 3]);
  94     }
  95 }
  96
  97 void moxie_translate_init(void)
  98 {
  99     int i;
 100     static int done_init;
 101     static const char * const gregnames[16] = {
 102         "$fp", "$sp", "$r0", "$r1",
 103         "$r2", "$r3", "$r4", "$r5",
 104         "$r6", "$r7", "$r8", "$r9",
 105         "$r10", "$r11", "$r12", "$r13"
 106     };
 107
 108     if (done_init) {
 109         return;
 110     }
 111     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 112     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
 113                                     offsetof(CPUMoxieState, pc), "$pc");
 114     for (i = 0; i < 16; i++)
 115         cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
 116                                               offsetof(CPUMoxieState, gregs[i]),
 117                                               gregnames[i]);
 118
 119     cc_a = tcg_global_mem_new_i32(TCG_AREG0,
 120                                   offsetof(CPUMoxieState, cc_a), "cc_a");
 121     cc_b = tcg_global_mem_new_i32(TCG_AREG0,
 122                                   offsetof(CPUMoxieState, cc_b), "cc_b");
 123
 124     done_init = 1;
 125 }
 126
 127 static inline void gen_goto_tb(CPUMoxieState *env, DisasContext *ctx,
 128                                int n, target_ulong dest)
 129 {
 130     TranslationBlock *tb;
 131     tb = ctx->tb;
 132
 133     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
 134         !ctx->singlestep_enabled) {
 135         tcg_gen_goto_tb(n);
 136         tcg_gen_movi_i32(cpu_pc, dest);
 137         tcg_gen_exit_tb((uintptr_t)tb + n);
 138     } else {
 139         tcg_gen_movi_i32(cpu_pc, dest);
 140         if (ctx->singlestep_enabled) {
 141             gen_helper_debug(cpu_env);
 142         }
 143         tcg_gen_exit_tb(0);
 144     }
 145 }
 146
 147 static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
 148 {
 149     CPUMoxieState *env = &cpu->env;
 150
 151     /* Local cache for the instruction opcode.  */
 152     int opcode;
 153     /* Set the default instruction length.  */
 154     int length = 2;
 155
 156     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
 157         tcg_gen_debug_insn_start(ctx->pc);
 158     }
 159
 160     /* Examine the 16-bit opcode.  */
 161     opcode = ctx->opcode;
 162
 163     /* Decode instruction.  */
 164     if (opcode & (1 << 15)) {
 165         if (opcode & (1 << 14)) {
 166             /* This is a Form 3 instruction.  */
 167             int inst = (opcode >> 10 & 0xf);
 168
 169 #define BRANCH(cond)                                                         \
 170     do {                                                                     \
 171         TCGLabel *l1 = gen_new_label();                                      \
 172         tcg_gen_brcond_i32(cond, cc_a, cc_b, l1);                            \
 173         gen_goto_tb(env, ctx, 1, ctx->pc+2);                                 \
 174         gen_set_label(l1);                                                   \
 175         gen_goto_tb(env, ctx, 0, extract_branch_offset(opcode) + ctx->pc+2); \
 176         ctx->bstate = BS_BRANCH;                                             \
 177     } while (0)
 178
 179             switch (inst) {
 180             case 0x00: /* beq */
 181                 BRANCH(TCG_COND_EQ);
 182                 break;
 183             case 0x01: /* bne */
 184                 BRANCH(TCG_COND_NE);
 185                 break;
 186             case 0x02: /* blt */
 187                 BRANCH(TCG_COND_LT);
 188                 break;
 189             case 0x03: /* bgt */
 190                 BRANCH(TCG_COND_GT);
 191                 break;
 192             case 0x04: /* bltu */
 193                 BRANCH(TCG_COND_LTU);
 194                 break;
 195             case 0x05: /* bgtu */
 196                 BRANCH(TCG_COND_GTU);
 197                 break;
 198             case 0x06: /* bge */
 199                 BRANCH(TCG_COND_GE);
 200                 break;
 201             case 0x07: /* ble */
 202                 BRANCH(TCG_COND_LE);
 203                 break;
 204             case 0x08: /* bgeu */
 205                 BRANCH(TCG_COND_GEU);
 206                 break;
 207             case 0x09: /* bleu */
 208                 BRANCH(TCG_COND_LEU);
 209                 break;
 210             default:
 211                 {
 212                     TCGv temp = tcg_temp_new_i32();
 213                     tcg_gen_movi_i32(cpu_pc, ctx->pc);
 214                     tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 215                     gen_helper_raise_exception(cpu_env, temp);
 216                     tcg_temp_free_i32(temp);
 217                 }
 218                 break;
 219             }
 220         } else {
 221             /* This is a Form 2 instruction.  */
 222             int inst = (opcode >> 12 & 0x3);
 223             switch (inst) {
 224             case 0x00: /* inc */
 225                 {
 226                     int a = (opcode >> 8) & 0xf;
 227                     unsigned int v = (opcode & 0xff);
 228                     tcg_gen_addi_i32(REG(a), REG(a), v);
 229                 }
 230                 break;
 231             case 0x01: /* dec */
 232                 {
 233                     int a = (opcode >> 8) & 0xf;
 234                     unsigned int v = (opcode & 0xff);
 235                     tcg_gen_subi_i32(REG(a), REG(a), v);
 236                 }
 237                 break;
 238             case 0x02: /* gsr */
 239                 {
 240                     int a = (opcode >> 8) & 0xf;
 241                     unsigned v = (opcode & 0xff);
 242                     tcg_gen_ld_i32(REG(a), cpu_env,
 243                                    offsetof(CPUMoxieState, sregs[v]));
 244                 }
 245                 break;
 246             case 0x03: /* ssr */
 247                 {
 248                     int a = (opcode >> 8) & 0xf;
 249                     unsigned v = (opcode & 0xff);
 250                     tcg_gen_st_i32(REG(a), cpu_env,
 251                                    offsetof(CPUMoxieState, sregs[v]));
 252                 }
 253                 break;
 254             default:
 255                 {
 256                     TCGv temp = tcg_temp_new_i32();
 257                     tcg_gen_movi_i32(cpu_pc, ctx->pc);
 258                     tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 259                     gen_helper_raise_exception(cpu_env, temp);
 260                     tcg_temp_free_i32(temp);
 261                 }
 262                 break;
 263             }
 264         }
 265     } else {
 266         /* This is a Form 1 instruction.  */
 267         int inst = opcode >> 8;
 268         switch (inst) {
 269         case 0x00: /* nop */
 270             break;
 271         case 0x01: /* ldi.l (immediate) */
 272             {
 273                 int reg = (opcode >> 4) & 0xf;
 274                 int val = cpu_ldl_code(env, ctx->pc+2);
 275                 tcg_gen_movi_i32(REG(reg), val);
 276                 length = 6;
 277             }
 278             break;
 279         case 0x02: /* mov (register-to-register) */
 280             {
 281                 int dest  = (opcode >> 4) & 0xf;
 282                 int src = opcode & 0xf;
 283                 tcg_gen_mov_i32(REG(dest), REG(src));
 284             }
 285             break;
 286         case 0x03: /* jsra */
 287             {
 288                 TCGv t1 = tcg_temp_new_i32();
 289                 TCGv t2 = tcg_temp_new_i32();
 290
 291                 tcg_gen_movi_i32(t1, ctx->pc + 6);
 292
 293                 /* Make space for the static chain and return address.  */
 294                 tcg_gen_subi_i32(t2, REG(1), 8);
 295                 tcg_gen_mov_i32(REG(1), t2);
 296                 tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
 297
 298                 /* Push the current frame pointer.  */
 299                 tcg_gen_subi_i32(t2, REG(1), 4);
 300                 tcg_gen_mov_i32(REG(1), t2);
 301                 tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
 302
 303                 /* Set the pc and $fp.  */
 304                 tcg_gen_mov_i32(REG(0), REG(1));
 305
 306                 gen_goto_tb(env, ctx, 0, cpu_ldl_code(env, ctx->pc+2));
 307
 308                 tcg_temp_free_i32(t1);
 309                 tcg_temp_free_i32(t2);
 310
 311                 ctx->bstate = BS_BRANCH;
 312                 length = 6;
 313             }
 314             break;
 315         case 0x04: /* ret */
 316             {
 317                 TCGv t1 = tcg_temp_new_i32();
 318
 319                 /* The new $sp is the old $fp.  */
 320                 tcg_gen_mov_i32(REG(1), REG(0));
 321
 322                 /* Pop the frame pointer.  */
 323                 tcg_gen_qemu_ld32u(REG(0), REG(1), ctx->memidx);
 324                 tcg_gen_addi_i32(t1, REG(1), 4);
 325                 tcg_gen_mov_i32(REG(1), t1);
 326
 327
 328                 /* Pop the return address and skip over the static chain
 329                    slot.  */
 330                 tcg_gen_qemu_ld32u(cpu_pc, REG(1), ctx->memidx);
 331                 tcg_gen_addi_i32(t1, REG(1), 8);
 332                 tcg_gen_mov_i32(REG(1), t1);
 333
 334                 tcg_temp_free_i32(t1);
 335
 336                 /* Jump... */
 337                 tcg_gen_exit_tb(0);
 338
 339                 ctx->bstate = BS_BRANCH;
 340             }
 341             break;
 342         case 0x05: /* add.l */
 343             {
 344                 int a = (opcode >> 4) & 0xf;
 345                 int b = opcode & 0xf;
 346
 347                 tcg_gen_add_i32(REG(a), REG(a), REG(b));
 348             }
 349             break;
 350         case 0x06: /* push */
 351             {
 352                 int a = (opcode >> 4) & 0xf;
 353                 int b = opcode & 0xf;
 354
 355                 TCGv t1 = tcg_temp_new_i32();
 356                 tcg_gen_subi_i32(t1, REG(a), 4);
 357                 tcg_gen_mov_i32(REG(a), t1);
 358                 tcg_gen_qemu_st32(REG(b), REG(a), ctx->memidx);
 359                 tcg_temp_free_i32(t1);
 360             }
 361             break;
 362         case 0x07: /* pop */
 363             {
 364                 int a = (opcode >> 4) & 0xf;
 365                 int b = opcode & 0xf;
 366                 TCGv t1 = tcg_temp_new_i32();
 367
 368                 tcg_gen_qemu_ld32u(REG(b), REG(a), ctx->memidx);
 369                 tcg_gen_addi_i32(t1, REG(a), 4);
 370                 tcg_gen_mov_i32(REG(a), t1);
 371                 tcg_temp_free_i32(t1);
 372             }
 373             break;
 374         case 0x08: /* lda.l */
 375             {
 376                 int reg = (opcode >> 4) & 0xf;
 377
 378                 TCGv ptr = tcg_temp_new_i32();
 379                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 380                 tcg_gen_qemu_ld32u(REG(reg), ptr, ctx->memidx);
 381                 tcg_temp_free_i32(ptr);
 382
 383                 length = 6;
 384             }
 385             break;
 386         case 0x09: /* sta.l */
 387             {
 388                 int val = (opcode >> 4) & 0xf;
 389
 390                 TCGv ptr = tcg_temp_new_i32();
 391                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 392                 tcg_gen_qemu_st32(REG(val), ptr, ctx->memidx);
 393                 tcg_temp_free_i32(ptr);
 394
 395                 length = 6;
 396             }
 397             break;
 398         case 0x0a: /* ld.l (register indirect) */
 399             {
 400                 int src  = opcode & 0xf;
 401                 int dest = (opcode >> 4) & 0xf;
 402
 403                 tcg_gen_qemu_ld32u(REG(dest), REG(src), ctx->memidx);
 404             }
 405             break;
 406         case 0x0b: /* st.l */
 407             {
 408                 int dest = (opcode >> 4) & 0xf;
 409                 int val  = opcode & 0xf;
 410
 411                 tcg_gen_qemu_st32(REG(val), REG(dest), ctx->memidx);
 412             }
 413             break;
 414         case 0x0c: /* ldo.l */
 415             {
 416                 int a = (opcode >> 4) & 0xf;
 417                 int b = opcode & 0xf;
 418
 419                 TCGv t1 = tcg_temp_new_i32();
 420                 TCGv t2 = tcg_temp_new_i32();
 421                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 422                 tcg_gen_qemu_ld32u(t2, t1, ctx->memidx);
 423                 tcg_gen_mov_i32(REG(a), t2);
 424
 425                 tcg_temp_free_i32(t1);
 426                 tcg_temp_free_i32(t2);
 427
 428                 length = 6;
 429             }
 430             break;
 431         case 0x0d: /* sto.l */
 432             {
 433                 int a = (opcode >> 4) & 0xf;
 434                 int b = opcode & 0xf;
 435
 436                 TCGv t1 = tcg_temp_new_i32();
 437                 TCGv t2 = tcg_temp_new_i32();
 438                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 439                 tcg_gen_qemu_st32(REG(b), t1, ctx->memidx);
 440
 441                 tcg_temp_free_i32(t1);
 442                 tcg_temp_free_i32(t2);
 443
 444                 length = 6;
 445             }
 446             break;
 447         case 0x0e: /* cmp */
 448             {
 449                 int a  = (opcode >> 4) & 0xf;
 450                 int b  = opcode & 0xf;
 451
 452                 tcg_gen_mov_i32(cc_a, REG(a));
 453                 tcg_gen_mov_i32(cc_b, REG(b));
 454             }
 455             break;
 456         case 0x19: /* jsr */
 457             {
 458                 int fnreg = (opcode >> 4) & 0xf;
 459
 460                 /* Load the stack pointer into T0.  */
 461                 TCGv t1 = tcg_temp_new_i32();
 462                 TCGv t2 = tcg_temp_new_i32();
 463
 464                 tcg_gen_movi_i32(t1, ctx->pc+2);
 465
 466                 /* Make space for the static chain and return address.  */
 467                 tcg_gen_subi_i32(t2, REG(1), 8);
 468                 tcg_gen_mov_i32(REG(1), t2);
 469                 tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
 470
 471                 /* Push the current frame pointer.  */
 472                 tcg_gen_subi_i32(t2, REG(1), 4);
 473                 tcg_gen_mov_i32(REG(1), t2);
 474                 tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
 475
 476                 /* Set the pc and $fp.  */
 477                 tcg_gen_mov_i32(REG(0), REG(1));
 478                 tcg_gen_mov_i32(cpu_pc, REG(fnreg));
 479                 tcg_temp_free_i32(t1);
 480                 tcg_temp_free_i32(t2);
 481                 tcg_gen_exit_tb(0);
 482                 ctx->bstate = BS_BRANCH;
 483             }
 484             break;
 485         case 0x1a: /* jmpa */
 486             {
 487                 tcg_gen_movi_i32(cpu_pc, cpu_ldl_code(env, ctx->pc+2));
 488                 tcg_gen_exit_tb(0);
 489                 ctx->bstate = BS_BRANCH;
 490                 length = 6;
 491             }
 492             break;
 493         case 0x1b: /* ldi.b (immediate) */
 494             {
 495                 int reg = (opcode >> 4) & 0xf;
 496                 int val = cpu_ldl_code(env, ctx->pc+2);
 497                 tcg_gen_movi_i32(REG(reg), val);
 498                 length = 6;
 499             }
 500             break;
 501         case 0x1c: /* ld.b (register indirect) */
 502             {
 503                 int src  = opcode & 0xf;
 504                 int dest = (opcode >> 4) & 0xf;
 505
 506                 tcg_gen_qemu_ld8u(REG(dest), REG(src), ctx->memidx);
 507             }
 508             break;
 509         case 0x1d: /* lda.b */
 510             {
 511                 int reg = (opcode >> 4) & 0xf;
 512
 513                 TCGv ptr = tcg_temp_new_i32();
 514                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 515                 tcg_gen_qemu_ld8u(REG(reg), ptr, ctx->memidx);
 516                 tcg_temp_free_i32(ptr);
 517
 518                 length = 6;
 519             }
 520             break;
 521         case 0x1e: /* st.b */
 522             {
 523                 int dest = (opcode >> 4) & 0xf;
 524                 int val  = opcode & 0xf;
 525
 526                 tcg_gen_qemu_st8(REG(val), REG(dest), ctx->memidx);
 527             }
 528             break;
 529         case 0x1f: /* sta.b */
 530             {
 531                 int val = (opcode >> 4) & 0xf;
 532
 533                 TCGv ptr = tcg_temp_new_i32();
 534                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 535                 tcg_gen_qemu_st8(REG(val), ptr, ctx->memidx);
 536                 tcg_temp_free_i32(ptr);
 537
 538                 length = 6;
 539             }
 540             break;
 541         case 0x20: /* ldi.s (immediate) */
 542             {
 543                 int reg = (opcode >> 4) & 0xf;
 544                 int val = cpu_ldl_code(env, ctx->pc+2);
 545                 tcg_gen_movi_i32(REG(reg), val);
 546                 length = 6;
 547             }
 548             break;
 549         case 0x21: /* ld.s (register indirect) */
 550             {
 551                 int src  = opcode & 0xf;
 552                 int dest = (opcode >> 4) & 0xf;
 553
 554                 tcg_gen_qemu_ld16u(REG(dest), REG(src), ctx->memidx);
 555             }
 556             break;
 557         case 0x22: /* lda.s */
 558             {
 559                 int reg = (opcode >> 4) & 0xf;
 560
 561                 TCGv ptr = tcg_temp_new_i32();
 562                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 563                 tcg_gen_qemu_ld16u(REG(reg), ptr, ctx->memidx);
 564                 tcg_temp_free_i32(ptr);
 565
 566                 length = 6;
 567             }
 568             break;
 569         case 0x23: /* st.s */
 570             {
 571                 int dest = (opcode >> 4) & 0xf;
 572                 int val  = opcode & 0xf;
 573
 574                 tcg_gen_qemu_st16(REG(val), REG(dest), ctx->memidx);
 575             }
 576             break;
 577         case 0x24: /* sta.s */
 578             {
 579                 int val = (opcode >> 4) & 0xf;
 580
 581                 TCGv ptr = tcg_temp_new_i32();
 582                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 583                 tcg_gen_qemu_st16(REG(val), ptr, ctx->memidx);
 584                 tcg_temp_free_i32(ptr);
 585
 586                 length = 6;
 587             }
 588             break;
 589         case 0x25: /* jmp */
 590             {
 591                 int reg = (opcode >> 4) & 0xf;
 592                 tcg_gen_mov_i32(cpu_pc, REG(reg));
 593                 tcg_gen_exit_tb(0);
 594                 ctx->bstate = BS_BRANCH;
 595             }
 596             break;
 597         case 0x26: /* and */
 598             {
 599                 int a = (opcode >> 4) & 0xf;
 600                 int b = opcode & 0xf;
 601
 602                 tcg_gen_and_i32(REG(a), REG(a), REG(b));
 603             }
 604             break;
 605         case 0x27: /* lshr */
 606             {
 607                 int a = (opcode >> 4) & 0xf;
 608                 int b = opcode & 0xf;
 609
 610                 TCGv sv = tcg_temp_new_i32();
 611                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 612                 tcg_gen_shr_i32(REG(a), REG(a), sv);
 613                 tcg_temp_free_i32(sv);
 614             }
 615             break;
 616         case 0x28: /* ashl */
 617             {
 618                 int a = (opcode >> 4) & 0xf;
 619                 int b = opcode & 0xf;
 620
 621                 TCGv sv = tcg_temp_new_i32();
 622                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 623                 tcg_gen_shl_i32(REG(a), REG(a), sv);
 624                 tcg_temp_free_i32(sv);
 625             }
 626             break;
 627         case 0x29: /* sub.l */
 628             {
 629                 int a = (opcode >> 4) & 0xf;
 630                 int b = opcode & 0xf;
 631
 632                 tcg_gen_sub_i32(REG(a), REG(a), REG(b));
 633             }
 634             break;
 635         case 0x2a: /* neg */
 636             {
 637                 int a = (opcode >> 4) & 0xf;
 638                 int b = opcode & 0xf;
 639
 640                 tcg_gen_neg_i32(REG(a), REG(b));
 641             }
 642             break;
 643         case 0x2b: /* or */
 644             {
 645                 int a = (opcode >> 4) & 0xf;
 646                 int b = opcode & 0xf;
 647
 648                 tcg_gen_or_i32(REG(a), REG(a), REG(b));
 649             }
 650             break;
 651         case 0x2c: /* not */
 652             {
 653                 int a = (opcode >> 4) & 0xf;
 654                 int b = opcode & 0xf;
 655
 656                 tcg_gen_not_i32(REG(a), REG(b));
 657             }
 658             break;
 659         case 0x2d: /* ashr */
 660             {
 661                 int a = (opcode >> 4) & 0xf;
 662                 int b = opcode & 0xf;
 663
 664                 TCGv sv = tcg_temp_new_i32();
 665                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 666                 tcg_gen_sar_i32(REG(a), REG(a), sv);
 667                 tcg_temp_free_i32(sv);
 668             }
 669             break;
 670         case 0x2e: /* xor */
 671             {
 672                 int a = (opcode >> 4) & 0xf;
 673                 int b = opcode & 0xf;
 674
 675                 tcg_gen_xor_i32(REG(a), REG(a), REG(b));
 676             }
 677             break;
 678         case 0x2f: /* mul.l */
 679             {
 680                 int a = (opcode >> 4) & 0xf;
 681                 int b = opcode & 0xf;
 682
 683                 tcg_gen_mul_i32(REG(a), REG(a), REG(b));
 684             }
 685             break;
 686         case 0x30: /* swi */
 687             {
 688                 int val = cpu_ldl_code(env, ctx->pc+2);
 689
 690                 TCGv temp = tcg_temp_new_i32();
 691                 tcg_gen_movi_i32(temp, val);
 692                 tcg_gen_st_i32(temp, cpu_env,
 693                                offsetof(CPUMoxieState, sregs[3]));
 694                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 695                 tcg_gen_movi_i32(temp, MOXIE_EX_SWI);
 696                 gen_helper_raise_exception(cpu_env, temp);
 697                 tcg_temp_free_i32(temp);
 698
 699                 length = 6;
 700             }
 701             break;
 702         case 0x31: /* div.l */
 703             {
 704                 int a = (opcode >> 4) & 0xf;
 705                 int b = opcode & 0xf;
 706                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 707                 gen_helper_div(REG(a), cpu_env, REG(a), REG(b));
 708             }
 709             break;
 710         case 0x32: /* udiv.l */
 711             {
 712                 int a = (opcode >> 4) & 0xf;
 713                 int b = opcode & 0xf;
 714                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 715                 gen_helper_udiv(REG(a), cpu_env, REG(a), REG(b));
 716             }
 717             break;
 718         case 0x33: /* mod.l */
 719             {
 720                 int a = (opcode >> 4) & 0xf;
 721                 int b = opcode & 0xf;
 722                 tcg_gen_rem_i32(REG(a), REG(a), REG(b));
 723             }
 724             break;
 725         case 0x34: /* umod.l */
 726             {
 727                 int a = (opcode >> 4) & 0xf;
 728                 int b = opcode & 0xf;
 729                 tcg_gen_remu_i32(REG(a), REG(a), REG(b));
 730             }
 731             break;
 732         case 0x35: /* brk */
 733             {
 734                 TCGv temp = tcg_temp_new_i32();
 735                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 736                 tcg_gen_movi_i32(temp, MOXIE_EX_BREAK);
 737                 gen_helper_raise_exception(cpu_env, temp);
 738                 tcg_temp_free_i32(temp);
 739             }
 740             break;
 741         case 0x36: /* ldo.b */
 742             {
 743                 int a = (opcode >> 4) & 0xf;
 744                 int b = opcode & 0xf;
 745
 746                 TCGv t1 = tcg_temp_new_i32();
 747                 TCGv t2 = tcg_temp_new_i32();
 748                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 749                 tcg_gen_qemu_ld8u(t2, t1, ctx->memidx);
 750                 tcg_gen_mov_i32(REG(a), t2);
 751
 752                 tcg_temp_free_i32(t1);
 753                 tcg_temp_free_i32(t2);
 754
 755                 length = 6;
 756             }
 757             break;
 758         case 0x37: /* sto.b */
 759             {
 760                 int a = (opcode >> 4) & 0xf;
 761                 int b = opcode & 0xf;
 762
 763                 TCGv t1 = tcg_temp_new_i32();
 764                 TCGv t2 = tcg_temp_new_i32();
 765                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 766                 tcg_gen_qemu_st8(REG(b), t1, ctx->memidx);
 767
 768                 tcg_temp_free_i32(t1);
 769                 tcg_temp_free_i32(t2);
 770
 771                 length = 6;
 772             }
 773             break;
 774         case 0x38: /* ldo.s */
 775             {
 776                 int a = (opcode >> 4) & 0xf;
 777                 int b = opcode & 0xf;
 778
 779                 TCGv t1 = tcg_temp_new_i32();
 780                 TCGv t2 = tcg_temp_new_i32();
 781                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 782                 tcg_gen_qemu_ld16u(t2, t1, ctx->memidx);
 783                 tcg_gen_mov_i32(REG(a), t2);
 784
 785                 tcg_temp_free_i32(t1);
 786                 tcg_temp_free_i32(t2);
 787
 788                 length = 6;
 789             }
 790             break;
 791         case 0x39: /* sto.s */
 792             {
 793                 int a = (opcode >> 4) & 0xf;
 794                 int b = opcode & 0xf;
 795
 796                 TCGv t1 = tcg_temp_new_i32();
 797                 TCGv t2 = tcg_temp_new_i32();
 798                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 799                 tcg_gen_qemu_st16(REG(b), t1, ctx->memidx);
 800                 tcg_temp_free_i32(t1);
 801                 tcg_temp_free_i32(t2);
 802
 803                 length = 6;
 804             }
 805             break;
 806         default:
 807             {
 808                 TCGv temp = tcg_temp_new_i32();
 809                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 810                 tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 811                 gen_helper_raise_exception(cpu_env, temp);
 812                 tcg_temp_free_i32(temp);
 813              }
 814             break;
 815         }
 816     }
 817
 818     return length;
 819 }
 820
 821 /* generate intermediate code for basic block 'tb'.  */
 822 static inline void
 823 gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
 824                                bool search_pc)
 825 {
 826     CPUState *cs = CPU(cpu);
 827     DisasContext ctx;
 828     target_ulong pc_start;
 829     CPUBreakpoint *bp;
 830     int j, lj = -1;
 831     CPUMoxieState *env = &cpu->env;
 832     int num_insns;
 833
 834     pc_start = tb->pc;
 835     ctx.pc = pc_start;
 836     ctx.saved_pc = -1;
 837     ctx.tb = tb;
 838     ctx.memidx = 0;
 839     ctx.singlestep_enabled = 0;
 840     ctx.bstate = BS_NONE;
 841     num_insns = 0;
 842
 843     gen_tb_start(tb);
 844     do {
 845         if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
 846             QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
 847                 if (ctx.pc == bp->pc) {
 848                     tcg_gen_movi_i32(cpu_pc, ctx.pc);
 849                     gen_helper_debug(cpu_env);
 850                     ctx.bstate = BS_EXCP;
 851                     goto done_generating;
 852                 }
 853             }
 854         }
 855
 856         if (search_pc) {
 857             j = tcg_op_buf_count();
 858             if (lj < j) {
 859                 lj++;
 860                 while (lj < j) {
 861                     tcg_ctx.gen_opc_instr_start[lj++] = 0;
 862                 }
 863             }
 864             tcg_ctx.gen_opc_pc[lj] = ctx.pc;
 865             tcg_ctx.gen_opc_instr_start[lj] = 1;
 866             tcg_ctx.gen_opc_icount[lj] = num_insns;
 867         }
 868         ctx.opcode = cpu_lduw_code(env, ctx.pc);
 869         ctx.pc += decode_opc(cpu, &ctx);
 870         num_insns++;
 871
 872         if (cs->singlestep_enabled) {
 873             break;
 874         }
 875
 876         if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
 877             break;
 878         }
 879     } while (ctx.bstate == BS_NONE && !tcg_op_buf_full());
 880
 881     if (cs->singlestep_enabled) {
 882         tcg_gen_movi_tl(cpu_pc, ctx.pc);
 883         gen_helper_debug(cpu_env);
 884     } else {
 885         switch (ctx.bstate) {
 886         case BS_STOP:
 887         case BS_NONE:
 888             gen_goto_tb(env, &ctx, 0, ctx.pc);
 889             break;
 890         case BS_EXCP:
 891             tcg_gen_exit_tb(0);
 892             break;
 893         case BS_BRANCH:
 894         default:
 895             break;
 896         }
 897     }
 898  done_generating:
 899     gen_tb_end(tb, num_insns);
 900
 901     if (search_pc) {
 902         j = tcg_op_buf_count();
 903         lj++;
 904         while (lj <= j) {
 905             tcg_ctx.gen_opc_instr_start[lj++] = 0;
 906         }
 907     } else {
 908         tb->size = ctx.pc - pc_start;
 909         tb->icount = num_insns;
 910     }
 911 }
 912
 913 void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
 914 {
 915     gen_intermediate_code_internal(moxie_env_get_cpu(env), tb, false);
 916 }
 917
 918 void gen_intermediate_code_pc(CPUMoxieState *env, struct TranslationBlock *tb)
 919 {
 920     gen_intermediate_code_internal(moxie_env_get_cpu(env), tb, true);
 921 }
 922
 923 void restore_state_to_opc(CPUMoxieState *env, TranslationBlock *tb, int pc_pos)
 924 {
 925     env->pc = tcg_ctx.gen_opc_pc[pc_pos];
 926 }