target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  34                                                         uint32_t exception,
  35                                                         int error_code,
  36                                                         uintptr_t pc)
  37 {
  38     CPUState *cs = CPU(mips_env_get_cpu(env));
  39
  40     if (exception < EXCP_SC) {
  41         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  42     }
  43     cs->exception_index = exception;
  44     env->error_code = error_code;
  45
  46     if (pc) {
  47         /* now we have a real cpu fault */
  48         cpu_restore_state(cs, pc);
  49     }
  50
  51     cpu_loop_exit(cs);
  52 }
  53
  54 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  55                                                     uint32_t exception,
  56                                                     uintptr_t pc)
  57 {
  58     do_raise_exception_err(env, exception, 0, pc);
  59 }
  60
  61 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  62                                 int error_code)
  63 {
  64     do_raise_exception_err(env, exception, error_code, 0);
  65 }
  66
  67 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  68 {
  69     do_raise_exception(env, exception, 0);
  70 }
  71
  72 #if defined(CONFIG_USER_ONLY)
  73 #define HELPER_LD(name, insn, type)                                     \
  74 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  75                              int mem_idx)                               \
  76 {                                                                       \
  77     return (type) cpu_##insn##_data(env, addr);                         \
  78 }
  79 #else
  80 #define HELPER_LD(name, insn, type)                                     \
  81 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  82                              int mem_idx)                               \
  83 {                                                                       \
  84     switch (mem_idx)                                                    \
  85     {                                                                   \
  86     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  87     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  88     default:                                                            \
  89     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  90     }                                                                   \
  91 }
  92 #endif
  93 HELPER_LD(lbu, ldub, uint8_t)
  94 HELPER_LD(lhu, lduw, uint16_t)
  95 HELPER_LD(lw, ldl, int32_t)
  96 HELPER_LD(ld, ldq, int64_t)
  97 #undef HELPER_LD
  98
  99 #if defined(CONFIG_USER_ONLY)
 100 #define HELPER_ST(name, insn, type)                                     \
 101 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 102                              type val, int mem_idx)                     \
 103 {                                                                       \
 104     cpu_##insn##_data(env, addr, val);                                  \
 105 }
 106 #else
 107 #define HELPER_ST(name, insn, type)                                     \
 108 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 109                              type val, int mem_idx)                     \
 110 {                                                                       \
 111     switch (mem_idx)                                                    \
 112     {                                                                   \
 113     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 114     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 115     default:                                                            \
 116     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 117     }                                                                   \
 118 }
 119 #endif
 120 HELPER_ST(sb, stb, uint8_t)
 121 HELPER_ST(sh, stw, uint16_t)
 122 HELPER_ST(sw, stl, uint32_t)
 123 HELPER_ST(sd, stq, uint64_t)
 124 #undef HELPER_ST
 125
 126 target_ulong helper_clo (target_ulong arg1)
 127 {
 128     return clo32(arg1);
 129 }
 130
 131 target_ulong helper_clz (target_ulong arg1)
 132 {
 133     return clz32(arg1);
 134 }
 135
 136 #if defined(TARGET_MIPS64)
 137 target_ulong helper_dclo (target_ulong arg1)
 138 {
 139     return clo64(arg1);
 140 }
 141
 142 target_ulong helper_dclz (target_ulong arg1)
 143 {
 144     return clz64(arg1);
 145 }
 146 #endif /* TARGET_MIPS64 */
 147
 148 /* 64 bits arithmetic for 32 bits hosts */
 149 static inline uint64_t get_HILO(CPUMIPSState *env)
 150 {
 151     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 152 }
 153
 154 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 155 {
 156     target_ulong tmp;
 157     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 158     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 159     return tmp;
 160 }
 161
 162 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 163 {
 164     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 165     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 166     return tmp;
 167 }
 168
 169 /* Multiplication variants of the vr54xx. */
 170 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 171                          target_ulong arg2)
 172 {
 173     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 174                                  (int64_t)(int32_t)arg2));
 175 }
 176
 177 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 178                           target_ulong arg2)
 179 {
 180     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 181                        (uint64_t)(uint32_t)arg2);
 182 }
 183
 184 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 185                          target_ulong arg2)
 186 {
 187     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 188                        (int64_t)(int32_t)arg2);
 189 }
 190
 191 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 192                            target_ulong arg2)
 193 {
 194     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 195                        (int64_t)(int32_t)arg2);
 196 }
 197
 198 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 199                           target_ulong arg2)
 200 {
 201     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 202                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 203 }
 204
 205 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 206                             target_ulong arg2)
 207 {
 208     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 209                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 210 }
 211
 212 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 213                          target_ulong arg2)
 214 {
 215     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 216                        (int64_t)(int32_t)arg2);
 217 }
 218
 219 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 220                            target_ulong arg2)
 221 {
 222     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 223                        (int64_t)(int32_t)arg2);
 224 }
 225
 226 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 227                           target_ulong arg2)
 228 {
 229     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 230                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 231 }
 232
 233 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 234                             target_ulong arg2)
 235 {
 236     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 237                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 238 }
 239
 240 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 241                           target_ulong arg2)
 242 {
 243     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 244 }
 245
 246 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 247                            target_ulong arg2)
 248 {
 249     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 250                        (uint64_t)(uint32_t)arg2);
 251 }
 252
 253 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 254                            target_ulong arg2)
 255 {
 256     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 257                        (int64_t)(int32_t)arg2);
 258 }
 259
 260 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 261                             target_ulong arg2)
 262 {
 263     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 264                        (uint64_t)(uint32_t)arg2);
 265 }
 266
 267 static inline target_ulong bitswap(target_ulong v)
 268 {
 269     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 270               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 271     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 272               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 273     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 274               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 275     return v;
 276 }
 277
 278 #ifdef TARGET_MIPS64
 279 target_ulong helper_dbitswap(target_ulong rt)
 280 {
 281     return bitswap(rt);
 282 }
 283 #endif
 284
 285 target_ulong helper_bitswap(target_ulong rt)
 286 {
 287     return (int32_t)bitswap(rt);
 288 }
 289
 290 #ifndef CONFIG_USER_ONLY
 291
 292 static inline hwaddr do_translate_address(CPUMIPSState *env,
 293                                                       target_ulong address,
 294                                                       int rw)
 295 {
 296     hwaddr lladdr;
 297
 298     lladdr = cpu_mips_translate_address(env, address, rw);
 299
 300     if (lladdr == -1LL) {
 301         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 302     } else {
 303         return lladdr;
 304     }
 305 }
 306
 307 #define HELPER_LD_ATOMIC(name, insn, almask)                                  \
 308 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 309 {                                                                             \
 310     if (arg & almask) {                                                       \
 311         env->CP0_BadVAddr = arg;                                              \
 312         helper_raise_exception(env, EXCP_AdEL);                               \
 313     }                                                                         \
 314     env->lladdr = do_translate_address(env, arg, 0);                          \
 315     env->llval = do_##insn(env, arg, mem_idx);                                \
 316     return env->llval;                                                        \
 317 }
 318 HELPER_LD_ATOMIC(ll, lw, 0x3)
 319 #ifdef TARGET_MIPS64
 320 HELPER_LD_ATOMIC(lld, ld, 0x7)
 321 #endif
 322 #undef HELPER_LD_ATOMIC
 323
 324 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 325 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 326                            target_ulong arg2, int mem_idx)                    \
 327 {                                                                             \
 328     target_long tmp;                                                          \
 329                                                                               \
 330     if (arg2 & almask) {                                                      \
 331         env->CP0_BadVAddr = arg2;                                             \
 332         helper_raise_exception(env, EXCP_AdES);                               \
 333     }                                                                         \
 334     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 335         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 336         if (tmp == env->llval) {                                              \
 337             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 338             return 1;                                                         \
 339         }                                                                     \
 340     }                                                                         \
 341     return 0;                                                                 \
 342 }
 343 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 344 #ifdef TARGET_MIPS64
 345 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 346 #endif
 347 #undef HELPER_ST_ATOMIC
 348 #endif
 349
 350 #ifdef TARGET_WORDS_BIGENDIAN
 351 #define GET_LMASK(v) ((v) & 3)
 352 #define GET_OFFSET(addr, offset) (addr + (offset))
 353 #else
 354 #define GET_LMASK(v) (((v) & 3) ^ 3)
 355 #define GET_OFFSET(addr, offset) (addr - (offset))
 356 #endif
 357
 358 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 359                 int mem_idx)
 360 {
 361     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 362
 363     if (GET_LMASK(arg2) <= 2)
 364         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 365
 366     if (GET_LMASK(arg2) <= 1)
 367         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 368
 369     if (GET_LMASK(arg2) == 0)
 370         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 371 }
 372
 373 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 374                 int mem_idx)
 375 {
 376     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 377
 378     if (GET_LMASK(arg2) >= 1)
 379         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 380
 381     if (GET_LMASK(arg2) >= 2)
 382         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 383
 384     if (GET_LMASK(arg2) == 3)
 385         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 386 }
 387
 388 #if defined(TARGET_MIPS64)
 389 /* "half" load and stores.  We must do the memory access inline,
 390    or fault handling won't work.  */
 391
 392 #ifdef TARGET_WORDS_BIGENDIAN
 393 #define GET_LMASK64(v) ((v) & 7)
 394 #else
 395 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 396 #endif
 397
 398 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 399                 int mem_idx)
 400 {
 401     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 402
 403     if (GET_LMASK64(arg2) <= 6)
 404         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 405
 406     if (GET_LMASK64(arg2) <= 5)
 407         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 408
 409     if (GET_LMASK64(arg2) <= 4)
 410         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 411
 412     if (GET_LMASK64(arg2) <= 3)
 413         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 414
 415     if (GET_LMASK64(arg2) <= 2)
 416         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 417
 418     if (GET_LMASK64(arg2) <= 1)
 419         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 420
 421     if (GET_LMASK64(arg2) <= 0)
 422         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 423 }
 424
 425 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 426                 int mem_idx)
 427 {
 428     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 429
 430     if (GET_LMASK64(arg2) >= 1)
 431         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 432
 433     if (GET_LMASK64(arg2) >= 2)
 434         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 435
 436     if (GET_LMASK64(arg2) >= 3)
 437         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 438
 439     if (GET_LMASK64(arg2) >= 4)
 440         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 441
 442     if (GET_LMASK64(arg2) >= 5)
 443         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 444
 445     if (GET_LMASK64(arg2) >= 6)
 446         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 447
 448     if (GET_LMASK64(arg2) == 7)
 449         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 450 }
 451 #endif /* TARGET_MIPS64 */
 452
 453 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 454
 455 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 456                 uint32_t mem_idx)
 457 {
 458     target_ulong base_reglist = reglist & 0xf;
 459     target_ulong do_r31 = reglist & 0x10;
 460
 461     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 462         target_ulong i;
 463
 464         for (i = 0; i < base_reglist; i++) {
 465             env->active_tc.gpr[multiple_regs[i]] =
 466                 (target_long)do_lw(env, addr, mem_idx);
 467             addr += 4;
 468         }
 469     }
 470
 471     if (do_r31) {
 472         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 473     }
 474 }
 475
 476 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 477                 uint32_t mem_idx)
 478 {
 479     target_ulong base_reglist = reglist & 0xf;
 480     target_ulong do_r31 = reglist & 0x10;
 481
 482     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 483         target_ulong i;
 484
 485         for (i = 0; i < base_reglist; i++) {
 486             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 487             addr += 4;
 488         }
 489     }
 490
 491     if (do_r31) {
 492         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 493     }
 494 }
 495
 496 #if defined(TARGET_MIPS64)
 497 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 498                 uint32_t mem_idx)
 499 {
 500     target_ulong base_reglist = reglist & 0xf;
 501     target_ulong do_r31 = reglist & 0x10;
 502
 503     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 504         target_ulong i;
 505
 506         for (i = 0; i < base_reglist; i++) {
 507             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 508             addr += 8;
 509         }
 510     }
 511
 512     if (do_r31) {
 513         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 514     }
 515 }
 516
 517 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 518                 uint32_t mem_idx)
 519 {
 520     target_ulong base_reglist = reglist & 0xf;
 521     target_ulong do_r31 = reglist & 0x10;
 522
 523     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 524         target_ulong i;
 525
 526         for (i = 0; i < base_reglist; i++) {
 527             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 528             addr += 8;
 529         }
 530     }
 531
 532     if (do_r31) {
 533         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 534     }
 535 }
 536 #endif
 537
 538 #ifndef CONFIG_USER_ONLY
 539 /* SMP helpers.  */
 540 static bool mips_vpe_is_wfi(MIPSCPU *c)
 541 {
 542     CPUState *cpu = CPU(c);
 543     CPUMIPSState *env = &c->env;
 544
 545     /* If the VPE is halted but otherwise active, it means it's waiting for
 546        an interrupt.  */
 547     return cpu->halted && mips_vpe_active(env);
 548 }
 549
 550 static inline void mips_vpe_wake(MIPSCPU *c)
 551 {
 552     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 553        because there might be other conditions that state that c should
 554        be sleeping.  */
 555     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 556 }
 557
 558 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 559 {
 560     CPUState *cs = CPU(cpu);
 561
 562     /* The VPE was shut off, really go to bed.
 563        Reset any old _WAKE requests.  */
 564     cs->halted = 1;
 565     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 566 }
 567
 568 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 569 {
 570     CPUMIPSState *c = &cpu->env;
 571
 572     /* FIXME: TC reschedule.  */
 573     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 574         mips_vpe_wake(cpu);
 575     }
 576 }
 577
 578 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 579 {
 580     CPUMIPSState *c = &cpu->env;
 581
 582     /* FIXME: TC reschedule.  */
 583     if (!mips_vpe_active(c)) {
 584         mips_vpe_sleep(cpu);
 585     }
 586 }
 587
 588 /**
 589  * mips_cpu_map_tc:
 590  * @env: CPU from which mapping is performed.
 591  * @tc: Should point to an int with the value of the global TC index.
 592  *
 593  * This function will transform @tc into a local index within the
 594  * returned #CPUMIPSState.
 595  */
 596 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 597           which depends on runtime setup. Can probably be fixed by
 598           walking the list of CPUMIPSStates.  */
 599 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 600 {
 601     MIPSCPU *cpu;
 602     CPUState *cs;
 603     CPUState *other_cs;
 604     int vpe_idx;
 605     int tc_idx = *tc;
 606
 607     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 608         /* Not allowed to address other CPUs.  */
 609         *tc = env->current_tc;
 610         return env;
 611     }
 612
 613     cs = CPU(mips_env_get_cpu(env));
 614     vpe_idx = tc_idx / cs->nr_threads;
 615     *tc = tc_idx % cs->nr_threads;
 616     other_cs = qemu_get_cpu(vpe_idx);
 617     if (other_cs == NULL) {
 618         return env;
 619     }
 620     cpu = MIPS_CPU(other_cs);
 621     return &cpu->env;
 622 }
 623
 624 /* The per VPE CP0_Status register shares some fields with the per TC
 625    CP0_TCStatus registers. These fields are wired to the same registers,
 626    so changes to either of them should be reflected on both registers.
 627
 628    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 629
 630    These helper call synchronizes the regs for a given cpu.  */
 631
 632 /* Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.  */
 633 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 634                                      int tc);  */
 635
 636 /* Called for updates to CP0_TCStatus.  */
 637 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 638                              target_ulong v)
 639 {
 640     uint32_t status;
 641     uint32_t tcu, tmx, tasid, tksu;
 642     uint32_t mask = ((1U << CP0St_CU3)
 643                        | (1 << CP0St_CU2)
 644                        | (1 << CP0St_CU1)
 645                        | (1 << CP0St_CU0)
 646                        | (1 << CP0St_MX)
 647                        | (3 << CP0St_KSU));
 648
 649     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 650     tmx = (v >> CP0TCSt_TMX) & 0x1;
 651     tasid = v & 0xff;
 652     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 653
 654     status = tcu << CP0St_CU0;
 655     status |= tmx << CP0St_MX;
 656     status |= tksu << CP0St_KSU;
 657
 658     cpu->CP0_Status &= ~mask;
 659     cpu->CP0_Status |= status;
 660
 661     /* Sync the TASID with EntryHi.  */
 662     cpu->CP0_EntryHi &= ~0xff;
 663     cpu->CP0_EntryHi = tasid;
 664
 665     compute_hflags(cpu);
 666 }
 667
 668 /* Called for updates to CP0_EntryHi.  */
 669 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 670 {
 671     int32_t *tcst;
 672     uint32_t asid, v = cpu->CP0_EntryHi;
 673
 674     asid = v & 0xff;
 675
 676     if (tc == cpu->current_tc) {
 677         tcst = &cpu->active_tc.CP0_TCStatus;
 678     } else {
 679         tcst = &cpu->tcs[tc].CP0_TCStatus;
 680     }
 681
 682     *tcst &= ~0xff;
 683     *tcst |= asid;
 684 }
 685
 686 /* CP0 helpers */
 687 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 688 {
 689     return env->mvp->CP0_MVPControl;
 690 }
 691
 692 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 693 {
 694     return env->mvp->CP0_MVPConf0;
 695 }
 696
 697 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 698 {
 699     return env->mvp->CP0_MVPConf1;
 700 }
 701
 702 target_ulong helper_mfc0_random(CPUMIPSState *env)
 703 {
 704     return (int32_t)cpu_mips_get_random(env);
 705 }
 706
 707 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 708 {
 709     return env->active_tc.CP0_TCStatus;
 710 }
 711
 712 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 713 {
 714     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 715     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 716
 717     if (other_tc == other->current_tc)
 718         return other->active_tc.CP0_TCStatus;
 719     else
 720         return other->tcs[other_tc].CP0_TCStatus;
 721 }
 722
 723 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 724 {
 725     return env->active_tc.CP0_TCBind;
 726 }
 727
 728 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 729 {
 730     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 731     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 732
 733     if (other_tc == other->current_tc)
 734         return other->active_tc.CP0_TCBind;
 735     else
 736         return other->tcs[other_tc].CP0_TCBind;
 737 }
 738
 739 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 740 {
 741     return env->active_tc.PC;
 742 }
 743
 744 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 745 {
 746     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 747     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 748
 749     if (other_tc == other->current_tc)
 750         return other->active_tc.PC;
 751     else
 752         return other->tcs[other_tc].PC;
 753 }
 754
 755 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 756 {
 757     return env->active_tc.CP0_TCHalt;
 758 }
 759
 760 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 761 {
 762     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 763     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 764
 765     if (other_tc == other->current_tc)
 766         return other->active_tc.CP0_TCHalt;
 767     else
 768         return other->tcs[other_tc].CP0_TCHalt;
 769 }
 770
 771 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 772 {
 773     return env->active_tc.CP0_TCContext;
 774 }
 775
 776 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 777 {
 778     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 779     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 780
 781     if (other_tc == other->current_tc)
 782         return other->active_tc.CP0_TCContext;
 783     else
 784         return other->tcs[other_tc].CP0_TCContext;
 785 }
 786
 787 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 788 {
 789     return env->active_tc.CP0_TCSchedule;
 790 }
 791
 792 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 793 {
 794     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 795     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 796
 797     if (other_tc == other->current_tc)
 798         return other->active_tc.CP0_TCSchedule;
 799     else
 800         return other->tcs[other_tc].CP0_TCSchedule;
 801 }
 802
 803 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 804 {
 805     return env->active_tc.CP0_TCScheFBack;
 806 }
 807
 808 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 809 {
 810     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 811     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 812
 813     if (other_tc == other->current_tc)
 814         return other->active_tc.CP0_TCScheFBack;
 815     else
 816         return other->tcs[other_tc].CP0_TCScheFBack;
 817 }
 818
 819 target_ulong helper_mfc0_count(CPUMIPSState *env)
 820 {
 821     return (int32_t)cpu_mips_get_count(env);
 822 }
 823
 824 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 825 {
 826     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 827     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 828
 829     return other->CP0_EntryHi;
 830 }
 831
 832 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 833 {
 834     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 835     int32_t tccause;
 836     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 837
 838     if (other_tc == other->current_tc) {
 839         tccause = other->CP0_Cause;
 840     } else {
 841         tccause = other->CP0_Cause;
 842     }
 843
 844     return tccause;
 845 }
 846
 847 target_ulong helper_mftc0_status(CPUMIPSState *env)
 848 {
 849     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 850     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 851
 852     return other->CP0_Status;
 853 }
 854
 855 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 856 {
 857     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 858 }
 859
 860 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 861 {
 862     return (int32_t)env->CP0_WatchLo[sel];
 863 }
 864
 865 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 866 {
 867     return env->CP0_WatchHi[sel];
 868 }
 869
 870 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 871 {
 872     target_ulong t0 = env->CP0_Debug;
 873     if (env->hflags & MIPS_HFLAG_DM)
 874         t0 |= 1 << CP0DB_DM;
 875
 876     return t0;
 877 }
 878
 879 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 880 {
 881     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 882     int32_t tcstatus;
 883     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 884
 885     if (other_tc == other->current_tc)
 886         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 887     else
 888         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 889
 890     /* XXX: Might be wrong, check with EJTAG spec. */
 891     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 892             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 893 }
 894
 895 #if defined(TARGET_MIPS64)
 896 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 897 {
 898     return env->active_tc.PC;
 899 }
 900
 901 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 902 {
 903     return env->active_tc.CP0_TCHalt;
 904 }
 905
 906 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 907 {
 908     return env->active_tc.CP0_TCContext;
 909 }
 910
 911 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 912 {
 913     return env->active_tc.CP0_TCSchedule;
 914 }
 915
 916 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 917 {
 918     return env->active_tc.CP0_TCScheFBack;
 919 }
 920
 921 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 922 {
 923     return env->lladdr >> env->CP0_LLAddr_shift;
 924 }
 925
 926 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 927 {
 928     return env->CP0_WatchLo[sel];
 929 }
 930 #endif /* TARGET_MIPS64 */
 931
 932 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 933 {
 934     uint32_t index_p = env->CP0_Index & 0x80000000;
 935     uint32_t tlb_index = arg1 & 0x7fffffff;
 936     if (tlb_index < env->tlb->nb_tlb) {
 937         if (env->insn_flags & ISA_MIPS32R6) {
 938             index_p |= arg1 & 0x80000000;
 939         }
 940         env->CP0_Index = index_p | tlb_index;
 941     }
 942 }
 943
 944 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 945 {
 946     uint32_t mask = 0;
 947     uint32_t newval;
 948
 949     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 950         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 951                 (1 << CP0MVPCo_EVP);
 952     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 953         mask |= (1 << CP0MVPCo_STLB);
 954     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 955
 956     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 957
 958     env->mvp->CP0_MVPControl = newval;
 959 }
 960
 961 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 962 {
 963     uint32_t mask;
 964     uint32_t newval;
 965
 966     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 967            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 968     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 969
 970     /* Yield scheduler intercept not implemented. */
 971     /* Gating storage scheduler intercept not implemented. */
 972
 973     // TODO: Enable/disable TCs.
 974
 975     env->CP0_VPEControl = newval;
 976 }
 977
 978 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 979 {
 980     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 981     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 982     uint32_t mask;
 983     uint32_t newval;
 984
 985     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 986            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 987     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 988
 989     /* TODO: Enable/disable TCs.  */
 990
 991     other->CP0_VPEControl = newval;
 992 }
 993
 994 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
 995 {
 996     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 997     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 998     /* FIXME: Mask away return zero on read bits.  */
 999     return other->CP0_VPEControl;
1000 }
1001
1002 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1003 {
1004     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1005     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1006
1007     return other->CP0_VPEConf0;
1008 }
1009
1010 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1011 {
1012     uint32_t mask = 0;
1013     uint32_t newval;
1014
1015     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1016         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1017             mask |= (0xff << CP0VPEC0_XTC);
1018         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1019     }
1020     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1021
1022     // TODO: TC exclusive handling due to ERL/EXL.
1023
1024     env->CP0_VPEConf0 = newval;
1025 }
1026
1027 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1028 {
1029     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1030     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1031     uint32_t mask = 0;
1032     uint32_t newval;
1033
1034     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1035     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1036
1037     /* TODO: TC exclusive handling due to ERL/EXL.  */
1038     other->CP0_VPEConf0 = newval;
1039 }
1040
1041 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1042 {
1043     uint32_t mask = 0;
1044     uint32_t newval;
1045
1046     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1047         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1048                 (0xff << CP0VPEC1_NCP1);
1049     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1050
1051     /* UDI not implemented. */
1052     /* CP2 not implemented. */
1053
1054     // TODO: Handle FPU (CP1) binding.
1055
1056     env->CP0_VPEConf1 = newval;
1057 }
1058
1059 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1060 {
1061     /* Yield qualifier inputs not implemented. */
1062     env->CP0_YQMask = 0x00000000;
1063 }
1064
1065 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1066 {
1067     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1068 }
1069
1070 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1071 {
1072     /* Large physaddr (PABITS) not implemented */
1073     /* 1k pages not implemented */
1074     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1075     env->CP0_EntryLo0 = (arg1 & 0x3FFFFFFF) | (rxi << (CP0EnLo_XI - 30));
1076 }
1077
1078 #if defined(TARGET_MIPS64)
1079 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1080 {
1081     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1082     env->CP0_EntryLo0 = (arg1 & 0x3FFFFFFF) | rxi;
1083 }
1084 #endif
1085
1086 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1087 {
1088     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1089     uint32_t newval;
1090
1091     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1092
1093     env->active_tc.CP0_TCStatus = newval;
1094     sync_c0_tcstatus(env, env->current_tc, newval);
1095 }
1096
1097 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1098 {
1099     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1100     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1101
1102     if (other_tc == other->current_tc)
1103         other->active_tc.CP0_TCStatus = arg1;
1104     else
1105         other->tcs[other_tc].CP0_TCStatus = arg1;
1106     sync_c0_tcstatus(other, other_tc, arg1);
1107 }
1108
1109 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1110 {
1111     uint32_t mask = (1 << CP0TCBd_TBE);
1112     uint32_t newval;
1113
1114     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1115         mask |= (1 << CP0TCBd_CurVPE);
1116     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1117     env->active_tc.CP0_TCBind = newval;
1118 }
1119
1120 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1121 {
1122     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1123     uint32_t mask = (1 << CP0TCBd_TBE);
1124     uint32_t newval;
1125     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1126
1127     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1128         mask |= (1 << CP0TCBd_CurVPE);
1129     if (other_tc == other->current_tc) {
1130         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1131         other->active_tc.CP0_TCBind = newval;
1132     } else {
1133         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1134         other->tcs[other_tc].CP0_TCBind = newval;
1135     }
1136 }
1137
1138 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1139 {
1140     env->active_tc.PC = arg1;
1141     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1142     env->lladdr = 0ULL;
1143     /* MIPS16 not implemented. */
1144 }
1145
1146 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1147 {
1148     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1149     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1150
1151     if (other_tc == other->current_tc) {
1152         other->active_tc.PC = arg1;
1153         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1154         other->lladdr = 0ULL;
1155         /* MIPS16 not implemented. */
1156     } else {
1157         other->tcs[other_tc].PC = arg1;
1158         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1159         other->lladdr = 0ULL;
1160         /* MIPS16 not implemented. */
1161     }
1162 }
1163
1164 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1165 {
1166     MIPSCPU *cpu = mips_env_get_cpu(env);
1167
1168     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1169
1170     // TODO: Halt TC / Restart (if allocated+active) TC.
1171     if (env->active_tc.CP0_TCHalt & 1) {
1172         mips_tc_sleep(cpu, env->current_tc);
1173     } else {
1174         mips_tc_wake(cpu, env->current_tc);
1175     }
1176 }
1177
1178 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1179 {
1180     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1182     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1183
1184     // TODO: Halt TC / Restart (if allocated+active) TC.
1185
1186     if (other_tc == other->current_tc)
1187         other->active_tc.CP0_TCHalt = arg1;
1188     else
1189         other->tcs[other_tc].CP0_TCHalt = arg1;
1190
1191     if (arg1 & 1) {
1192         mips_tc_sleep(other_cpu, other_tc);
1193     } else {
1194         mips_tc_wake(other_cpu, other_tc);
1195     }
1196 }
1197
1198 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1199 {
1200     env->active_tc.CP0_TCContext = arg1;
1201 }
1202
1203 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1204 {
1205     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1206     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1207
1208     if (other_tc == other->current_tc)
1209         other->active_tc.CP0_TCContext = arg1;
1210     else
1211         other->tcs[other_tc].CP0_TCContext = arg1;
1212 }
1213
1214 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1215 {
1216     env->active_tc.CP0_TCSchedule = arg1;
1217 }
1218
1219 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1220 {
1221     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1222     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1223
1224     if (other_tc == other->current_tc)
1225         other->active_tc.CP0_TCSchedule = arg1;
1226     else
1227         other->tcs[other_tc].CP0_TCSchedule = arg1;
1228 }
1229
1230 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1231 {
1232     env->active_tc.CP0_TCScheFBack = arg1;
1233 }
1234
1235 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1236 {
1237     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1238     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1239
1240     if (other_tc == other->current_tc)
1241         other->active_tc.CP0_TCScheFBack = arg1;
1242     else
1243         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1244 }
1245
1246 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1247 {
1248     /* Large physaddr (PABITS) not implemented */
1249     /* 1k pages not implemented */
1250     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1251     env->CP0_EntryLo1 = (arg1 & 0x3FFFFFFF) | (rxi << (CP0EnLo_XI - 30));
1252 }
1253
1254 #if defined(TARGET_MIPS64)
1255 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1256 {
1257     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1258     env->CP0_EntryLo1 = (arg1 & 0x3FFFFFFF) | rxi;
1259 }
1260 #endif
1261
1262 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1263 {
1264     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1265 }
1266
1267 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1268 {
1269     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1270     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1271         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1272          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1273          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1274         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1275     }
1276 }
1277
1278 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1279 {
1280     /* SmartMIPS not implemented */
1281     /* Large physaddr (PABITS) not implemented */
1282     /* 1k pages not implemented */
1283     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1284                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1285 }
1286
1287 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1288 {
1289     if (env->insn_flags & ISA_MIPS32R6) {
1290         if (arg1 < env->tlb->nb_tlb) {
1291             env->CP0_Wired = arg1;
1292         }
1293     } else {
1294         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1295     }
1296 }
1297
1298 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1299 {
1300     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1301 }
1302
1303 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1304 {
1305     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1306 }
1307
1308 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1309 {
1310     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1311 }
1312
1313 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1314 {
1315     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1316 }
1317
1318 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1319 {
1320     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1321 }
1322
1323 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1324 {
1325     uint32_t mask = 0x0000000F;
1326
1327     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1328         mask |= (1 << 29);
1329
1330         if (arg1 & (1 << 29)) {
1331             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1332         } else {
1333             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1334         }
1335     }
1336
1337     env->CP0_HWREna = arg1 & mask;
1338 }
1339
1340 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1341 {
1342     cpu_mips_store_count(env, arg1);
1343 }
1344
1345 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1346 {
1347     target_ulong old, val, mask;
1348     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1349     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1350         mask |= 1 << CP0EnHi_EHINV;
1351     }
1352
1353     /* 1k pages not implemented */
1354 #if defined(TARGET_MIPS64)
1355     if (env->insn_flags & ISA_MIPS32R6) {
1356         int entryhi_r = extract64(arg1, 62, 2);
1357         int config0_at = extract32(env->CP0_Config0, 13, 2);
1358         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1359         if ((entryhi_r == 2) ||
1360             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1361             /* skip EntryHi.R field if new value is reserved */
1362             mask &= ~(0x3ull << 62);
1363         }
1364     }
1365     mask &= env->SEGMask;
1366 #endif
1367     old = env->CP0_EntryHi;
1368     val = (arg1 & mask) | (old & ~mask);
1369     env->CP0_EntryHi = val;
1370     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1371         sync_c0_entryhi(env, env->current_tc);
1372     }
1373     /* If the ASID changes, flush qemu's TLB.  */
1374     if ((old & 0xFF) != (val & 0xFF))
1375         cpu_mips_tlb_flush(env, 1);
1376 }
1377
1378 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1379 {
1380     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1381     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1382
1383     other->CP0_EntryHi = arg1;
1384     sync_c0_entryhi(other, other_tc);
1385 }
1386
1387 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1388 {
1389     cpu_mips_store_compare(env, arg1);
1390 }
1391
1392 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1393 {
1394     MIPSCPU *cpu = mips_env_get_cpu(env);
1395     uint32_t val, old;
1396
1397     old = env->CP0_Status;
1398     cpu_mips_store_status(env, arg1);
1399     val = env->CP0_Status;
1400
1401     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1402         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1403                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1404                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1405                 env->CP0_Cause);
1406         switch (env->hflags & MIPS_HFLAG_KSU) {
1407         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1408         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1409         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1410         default:
1411             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1412             break;
1413         }
1414     }
1415 }
1416
1417 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1418 {
1419     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1420     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1421     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1422
1423     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1424     sync_c0_status(env, other, other_tc);
1425 }
1426
1427 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1428 {
1429     /* vectored interrupts not implemented, no performance counters. */
1430     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1431 }
1432
1433 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1434 {
1435     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1436     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1437 }
1438
1439 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1440 {
1441     cpu_mips_store_cause(env, arg1);
1442 }
1443
1444 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1445 {
1446     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1447     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1448
1449     cpu_mips_store_cause(other, arg1);
1450 }
1451
1452 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1453 {
1454     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1455     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1456
1457     return other->CP0_EPC;
1458 }
1459
1460 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1461 {
1462     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1463     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1464
1465     return other->CP0_EBase;
1466 }
1467
1468 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1469 {
1470     /* vectored interrupts not implemented */
1471     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1472 }
1473
1474 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1475 {
1476     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1477     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1478     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1479 }
1480
1481 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1482 {
1483     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1484     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1485
1486     switch (idx) {
1487     case 0: return other->CP0_Config0;
1488     case 1: return other->CP0_Config1;
1489     case 2: return other->CP0_Config2;
1490     case 3: return other->CP0_Config3;
1491     /* 4 and 5 are reserved.  */
1492     case 6: return other->CP0_Config6;
1493     case 7: return other->CP0_Config7;
1494     default:
1495         break;
1496     }
1497     return 0;
1498 }
1499
1500 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1501 {
1502     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1503 }
1504
1505 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1506 {
1507     /* tertiary/secondary caches not implemented */
1508     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1509 }
1510
1511 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1512 {
1513     if (env->insn_flags & ASE_MICROMIPS) {
1514         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1515                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1516     }
1517 }
1518
1519 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1520 {
1521     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1522                        (arg1 & env->CP0_Config4_rw_bitmask);
1523 }
1524
1525 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1526 {
1527     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1528                        (arg1 & env->CP0_Config5_rw_bitmask);
1529     compute_hflags(env);
1530 }
1531
1532 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1533 {
1534     target_long mask = env->CP0_LLAddr_rw_bitmask;
1535     arg1 = arg1 << env->CP0_LLAddr_shift;
1536     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1537 }
1538
1539 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1540 {
1541     /* Watch exceptions for instructions, data loads, data stores
1542        not implemented. */
1543     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1544 }
1545
1546 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1547 {
1548     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1549     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1550 }
1551
1552 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1553 {
1554     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1555     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1556 }
1557
1558 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1559 {
1560     env->CP0_Framemask = arg1; /* XXX */
1561 }
1562
1563 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1564 {
1565     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1566     if (arg1 & (1 << CP0DB_DM))
1567         env->hflags |= MIPS_HFLAG_DM;
1568     else
1569         env->hflags &= ~MIPS_HFLAG_DM;
1570 }
1571
1572 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1573 {
1574     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1575     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1576     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1577
1578     /* XXX: Might be wrong, check with EJTAG spec. */
1579     if (other_tc == other->current_tc)
1580         other->active_tc.CP0_Debug_tcstatus = val;
1581     else
1582         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1583     other->CP0_Debug = (other->CP0_Debug &
1584                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1585                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1586 }
1587
1588 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1589 {
1590     env->CP0_Performance0 = arg1 & 0x000007ff;
1591 }
1592
1593 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1594 {
1595     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1596 }
1597
1598 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1599 {
1600     env->CP0_DataLo = arg1; /* XXX */
1601 }
1602
1603 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1604 {
1605     env->CP0_TagHi = arg1; /* XXX */
1606 }
1607
1608 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1609 {
1610     env->CP0_DataHi = arg1; /* XXX */
1611 }
1612
1613 /* MIPS MT functions */
1614 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1615 {
1616     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1617     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1618
1619     if (other_tc == other->current_tc)
1620         return other->active_tc.gpr[sel];
1621     else
1622         return other->tcs[other_tc].gpr[sel];
1623 }
1624
1625 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1626 {
1627     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1628     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1629
1630     if (other_tc == other->current_tc)
1631         return other->active_tc.LO[sel];
1632     else
1633         return other->tcs[other_tc].LO[sel];
1634 }
1635
1636 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1637 {
1638     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1639     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1640
1641     if (other_tc == other->current_tc)
1642         return other->active_tc.HI[sel];
1643     else
1644         return other->tcs[other_tc].HI[sel];
1645 }
1646
1647 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1648 {
1649     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1650     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1651
1652     if (other_tc == other->current_tc)
1653         return other->active_tc.ACX[sel];
1654     else
1655         return other->tcs[other_tc].ACX[sel];
1656 }
1657
1658 target_ulong helper_mftdsp(CPUMIPSState *env)
1659 {
1660     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1661     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1662
1663     if (other_tc == other->current_tc)
1664         return other->active_tc.DSPControl;
1665     else
1666         return other->tcs[other_tc].DSPControl;
1667 }
1668
1669 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1670 {
1671     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1672     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1673
1674     if (other_tc == other->current_tc)
1675         other->active_tc.gpr[sel] = arg1;
1676     else
1677         other->tcs[other_tc].gpr[sel] = arg1;
1678 }
1679
1680 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1681 {
1682     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1683     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1684
1685     if (other_tc == other->current_tc)
1686         other->active_tc.LO[sel] = arg1;
1687     else
1688         other->tcs[other_tc].LO[sel] = arg1;
1689 }
1690
1691 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1692 {
1693     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1694     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1695
1696     if (other_tc == other->current_tc)
1697         other->active_tc.HI[sel] = arg1;
1698     else
1699         other->tcs[other_tc].HI[sel] = arg1;
1700 }
1701
1702 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1703 {
1704     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1705     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1706
1707     if (other_tc == other->current_tc)
1708         other->active_tc.ACX[sel] = arg1;
1709     else
1710         other->tcs[other_tc].ACX[sel] = arg1;
1711 }
1712
1713 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1714 {
1715     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1716     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1717
1718     if (other_tc == other->current_tc)
1719         other->active_tc.DSPControl = arg1;
1720     else
1721         other->tcs[other_tc].DSPControl = arg1;
1722 }
1723
1724 /* MIPS MT functions */
1725 target_ulong helper_dmt(void)
1726 {
1727     // TODO
1728      return 0;
1729 }
1730
1731 target_ulong helper_emt(void)
1732 {
1733     // TODO
1734     return 0;
1735 }
1736
1737 target_ulong helper_dvpe(CPUMIPSState *env)
1738 {
1739     CPUState *other_cs = first_cpu;
1740     target_ulong prev = env->mvp->CP0_MVPControl;
1741
1742     CPU_FOREACH(other_cs) {
1743         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1744         /* Turn off all VPEs except the one executing the dvpe.  */
1745         if (&other_cpu->env != env) {
1746             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1747             mips_vpe_sleep(other_cpu);
1748         }
1749     }
1750     return prev;
1751 }
1752
1753 target_ulong helper_evpe(CPUMIPSState *env)
1754 {
1755     CPUState *other_cs = first_cpu;
1756     target_ulong prev = env->mvp->CP0_MVPControl;
1757
1758     CPU_FOREACH(other_cs) {
1759         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1760
1761         if (&other_cpu->env != env
1762             /* If the VPE is WFI, don't disturb its sleep.  */
1763             && !mips_vpe_is_wfi(other_cpu)) {
1764             /* Enable the VPE.  */
1765             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1766             mips_vpe_wake(other_cpu); /* And wake it up.  */
1767         }
1768     }
1769     return prev;
1770 }
1771 #endif /* !CONFIG_USER_ONLY */
1772
1773 void helper_fork(target_ulong arg1, target_ulong arg2)
1774 {
1775     // arg1 = rt, arg2 = rs
1776     // TODO: store to TC register
1777 }
1778
1779 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1780 {
1781     target_long arg1 = arg;
1782
1783     if (arg1 < 0) {
1784         /* No scheduling policy implemented. */
1785         if (arg1 != -2) {
1786             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1787                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1788                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1789                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1790                 helper_raise_exception(env, EXCP_THREAD);
1791             }
1792         }
1793     } else if (arg1 == 0) {
1794         if (0 /* TODO: TC underflow */) {
1795             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1796             helper_raise_exception(env, EXCP_THREAD);
1797         } else {
1798             // TODO: Deallocate TC
1799         }
1800     } else if (arg1 > 0) {
1801         /* Yield qualifier inputs not implemented. */
1802         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1803         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1804         helper_raise_exception(env, EXCP_THREAD);
1805     }
1806     return env->CP0_YQMask;
1807 }
1808
1809 #ifndef CONFIG_USER_ONLY
1810 /* TLB management */
1811 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1812 {
1813     MIPSCPU *cpu = mips_env_get_cpu(env);
1814
1815     /* Flush qemu's TLB and discard all shadowed entries.  */
1816     tlb_flush(CPU(cpu), flush_global);
1817     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1818 }
1819
1820 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1821 {
1822     /* Discard entries from env->tlb[first] onwards.  */
1823     while (env->tlb->tlb_in_use > first) {
1824         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1825     }
1826 }
1827
1828 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1829 {
1830     r4k_tlb_t *tlb;
1831
1832     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1833     tlb = &env->tlb->mmu.r4k.tlb[idx];
1834     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1835         tlb->EHINV = 1;
1836         return;
1837     }
1838     tlb->EHINV = 0;
1839     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1840 #if defined(TARGET_MIPS64)
1841     tlb->VPN &= env->SEGMask;
1842 #endif
1843     tlb->ASID = env->CP0_EntryHi & 0xFF;
1844     tlb->PageMask = env->CP0_PageMask;
1845     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1846     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1847     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1848     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1849     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1850     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1851     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1852     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1853     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1854     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1855     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1856     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1857     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1858 }
1859
1860 void r4k_helper_tlbinv(CPUMIPSState *env)
1861 {
1862     int idx;
1863     r4k_tlb_t *tlb;
1864     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1865
1866     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1867         tlb = &env->tlb->mmu.r4k.tlb[idx];
1868         if (!tlb->G && tlb->ASID == ASID) {
1869             tlb->EHINV = 1;
1870         }
1871     }
1872     cpu_mips_tlb_flush(env, 1);
1873 }
1874
1875 void r4k_helper_tlbinvf(CPUMIPSState *env)
1876 {
1877     int idx;
1878
1879     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1880         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1881     }
1882     cpu_mips_tlb_flush(env, 1);
1883 }
1884
1885 void r4k_helper_tlbwi(CPUMIPSState *env)
1886 {
1887     r4k_tlb_t *tlb;
1888     int idx;
1889     target_ulong VPN;
1890     uint8_t ASID;
1891     bool G, V0, D0, V1, D1;
1892
1893     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1894     tlb = &env->tlb->mmu.r4k.tlb[idx];
1895     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1896 #if defined(TARGET_MIPS64)
1897     VPN &= env->SEGMask;
1898 #endif
1899     ASID = env->CP0_EntryHi & 0xff;
1900     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1901     V0 = (env->CP0_EntryLo0 & 2) != 0;
1902     D0 = (env->CP0_EntryLo0 & 4) != 0;
1903     V1 = (env->CP0_EntryLo1 & 2) != 0;
1904     D1 = (env->CP0_EntryLo1 & 4) != 0;
1905
1906     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1907        permissions on the current entry. */
1908     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1909         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1910         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1911         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1912     }
1913
1914     r4k_invalidate_tlb(env, idx, 0);
1915     r4k_fill_tlb(env, idx);
1916 }
1917
1918 void r4k_helper_tlbwr(CPUMIPSState *env)
1919 {
1920     int r = cpu_mips_get_random(env);
1921
1922     r4k_invalidate_tlb(env, r, 1);
1923     r4k_fill_tlb(env, r);
1924 }
1925
1926 void r4k_helper_tlbp(CPUMIPSState *env)
1927 {
1928     r4k_tlb_t *tlb;
1929     target_ulong mask;
1930     target_ulong tag;
1931     target_ulong VPN;
1932     uint8_t ASID;
1933     int i;
1934
1935     ASID = env->CP0_EntryHi & 0xFF;
1936     for (i = 0; i < env->tlb->nb_tlb; i++) {
1937         tlb = &env->tlb->mmu.r4k.tlb[i];
1938         /* 1k pages are not supported. */
1939         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1940         tag = env->CP0_EntryHi & ~mask;
1941         VPN = tlb->VPN & ~mask;
1942 #if defined(TARGET_MIPS64)
1943         tag &= env->SEGMask;
1944 #endif
1945         /* Check ASID, virtual page number & size */
1946         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
1947             /* TLB match */
1948             env->CP0_Index = i;
1949             break;
1950         }
1951     }
1952     if (i == env->tlb->nb_tlb) {
1953         /* No match.  Discard any shadow entries, if any of them match.  */
1954         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1955             tlb = &env->tlb->mmu.r4k.tlb[i];
1956             /* 1k pages are not supported. */
1957             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1958             tag = env->CP0_EntryHi & ~mask;
1959             VPN = tlb->VPN & ~mask;
1960 #if defined(TARGET_MIPS64)
1961             tag &= env->SEGMask;
1962 #endif
1963             /* Check ASID, virtual page number & size */
1964             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1965                 r4k_mips_tlb_flush_extra (env, i);
1966                 break;
1967             }
1968         }
1969
1970         env->CP0_Index |= 0x80000000;
1971     }
1972 }
1973
1974 void r4k_helper_tlbr(CPUMIPSState *env)
1975 {
1976     r4k_tlb_t *tlb;
1977     uint8_t ASID;
1978     int idx;
1979
1980     ASID = env->CP0_EntryHi & 0xFF;
1981     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1982     tlb = &env->tlb->mmu.r4k.tlb[idx];
1983
1984     /* If this will change the current ASID, flush qemu's TLB.  */
1985     if (ASID != tlb->ASID)
1986         cpu_mips_tlb_flush (env, 1);
1987
1988     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1989
1990     if (tlb->EHINV) {
1991         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
1992         env->CP0_PageMask = 0;
1993         env->CP0_EntryLo0 = 0;
1994         env->CP0_EntryLo1 = 0;
1995     } else {
1996         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1997         env->CP0_PageMask = tlb->PageMask;
1998         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1999                         ((target_ulong)tlb->RI0 << CP0EnLo_RI) |
2000                         ((target_ulong)tlb->XI0 << CP0EnLo_XI) |
2001                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
2002         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2003                         ((target_ulong)tlb->RI1 << CP0EnLo_RI) |
2004                         ((target_ulong)tlb->XI1 << CP0EnLo_XI) |
2005                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
2006     }
2007 }
2008
2009 void helper_tlbwi(CPUMIPSState *env)
2010 {
2011     env->tlb->helper_tlbwi(env);
2012 }
2013
2014 void helper_tlbwr(CPUMIPSState *env)
2015 {
2016     env->tlb->helper_tlbwr(env);
2017 }
2018
2019 void helper_tlbp(CPUMIPSState *env)
2020 {
2021     env->tlb->helper_tlbp(env);
2022 }
2023
2024 void helper_tlbr(CPUMIPSState *env)
2025 {
2026     env->tlb->helper_tlbr(env);
2027 }
2028
2029 void helper_tlbinv(CPUMIPSState *env)
2030 {
2031     env->tlb->helper_tlbinv(env);
2032 }
2033
2034 void helper_tlbinvf(CPUMIPSState *env)
2035 {
2036     env->tlb->helper_tlbinvf(env);
2037 }
2038
2039 /* Specials */
2040 target_ulong helper_di(CPUMIPSState *env)
2041 {
2042     target_ulong t0 = env->CP0_Status;
2043
2044     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2045     return t0;
2046 }
2047
2048 target_ulong helper_ei(CPUMIPSState *env)
2049 {
2050     target_ulong t0 = env->CP0_Status;
2051
2052     env->CP0_Status = t0 | (1 << CP0St_IE);
2053     return t0;
2054 }
2055
2056 static void debug_pre_eret(CPUMIPSState *env)
2057 {
2058     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2059         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2060                 env->active_tc.PC, env->CP0_EPC);
2061         if (env->CP0_Status & (1 << CP0St_ERL))
2062             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2063         if (env->hflags & MIPS_HFLAG_DM)
2064             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2065         qemu_log("\n");
2066     }
2067 }
2068
2069 static void debug_post_eret(CPUMIPSState *env)
2070 {
2071     MIPSCPU *cpu = mips_env_get_cpu(env);
2072
2073     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2074         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2075                 env->active_tc.PC, env->CP0_EPC);
2076         if (env->CP0_Status & (1 << CP0St_ERL))
2077             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2078         if (env->hflags & MIPS_HFLAG_DM)
2079             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2080         switch (env->hflags & MIPS_HFLAG_KSU) {
2081         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2082         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2083         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2084         default:
2085             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2086             break;
2087         }
2088     }
2089 }
2090
2091 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2092 {
2093     env->active_tc.PC = error_pc & ~(target_ulong)1;
2094     if (error_pc & 1) {
2095         env->hflags |= MIPS_HFLAG_M16;
2096     } else {
2097         env->hflags &= ~(MIPS_HFLAG_M16);
2098     }
2099 }
2100
2101 void helper_eret(CPUMIPSState *env)
2102 {
2103     debug_pre_eret(env);
2104     if (env->CP0_Status & (1 << CP0St_ERL)) {
2105         set_pc(env, env->CP0_ErrorEPC);
2106         env->CP0_Status &= ~(1 << CP0St_ERL);
2107     } else {
2108         set_pc(env, env->CP0_EPC);
2109         env->CP0_Status &= ~(1 << CP0St_EXL);
2110     }
2111     compute_hflags(env);
2112     debug_post_eret(env);
2113     env->lladdr = 1;
2114 }
2115
2116 void helper_deret(CPUMIPSState *env)
2117 {
2118     debug_pre_eret(env);
2119     set_pc(env, env->CP0_DEPC);
2120
2121     env->hflags &= MIPS_HFLAG_DM;
2122     compute_hflags(env);
2123     debug_post_eret(env);
2124     env->lladdr = 1;
2125 }
2126 #endif /* !CONFIG_USER_ONLY */
2127
2128 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2129 {
2130     if ((env->hflags & MIPS_HFLAG_CP0) ||
2131         (env->CP0_HWREna & (1 << 0)))
2132         return env->CP0_EBase & 0x3ff;
2133     else
2134         helper_raise_exception(env, EXCP_RI);
2135
2136     return 0;
2137 }
2138
2139 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2140 {
2141     if ((env->hflags & MIPS_HFLAG_CP0) ||
2142         (env->CP0_HWREna & (1 << 1)))
2143         return env->SYNCI_Step;
2144     else
2145         helper_raise_exception(env, EXCP_RI);
2146
2147     return 0;
2148 }
2149
2150 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2151 {
2152     if ((env->hflags & MIPS_HFLAG_CP0) ||
2153         (env->CP0_HWREna & (1 << 2)))
2154         return env->CP0_Count;
2155     else
2156         helper_raise_exception(env, EXCP_RI);
2157
2158     return 0;
2159 }
2160
2161 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2162 {
2163     if ((env->hflags & MIPS_HFLAG_CP0) ||
2164         (env->CP0_HWREna & (1 << 3)))
2165         return env->CCRes;
2166     else
2167         helper_raise_exception(env, EXCP_RI);
2168
2169     return 0;
2170 }
2171
2172 void helper_pmon(CPUMIPSState *env, int function)
2173 {
2174     function /= 2;
2175     switch (function) {
2176     case 2: /* TODO: char inbyte(int waitflag); */
2177         if (env->active_tc.gpr[4] == 0)
2178             env->active_tc.gpr[2] = -1;
2179         /* Fall through */
2180     case 11: /* TODO: char inbyte (void); */
2181         env->active_tc.gpr[2] = -1;
2182         break;
2183     case 3:
2184     case 12:
2185         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2186         break;
2187     case 17:
2188         break;
2189     case 158:
2190         {
2191             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2192             printf("%s", fmt);
2193         }
2194         break;
2195     }
2196 }
2197
2198 void helper_wait(CPUMIPSState *env)
2199 {
2200     CPUState *cs = CPU(mips_env_get_cpu(env));
2201
2202     cs->halted = 1;
2203     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2204     helper_raise_exception(env, EXCP_HLT);
2205 }
2206
2207 #if !defined(CONFIG_USER_ONLY)
2208
2209 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2210                                   int access_type, int is_user,
2211                                   uintptr_t retaddr)
2212 {
2213     MIPSCPU *cpu = MIPS_CPU(cs);
2214     CPUMIPSState *env = &cpu->env;
2215     int error_code = 0;
2216     int excp;
2217
2218     env->CP0_BadVAddr = addr;
2219
2220     if (access_type == MMU_DATA_STORE) {
2221         excp = EXCP_AdES;
2222     } else {
2223         excp = EXCP_AdEL;
2224         if (access_type == MMU_INST_FETCH) {
2225             error_code |= EXCP_INST_NOTAVAIL;
2226         }
2227     }
2228
2229     do_raise_exception_err(env, excp, error_code, retaddr);
2230 }
2231
2232 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2233               uintptr_t retaddr)
2234 {
2235     int ret;
2236
2237     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2238     if (ret) {
2239         MIPSCPU *cpu = MIPS_CPU(cs);
2240         CPUMIPSState *env = &cpu->env;
2241
2242         do_raise_exception_err(env, cs->exception_index,
2243                                env->error_code, retaddr);
2244     }
2245 }
2246
2247 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2248                                 bool is_write, bool is_exec, int unused,
2249                                 unsigned size)
2250 {
2251     MIPSCPU *cpu = MIPS_CPU(cs);
2252     CPUMIPSState *env = &cpu->env;
2253
2254     /*
2255      * Raising an exception with KVM enabled will crash because it won't be from
2256      * the main execution loop so the longjmp won't have a matching setjmp.
2257      * Until we can trigger a bus error exception through KVM lets just ignore
2258      * the access.
2259      */
2260     if (kvm_enabled()) {
2261         return;
2262     }
2263
2264     if (is_exec) {
2265         helper_raise_exception(env, EXCP_IBE);
2266     } else {
2267         helper_raise_exception(env, EXCP_DBE);
2268     }
2269 }
2270 #endif /* !CONFIG_USER_ONLY */
2271
2272 /* Complex FPU operations which may need stack space. */
2273
2274 #define FLOAT_TWO32 make_float32(1 << 30)
2275 #define FLOAT_TWO64 make_float64(1ULL << 62)
2276 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2277 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2278
2279 /* convert MIPS rounding mode in FCR31 to IEEE library */
2280 unsigned int ieee_rm[] = {
2281     float_round_nearest_even,
2282     float_round_to_zero,
2283     float_round_up,
2284     float_round_down
2285 };
2286
2287 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2288 {
2289     target_ulong arg1 = 0;
2290
2291     switch (reg) {
2292     case 0:
2293         arg1 = (int32_t)env->active_fpu.fcr0;
2294         break;
2295     case 1:
2296         /* UFR Support - Read Status FR */
2297         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2298             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2299                 arg1 = (int32_t)
2300                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2301             } else {
2302                 helper_raise_exception(env, EXCP_RI);
2303             }
2304         }
2305         break;
2306     case 25:
2307         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2308         break;
2309     case 26:
2310         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2311         break;
2312     case 28:
2313         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2314         break;
2315     default:
2316         arg1 = (int32_t)env->active_fpu.fcr31;
2317         break;
2318     }
2319
2320     return arg1;
2321 }
2322
2323 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2324 {
2325     switch (fs) {
2326     case 1:
2327         /* UFR Alias - Reset Status FR */
2328         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2329             return;
2330         }
2331         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2332             env->CP0_Status &= ~(1 << CP0St_FR);
2333             compute_hflags(env);
2334         } else {
2335             helper_raise_exception(env, EXCP_RI);
2336         }
2337         break;
2338     case 4:
2339         /* UNFR Alias - Set Status FR */
2340         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2341             return;
2342         }
2343         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2344             env->CP0_Status |= (1 << CP0St_FR);
2345             compute_hflags(env);
2346         } else {
2347             helper_raise_exception(env, EXCP_RI);
2348         }
2349         break;
2350     case 25:
2351         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2352             return;
2353         }
2354         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2355                      ((arg1 & 0x1) << 23);
2356         break;
2357     case 26:
2358         if (arg1 & 0x007c0000)
2359             return;
2360         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2361         break;
2362     case 28:
2363         if (arg1 & 0x007c0000)
2364             return;
2365         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2366                      ((arg1 & 0x4) << 22);
2367         break;
2368     case 31:
2369         if (env->insn_flags & ISA_MIPS32R6) {
2370             uint32_t mask = 0xfefc0000;
2371             env->active_fpu.fcr31 = (arg1 & ~mask) |
2372                 (env->active_fpu.fcr31 & mask);
2373         } else if (!(arg1 & 0x007c0000)) {
2374             env->active_fpu.fcr31 = arg1;
2375         }
2376         break;
2377     default:
2378         return;
2379     }
2380     /* set rounding mode */
2381     restore_rounding_mode(env);
2382     /* set flush-to-zero mode */
2383     restore_flush_mode(env);
2384     set_float_exception_flags(0, &env->active_fpu.fp_status);
2385     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2386         do_raise_exception(env, EXCP_FPE, GETPC());
2387 }
2388
2389 int ieee_ex_to_mips(int xcpt)
2390 {
2391     int ret = 0;
2392     if (xcpt) {
2393         if (xcpt & float_flag_invalid) {
2394             ret |= FP_INVALID;
2395         }
2396         if (xcpt & float_flag_overflow) {
2397             ret |= FP_OVERFLOW;
2398         }
2399         if (xcpt & float_flag_underflow) {
2400             ret |= FP_UNDERFLOW;
2401         }
2402         if (xcpt & float_flag_divbyzero) {
2403             ret |= FP_DIV0;
2404         }
2405         if (xcpt & float_flag_inexact) {
2406             ret |= FP_INEXACT;
2407         }
2408     }
2409     return ret;
2410 }
2411
2412 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2413 {
2414     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2415
2416     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2417
2418     if (tmp) {
2419         set_float_exception_flags(0, &env->active_fpu.fp_status);
2420
2421         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2422             do_raise_exception(env, EXCP_FPE, pc);
2423         } else {
2424             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2425         }
2426     }
2427 }
2428
2429 /* Float support.
2430    Single precition routines have a "s" suffix, double precision a
2431    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2432    paired single lower "pl", paired single upper "pu".  */
2433
2434 /* unary operations, modifying fp status  */
2435 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2436 {
2437     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2438     update_fcr31(env, GETPC());
2439     return fdt0;
2440 }
2441
2442 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2443 {
2444     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2445     update_fcr31(env, GETPC());
2446     return fst0;
2447 }
2448
2449 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2450 {
2451     uint64_t fdt2;
2452
2453     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2454     update_fcr31(env, GETPC());
2455     return fdt2;
2456 }
2457
2458 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2459 {
2460     uint64_t fdt2;
2461
2462     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2463     update_fcr31(env, GETPC());
2464     return fdt2;
2465 }
2466
2467 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2468 {
2469     uint64_t fdt2;
2470
2471     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2472     update_fcr31(env, GETPC());
2473     return fdt2;
2474 }
2475
2476 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2477 {
2478     uint64_t dt2;
2479
2480     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2481     if (get_float_exception_flags(&env->active_fpu.fp_status)
2482         & (float_flag_invalid | float_flag_overflow)) {
2483         dt2 = FP_TO_INT64_OVERFLOW;
2484     }
2485     update_fcr31(env, GETPC());
2486     return dt2;
2487 }
2488
2489 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2490 {
2491     uint64_t dt2;
2492
2493     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2494     if (get_float_exception_flags(&env->active_fpu.fp_status)
2495         & (float_flag_invalid | float_flag_overflow)) {
2496         dt2 = FP_TO_INT64_OVERFLOW;
2497     }
2498     update_fcr31(env, GETPC());
2499     return dt2;
2500 }
2501
2502 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2503 {
2504     uint32_t fst2;
2505     uint32_t fsth2;
2506
2507     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2508     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2509     update_fcr31(env, GETPC());
2510     return ((uint64_t)fsth2 << 32) | fst2;
2511 }
2512
2513 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2514 {
2515     uint32_t wt2;
2516     uint32_t wth2;
2517     int excp, excph;
2518
2519     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2520     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2521     if (excp & (float_flag_overflow | float_flag_invalid)) {
2522         wt2 = FP_TO_INT32_OVERFLOW;
2523     }
2524
2525     set_float_exception_flags(0, &env->active_fpu.fp_status);
2526     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2527     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2528     if (excph & (float_flag_overflow | float_flag_invalid)) {
2529         wth2 = FP_TO_INT32_OVERFLOW;
2530     }
2531
2532     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2533     update_fcr31(env, GETPC());
2534
2535     return ((uint64_t)wth2 << 32) | wt2;
2536 }
2537
2538 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2539 {
2540     uint32_t fst2;
2541
2542     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2543     update_fcr31(env, GETPC());
2544     return fst2;
2545 }
2546
2547 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2548 {
2549     uint32_t fst2;
2550
2551     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2552     update_fcr31(env, GETPC());
2553     return fst2;
2554 }
2555
2556 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2557 {
2558     uint32_t fst2;
2559
2560     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2561     update_fcr31(env, GETPC());
2562     return fst2;
2563 }
2564
2565 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2566 {
2567     uint32_t wt2;
2568
2569     wt2 = wt0;
2570     update_fcr31(env, GETPC());
2571     return wt2;
2572 }
2573
2574 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2575 {
2576     uint32_t wt2;
2577
2578     wt2 = wth0;
2579     update_fcr31(env, GETPC());
2580     return wt2;
2581 }
2582
2583 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2584 {
2585     uint32_t wt2;
2586
2587     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2588     if (get_float_exception_flags(&env->active_fpu.fp_status)
2589         & (float_flag_invalid | float_flag_overflow)) {
2590         wt2 = FP_TO_INT32_OVERFLOW;
2591     }
2592     update_fcr31(env, GETPC());
2593     return wt2;
2594 }
2595
2596 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2597 {
2598     uint32_t wt2;
2599
2600     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2601     if (get_float_exception_flags(&env->active_fpu.fp_status)
2602         & (float_flag_invalid | float_flag_overflow)) {
2603         wt2 = FP_TO_INT32_OVERFLOW;
2604     }
2605     update_fcr31(env, GETPC());
2606     return wt2;
2607 }
2608
2609 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2610 {
2611     uint64_t dt2;
2612
2613     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2614     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2615     restore_rounding_mode(env);
2616     if (get_float_exception_flags(&env->active_fpu.fp_status)
2617         & (float_flag_invalid | float_flag_overflow)) {
2618         dt2 = FP_TO_INT64_OVERFLOW;
2619     }
2620     update_fcr31(env, GETPC());
2621     return dt2;
2622 }
2623
2624 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2625 {
2626     uint64_t dt2;
2627
2628     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2629     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2630     restore_rounding_mode(env);
2631     if (get_float_exception_flags(&env->active_fpu.fp_status)
2632         & (float_flag_invalid | float_flag_overflow)) {
2633         dt2 = FP_TO_INT64_OVERFLOW;
2634     }
2635     update_fcr31(env, GETPC());
2636     return dt2;
2637 }
2638
2639 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2640 {
2641     uint32_t wt2;
2642
2643     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2644     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2645     restore_rounding_mode(env);
2646     if (get_float_exception_flags(&env->active_fpu.fp_status)
2647         & (float_flag_invalid | float_flag_overflow)) {
2648         wt2 = FP_TO_INT32_OVERFLOW;
2649     }
2650     update_fcr31(env, GETPC());
2651     return wt2;
2652 }
2653
2654 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2655 {
2656     uint32_t wt2;
2657
2658     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2659     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2660     restore_rounding_mode(env);
2661     if (get_float_exception_flags(&env->active_fpu.fp_status)
2662         & (float_flag_invalid | float_flag_overflow)) {
2663         wt2 = FP_TO_INT32_OVERFLOW;
2664     }
2665     update_fcr31(env, GETPC());
2666     return wt2;
2667 }
2668
2669 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2670 {
2671     uint64_t dt2;
2672
2673     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2674     if (get_float_exception_flags(&env->active_fpu.fp_status)
2675         & (float_flag_invalid | float_flag_overflow)) {
2676         dt2 = FP_TO_INT64_OVERFLOW;
2677     }
2678     update_fcr31(env, GETPC());
2679     return dt2;
2680 }
2681
2682 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2683 {
2684     uint64_t dt2;
2685
2686     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2687     if (get_float_exception_flags(&env->active_fpu.fp_status)
2688         & (float_flag_invalid | float_flag_overflow)) {
2689         dt2 = FP_TO_INT64_OVERFLOW;
2690     }
2691     update_fcr31(env, GETPC());
2692     return dt2;
2693 }
2694
2695 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2696 {
2697     uint32_t wt2;
2698
2699     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2700     if (get_float_exception_flags(&env->active_fpu.fp_status)
2701         & (float_flag_invalid | float_flag_overflow)) {
2702         wt2 = FP_TO_INT32_OVERFLOW;
2703     }
2704     update_fcr31(env, GETPC());
2705     return wt2;
2706 }
2707
2708 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2709 {
2710     uint32_t wt2;
2711
2712     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2713     if (get_float_exception_flags(&env->active_fpu.fp_status)
2714         & (float_flag_invalid | float_flag_overflow)) {
2715         wt2 = FP_TO_INT32_OVERFLOW;
2716     }
2717     update_fcr31(env, GETPC());
2718     return wt2;
2719 }
2720
2721 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2722 {
2723     uint64_t dt2;
2724
2725     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2726     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2727     restore_rounding_mode(env);
2728     if (get_float_exception_flags(&env->active_fpu.fp_status)
2729         & (float_flag_invalid | float_flag_overflow)) {
2730         dt2 = FP_TO_INT64_OVERFLOW;
2731     }
2732     update_fcr31(env, GETPC());
2733     return dt2;
2734 }
2735
2736 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2737 {
2738     uint64_t dt2;
2739
2740     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2741     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2742     restore_rounding_mode(env);
2743     if (get_float_exception_flags(&env->active_fpu.fp_status)
2744         & (float_flag_invalid | float_flag_overflow)) {
2745         dt2 = FP_TO_INT64_OVERFLOW;
2746     }
2747     update_fcr31(env, GETPC());
2748     return dt2;
2749 }
2750
2751 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2752 {
2753     uint32_t wt2;
2754
2755     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2756     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2757     restore_rounding_mode(env);
2758     if (get_float_exception_flags(&env->active_fpu.fp_status)
2759         & (float_flag_invalid | float_flag_overflow)) {
2760         wt2 = FP_TO_INT32_OVERFLOW;
2761     }
2762     update_fcr31(env, GETPC());
2763     return wt2;
2764 }
2765
2766 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2767 {
2768     uint32_t wt2;
2769
2770     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2771     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2772     restore_rounding_mode(env);
2773     if (get_float_exception_flags(&env->active_fpu.fp_status)
2774         & (float_flag_invalid | float_flag_overflow)) {
2775         wt2 = FP_TO_INT32_OVERFLOW;
2776     }
2777     update_fcr31(env, GETPC());
2778     return wt2;
2779 }
2780
2781 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2782 {
2783     uint64_t dt2;
2784
2785     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2786     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2787     restore_rounding_mode(env);
2788     if (get_float_exception_flags(&env->active_fpu.fp_status)
2789         & (float_flag_invalid | float_flag_overflow)) {
2790         dt2 = FP_TO_INT64_OVERFLOW;
2791     }
2792     update_fcr31(env, GETPC());
2793     return dt2;
2794 }
2795
2796 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2797 {
2798     uint64_t dt2;
2799
2800     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2801     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2802     restore_rounding_mode(env);
2803     if (get_float_exception_flags(&env->active_fpu.fp_status)
2804         & (float_flag_invalid | float_flag_overflow)) {
2805         dt2 = FP_TO_INT64_OVERFLOW;
2806     }
2807     update_fcr31(env, GETPC());
2808     return dt2;
2809 }
2810
2811 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2812 {
2813     uint32_t wt2;
2814
2815     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2816     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2817     restore_rounding_mode(env);
2818     if (get_float_exception_flags(&env->active_fpu.fp_status)
2819         & (float_flag_invalid | float_flag_overflow)) {
2820         wt2 = FP_TO_INT32_OVERFLOW;
2821     }
2822     update_fcr31(env, GETPC());
2823     return wt2;
2824 }
2825
2826 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2827 {
2828     uint32_t wt2;
2829
2830     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2831     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2832     restore_rounding_mode(env);
2833     if (get_float_exception_flags(&env->active_fpu.fp_status)
2834         & (float_flag_invalid | float_flag_overflow)) {
2835         wt2 = FP_TO_INT32_OVERFLOW;
2836     }
2837     update_fcr31(env, GETPC());
2838     return wt2;
2839 }
2840
2841 /* unary operations, not modifying fp status  */
2842 #define FLOAT_UNOP(name)                                       \
2843 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2844 {                                                              \
2845     return float64_ ## name(fdt0);                             \
2846 }                                                              \
2847 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2848 {                                                              \
2849     return float32_ ## name(fst0);                             \
2850 }                                                              \
2851 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2852 {                                                              \
2853     uint32_t wt0;                                              \
2854     uint32_t wth0;                                             \
2855                                                                \
2856     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2857     wth0 = float32_ ## name(fdt0 >> 32);                       \
2858     return ((uint64_t)wth0 << 32) | wt0;                       \
2859 }
2860 FLOAT_UNOP(abs)
2861 FLOAT_UNOP(chs)
2862 #undef FLOAT_UNOP
2863
2864 /* MIPS specific unary operations */
2865 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2866 {
2867     uint64_t fdt2;
2868
2869     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2870     update_fcr31(env, GETPC());
2871     return fdt2;
2872 }
2873
2874 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2875 {
2876     uint32_t fst2;
2877
2878     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2879     update_fcr31(env, GETPC());
2880     return fst2;
2881 }
2882
2883 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2884 {
2885     uint64_t fdt2;
2886
2887     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2888     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2889     update_fcr31(env, GETPC());
2890     return fdt2;
2891 }
2892
2893 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2894 {
2895     uint32_t fst2;
2896
2897     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2898     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2899     update_fcr31(env, GETPC());
2900     return fst2;
2901 }
2902
2903 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2904 {
2905     uint64_t fdt2;
2906
2907     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2908     update_fcr31(env, GETPC());
2909     return fdt2;
2910 }
2911
2912 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2913 {
2914     uint32_t fst2;
2915
2916     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2917     update_fcr31(env, GETPC());
2918     return fst2;
2919 }
2920
2921 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2922 {
2923     uint32_t fst2;
2924     uint32_t fsth2;
2925
2926     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2927     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2928     update_fcr31(env, GETPC());
2929     return ((uint64_t)fsth2 << 32) | fst2;
2930 }
2931
2932 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2933 {
2934     uint64_t fdt2;
2935
2936     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2937     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2938     update_fcr31(env, GETPC());
2939     return fdt2;
2940 }
2941
2942 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2943 {
2944     uint32_t fst2;
2945
2946     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2947     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2948     update_fcr31(env, GETPC());
2949     return fst2;
2950 }
2951
2952 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2953 {
2954     uint32_t fst2;
2955     uint32_t fsth2;
2956
2957     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2958     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2959     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2960     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2961     update_fcr31(env, GETPC());
2962     return ((uint64_t)fsth2 << 32) | fst2;
2963 }
2964
2965 #define FLOAT_RINT(name, bits)                                              \
2966 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
2967                                           uint ## bits ## _t fs)            \
2968 {                                                                           \
2969     uint ## bits ## _t fdret;                                               \
2970                                                                             \
2971     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
2972     update_fcr31(env, GETPC());                                             \
2973     return fdret;                                                           \
2974 }
2975
2976 FLOAT_RINT(rint_s, 32)
2977 FLOAT_RINT(rint_d, 64)
2978 #undef FLOAT_RINT
2979
2980 #define FLOAT_CLASS_SIGNALING_NAN      0x001
2981 #define FLOAT_CLASS_QUIET_NAN          0x002
2982 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
2983 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
2984 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
2985 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
2986 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
2987 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
2988 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
2989 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
2990
2991 #define FLOAT_CLASS(name, bits)                                      \
2992 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
2993 {                                                                    \
2994     if (float ## bits ## _is_signaling_nan(arg)) {                   \
2995         return FLOAT_CLASS_SIGNALING_NAN;                            \
2996     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
2997         return FLOAT_CLASS_QUIET_NAN;                                \
2998     } else if (float ## bits ## _is_neg(arg)) {                      \
2999         if (float ## bits ## _is_infinity(arg)) {                    \
3000             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3001         } else if (float ## bits ## _is_zero(arg)) {                 \
3002             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3003         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3004             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3005         } else {                                                     \
3006             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3007         }                                                            \
3008     } else {                                                         \
3009         if (float ## bits ## _is_infinity(arg)) {                    \
3010             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3011         } else if (float ## bits ## _is_zero(arg)) {                 \
3012             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3013         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3014             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3015         } else {                                                     \
3016             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3017         }                                                            \
3018     }                                                                \
3019 }
3020
3021 FLOAT_CLASS(class_s, 32)
3022 FLOAT_CLASS(class_d, 64)
3023 #undef FLOAT_CLASS
3024
3025 /* binary operations */
3026 #define FLOAT_BINOP(name)                                          \
3027 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3028                                      uint64_t fdt0, uint64_t fdt1) \
3029 {                                                                  \
3030     uint64_t dt2;                                                  \
3031                                                                    \
3032     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3033     update_fcr31(env, GETPC());                                    \
3034     return dt2;                                                    \
3035 }                                                                  \
3036                                                                    \
3037 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3038                                      uint32_t fst0, uint32_t fst1) \
3039 {                                                                  \
3040     uint32_t wt2;                                                  \
3041                                                                    \
3042     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3043     update_fcr31(env, GETPC());                                    \
3044     return wt2;                                                    \
3045 }                                                                  \
3046                                                                    \
3047 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3048                                       uint64_t fdt0,               \
3049                                       uint64_t fdt1)               \
3050 {                                                                  \
3051     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3052     uint32_t fsth0 = fdt0 >> 32;                                   \
3053     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3054     uint32_t fsth1 = fdt1 >> 32;                                   \
3055     uint32_t wt2;                                                  \
3056     uint32_t wth2;                                                 \
3057                                                                    \
3058     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3059     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3060     update_fcr31(env, GETPC());                                    \
3061     return ((uint64_t)wth2 << 32) | wt2;                           \
3062 }
3063
3064 FLOAT_BINOP(add)
3065 FLOAT_BINOP(sub)
3066 FLOAT_BINOP(mul)
3067 FLOAT_BINOP(div)
3068 #undef FLOAT_BINOP
3069
3070 /* MIPS specific binary operations */
3071 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3072 {
3073     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3074     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3075     update_fcr31(env, GETPC());
3076     return fdt2;
3077 }
3078
3079 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3080 {
3081     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3082     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3083     update_fcr31(env, GETPC());
3084     return fst2;
3085 }
3086
3087 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3088 {
3089     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3090     uint32_t fsth0 = fdt0 >> 32;
3091     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3092     uint32_t fsth2 = fdt2 >> 32;
3093
3094     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3095     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3096     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3097     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3098     update_fcr31(env, GETPC());
3099     return ((uint64_t)fsth2 << 32) | fst2;
3100 }
3101
3102 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3103 {
3104     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3105     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3106     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3107     update_fcr31(env, GETPC());
3108     return fdt2;
3109 }
3110
3111 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3112 {
3113     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3114     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3115     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3116     update_fcr31(env, GETPC());
3117     return fst2;
3118 }
3119
3120 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3121 {
3122     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3123     uint32_t fsth0 = fdt0 >> 32;
3124     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3125     uint32_t fsth2 = fdt2 >> 32;
3126
3127     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3128     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3129     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3130     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3131     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3132     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3133     update_fcr31(env, GETPC());
3134     return ((uint64_t)fsth2 << 32) | fst2;
3135 }
3136
3137 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3138 {
3139     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3140     uint32_t fsth0 = fdt0 >> 32;
3141     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3142     uint32_t fsth1 = fdt1 >> 32;
3143     uint32_t fst2;
3144     uint32_t fsth2;
3145
3146     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3147     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3148     update_fcr31(env, GETPC());
3149     return ((uint64_t)fsth2 << 32) | fst2;
3150 }
3151
3152 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3153 {
3154     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3155     uint32_t fsth0 = fdt0 >> 32;
3156     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3157     uint32_t fsth1 = fdt1 >> 32;
3158     uint32_t fst2;
3159     uint32_t fsth2;
3160
3161     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3162     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3163     update_fcr31(env, GETPC());
3164     return ((uint64_t)fsth2 << 32) | fst2;
3165 }
3166
3167 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
3168 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3169                                           uint ## bits ## _t fs,        \
3170                                           uint ## bits ## _t ft)        \
3171 {                                                                       \
3172     uint ## bits ## _t fdret;                                           \
3173                                                                         \
3174     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
3175                                            &env->active_fpu.fp_status); \
3176     update_fcr31(env, GETPC());                                         \
3177     return fdret;                                                       \
3178 }
3179
3180 FLOAT_MINMAX(max_s, 32, maxnum)
3181 FLOAT_MINMAX(max_d, 64, maxnum)
3182 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3183 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3184
3185 FLOAT_MINMAX(min_s, 32, minnum)
3186 FLOAT_MINMAX(min_d, 64, minnum)
3187 FLOAT_MINMAX(mina_s, 32, minnummag)
3188 FLOAT_MINMAX(mina_d, 64, minnummag)
3189 #undef FLOAT_MINMAX
3190
3191 /* ternary operations */
3192 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3193 {                                                                    \
3194     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3195     if ((flags) & float_muladd_negate_c) {                           \
3196         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3197     } else {                                                         \
3198         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3199     }                                                                \
3200     if ((flags) & float_muladd_negate_result) {                      \
3201         a = prefix##_chs(a);                                         \
3202     }                                                                \
3203 }
3204
3205 /* FMA based operations */
3206 #define FLOAT_FMA(name, type)                                        \
3207 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3208                                      uint64_t fdt0, uint64_t fdt1,   \
3209                                      uint64_t fdt2)                  \
3210 {                                                                    \
3211     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3212     update_fcr31(env, GETPC());                                      \
3213     return fdt0;                                                     \
3214 }                                                                    \
3215                                                                      \
3216 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3217                                      uint32_t fst0, uint32_t fst1,   \
3218                                      uint32_t fst2)                  \
3219 {                                                                    \
3220     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3221     update_fcr31(env, GETPC());                                      \
3222     return fst0;                                                     \
3223 }                                                                    \
3224                                                                      \
3225 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3226                                       uint64_t fdt0, uint64_t fdt1,  \
3227                                       uint64_t fdt2)                 \
3228 {                                                                    \
3229     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3230     uint32_t fsth0 = fdt0 >> 32;                                     \
3231     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3232     uint32_t fsth1 = fdt1 >> 32;                                     \
3233     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3234     uint32_t fsth2 = fdt2 >> 32;                                     \
3235                                                                      \
3236     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3237     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3238     update_fcr31(env, GETPC());                                      \
3239     return ((uint64_t)fsth0 << 32) | fst0;                           \
3240 }
3241 FLOAT_FMA(madd, 0)
3242 FLOAT_FMA(msub, float_muladd_negate_c)
3243 FLOAT_FMA(nmadd, float_muladd_negate_result)
3244 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3245 #undef FLOAT_FMA
3246
3247 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
3248 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3249                                           uint ## bits ## _t fs,        \
3250                                           uint ## bits ## _t ft,        \
3251                                           uint ## bits ## _t fd)        \
3252 {                                                                       \
3253     uint ## bits ## _t fdret;                                           \
3254                                                                         \
3255     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
3256                                      &env->active_fpu.fp_status);       \
3257     update_fcr31(env, GETPC());                                         \
3258     return fdret;                                                       \
3259 }
3260
3261 FLOAT_FMADDSUB(maddf_s, 32, 0)
3262 FLOAT_FMADDSUB(maddf_d, 64, 0)
3263 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3264 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3265 #undef FLOAT_FMADDSUB
3266
3267 /* compare operations */
3268 #define FOP_COND_D(op, cond)                                   \
3269 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3270                          uint64_t fdt1, int cc)                \
3271 {                                                              \
3272     int c;                                                     \
3273     c = cond;                                                  \
3274     update_fcr31(env, GETPC());                                \
3275     if (c)                                                     \
3276         SET_FP_COND(cc, env->active_fpu);                      \
3277     else                                                       \
3278         CLEAR_FP_COND(cc, env->active_fpu);                    \
3279 }                                                              \
3280 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3281                             uint64_t fdt1, int cc)             \
3282 {                                                              \
3283     int c;                                                     \
3284     fdt0 = float64_abs(fdt0);                                  \
3285     fdt1 = float64_abs(fdt1);                                  \
3286     c = cond;                                                  \
3287     update_fcr31(env, GETPC());                                \
3288     if (c)                                                     \
3289         SET_FP_COND(cc, env->active_fpu);                      \
3290     else                                                       \
3291         CLEAR_FP_COND(cc, env->active_fpu);                    \
3292 }
3293
3294 /* NOTE: the comma operator will make "cond" to eval to false,
3295  * but float64_unordered_quiet() is still called. */
3296 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3297 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3298 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3299 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3300 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3301 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3302 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3303 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3304 /* NOTE: the comma operator will make "cond" to eval to false,
3305  * but float64_unordered() is still called. */
3306 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3307 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3308 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3309 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3310 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3311 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3312 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3313 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3314
3315 #define FOP_COND_S(op, cond)                                   \
3316 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3317                          uint32_t fst1, int cc)                \
3318 {                                                              \
3319     int c;                                                     \
3320     c = cond;                                                  \
3321     update_fcr31(env, GETPC());                                \
3322     if (c)                                                     \
3323         SET_FP_COND(cc, env->active_fpu);                      \
3324     else                                                       \
3325         CLEAR_FP_COND(cc, env->active_fpu);                    \
3326 }                                                              \
3327 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3328                             uint32_t fst1, int cc)             \
3329 {                                                              \
3330     int c;                                                     \
3331     fst0 = float32_abs(fst0);                                  \
3332     fst1 = float32_abs(fst1);                                  \
3333     c = cond;                                                  \
3334     update_fcr31(env, GETPC());                                \
3335     if (c)                                                     \
3336         SET_FP_COND(cc, env->active_fpu);                      \
3337     else                                                       \
3338         CLEAR_FP_COND(cc, env->active_fpu);                    \
3339 }
3340
3341 /* NOTE: the comma operator will make "cond" to eval to false,
3342  * but float32_unordered_quiet() is still called. */
3343 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3344 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3345 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3346 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3347 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3348 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3349 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3350 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3351 /* NOTE: the comma operator will make "cond" to eval to false,
3352  * but float32_unordered() is still called. */
3353 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3354 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3355 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3356 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3357 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3358 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3359 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3360 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3361
3362 #define FOP_COND_PS(op, condl, condh)                           \
3363 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3364                           uint64_t fdt1, int cc)                \
3365 {                                                               \
3366     uint32_t fst0, fsth0, fst1, fsth1;                          \
3367     int ch, cl;                                                 \
3368     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3369     fsth0 = fdt0 >> 32;                                         \
3370     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3371     fsth1 = fdt1 >> 32;                                         \
3372     cl = condl;                                                 \
3373     ch = condh;                                                 \
3374     update_fcr31(env, GETPC());                                 \
3375     if (cl)                                                     \
3376         SET_FP_COND(cc, env->active_fpu);                       \
3377     else                                                        \
3378         CLEAR_FP_COND(cc, env->active_fpu);                     \
3379     if (ch)                                                     \
3380         SET_FP_COND(cc + 1, env->active_fpu);                   \
3381     else                                                        \
3382         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3383 }                                                               \
3384 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3385                              uint64_t fdt1, int cc)             \
3386 {                                                               \
3387     uint32_t fst0, fsth0, fst1, fsth1;                          \
3388     int ch, cl;                                                 \
3389     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3390     fsth0 = float32_abs(fdt0 >> 32);                            \
3391     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3392     fsth1 = float32_abs(fdt1 >> 32);                            \
3393     cl = condl;                                                 \
3394     ch = condh;                                                 \
3395     update_fcr31(env, GETPC());                                 \
3396     if (cl)                                                     \
3397         SET_FP_COND(cc, env->active_fpu);                       \
3398     else                                                        \
3399         CLEAR_FP_COND(cc, env->active_fpu);                     \
3400     if (ch)                                                     \
3401         SET_FP_COND(cc + 1, env->active_fpu);                   \
3402     else                                                        \
3403         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3404 }
3405
3406 /* NOTE: the comma operator will make "cond" to eval to false,
3407  * but float32_unordered_quiet() is still called. */
3408 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3409                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3410 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3411                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3412 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3413                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3414 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3415                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3416 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3417                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3418 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3419                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3420 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3421                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3422 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3423                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3424 /* NOTE: the comma operator will make "cond" to eval to false,
3425  * but float32_unordered() is still called. */
3426 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3427                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3428 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3429                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3430 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3431                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3432 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3433                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3434 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3435                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3436 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3437                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3438 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3439                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3440 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3441                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3442
3443 /* R6 compare operations */
3444 #define FOP_CONDN_D(op, cond)                                       \
3445 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3446                          uint64_t fdt1)                             \
3447 {                                                                   \
3448     uint64_t c;                                                     \
3449     c = cond;                                                       \
3450     update_fcr31(env, GETPC());                                     \
3451     if (c) {                                                        \
3452         return -1;                                                  \
3453     } else {                                                        \
3454         return 0;                                                   \
3455     }                                                               \
3456 }
3457
3458 /* NOTE: the comma operator will make "cond" to eval to false,
3459  * but float64_unordered_quiet() is still called. */
3460 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3461 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3462 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3463 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3464                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3465 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3466 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3467                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3468 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3469 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3470                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3471 /* NOTE: the comma operator will make "cond" to eval to false,
3472  * but float64_unordered() is still called. */
3473 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3474 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3475 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3476 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3477                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3478 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3479 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3480                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3481 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3482 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3483                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3484 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3485                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3486 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3487                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3488                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3489 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3490                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3491 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3492                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3493 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3494                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3495                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3496 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3497                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3498
3499 #define FOP_CONDN_S(op, cond)                                       \
3500 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3501                          uint32_t fst1)                             \
3502 {                                                                   \
3503     uint64_t c;                                                     \
3504     c = cond;                                                       \
3505     update_fcr31(env, GETPC());                                     \
3506     if (c) {                                                        \
3507         return -1;                                                  \
3508     } else {                                                        \
3509         return 0;                                                   \
3510     }                                                               \
3511 }
3512
3513 /* NOTE: the comma operator will make "cond" to eval to false,
3514  * but float32_unordered_quiet() is still called. */
3515 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3516 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3517 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3518 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3519                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3520 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3521 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3522                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3523 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3524 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3525                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3526 /* NOTE: the comma operator will make "cond" to eval to false,
3527  * but float32_unordered() is still called. */
3528 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3529 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3530 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3531 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3532                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3533 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3534 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3535                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3536 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3537 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3538                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3539 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3540                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3541 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3542                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3543                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3544 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3545                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3546 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3547                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3548 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3549                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3550                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3551 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3552                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3553
3554 /* MSA */
3555 /* Data format min and max values */
3556 #define DF_BITS(df) (1 << ((df) + 3))
3557
3558 /* Element-by-element access macros */
3559 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3560
3561 void helper_msa_ld_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs,
3562                      int32_t s10)
3563 {
3564     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3565     target_ulong addr = env->active_tc.gpr[rs] + (s10 << df);
3566     int i;
3567
3568     switch (df) {
3569     case DF_BYTE:
3570         for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
3571             pwd->b[i] = do_lbu(env, addr + (i << DF_BYTE),
3572                                 env->hflags & MIPS_HFLAG_KSU);
3573         }
3574         break;
3575     case DF_HALF:
3576         for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
3577             pwd->h[i] = do_lhu(env, addr + (i << DF_HALF),
3578                                 env->hflags & MIPS_HFLAG_KSU);
3579         }
3580         break;
3581     case DF_WORD:
3582         for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3583             pwd->w[i] = do_lw(env, addr + (i << DF_WORD),
3584                                 env->hflags & MIPS_HFLAG_KSU);
3585         }
3586         break;
3587     case DF_DOUBLE:
3588         for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3589             pwd->d[i] = do_ld(env, addr + (i << DF_DOUBLE),
3590                                 env->hflags & MIPS_HFLAG_KSU);
3591         }
3592         break;
3593     }
3594 }
3595
3596 void helper_msa_st_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs,
3597                      int32_t s10)
3598 {
3599     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3600     target_ulong addr = env->active_tc.gpr[rs] + (s10 << df);
3601     int i;
3602
3603     switch (df) {
3604     case DF_BYTE:
3605         for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
3606             do_sb(env, addr + (i << DF_BYTE), pwd->b[i],
3607                     env->hflags & MIPS_HFLAG_KSU);
3608         }
3609         break;
3610     case DF_HALF:
3611         for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
3612             do_sh(env, addr + (i << DF_HALF), pwd->h[i],
3613                     env->hflags & MIPS_HFLAG_KSU);
3614         }
3615         break;
3616     case DF_WORD:
3617         for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3618             do_sw(env, addr + (i << DF_WORD), pwd->w[i],
3619                     env->hflags & MIPS_HFLAG_KSU);
3620         }
3621         break;
3622     case DF_DOUBLE:
3623         for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3624             do_sd(env, addr + (i << DF_DOUBLE), pwd->d[i],
3625                     env->hflags & MIPS_HFLAG_KSU);
3626         }
3627         break;
3628     }
3629 }