tests/i440fx-test.c

   1 /*
   2  * qtest I440FX test case
   3  *
   4  * Copyright IBM, Corp. 2012-2013
   5  * Copyright Red Hat, Inc. 2013
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *  Laszlo Ersek      <lersek@redhat.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  */
  14
  15 #include "libqos/pci.h"
  16 #include "libqos/pci-pc.h"
  17 #include "libqtest.h"
  18
  19 #include "hw/pci/pci_regs.h"
  20
  21 #include <glib.h>
  22 #include <string.h>
  23
  24 #define BROKEN 1
  25
  26 #define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
  27
  28 typedef struct TestData
  29 {
  30     int num_cpus;
  31     QPCIBus *bus;
  32 } TestData;
  33
  34 static void test_i440fx_defaults(gconstpointer opaque)
  35 {
  36     const TestData *s = opaque;
  37     QPCIDevice *dev;
  38     uint32_t value;
  39
  40     dev = qpci_device_find(s->bus, QPCI_DEVFN(0, 0));
  41     g_assert(dev != NULL);
  42
  43     /* 3.2.2 */
  44     g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
  45     /* 3.2.3 */
  46     g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
  47 #ifndef BROKEN
  48     /* 3.2.4 */
  49     g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
  50     /* 3.2.5 */
  51     g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
  52 #endif
  53     /* 3.2.7 */
  54     g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
  55     g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
  56     /* 3.2.8 */
  57     g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
  58     /* 3.2.9 */
  59     g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
  60     /* 3.2.10 */
  61     g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
  62
  63     /* 3.2.11 */
  64     value = qpci_config_readw(dev, 0x50); /* PMCCFG */
  65     if (s->num_cpus == 1) { /* WPE */
  66         g_assert(!(value & (1 << 15)));
  67     } else {
  68         g_assert((value & (1 << 15)));
  69     }
  70
  71     g_assert(!(value & (1 << 6))); /* EPTE */
  72
  73     /* 3.2.12 */
  74     g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
  75     /* 3.2.13 */
  76 #ifndef BROKEN
  77     g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
  78 #endif
  79     /* 3.2.14 */
  80     g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
  81     /* 3.2.15 */
  82     g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
  83 #ifndef BROKEN
  84     /* 3.2.16 */
  85     g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
  86     /* 3.2.17 */
  87     g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
  88 #endif
  89     /* 3.2.18 */
  90     g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
  91     g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
  92     g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
  93     g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
  94     g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
  95     g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
  96     g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
  97 #ifndef BROKEN
  98     /* 3.2.19 */
  99     g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
 100     g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
 101     g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
 102     g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
 103     g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
 104     g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
 105     g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
 106     g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
 107 #endif
 108     /* 3.2.20 */
 109     g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
 110     /* 3.2.21 */
 111     g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
 112 #ifndef BROKEN
 113     /* 3.2.22 */
 114     g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
 115 #endif
 116     /* 3.2.23 */
 117     g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
 118     /* 3.2.24 */
 119     g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
 120     /* 3.2.25 */
 121     g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
 122     /* 3.2.26 */
 123     g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
 124 }
 125
 126 #define PAM_RE 1
 127 #define PAM_WE 2
 128
 129 static void pam_set(QPCIDevice *dev, int index, int flags)
 130 {
 131     int regno = 0x59 + (index / 2);
 132     uint8_t reg;
 133
 134     reg = qpci_config_readb(dev, regno);
 135     if (index & 1) {
 136         reg = (reg & 0x0F) | (flags << 4);
 137     } else {
 138         reg = (reg & 0xF0) | flags;
 139     }
 140     qpci_config_writeb(dev, regno, reg);
 141 }
 142
 143 static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
 144 {
 145     uint32_t size = end - start + 1;
 146     gboolean ret = TRUE;
 147     uint8_t *data;
 148     int i;
 149
 150     data = g_malloc0(size);
 151     memread(start, data, size);
 152
 153     g_test_message("verify_area: data[0] = 0x%x", data[0]);
 154
 155     for (i = 0; i < size; i++) {
 156         if (data[i] != value) {
 157             ret = FALSE;
 158             break;
 159         }
 160     }
 161
 162     g_free(data);
 163
 164     return ret;
 165 }
 166
 167 static void write_area(uint32_t start, uint32_t end, uint8_t value)
 168 {
 169     uint32_t size = end - start + 1;
 170     uint8_t *data;
 171
 172     data = g_malloc0(size);
 173     memset(data, value, size);
 174     memwrite(start, data, size);
 175
 176     g_free(data);
 177 }
 178
 179 static void test_i440fx_pam(gconstpointer opaque)
 180 {
 181     const TestData *s = opaque;
 182     QPCIDevice *dev;
 183     int i;
 184     static struct {
 185         uint32_t start;
 186         uint32_t end;
 187     } pam_area[] = {
 188         { 0, 0 },             /* Reserved */
 189         { 0xF0000, 0xFFFFF }, /* BIOS Area */
 190         { 0xC0000, 0xC3FFF }, /* Option ROM */
 191         { 0xC4000, 0xC7FFF }, /* Option ROM */
 192         { 0xC8000, 0xCBFFF }, /* Option ROM */
 193         { 0xCC000, 0xCFFFF }, /* Option ROM */
 194         { 0xD0000, 0xD3FFF }, /* Option ROM */
 195         { 0xD4000, 0xD7FFF }, /* Option ROM */
 196         { 0xD8000, 0xDBFFF }, /* Option ROM */
 197         { 0xDC000, 0xDFFFF }, /* Option ROM */
 198         { 0xE0000, 0xE3FFF }, /* BIOS Extension */
 199         { 0xE4000, 0xE7FFF }, /* BIOS Extension */
 200         { 0xE8000, 0xEBFFF }, /* BIOS Extension */
 201         { 0xEC000, 0xEFFFF }, /* BIOS Extension */
 202     };
 203
 204     dev = qpci_device_find(s->bus, QPCI_DEVFN(0, 0));
 205     g_assert(dev != NULL);
 206
 207     for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
 208         if (pam_area[i].start == pam_area[i].end) {
 209             continue;
 210         }
 211
 212         g_test_message("Checking area 0x%05x..0x%05x",
 213                        pam_area[i].start, pam_area[i].end);
 214         /* Switch to RE for the area */
 215         pam_set(dev, i, PAM_RE);
 216         /* Verify the RAM is all zeros */
 217         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
 218
 219         /* Switch to WE for the area */
 220         pam_set(dev, i, PAM_RE | PAM_WE);
 221         /* Write out a non-zero mask to the full area */
 222         write_area(pam_area[i].start, pam_area[i].end, 0x42);
 223
 224 #ifndef BROKEN
 225         /* QEMU only supports a limited form of PAM */
 226
 227         /* Switch to !RE for the area */
 228         pam_set(dev, i, PAM_WE);
 229         /* Verify the area is not our mask */
 230         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 231 #endif
 232
 233         /* Verify the area is our new mask */
 234         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 235
 236         /* Write out a new mask */
 237         write_area(pam_area[i].start, pam_area[i].end, 0x82);
 238
 239 #ifndef BROKEN
 240         /* QEMU only supports a limited form of PAM */
 241
 242         /* Verify the area is not our mask */
 243         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 244
 245         /* Switch to RE for the area */
 246         pam_set(dev, i, PAM_RE | PAM_WE);
 247 #endif
 248         /* Verify the area is our new mask */
 249         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 250
 251         /* Reset area */
 252         pam_set(dev, i, 0);
 253
 254         /* Verify the area is not our new mask */
 255         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 256     }
 257 }
 258
 259 int main(int argc, char **argv)
 260 {
 261     TestData data;
 262     char *cmdline;
 263     int ret;
 264
 265     g_test_init(&argc, &argv, NULL);
 266
 267     data.num_cpus = 1;
 268
 269     cmdline = g_strdup_printf("-smp %d", data.num_cpus);
 270     qtest_start(cmdline);
 271     g_free(cmdline);
 272
 273     data.bus = qpci_init_pc();
 274
 275     g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
 276     g_test_add_data_func("/i440fx/pam", &data, test_i440fx_pam);
 277
 278     ret = g_test_run();
 279
 280     qtest_end();
 281
 282     return ret;
 283 }