2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
4 * Copyright (c) 2017 SiFive, Inc.
6 * Provides a board compatible with the SiFive Freedom E SDK:
9 * 1) CLINT (Core Level Interruptor)
10 * 2) PLIC (Platform Level Interrupt Controller)
11 * 3) PRCI (Power, Reset, Clock, Interrupt)
12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
13 * 5) Flash memory emulated as RAM
15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
16 * The OTP ROM and Flash boot code will be emulated in a future version.
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2 or later, as published by the Free Software Foundation.
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
31 #include "qemu/osdep.h"
33 #include "qemu/error-report.h"
34 #include "qapi/error.h"
36 #include "hw/boards.h"
37 #include "hw/loader.h"
38 #include "hw/sysbus.h"
39 #include "hw/char/serial.h"
40 #include "target/riscv/cpu.h"
41 #include "hw/riscv/riscv_hart.h"
42 #include "hw/riscv/sifive_plic.h"
43 #include "hw/riscv/sifive_clint.h"
44 #include "hw/riscv/sifive_prci.h"
45 #include "hw/riscv/sifive_uart.h"
46 #include "hw/riscv/sifive_e.h"
47 #include "chardev/char.h"
48 #include "sysemu/arch_init.h"
49 #include "exec/address-spaces.h"
52 static const struct MemmapEntry
{
55 } sifive_e_memmap
[] = {
56 [SIFIVE_E_DEBUG
] = { 0x0, 0x100 },
57 [SIFIVE_E_MROM
] = { 0x1000, 0x2000 },
58 [SIFIVE_E_OTP
] = { 0x20000, 0x2000 },
59 [SIFIVE_E_CLINT
] = { 0x2000000, 0x10000 },
60 [SIFIVE_E_PLIC
] = { 0xc000000, 0x4000000 },
61 [SIFIVE_E_AON
] = { 0x10000000, 0x8000 },
62 [SIFIVE_E_PRCI
] = { 0x10008000, 0x8000 },
63 [SIFIVE_E_OTP_CTRL
] = { 0x10010000, 0x1000 },
64 [SIFIVE_E_GPIO0
] = { 0x10012000, 0x1000 },
65 [SIFIVE_E_UART0
] = { 0x10013000, 0x1000 },
66 [SIFIVE_E_QSPI0
] = { 0x10014000, 0x1000 },
67 [SIFIVE_E_PWM0
] = { 0x10015000, 0x1000 },
68 [SIFIVE_E_UART1
] = { 0x10023000, 0x1000 },
69 [SIFIVE_E_QSPI1
] = { 0x10024000, 0x1000 },
70 [SIFIVE_E_PWM1
] = { 0x10025000, 0x1000 },
71 [SIFIVE_E_QSPI2
] = { 0x10034000, 0x1000 },
72 [SIFIVE_E_PWM2
] = { 0x10035000, 0x1000 },
73 [SIFIVE_E_XIP
] = { 0x20000000, 0x20000000 },
74 [SIFIVE_E_DTIM
] = { 0x80000000, 0x4000 }
77 static void copy_le32_to_phys(hwaddr pa
, uint32_t *rom
, size_t len
)
80 for (i
= 0; i
< (len
>> 2); i
++) {
81 stl_phys(&address_space_memory
, pa
+ (i
<< 2), rom
[i
]);
85 static uint64_t load_kernel(const char *kernel_filename
)
87 uint64_t kernel_entry
, kernel_high
;
89 if (load_elf(kernel_filename
, NULL
, NULL
,
90 &kernel_entry
, NULL
, &kernel_high
,
91 0, ELF_MACHINE
, 1, 0) < 0) {
92 error_report("qemu: could not load kernel '%s'", kernel_filename
);
98 static void sifive_mmio_emulate(MemoryRegion
*parent
, const char *name
,
99 uintptr_t offset
, uintptr_t length
)
101 MemoryRegion
*mock_mmio
= g_new(MemoryRegion
, 1);
102 memory_region_init_ram(mock_mmio
, NULL
, name
, length
, &error_fatal
);
103 memory_region_add_subregion(parent
, offset
, mock_mmio
);
106 static void riscv_sifive_e_init(MachineState
*machine
)
108 const struct MemmapEntry
*memmap
= sifive_e_memmap
;
110 SiFiveEState
*s
= g_new0(SiFiveEState
, 1);
111 MemoryRegion
*sys_mem
= get_system_memory();
112 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
113 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
114 MemoryRegion
*xip_mem
= g_new(MemoryRegion
, 1);
117 object_initialize(&s
->soc
, sizeof(s
->soc
), TYPE_RISCV_HART_ARRAY
);
118 object_property_add_child(OBJECT(machine
), "soc", OBJECT(&s
->soc
),
120 object_property_set_str(OBJECT(&s
->soc
), SIFIVE_E_CPU
, "cpu-type",
122 object_property_set_int(OBJECT(&s
->soc
), smp_cpus
, "num-harts",
124 object_property_set_bool(OBJECT(&s
->soc
), true, "realized",
127 /* Data Tightly Integrated Memory */
128 memory_region_init_ram(main_mem
, NULL
, "riscv.sifive.e.ram",
129 memmap
[SIFIVE_E_DTIM
].size
, &error_fatal
);
130 memory_region_add_subregion(sys_mem
,
131 memmap
[SIFIVE_E_DTIM
].base
, main_mem
);
134 memory_region_init_ram(mask_rom
, NULL
, "riscv.sifive.e.mrom",
135 memmap
[SIFIVE_E_MROM
].size
, &error_fatal
);
136 memory_region_add_subregion(sys_mem
,
137 memmap
[SIFIVE_E_MROM
].base
, mask_rom
);
140 s
->plic
= sifive_plic_create(memmap
[SIFIVE_E_PLIC
].base
,
141 (char *)SIFIVE_E_PLIC_HART_CONFIG
,
142 SIFIVE_E_PLIC_NUM_SOURCES
,
143 SIFIVE_E_PLIC_NUM_PRIORITIES
,
144 SIFIVE_E_PLIC_PRIORITY_BASE
,
145 SIFIVE_E_PLIC_PENDING_BASE
,
146 SIFIVE_E_PLIC_ENABLE_BASE
,
147 SIFIVE_E_PLIC_ENABLE_STRIDE
,
148 SIFIVE_E_PLIC_CONTEXT_BASE
,
149 SIFIVE_E_PLIC_CONTEXT_STRIDE
,
150 memmap
[SIFIVE_E_PLIC
].size
);
151 sifive_clint_create(memmap
[SIFIVE_E_CLINT
].base
,
152 memmap
[SIFIVE_E_CLINT
].size
, smp_cpus
,
153 SIFIVE_SIP_BASE
, SIFIVE_TIMECMP_BASE
, SIFIVE_TIME_BASE
);
154 sifive_mmio_emulate(sys_mem
, "riscv.sifive.e.aon",
155 memmap
[SIFIVE_E_AON
].base
, memmap
[SIFIVE_E_AON
].size
);
156 sifive_prci_create(memmap
[SIFIVE_E_PRCI
].base
);
157 sifive_mmio_emulate(sys_mem
, "riscv.sifive.e.gpio0",
158 memmap
[SIFIVE_E_GPIO0
].base
, memmap
[SIFIVE_E_GPIO0
].size
);
159 sifive_uart_create(sys_mem
, memmap
[SIFIVE_E_UART0
].base
,
160 serial_hd(0), SIFIVE_PLIC(s
->plic
)->irqs
[SIFIVE_E_UART0_IRQ
]);
161 sifive_mmio_emulate(sys_mem
, "riscv.sifive.e.qspi0",
162 memmap
[SIFIVE_E_QSPI0
].base
, memmap
[SIFIVE_E_QSPI0
].size
);
163 sifive_mmio_emulate(sys_mem
, "riscv.sifive.e.pwm0",
164 memmap
[SIFIVE_E_PWM0
].base
, memmap
[SIFIVE_E_PWM0
].size
);
165 /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
166 serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */
167 sifive_mmio_emulate(sys_mem
, "riscv.sifive.e.qspi1",
168 memmap
[SIFIVE_E_QSPI1
].base
, memmap
[SIFIVE_E_QSPI1
].size
);
169 sifive_mmio_emulate(sys_mem
, "riscv.sifive.e.pwm1",
170 memmap
[SIFIVE_E_PWM1
].base
, memmap
[SIFIVE_E_PWM1
].size
);
171 sifive_mmio_emulate(sys_mem
, "riscv.sifive.e.qspi2",
172 memmap
[SIFIVE_E_QSPI2
].base
, memmap
[SIFIVE_E_QSPI2
].size
);
173 sifive_mmio_emulate(sys_mem
, "riscv.sifive.e.pwm2",
174 memmap
[SIFIVE_E_PWM2
].base
, memmap
[SIFIVE_E_PWM2
].size
);
177 memory_region_init_ram(xip_mem
, NULL
, "riscv.sifive.e.xip",
178 memmap
[SIFIVE_E_XIP
].size
, &error_fatal
);
179 memory_region_set_readonly(xip_mem
, true);
180 memory_region_add_subregion(sys_mem
, memmap
[SIFIVE_E_XIP
].base
, xip_mem
);
182 /* Mask ROM reset vector */
183 uint32_t reset_vec
[2] = {
184 0x204002b7, /* 0x1000: lui t0,0x20400 */
185 0x00028067, /* 0x1004: jr t0 */
188 /* copy in the reset vector */
189 copy_le32_to_phys(memmap
[SIFIVE_E_MROM
].base
, reset_vec
, sizeof(reset_vec
));
190 memory_region_set_readonly(mask_rom
, true);
192 if (machine
->kernel_filename
) {
193 load_kernel(machine
->kernel_filename
);
197 static int riscv_sifive_e_sysbus_device_init(SysBusDevice
*sysbusdev
)
202 static void riscv_sifive_e_class_init(ObjectClass
*klass
, void *data
)
204 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
205 k
->init
= riscv_sifive_e_sysbus_device_init
;
208 static const TypeInfo riscv_sifive_e_device
= {
209 .name
= TYPE_SIFIVE_E
,
210 .parent
= TYPE_SYS_BUS_DEVICE
,
211 .instance_size
= sizeof(SiFiveEState
),
212 .class_init
= riscv_sifive_e_class_init
,
215 static void riscv_sifive_e_machine_init(MachineClass
*mc
)
217 mc
->desc
= "RISC-V Board compatible with SiFive E SDK";
218 mc
->init
= riscv_sifive_e_init
;
222 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init
)
224 static void riscv_sifive_e_register_types(void)
226 type_register_static(&riscv_sifive_e_device
);
229 type_init(riscv_sifive_e_register_types
);