4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
30 #include "qemu-common.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
44 static const char *cpu_model
;
45 unsigned long mmap_min_addr
;
46 #if defined(CONFIG_USE_GUEST_BASE)
47 unsigned long guest_base
;
49 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51 * When running 32-on-64 we should make sure we can fit all of the possible
52 * guest address space into a contiguous chunk of virtual host memory.
54 * This way we will never overlap with our own libraries or binaries or stack
55 * or anything else that QEMU maps.
58 /* MIPS only supports 31 bits of virtual address space for user space */
59 unsigned long reserved_va
= 0x77000000;
61 unsigned long reserved_va
= 0xf7000000;
64 unsigned long reserved_va
;
68 static void usage(void);
70 static const char *interp_prefix
= CONFIG_QEMU_INTERP_PREFIX
;
71 const char *qemu_uname_release
;
73 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
74 we allocate a bigger stack. Need a better solution, for example
75 by remapping the process stack directly at the right place */
76 unsigned long guest_stack_size
= 8 * 1024 * 1024UL;
78 void gemu_log(const char *fmt
, ...)
83 vfprintf(stderr
, fmt
, ap
);
87 #if defined(TARGET_I386)
88 int cpu_get_pic_interrupt(CPUX86State
*env
)
94 /***********************************************************/
95 /* Helper routines for implementing atomic operations. */
97 /* To implement exclusive operations we force all cpus to syncronise.
98 We don't require a full sync, only that no cpus are executing guest code.
99 The alternative is to map target atomic ops onto host equivalents,
100 which requires quite a lot of per host/target work. */
101 static pthread_mutex_t cpu_list_mutex
= PTHREAD_MUTEX_INITIALIZER
;
102 static pthread_mutex_t exclusive_lock
= PTHREAD_MUTEX_INITIALIZER
;
103 static pthread_cond_t exclusive_cond
= PTHREAD_COND_INITIALIZER
;
104 static pthread_cond_t exclusive_resume
= PTHREAD_COND_INITIALIZER
;
105 static int pending_cpus
;
107 /* Make sure everything is in a consistent state for calling fork(). */
108 void fork_start(void)
110 pthread_mutex_lock(&tcg_ctx
.tb_ctx
.tb_lock
);
111 pthread_mutex_lock(&exclusive_lock
);
115 void fork_end(int child
)
117 mmap_fork_end(child
);
119 CPUState
*cpu
, *next_cpu
;
120 /* Child processes created by fork() only have a single thread.
121 Discard information about the parent threads. */
122 CPU_FOREACH_SAFE(cpu
, next_cpu
) {
123 if (cpu
!= thread_cpu
) {
124 QTAILQ_REMOVE(&cpus
, thread_cpu
, node
);
128 pthread_mutex_init(&exclusive_lock
, NULL
);
129 pthread_mutex_init(&cpu_list_mutex
, NULL
);
130 pthread_cond_init(&exclusive_cond
, NULL
);
131 pthread_cond_init(&exclusive_resume
, NULL
);
132 pthread_mutex_init(&tcg_ctx
.tb_ctx
.tb_lock
, NULL
);
133 gdbserver_fork((CPUArchState
*)thread_cpu
->env_ptr
);
135 pthread_mutex_unlock(&exclusive_lock
);
136 pthread_mutex_unlock(&tcg_ctx
.tb_ctx
.tb_lock
);
140 /* Wait for pending exclusive operations to complete. The exclusive lock
142 static inline void exclusive_idle(void)
144 while (pending_cpus
) {
145 pthread_cond_wait(&exclusive_resume
, &exclusive_lock
);
149 /* Start an exclusive operation.
150 Must only be called from outside cpu_arm_exec. */
151 static inline void start_exclusive(void)
155 pthread_mutex_lock(&exclusive_lock
);
159 /* Make all other cpus stop executing. */
160 CPU_FOREACH(other_cpu
) {
161 if (other_cpu
->running
) {
166 if (pending_cpus
> 1) {
167 pthread_cond_wait(&exclusive_cond
, &exclusive_lock
);
171 /* Finish an exclusive operation. */
172 static inline void __attribute__((unused
)) end_exclusive(void)
175 pthread_cond_broadcast(&exclusive_resume
);
176 pthread_mutex_unlock(&exclusive_lock
);
179 /* Wait for exclusive ops to finish, and begin cpu execution. */
180 static inline void cpu_exec_start(CPUState
*cpu
)
182 pthread_mutex_lock(&exclusive_lock
);
185 pthread_mutex_unlock(&exclusive_lock
);
188 /* Mark cpu as not executing, and release pending exclusive ops. */
189 static inline void cpu_exec_end(CPUState
*cpu
)
191 pthread_mutex_lock(&exclusive_lock
);
192 cpu
->running
= false;
193 if (pending_cpus
> 1) {
195 if (pending_cpus
== 1) {
196 pthread_cond_signal(&exclusive_cond
);
200 pthread_mutex_unlock(&exclusive_lock
);
203 void cpu_list_lock(void)
205 pthread_mutex_lock(&cpu_list_mutex
);
208 void cpu_list_unlock(void)
210 pthread_mutex_unlock(&cpu_list_mutex
);
215 /***********************************************************/
216 /* CPUX86 core interface */
218 uint64_t cpu_get_tsc(CPUX86State
*env
)
220 return cpu_get_real_ticks();
223 static void write_dt(void *ptr
, unsigned long addr
, unsigned long limit
,
228 e1
= (addr
<< 16) | (limit
& 0xffff);
229 e2
= ((addr
>> 16) & 0xff) | (addr
& 0xff000000) | (limit
& 0x000f0000);
236 static uint64_t *idt_table
;
238 static void set_gate64(void *ptr
, unsigned int type
, unsigned int dpl
,
239 uint64_t addr
, unsigned int sel
)
242 e1
= (addr
& 0xffff) | (sel
<< 16);
243 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
247 p
[2] = tswap32(addr
>> 32);
250 /* only dpl matters as we do only user space emulation */
251 static void set_idt(int n
, unsigned int dpl
)
253 set_gate64(idt_table
+ n
* 2, 0, dpl
, 0, 0);
256 static void set_gate(void *ptr
, unsigned int type
, unsigned int dpl
,
257 uint32_t addr
, unsigned int sel
)
260 e1
= (addr
& 0xffff) | (sel
<< 16);
261 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
267 /* only dpl matters as we do only user space emulation */
268 static void set_idt(int n
, unsigned int dpl
)
270 set_gate(idt_table
+ n
, 0, dpl
, 0, 0);
274 void cpu_loop(CPUX86State
*env
)
276 CPUState
*cs
= CPU(x86_env_get_cpu(env
));
279 target_siginfo_t info
;
283 trapnr
= cpu_x86_exec(env
);
287 /* linux syscall from int $0x80 */
288 env
->regs
[R_EAX
] = do_syscall(env
,
300 /* linux syscall from syscall instruction */
301 env
->regs
[R_EAX
] = do_syscall(env
,
314 info
.si_signo
= TARGET_SIGBUS
;
316 info
.si_code
= TARGET_SI_KERNEL
;
317 info
._sifields
._sigfault
._addr
= 0;
318 queue_signal(env
, info
.si_signo
, &info
);
321 /* XXX: potential problem if ABI32 */
322 #ifndef TARGET_X86_64
323 if (env
->eflags
& VM_MASK
) {
324 handle_vm86_fault(env
);
328 info
.si_signo
= TARGET_SIGSEGV
;
330 info
.si_code
= TARGET_SI_KERNEL
;
331 info
._sifields
._sigfault
._addr
= 0;
332 queue_signal(env
, info
.si_signo
, &info
);
336 info
.si_signo
= TARGET_SIGSEGV
;
338 if (!(env
->error_code
& 1))
339 info
.si_code
= TARGET_SEGV_MAPERR
;
341 info
.si_code
= TARGET_SEGV_ACCERR
;
342 info
._sifields
._sigfault
._addr
= env
->cr
[2];
343 queue_signal(env
, info
.si_signo
, &info
);
346 #ifndef TARGET_X86_64
347 if (env
->eflags
& VM_MASK
) {
348 handle_vm86_trap(env
, trapnr
);
352 /* division by zero */
353 info
.si_signo
= TARGET_SIGFPE
;
355 info
.si_code
= TARGET_FPE_INTDIV
;
356 info
._sifields
._sigfault
._addr
= env
->eip
;
357 queue_signal(env
, info
.si_signo
, &info
);
362 #ifndef TARGET_X86_64
363 if (env
->eflags
& VM_MASK
) {
364 handle_vm86_trap(env
, trapnr
);
368 info
.si_signo
= TARGET_SIGTRAP
;
370 if (trapnr
== EXCP01_DB
) {
371 info
.si_code
= TARGET_TRAP_BRKPT
;
372 info
._sifields
._sigfault
._addr
= env
->eip
;
374 info
.si_code
= TARGET_SI_KERNEL
;
375 info
._sifields
._sigfault
._addr
= 0;
377 queue_signal(env
, info
.si_signo
, &info
);
382 #ifndef TARGET_X86_64
383 if (env
->eflags
& VM_MASK
) {
384 handle_vm86_trap(env
, trapnr
);
388 info
.si_signo
= TARGET_SIGSEGV
;
390 info
.si_code
= TARGET_SI_KERNEL
;
391 info
._sifields
._sigfault
._addr
= 0;
392 queue_signal(env
, info
.si_signo
, &info
);
396 info
.si_signo
= TARGET_SIGILL
;
398 info
.si_code
= TARGET_ILL_ILLOPN
;
399 info
._sifields
._sigfault
._addr
= env
->eip
;
400 queue_signal(env
, info
.si_signo
, &info
);
403 /* just indicate that signals should be handled asap */
409 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
414 info
.si_code
= TARGET_TRAP_BRKPT
;
415 queue_signal(env
, info
.si_signo
, &info
);
420 pc
= env
->segs
[R_CS
].base
+ env
->eip
;
421 fprintf(stderr
, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
425 process_pending_signals(env
);
432 #define get_user_code_u32(x, gaddr, doswap) \
433 ({ abi_long __r = get_user_u32((x), (gaddr)); \
434 if (!__r && (doswap)) { \
440 #define get_user_code_u16(x, gaddr, doswap) \
441 ({ abi_long __r = get_user_u16((x), (gaddr)); \
442 if (!__r && (doswap)) { \
449 /* Commpage handling -- there is no commpage for AArch64 */
452 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
454 * r0 = pointer to oldval
455 * r1 = pointer to newval
456 * r2 = pointer to target value
459 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
460 * C set if *ptr was changed, clear if no exchange happened
462 * Note segv's in kernel helpers are a bit tricky, we can set the
463 * data address sensibly but the PC address is just the entry point.
465 static void arm_kernel_cmpxchg64_helper(CPUARMState
*env
)
467 uint64_t oldval
, newval
, val
;
469 target_siginfo_t info
;
471 /* Based on the 32 bit code in do_kernel_trap */
473 /* XXX: This only works between threads, not between processes.
474 It's probably possible to implement this with native host
475 operations. However things like ldrex/strex are much harder so
476 there's not much point trying. */
478 cpsr
= cpsr_read(env
);
481 if (get_user_u64(oldval
, env
->regs
[0])) {
482 env
->exception
.vaddress
= env
->regs
[0];
486 if (get_user_u64(newval
, env
->regs
[1])) {
487 env
->exception
.vaddress
= env
->regs
[1];
491 if (get_user_u64(val
, addr
)) {
492 env
->exception
.vaddress
= addr
;
499 if (put_user_u64(val
, addr
)) {
500 env
->exception
.vaddress
= addr
;
510 cpsr_write(env
, cpsr
, CPSR_C
);
516 /* We get the PC of the entry address - which is as good as anything,
517 on a real kernel what you get depends on which mode it uses. */
518 info
.si_signo
= TARGET_SIGSEGV
;
520 /* XXX: check env->error_code */
521 info
.si_code
= TARGET_SEGV_MAPERR
;
522 info
._sifields
._sigfault
._addr
= env
->exception
.vaddress
;
523 queue_signal(env
, info
.si_signo
, &info
);
526 /* Handle a jump to the kernel code page. */
528 do_kernel_trap(CPUARMState
*env
)
534 switch (env
->regs
[15]) {
535 case 0xffff0fa0: /* __kernel_memory_barrier */
536 /* ??? No-op. Will need to do better for SMP. */
538 case 0xffff0fc0: /* __kernel_cmpxchg */
539 /* XXX: This only works between threads, not between processes.
540 It's probably possible to implement this with native host
541 operations. However things like ldrex/strex are much harder so
542 there's not much point trying. */
544 cpsr
= cpsr_read(env
);
546 /* FIXME: This should SEGV if the access fails. */
547 if (get_user_u32(val
, addr
))
549 if (val
== env
->regs
[0]) {
551 /* FIXME: Check for segfaults. */
552 put_user_u32(val
, addr
);
559 cpsr_write(env
, cpsr
, CPSR_C
);
562 case 0xffff0fe0: /* __kernel_get_tls */
563 env
->regs
[0] = cpu_get_tls(env
);
565 case 0xffff0f60: /* __kernel_cmpxchg64 */
566 arm_kernel_cmpxchg64_helper(env
);
572 /* Jump back to the caller. */
573 addr
= env
->regs
[14];
578 env
->regs
[15] = addr
;
583 /* Store exclusive handling for AArch32 */
584 static int do_strex(CPUARMState
*env
)
592 if (env
->exclusive_addr
!= env
->exclusive_test
) {
595 /* We know we're always AArch32 so the address is in uint32_t range
596 * unless it was the -1 exclusive-monitor-lost value (which won't
597 * match exclusive_test above).
599 assert(extract64(env
->exclusive_addr
, 32, 32) == 0);
600 addr
= env
->exclusive_addr
;
601 size
= env
->exclusive_info
& 0xf;
604 segv
= get_user_u8(val
, addr
);
607 segv
= get_user_u16(val
, addr
);
611 segv
= get_user_u32(val
, addr
);
617 env
->exception
.vaddress
= addr
;
622 segv
= get_user_u32(valhi
, addr
+ 4);
624 env
->exception
.vaddress
= addr
+ 4;
627 val
= deposit64(val
, 32, 32, valhi
);
629 if (val
!= env
->exclusive_val
) {
633 val
= env
->regs
[(env
->exclusive_info
>> 8) & 0xf];
636 segv
= put_user_u8(val
, addr
);
639 segv
= put_user_u16(val
, addr
);
643 segv
= put_user_u32(val
, addr
);
647 env
->exception
.vaddress
= addr
;
651 val
= env
->regs
[(env
->exclusive_info
>> 12) & 0xf];
652 segv
= put_user_u32(val
, addr
+ 4);
654 env
->exception
.vaddress
= addr
+ 4;
661 env
->regs
[(env
->exclusive_info
>> 4) & 0xf] = rc
;
667 void cpu_loop(CPUARMState
*env
)
669 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
671 unsigned int n
, insn
;
672 target_siginfo_t info
;
677 trapnr
= cpu_arm_exec(env
);
682 TaskState
*ts
= cs
->opaque
;
686 /* we handle the FPU emulation here, as Linux */
687 /* we get the opcode */
688 /* FIXME - what to do if get_user() fails? */
689 get_user_code_u32(opcode
, env
->regs
[15], env
->bswap_code
);
691 rc
= EmulateAll(opcode
, &ts
->fpa
, env
);
692 if (rc
== 0) { /* illegal instruction */
693 info
.si_signo
= TARGET_SIGILL
;
695 info
.si_code
= TARGET_ILL_ILLOPN
;
696 info
._sifields
._sigfault
._addr
= env
->regs
[15];
697 queue_signal(env
, info
.si_signo
, &info
);
698 } else if (rc
< 0) { /* FP exception */
701 /* translate softfloat flags to FPSR flags */
702 if (-rc
& float_flag_invalid
)
704 if (-rc
& float_flag_divbyzero
)
706 if (-rc
& float_flag_overflow
)
708 if (-rc
& float_flag_underflow
)
710 if (-rc
& float_flag_inexact
)
713 FPSR fpsr
= ts
->fpa
.fpsr
;
714 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
716 if (fpsr
& (arm_fpe
<< 16)) { /* exception enabled? */
717 info
.si_signo
= TARGET_SIGFPE
;
720 /* ordered by priority, least first */
721 if (arm_fpe
& BIT_IXC
) info
.si_code
= TARGET_FPE_FLTRES
;
722 if (arm_fpe
& BIT_UFC
) info
.si_code
= TARGET_FPE_FLTUND
;
723 if (arm_fpe
& BIT_OFC
) info
.si_code
= TARGET_FPE_FLTOVF
;
724 if (arm_fpe
& BIT_DZC
) info
.si_code
= TARGET_FPE_FLTDIV
;
725 if (arm_fpe
& BIT_IOC
) info
.si_code
= TARGET_FPE_FLTINV
;
727 info
._sifields
._sigfault
._addr
= env
->regs
[15];
728 queue_signal(env
, info
.si_signo
, &info
);
733 /* accumulate unenabled exceptions */
734 if ((!(fpsr
& BIT_IXE
)) && (arm_fpe
& BIT_IXC
))
736 if ((!(fpsr
& BIT_UFE
)) && (arm_fpe
& BIT_UFC
))
738 if ((!(fpsr
& BIT_OFE
)) && (arm_fpe
& BIT_OFC
))
740 if ((!(fpsr
& BIT_DZE
)) && (arm_fpe
& BIT_DZC
))
742 if ((!(fpsr
& BIT_IOE
)) && (arm_fpe
& BIT_IOC
))
745 } else { /* everything OK */
756 if (trapnr
== EXCP_BKPT
) {
758 /* FIXME - what to do if get_user() fails? */
759 get_user_code_u16(insn
, env
->regs
[15], env
->bswap_code
);
763 /* FIXME - what to do if get_user() fails? */
764 get_user_code_u32(insn
, env
->regs
[15], env
->bswap_code
);
765 n
= (insn
& 0xf) | ((insn
>> 4) & 0xff0);
770 /* FIXME - what to do if get_user() fails? */
771 get_user_code_u16(insn
, env
->regs
[15] - 2,
775 /* FIXME - what to do if get_user() fails? */
776 get_user_code_u32(insn
, env
->regs
[15] - 4,
782 if (n
== ARM_NR_cacheflush
) {
784 } else if (n
== ARM_NR_semihosting
785 || n
== ARM_NR_thumb_semihosting
) {
786 env
->regs
[0] = do_arm_semihosting (env
);
787 } else if (n
== 0 || n
>= ARM_SYSCALL_BASE
|| env
->thumb
) {
789 if (env
->thumb
|| n
== 0) {
792 n
-= ARM_SYSCALL_BASE
;
795 if ( n
> ARM_NR_BASE
) {
797 case ARM_NR_cacheflush
:
801 cpu_set_tls(env
, env
->regs
[0]);
804 case ARM_NR_breakpoint
:
805 env
->regs
[15] -= env
->thumb
? 2 : 4;
808 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
810 env
->regs
[0] = -TARGET_ENOSYS
;
814 env
->regs
[0] = do_syscall(env
,
830 /* just indicate that signals should be handled asap */
833 if (!do_strex(env
)) {
836 /* fall through for segv */
837 case EXCP_PREFETCH_ABORT
:
838 case EXCP_DATA_ABORT
:
839 addr
= env
->exception
.vaddress
;
841 info
.si_signo
= TARGET_SIGSEGV
;
843 /* XXX: check env->error_code */
844 info
.si_code
= TARGET_SEGV_MAPERR
;
845 info
._sifields
._sigfault
._addr
= addr
;
846 queue_signal(env
, info
.si_signo
, &info
);
854 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
859 info
.si_code
= TARGET_TRAP_BRKPT
;
860 queue_signal(env
, info
.si_signo
, &info
);
864 case EXCP_KERNEL_TRAP
:
865 if (do_kernel_trap(env
))
870 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n",
872 cpu_dump_state(cs
, stderr
, fprintf
, 0);
875 process_pending_signals(env
);
882 * Handle AArch64 store-release exclusive
884 * rs = gets the status result of store exclusive
885 * rt = is the register that is stored
886 * rt2 = is the second register store (in STP)
889 static int do_strex_a64(CPUARMState
*env
)
900 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
901 size
= extract32(env
->exclusive_info
, 0, 2);
902 is_pair
= extract32(env
->exclusive_info
, 2, 1);
903 rs
= extract32(env
->exclusive_info
, 4, 5);
904 rt
= extract32(env
->exclusive_info
, 9, 5);
905 rt2
= extract32(env
->exclusive_info
, 14, 5);
907 addr
= env
->exclusive_addr
;
909 if (addr
!= env
->exclusive_test
) {
915 segv
= get_user_u8(val
, addr
);
918 segv
= get_user_u16(val
, addr
);
921 segv
= get_user_u32(val
, addr
);
924 segv
= get_user_u64(val
, addr
);
930 env
->exception
.vaddress
= addr
;
933 if (val
!= env
->exclusive_val
) {
938 segv
= get_user_u32(val
, addr
+ 4);
940 segv
= get_user_u64(val
, addr
+ 8);
943 env
->exception
.vaddress
= addr
+ (size
== 2 ? 4 : 8);
946 if (val
!= env
->exclusive_high
) {
950 /* handle the zero register */
951 val
= rt
== 31 ? 0 : env
->xregs
[rt
];
954 segv
= put_user_u8(val
, addr
);
957 segv
= put_user_u16(val
, addr
);
960 segv
= put_user_u32(val
, addr
);
963 segv
= put_user_u64(val
, addr
);
970 /* handle the zero register */
971 val
= rt2
== 31 ? 0 : env
->xregs
[rt2
];
973 segv
= put_user_u32(val
, addr
+ 4);
975 segv
= put_user_u64(val
, addr
+ 8);
978 env
->exception
.vaddress
= addr
+ (size
== 2 ? 4 : 8);
985 /* rs == 31 encodes a write to the ZR, thus throwing away
986 * the status return. This is rather silly but valid.
992 /* instruction faulted, PC does not advance */
993 /* either way a strex releases any exclusive lock we have */
994 env
->exclusive_addr
= -1;
999 /* AArch64 main loop */
1000 void cpu_loop(CPUARMState
*env
)
1002 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
1004 target_siginfo_t info
;
1008 trapnr
= cpu_arm_exec(env
);
1013 env
->xregs
[0] = do_syscall(env
,
1023 case EXCP_INTERRUPT
:
1024 /* just indicate that signals should be handled asap */
1027 info
.si_signo
= TARGET_SIGILL
;
1029 info
.si_code
= TARGET_ILL_ILLOPN
;
1030 info
._sifields
._sigfault
._addr
= env
->pc
;
1031 queue_signal(env
, info
.si_signo
, &info
);
1034 if (!do_strex_a64(env
)) {
1037 /* fall through for segv */
1038 case EXCP_PREFETCH_ABORT
:
1039 case EXCP_DATA_ABORT
:
1040 info
.si_signo
= TARGET_SIGSEGV
;
1042 /* XXX: check env->error_code */
1043 info
.si_code
= TARGET_SEGV_MAPERR
;
1044 info
._sifields
._sigfault
._addr
= env
->exception
.vaddress
;
1045 queue_signal(env
, info
.si_signo
, &info
);
1049 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1051 info
.si_signo
= sig
;
1053 info
.si_code
= TARGET_TRAP_BRKPT
;
1054 queue_signal(env
, info
.si_signo
, &info
);
1058 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n",
1060 cpu_dump_state(cs
, stderr
, fprintf
, 0);
1063 process_pending_signals(env
);
1064 /* Exception return on AArch64 always clears the exclusive monitor,
1065 * so any return to running guest code implies this.
1066 * A strex (successful or otherwise) also clears the monitor, so
1067 * we don't need to specialcase EXCP_STREX.
1069 env
->exclusive_addr
= -1;
1072 #endif /* ndef TARGET_ABI32 */
1076 #ifdef TARGET_UNICORE32
1078 void cpu_loop(CPUUniCore32State
*env
)
1080 CPUState
*cs
= CPU(uc32_env_get_cpu(env
));
1082 unsigned int n
, insn
;
1083 target_siginfo_t info
;
1087 trapnr
= uc32_cpu_exec(env
);
1090 case UC32_EXCP_PRIV
:
1093 get_user_u32(insn
, env
->regs
[31] - 4);
1094 n
= insn
& 0xffffff;
1096 if (n
>= UC32_SYSCALL_BASE
) {
1098 n
-= UC32_SYSCALL_BASE
;
1099 if (n
== UC32_SYSCALL_NR_set_tls
) {
1100 cpu_set_tls(env
, env
->regs
[0]);
1103 env
->regs
[0] = do_syscall(env
,
1118 case UC32_EXCP_DTRAP
:
1119 case UC32_EXCP_ITRAP
:
1120 info
.si_signo
= TARGET_SIGSEGV
;
1122 /* XXX: check env->error_code */
1123 info
.si_code
= TARGET_SEGV_MAPERR
;
1124 info
._sifields
._sigfault
._addr
= env
->cp0
.c4_faultaddr
;
1125 queue_signal(env
, info
.si_signo
, &info
);
1127 case EXCP_INTERRUPT
:
1128 /* just indicate that signals should be handled asap */
1134 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1136 info
.si_signo
= sig
;
1138 info
.si_code
= TARGET_TRAP_BRKPT
;
1139 queue_signal(env
, info
.si_signo
, &info
);
1146 process_pending_signals(env
);
1150 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
1151 cpu_dump_state(cs
, stderr
, fprintf
, 0);
1157 #define SPARC64_STACK_BIAS 2047
1161 /* WARNING: dealing with register windows _is_ complicated. More info
1162 can be found at http://www.sics.se/~psm/sparcstack.html */
1163 static inline int get_reg_index(CPUSPARCState
*env
, int cwp
, int index
)
1165 index
= (index
+ cwp
* 16) % (16 * env
->nwindows
);
1166 /* wrap handling : if cwp is on the last window, then we use the
1167 registers 'after' the end */
1168 if (index
< 8 && env
->cwp
== env
->nwindows
- 1)
1169 index
+= 16 * env
->nwindows
;
1173 /* save the register window 'cwp1' */
1174 static inline void save_window_offset(CPUSPARCState
*env
, int cwp1
)
1179 sp_ptr
= env
->regbase
[get_reg_index(env
, cwp1
, 6)];
1180 #ifdef TARGET_SPARC64
1182 sp_ptr
+= SPARC64_STACK_BIAS
;
1184 #if defined(DEBUG_WIN)
1185 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx
" save_cwp=%d\n",
1188 for(i
= 0; i
< 16; i
++) {
1189 /* FIXME - what to do if put_user() fails? */
1190 put_user_ual(env
->regbase
[get_reg_index(env
, cwp1
, 8 + i
)], sp_ptr
);
1191 sp_ptr
+= sizeof(abi_ulong
);
1195 static void save_window(CPUSPARCState
*env
)
1197 #ifndef TARGET_SPARC64
1198 unsigned int new_wim
;
1199 new_wim
= ((env
->wim
>> 1) | (env
->wim
<< (env
->nwindows
- 1))) &
1200 ((1LL << env
->nwindows
) - 1);
1201 save_window_offset(env
, cpu_cwp_dec(env
, env
->cwp
- 2));
1204 save_window_offset(env
, cpu_cwp_dec(env
, env
->cwp
- 2));
1210 static void restore_window(CPUSPARCState
*env
)
1212 #ifndef TARGET_SPARC64
1213 unsigned int new_wim
;
1215 unsigned int i
, cwp1
;
1218 #ifndef TARGET_SPARC64
1219 new_wim
= ((env
->wim
<< 1) | (env
->wim
>> (env
->nwindows
- 1))) &
1220 ((1LL << env
->nwindows
) - 1);
1223 /* restore the invalid window */
1224 cwp1
= cpu_cwp_inc(env
, env
->cwp
+ 1);
1225 sp_ptr
= env
->regbase
[get_reg_index(env
, cwp1
, 6)];
1226 #ifdef TARGET_SPARC64
1228 sp_ptr
+= SPARC64_STACK_BIAS
;
1230 #if defined(DEBUG_WIN)
1231 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx
" load_cwp=%d\n",
1234 for(i
= 0; i
< 16; i
++) {
1235 /* FIXME - what to do if get_user() fails? */
1236 get_user_ual(env
->regbase
[get_reg_index(env
, cwp1
, 8 + i
)], sp_ptr
);
1237 sp_ptr
+= sizeof(abi_ulong
);
1239 #ifdef TARGET_SPARC64
1241 if (env
->cleanwin
< env
->nwindows
- 1)
1249 static void flush_windows(CPUSPARCState
*env
)
1255 /* if restore would invoke restore_window(), then we can stop */
1256 cwp1
= cpu_cwp_inc(env
, env
->cwp
+ offset
);
1257 #ifndef TARGET_SPARC64
1258 if (env
->wim
& (1 << cwp1
))
1261 if (env
->canrestore
== 0)
1266 save_window_offset(env
, cwp1
);
1269 cwp1
= cpu_cwp_inc(env
, env
->cwp
+ 1);
1270 #ifndef TARGET_SPARC64
1271 /* set wim so that restore will reload the registers */
1272 env
->wim
= 1 << cwp1
;
1274 #if defined(DEBUG_WIN)
1275 printf("flush_windows: nb=%d\n", offset
- 1);
1279 void cpu_loop (CPUSPARCState
*env
)
1281 CPUState
*cs
= CPU(sparc_env_get_cpu(env
));
1284 target_siginfo_t info
;
1288 trapnr
= cpu_sparc_exec (env
);
1291 /* Compute PSR before exposing state. */
1292 if (env
->cc_op
!= CC_OP_FLAGS
) {
1297 #ifndef TARGET_SPARC64
1304 ret
= do_syscall (env
, env
->gregs
[1],
1305 env
->regwptr
[0], env
->regwptr
[1],
1306 env
->regwptr
[2], env
->regwptr
[3],
1307 env
->regwptr
[4], env
->regwptr
[5],
1309 if ((abi_ulong
)ret
>= (abi_ulong
)(-515)) {
1310 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1311 env
->xcc
|= PSR_CARRY
;
1313 env
->psr
|= PSR_CARRY
;
1317 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1318 env
->xcc
&= ~PSR_CARRY
;
1320 env
->psr
&= ~PSR_CARRY
;
1323 env
->regwptr
[0] = ret
;
1324 /* next instruction */
1326 env
->npc
= env
->npc
+ 4;
1328 case 0x83: /* flush windows */
1333 /* next instruction */
1335 env
->npc
= env
->npc
+ 4;
1337 #ifndef TARGET_SPARC64
1338 case TT_WIN_OVF
: /* window overflow */
1341 case TT_WIN_UNF
: /* window underflow */
1342 restore_window(env
);
1347 info
.si_signo
= TARGET_SIGSEGV
;
1349 /* XXX: check env->error_code */
1350 info
.si_code
= TARGET_SEGV_MAPERR
;
1351 info
._sifields
._sigfault
._addr
= env
->mmuregs
[4];
1352 queue_signal(env
, info
.si_signo
, &info
);
1356 case TT_SPILL
: /* window overflow */
1359 case TT_FILL
: /* window underflow */
1360 restore_window(env
);
1365 info
.si_signo
= TARGET_SIGSEGV
;
1367 /* XXX: check env->error_code */
1368 info
.si_code
= TARGET_SEGV_MAPERR
;
1369 if (trapnr
== TT_DFAULT
)
1370 info
._sifields
._sigfault
._addr
= env
->dmmuregs
[4];
1372 info
._sifields
._sigfault
._addr
= cpu_tsptr(env
)->tpc
;
1373 queue_signal(env
, info
.si_signo
, &info
);
1376 #ifndef TARGET_ABI32
1379 sparc64_get_context(env
);
1383 sparc64_set_context(env
);
1387 case EXCP_INTERRUPT
:
1388 /* just indicate that signals should be handled asap */
1392 info
.si_signo
= TARGET_SIGILL
;
1394 info
.si_code
= TARGET_ILL_ILLOPC
;
1395 info
._sifields
._sigfault
._addr
= env
->pc
;
1396 queue_signal(env
, info
.si_signo
, &info
);
1403 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1406 info
.si_signo
= sig
;
1408 info
.si_code
= TARGET_TRAP_BRKPT
;
1409 queue_signal(env
, info
.si_signo
, &info
);
1414 printf ("Unhandled trap: 0x%x\n", trapnr
);
1415 cpu_dump_state(cs
, stderr
, fprintf
, 0);
1418 process_pending_signals (env
);
1425 static inline uint64_t cpu_ppc_get_tb(CPUPPCState
*env
)
1431 uint64_t cpu_ppc_load_tbl(CPUPPCState
*env
)
1433 return cpu_ppc_get_tb(env
);
1436 uint32_t cpu_ppc_load_tbu(CPUPPCState
*env
)
1438 return cpu_ppc_get_tb(env
) >> 32;
1441 uint64_t cpu_ppc_load_atbl(CPUPPCState
*env
)
1443 return cpu_ppc_get_tb(env
);
1446 uint32_t cpu_ppc_load_atbu(CPUPPCState
*env
)
1448 return cpu_ppc_get_tb(env
) >> 32;
1451 uint32_t cpu_ppc601_load_rtcu(CPUPPCState
*env
)
1452 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1454 uint32_t cpu_ppc601_load_rtcl(CPUPPCState
*env
)
1456 return cpu_ppc_load_tbl(env
) & 0x3FFFFF80;
1459 /* XXX: to be fixed */
1460 int ppc_dcr_read (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t *valp
)
1465 int ppc_dcr_write (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t val
)
1470 #define EXCP_DUMP(env, fmt, ...) \
1472 CPUState *cs = ENV_GET_CPU(env); \
1473 fprintf(stderr, fmt , ## __VA_ARGS__); \
1474 cpu_dump_state(cs, stderr, fprintf, 0); \
1475 qemu_log(fmt, ## __VA_ARGS__); \
1476 if (qemu_log_enabled()) { \
1477 log_cpu_state(cs, 0); \
1481 static int do_store_exclusive(CPUPPCState
*env
)
1484 target_ulong page_addr
;
1485 target_ulong val
, val2
__attribute__((unused
)) = 0;
1489 addr
= env
->reserve_ea
;
1490 page_addr
= addr
& TARGET_PAGE_MASK
;
1493 flags
= page_get_flags(page_addr
);
1494 if ((flags
& PAGE_READ
) == 0) {
1497 int reg
= env
->reserve_info
& 0x1f;
1498 int size
= env
->reserve_info
>> 5;
1501 if (addr
== env
->reserve_addr
) {
1503 case 1: segv
= get_user_u8(val
, addr
); break;
1504 case 2: segv
= get_user_u16(val
, addr
); break;
1505 case 4: segv
= get_user_u32(val
, addr
); break;
1506 #if defined(TARGET_PPC64)
1507 case 8: segv
= get_user_u64(val
, addr
); break;
1509 segv
= get_user_u64(val
, addr
);
1511 segv
= get_user_u64(val2
, addr
+ 8);
1518 if (!segv
&& val
== env
->reserve_val
) {
1519 val
= env
->gpr
[reg
];
1521 case 1: segv
= put_user_u8(val
, addr
); break;
1522 case 2: segv
= put_user_u16(val
, addr
); break;
1523 case 4: segv
= put_user_u32(val
, addr
); break;
1524 #if defined(TARGET_PPC64)
1525 case 8: segv
= put_user_u64(val
, addr
); break;
1527 if (val2
== env
->reserve_val2
) {
1530 val
= env
->gpr
[reg
+1];
1532 val2
= env
->gpr
[reg
+1];
1534 segv
= put_user_u64(val
, addr
);
1536 segv
= put_user_u64(val2
, addr
+ 8);
1549 env
->crf
[0] = (stored
<< 1) | xer_so
;
1550 env
->reserve_addr
= (target_ulong
)-1;
1560 void cpu_loop(CPUPPCState
*env
)
1562 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
1563 target_siginfo_t info
;
1569 trapnr
= cpu_ppc_exec(env
);
1572 case POWERPC_EXCP_NONE
:
1575 case POWERPC_EXCP_CRITICAL
: /* Critical input */
1576 cpu_abort(cs
, "Critical interrupt while in user mode. "
1579 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
1580 cpu_abort(cs
, "Machine check exception while in user mode. "
1583 case POWERPC_EXCP_DSI
: /* Data storage exception */
1584 EXCP_DUMP(env
, "Invalid data memory access: 0x" TARGET_FMT_lx
"\n",
1586 /* XXX: check this. Seems bugged */
1587 switch (env
->error_code
& 0xFF000000) {
1589 info
.si_signo
= TARGET_SIGSEGV
;
1591 info
.si_code
= TARGET_SEGV_MAPERR
;
1594 info
.si_signo
= TARGET_SIGILL
;
1596 info
.si_code
= TARGET_ILL_ILLADR
;
1599 info
.si_signo
= TARGET_SIGSEGV
;
1601 info
.si_code
= TARGET_SEGV_ACCERR
;
1604 /* Let's send a regular segfault... */
1605 EXCP_DUMP(env
, "Invalid segfault errno (%02x)\n",
1607 info
.si_signo
= TARGET_SIGSEGV
;
1609 info
.si_code
= TARGET_SEGV_MAPERR
;
1612 info
._sifields
._sigfault
._addr
= env
->nip
;
1613 queue_signal(env
, info
.si_signo
, &info
);
1615 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
1616 EXCP_DUMP(env
, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1617 "\n", env
->spr
[SPR_SRR0
]);
1618 /* XXX: check this */
1619 switch (env
->error_code
& 0xFF000000) {
1621 info
.si_signo
= TARGET_SIGSEGV
;
1623 info
.si_code
= TARGET_SEGV_MAPERR
;
1627 info
.si_signo
= TARGET_SIGSEGV
;
1629 info
.si_code
= TARGET_SEGV_ACCERR
;
1632 /* Let's send a regular segfault... */
1633 EXCP_DUMP(env
, "Invalid segfault errno (%02x)\n",
1635 info
.si_signo
= TARGET_SIGSEGV
;
1637 info
.si_code
= TARGET_SEGV_MAPERR
;
1640 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1641 queue_signal(env
, info
.si_signo
, &info
);
1643 case POWERPC_EXCP_EXTERNAL
: /* External input */
1644 cpu_abort(cs
, "External interrupt while in user mode. "
1647 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
1648 EXCP_DUMP(env
, "Unaligned memory access\n");
1649 /* XXX: check this */
1650 info
.si_signo
= TARGET_SIGBUS
;
1652 info
.si_code
= TARGET_BUS_ADRALN
;
1653 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1654 queue_signal(env
, info
.si_signo
, &info
);
1656 case POWERPC_EXCP_PROGRAM
: /* Program exception */
1657 /* XXX: check this */
1658 switch (env
->error_code
& ~0xF) {
1659 case POWERPC_EXCP_FP
:
1660 EXCP_DUMP(env
, "Floating point program exception\n");
1661 info
.si_signo
= TARGET_SIGFPE
;
1663 switch (env
->error_code
& 0xF) {
1664 case POWERPC_EXCP_FP_OX
:
1665 info
.si_code
= TARGET_FPE_FLTOVF
;
1667 case POWERPC_EXCP_FP_UX
:
1668 info
.si_code
= TARGET_FPE_FLTUND
;
1670 case POWERPC_EXCP_FP_ZX
:
1671 case POWERPC_EXCP_FP_VXZDZ
:
1672 info
.si_code
= TARGET_FPE_FLTDIV
;
1674 case POWERPC_EXCP_FP_XX
:
1675 info
.si_code
= TARGET_FPE_FLTRES
;
1677 case POWERPC_EXCP_FP_VXSOFT
:
1678 info
.si_code
= TARGET_FPE_FLTINV
;
1680 case POWERPC_EXCP_FP_VXSNAN
:
1681 case POWERPC_EXCP_FP_VXISI
:
1682 case POWERPC_EXCP_FP_VXIDI
:
1683 case POWERPC_EXCP_FP_VXIMZ
:
1684 case POWERPC_EXCP_FP_VXVC
:
1685 case POWERPC_EXCP_FP_VXSQRT
:
1686 case POWERPC_EXCP_FP_VXCVI
:
1687 info
.si_code
= TARGET_FPE_FLTSUB
;
1690 EXCP_DUMP(env
, "Unknown floating point exception (%02x)\n",
1695 case POWERPC_EXCP_INVAL
:
1696 EXCP_DUMP(env
, "Invalid instruction\n");
1697 info
.si_signo
= TARGET_SIGILL
;
1699 switch (env
->error_code
& 0xF) {
1700 case POWERPC_EXCP_INVAL_INVAL
:
1701 info
.si_code
= TARGET_ILL_ILLOPC
;
1703 case POWERPC_EXCP_INVAL_LSWX
:
1704 info
.si_code
= TARGET_ILL_ILLOPN
;
1706 case POWERPC_EXCP_INVAL_SPR
:
1707 info
.si_code
= TARGET_ILL_PRVREG
;
1709 case POWERPC_EXCP_INVAL_FP
:
1710 info
.si_code
= TARGET_ILL_COPROC
;
1713 EXCP_DUMP(env
, "Unknown invalid operation (%02x)\n",
1714 env
->error_code
& 0xF);
1715 info
.si_code
= TARGET_ILL_ILLADR
;
1719 case POWERPC_EXCP_PRIV
:
1720 EXCP_DUMP(env
, "Privilege violation\n");
1721 info
.si_signo
= TARGET_SIGILL
;
1723 switch (env
->error_code
& 0xF) {
1724 case POWERPC_EXCP_PRIV_OPC
:
1725 info
.si_code
= TARGET_ILL_PRVOPC
;
1727 case POWERPC_EXCP_PRIV_REG
:
1728 info
.si_code
= TARGET_ILL_PRVREG
;
1731 EXCP_DUMP(env
, "Unknown privilege violation (%02x)\n",
1732 env
->error_code
& 0xF);
1733 info
.si_code
= TARGET_ILL_PRVOPC
;
1737 case POWERPC_EXCP_TRAP
:
1738 cpu_abort(cs
, "Tried to call a TRAP\n");
1741 /* Should not happen ! */
1742 cpu_abort(cs
, "Unknown program exception (%02x)\n",
1746 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1747 queue_signal(env
, info
.si_signo
, &info
);
1749 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
1750 EXCP_DUMP(env
, "No floating point allowed\n");
1751 info
.si_signo
= TARGET_SIGILL
;
1753 info
.si_code
= TARGET_ILL_COPROC
;
1754 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1755 queue_signal(env
, info
.si_signo
, &info
);
1757 case POWERPC_EXCP_SYSCALL
: /* System call exception */
1758 cpu_abort(cs
, "Syscall exception while in user mode. "
1761 case POWERPC_EXCP_APU
: /* Auxiliary processor unavailable */
1762 EXCP_DUMP(env
, "No APU instruction allowed\n");
1763 info
.si_signo
= TARGET_SIGILL
;
1765 info
.si_code
= TARGET_ILL_COPROC
;
1766 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1767 queue_signal(env
, info
.si_signo
, &info
);
1769 case POWERPC_EXCP_DECR
: /* Decrementer exception */
1770 cpu_abort(cs
, "Decrementer interrupt while in user mode. "
1773 case POWERPC_EXCP_FIT
: /* Fixed-interval timer interrupt */
1774 cpu_abort(cs
, "Fix interval timer interrupt while in user mode. "
1777 case POWERPC_EXCP_WDT
: /* Watchdog timer interrupt */
1778 cpu_abort(cs
, "Watchdog timer interrupt while in user mode. "
1781 case POWERPC_EXCP_DTLB
: /* Data TLB error */
1782 cpu_abort(cs
, "Data TLB exception while in user mode. "
1785 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
1786 cpu_abort(cs
, "Instruction TLB exception while in user mode. "
1789 case POWERPC_EXCP_SPEU
: /* SPE/embedded floating-point unavail. */
1790 EXCP_DUMP(env
, "No SPE/floating-point instruction allowed\n");
1791 info
.si_signo
= TARGET_SIGILL
;
1793 info
.si_code
= TARGET_ILL_COPROC
;
1794 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1795 queue_signal(env
, info
.si_signo
, &info
);
1797 case POWERPC_EXCP_EFPDI
: /* Embedded floating-point data IRQ */
1798 cpu_abort(cs
, "Embedded floating-point data IRQ not handled\n");
1800 case POWERPC_EXCP_EFPRI
: /* Embedded floating-point round IRQ */
1801 cpu_abort(cs
, "Embedded floating-point round IRQ not handled\n");
1803 case POWERPC_EXCP_EPERFM
: /* Embedded performance monitor IRQ */
1804 cpu_abort(cs
, "Performance monitor exception not handled\n");
1806 case POWERPC_EXCP_DOORI
: /* Embedded doorbell interrupt */
1807 cpu_abort(cs
, "Doorbell interrupt while in user mode. "
1810 case POWERPC_EXCP_DOORCI
: /* Embedded doorbell critical interrupt */
1811 cpu_abort(cs
, "Doorbell critical interrupt while in user mode. "
1814 case POWERPC_EXCP_RESET
: /* System reset exception */
1815 cpu_abort(cs
, "Reset interrupt while in user mode. "
1818 case POWERPC_EXCP_DSEG
: /* Data segment exception */
1819 cpu_abort(cs
, "Data segment exception while in user mode. "
1822 case POWERPC_EXCP_ISEG
: /* Instruction segment exception */
1823 cpu_abort(cs
, "Instruction segment exception "
1824 "while in user mode. Aborting\n");
1826 /* PowerPC 64 with hypervisor mode support */
1827 case POWERPC_EXCP_HDECR
: /* Hypervisor decrementer exception */
1828 cpu_abort(cs
, "Hypervisor decrementer interrupt "
1829 "while in user mode. Aborting\n");
1831 case POWERPC_EXCP_TRACE
: /* Trace exception */
1833 * we use this exception to emulate step-by-step execution mode.
1836 /* PowerPC 64 with hypervisor mode support */
1837 case POWERPC_EXCP_HDSI
: /* Hypervisor data storage exception */
1838 cpu_abort(cs
, "Hypervisor data storage exception "
1839 "while in user mode. Aborting\n");
1841 case POWERPC_EXCP_HISI
: /* Hypervisor instruction storage excp */
1842 cpu_abort(cs
, "Hypervisor instruction storage exception "
1843 "while in user mode. Aborting\n");
1845 case POWERPC_EXCP_HDSEG
: /* Hypervisor data segment exception */
1846 cpu_abort(cs
, "Hypervisor data segment exception "
1847 "while in user mode. Aborting\n");
1849 case POWERPC_EXCP_HISEG
: /* Hypervisor instruction segment excp */
1850 cpu_abort(cs
, "Hypervisor instruction segment exception "
1851 "while in user mode. Aborting\n");
1853 case POWERPC_EXCP_VPU
: /* Vector unavailable exception */
1854 EXCP_DUMP(env
, "No Altivec instructions allowed\n");
1855 info
.si_signo
= TARGET_SIGILL
;
1857 info
.si_code
= TARGET_ILL_COPROC
;
1858 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1859 queue_signal(env
, info
.si_signo
, &info
);
1861 case POWERPC_EXCP_PIT
: /* Programmable interval timer IRQ */
1862 cpu_abort(cs
, "Programmable interval timer interrupt "
1863 "while in user mode. Aborting\n");
1865 case POWERPC_EXCP_IO
: /* IO error exception */
1866 cpu_abort(cs
, "IO error exception while in user mode. "
1869 case POWERPC_EXCP_RUNM
: /* Run mode exception */
1870 cpu_abort(cs
, "Run mode exception while in user mode. "
1873 case POWERPC_EXCP_EMUL
: /* Emulation trap exception */
1874 cpu_abort(cs
, "Emulation trap exception not handled\n");
1876 case POWERPC_EXCP_IFTLB
: /* Instruction fetch TLB error */
1877 cpu_abort(cs
, "Instruction fetch TLB exception "
1878 "while in user-mode. Aborting");
1880 case POWERPC_EXCP_DLTLB
: /* Data load TLB miss */
1881 cpu_abort(cs
, "Data load TLB exception while in user-mode. "
1884 case POWERPC_EXCP_DSTLB
: /* Data store TLB miss */
1885 cpu_abort(cs
, "Data store TLB exception while in user-mode. "
1888 case POWERPC_EXCP_FPA
: /* Floating-point assist exception */
1889 cpu_abort(cs
, "Floating-point assist exception not handled\n");
1891 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
1892 cpu_abort(cs
, "Instruction address breakpoint exception "
1895 case POWERPC_EXCP_SMI
: /* System management interrupt */
1896 cpu_abort(cs
, "System management interrupt while in user mode. "
1899 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
1900 cpu_abort(cs
, "Thermal interrupt interrupt while in user mode. "
1903 case POWERPC_EXCP_PERFM
: /* Embedded performance monitor IRQ */
1904 cpu_abort(cs
, "Performance monitor exception not handled\n");
1906 case POWERPC_EXCP_VPUA
: /* Vector assist exception */
1907 cpu_abort(cs
, "Vector assist exception not handled\n");
1909 case POWERPC_EXCP_SOFTP
: /* Soft patch exception */
1910 cpu_abort(cs
, "Soft patch exception not handled\n");
1912 case POWERPC_EXCP_MAINT
: /* Maintenance exception */
1913 cpu_abort(cs
, "Maintenance exception while in user mode. "
1916 case POWERPC_EXCP_STOP
: /* stop translation */
1917 /* We did invalidate the instruction cache. Go on */
1919 case POWERPC_EXCP_BRANCH
: /* branch instruction: */
1920 /* We just stopped because of a branch. Go on */
1922 case POWERPC_EXCP_SYSCALL_USER
:
1923 /* system call in user-mode emulation */
1925 * PPC ABI uses overflow flag in cr0 to signal an error
1928 env
->crf
[0] &= ~0x1;
1929 ret
= do_syscall(env
, env
->gpr
[0], env
->gpr
[3], env
->gpr
[4],
1930 env
->gpr
[5], env
->gpr
[6], env
->gpr
[7],
1932 if (ret
== (target_ulong
)(-TARGET_QEMU_ESIGRETURN
)) {
1933 /* Returning from a successful sigreturn syscall.
1934 Avoid corrupting register state. */
1937 if (ret
> (target_ulong
)(-515)) {
1943 case POWERPC_EXCP_STCX
:
1944 if (do_store_exclusive(env
)) {
1945 info
.si_signo
= TARGET_SIGSEGV
;
1947 info
.si_code
= TARGET_SEGV_MAPERR
;
1948 info
._sifields
._sigfault
._addr
= env
->nip
;
1949 queue_signal(env
, info
.si_signo
, &info
);
1956 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1958 info
.si_signo
= sig
;
1960 info
.si_code
= TARGET_TRAP_BRKPT
;
1961 queue_signal(env
, info
.si_signo
, &info
);
1965 case EXCP_INTERRUPT
:
1966 /* just indicate that signals should be handled asap */
1969 cpu_abort(cs
, "Unknown exception 0x%d. Aborting\n", trapnr
);
1972 process_pending_signals(env
);
1979 # ifdef TARGET_ABI_MIPSO32
1980 # define MIPS_SYS(name, args) args,
1981 static const uint8_t mips_syscall_args
[] = {
1982 MIPS_SYS(sys_syscall
, 8) /* 4000 */
1983 MIPS_SYS(sys_exit
, 1)
1984 MIPS_SYS(sys_fork
, 0)
1985 MIPS_SYS(sys_read
, 3)
1986 MIPS_SYS(sys_write
, 3)
1987 MIPS_SYS(sys_open
, 3) /* 4005 */
1988 MIPS_SYS(sys_close
, 1)
1989 MIPS_SYS(sys_waitpid
, 3)
1990 MIPS_SYS(sys_creat
, 2)
1991 MIPS_SYS(sys_link
, 2)
1992 MIPS_SYS(sys_unlink
, 1) /* 4010 */
1993 MIPS_SYS(sys_execve
, 0)
1994 MIPS_SYS(sys_chdir
, 1)
1995 MIPS_SYS(sys_time
, 1)
1996 MIPS_SYS(sys_mknod
, 3)
1997 MIPS_SYS(sys_chmod
, 2) /* 4015 */
1998 MIPS_SYS(sys_lchown
, 3)
1999 MIPS_SYS(sys_ni_syscall
, 0)
2000 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_stat */
2001 MIPS_SYS(sys_lseek
, 3)
2002 MIPS_SYS(sys_getpid
, 0) /* 4020 */
2003 MIPS_SYS(sys_mount
, 5)
2004 MIPS_SYS(sys_umount
, 1)
2005 MIPS_SYS(sys_setuid
, 1)
2006 MIPS_SYS(sys_getuid
, 0)
2007 MIPS_SYS(sys_stime
, 1) /* 4025 */
2008 MIPS_SYS(sys_ptrace
, 4)
2009 MIPS_SYS(sys_alarm
, 1)
2010 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_fstat */
2011 MIPS_SYS(sys_pause
, 0)
2012 MIPS_SYS(sys_utime
, 2) /* 4030 */
2013 MIPS_SYS(sys_ni_syscall
, 0)
2014 MIPS_SYS(sys_ni_syscall
, 0)
2015 MIPS_SYS(sys_access
, 2)
2016 MIPS_SYS(sys_nice
, 1)
2017 MIPS_SYS(sys_ni_syscall
, 0) /* 4035 */
2018 MIPS_SYS(sys_sync
, 0)
2019 MIPS_SYS(sys_kill
, 2)
2020 MIPS_SYS(sys_rename
, 2)
2021 MIPS_SYS(sys_mkdir
, 2)
2022 MIPS_SYS(sys_rmdir
, 1) /* 4040 */
2023 MIPS_SYS(sys_dup
, 1)
2024 MIPS_SYS(sys_pipe
, 0)
2025 MIPS_SYS(sys_times
, 1)
2026 MIPS_SYS(sys_ni_syscall
, 0)
2027 MIPS_SYS(sys_brk
, 1) /* 4045 */
2028 MIPS_SYS(sys_setgid
, 1)
2029 MIPS_SYS(sys_getgid
, 0)
2030 MIPS_SYS(sys_ni_syscall
, 0) /* was signal(2) */
2031 MIPS_SYS(sys_geteuid
, 0)
2032 MIPS_SYS(sys_getegid
, 0) /* 4050 */
2033 MIPS_SYS(sys_acct
, 0)
2034 MIPS_SYS(sys_umount2
, 2)
2035 MIPS_SYS(sys_ni_syscall
, 0)
2036 MIPS_SYS(sys_ioctl
, 3)
2037 MIPS_SYS(sys_fcntl
, 3) /* 4055 */
2038 MIPS_SYS(sys_ni_syscall
, 2)
2039 MIPS_SYS(sys_setpgid
, 2)
2040 MIPS_SYS(sys_ni_syscall
, 0)
2041 MIPS_SYS(sys_olduname
, 1)
2042 MIPS_SYS(sys_umask
, 1) /* 4060 */
2043 MIPS_SYS(sys_chroot
, 1)
2044 MIPS_SYS(sys_ustat
, 2)
2045 MIPS_SYS(sys_dup2
, 2)
2046 MIPS_SYS(sys_getppid
, 0)
2047 MIPS_SYS(sys_getpgrp
, 0) /* 4065 */
2048 MIPS_SYS(sys_setsid
, 0)
2049 MIPS_SYS(sys_sigaction
, 3)
2050 MIPS_SYS(sys_sgetmask
, 0)
2051 MIPS_SYS(sys_ssetmask
, 1)
2052 MIPS_SYS(sys_setreuid
, 2) /* 4070 */
2053 MIPS_SYS(sys_setregid
, 2)
2054 MIPS_SYS(sys_sigsuspend
, 0)
2055 MIPS_SYS(sys_sigpending
, 1)
2056 MIPS_SYS(sys_sethostname
, 2)
2057 MIPS_SYS(sys_setrlimit
, 2) /* 4075 */
2058 MIPS_SYS(sys_getrlimit
, 2)
2059 MIPS_SYS(sys_getrusage
, 2)
2060 MIPS_SYS(sys_gettimeofday
, 2)
2061 MIPS_SYS(sys_settimeofday
, 2)
2062 MIPS_SYS(sys_getgroups
, 2) /* 4080 */
2063 MIPS_SYS(sys_setgroups
, 2)
2064 MIPS_SYS(sys_ni_syscall
, 0) /* old_select */
2065 MIPS_SYS(sys_symlink
, 2)
2066 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_lstat */
2067 MIPS_SYS(sys_readlink
, 3) /* 4085 */
2068 MIPS_SYS(sys_uselib
, 1)
2069 MIPS_SYS(sys_swapon
, 2)
2070 MIPS_SYS(sys_reboot
, 3)
2071 MIPS_SYS(old_readdir
, 3)
2072 MIPS_SYS(old_mmap
, 6) /* 4090 */
2073 MIPS_SYS(sys_munmap
, 2)
2074 MIPS_SYS(sys_truncate
, 2)
2075 MIPS_SYS(sys_ftruncate
, 2)
2076 MIPS_SYS(sys_fchmod
, 2)
2077 MIPS_SYS(sys_fchown
, 3) /* 4095 */
2078 MIPS_SYS(sys_getpriority
, 2)
2079 MIPS_SYS(sys_setpriority
, 3)
2080 MIPS_SYS(sys_ni_syscall
, 0)
2081 MIPS_SYS(sys_statfs
, 2)
2082 MIPS_SYS(sys_fstatfs
, 2) /* 4100 */
2083 MIPS_SYS(sys_ni_syscall
, 0) /* was ioperm(2) */
2084 MIPS_SYS(sys_socketcall
, 2)
2085 MIPS_SYS(sys_syslog
, 3)
2086 MIPS_SYS(sys_setitimer
, 3)
2087 MIPS_SYS(sys_getitimer
, 2) /* 4105 */
2088 MIPS_SYS(sys_newstat
, 2)
2089 MIPS_SYS(sys_newlstat
, 2)
2090 MIPS_SYS(sys_newfstat
, 2)
2091 MIPS_SYS(sys_uname
, 1)
2092 MIPS_SYS(sys_ni_syscall
, 0) /* 4110 was iopl(2) */
2093 MIPS_SYS(sys_vhangup
, 0)
2094 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_idle() */
2095 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_vm86 */
2096 MIPS_SYS(sys_wait4
, 4)
2097 MIPS_SYS(sys_swapoff
, 1) /* 4115 */
2098 MIPS_SYS(sys_sysinfo
, 1)
2099 MIPS_SYS(sys_ipc
, 6)
2100 MIPS_SYS(sys_fsync
, 1)
2101 MIPS_SYS(sys_sigreturn
, 0)
2102 MIPS_SYS(sys_clone
, 6) /* 4120 */
2103 MIPS_SYS(sys_setdomainname
, 2)
2104 MIPS_SYS(sys_newuname
, 1)
2105 MIPS_SYS(sys_ni_syscall
, 0) /* sys_modify_ldt */
2106 MIPS_SYS(sys_adjtimex
, 1)
2107 MIPS_SYS(sys_mprotect
, 3) /* 4125 */
2108 MIPS_SYS(sys_sigprocmask
, 3)
2109 MIPS_SYS(sys_ni_syscall
, 0) /* was create_module */
2110 MIPS_SYS(sys_init_module
, 5)
2111 MIPS_SYS(sys_delete_module
, 1)
2112 MIPS_SYS(sys_ni_syscall
, 0) /* 4130 was get_kernel_syms */
2113 MIPS_SYS(sys_quotactl
, 0)
2114 MIPS_SYS(sys_getpgid
, 1)
2115 MIPS_SYS(sys_fchdir
, 1)
2116 MIPS_SYS(sys_bdflush
, 2)
2117 MIPS_SYS(sys_sysfs
, 3) /* 4135 */
2118 MIPS_SYS(sys_personality
, 1)
2119 MIPS_SYS(sys_ni_syscall
, 0) /* for afs_syscall */
2120 MIPS_SYS(sys_setfsuid
, 1)
2121 MIPS_SYS(sys_setfsgid
, 1)
2122 MIPS_SYS(sys_llseek
, 5) /* 4140 */
2123 MIPS_SYS(sys_getdents
, 3)
2124 MIPS_SYS(sys_select
, 5)
2125 MIPS_SYS(sys_flock
, 2)
2126 MIPS_SYS(sys_msync
, 3)
2127 MIPS_SYS(sys_readv
, 3) /* 4145 */
2128 MIPS_SYS(sys_writev
, 3)
2129 MIPS_SYS(sys_cacheflush
, 3)
2130 MIPS_SYS(sys_cachectl
, 3)
2131 MIPS_SYS(sys_sysmips
, 4)
2132 MIPS_SYS(sys_ni_syscall
, 0) /* 4150 */
2133 MIPS_SYS(sys_getsid
, 1)
2134 MIPS_SYS(sys_fdatasync
, 0)
2135 MIPS_SYS(sys_sysctl
, 1)
2136 MIPS_SYS(sys_mlock
, 2)
2137 MIPS_SYS(sys_munlock
, 2) /* 4155 */
2138 MIPS_SYS(sys_mlockall
, 1)
2139 MIPS_SYS(sys_munlockall
, 0)
2140 MIPS_SYS(sys_sched_setparam
, 2)
2141 MIPS_SYS(sys_sched_getparam
, 2)
2142 MIPS_SYS(sys_sched_setscheduler
, 3) /* 4160 */
2143 MIPS_SYS(sys_sched_getscheduler
, 1)
2144 MIPS_SYS(sys_sched_yield
, 0)
2145 MIPS_SYS(sys_sched_get_priority_max
, 1)
2146 MIPS_SYS(sys_sched_get_priority_min
, 1)
2147 MIPS_SYS(sys_sched_rr_get_interval
, 2) /* 4165 */
2148 MIPS_SYS(sys_nanosleep
, 2)
2149 MIPS_SYS(sys_mremap
, 5)
2150 MIPS_SYS(sys_accept
, 3)
2151 MIPS_SYS(sys_bind
, 3)
2152 MIPS_SYS(sys_connect
, 3) /* 4170 */
2153 MIPS_SYS(sys_getpeername
, 3)
2154 MIPS_SYS(sys_getsockname
, 3)
2155 MIPS_SYS(sys_getsockopt
, 5)
2156 MIPS_SYS(sys_listen
, 2)
2157 MIPS_SYS(sys_recv
, 4) /* 4175 */
2158 MIPS_SYS(sys_recvfrom
, 6)
2159 MIPS_SYS(sys_recvmsg
, 3)
2160 MIPS_SYS(sys_send
, 4)
2161 MIPS_SYS(sys_sendmsg
, 3)
2162 MIPS_SYS(sys_sendto
, 6) /* 4180 */
2163 MIPS_SYS(sys_setsockopt
, 5)
2164 MIPS_SYS(sys_shutdown
, 2)
2165 MIPS_SYS(sys_socket
, 3)
2166 MIPS_SYS(sys_socketpair
, 4)
2167 MIPS_SYS(sys_setresuid
, 3) /* 4185 */
2168 MIPS_SYS(sys_getresuid
, 3)
2169 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_query_module */
2170 MIPS_SYS(sys_poll
, 3)
2171 MIPS_SYS(sys_nfsservctl
, 3)
2172 MIPS_SYS(sys_setresgid
, 3) /* 4190 */
2173 MIPS_SYS(sys_getresgid
, 3)
2174 MIPS_SYS(sys_prctl
, 5)
2175 MIPS_SYS(sys_rt_sigreturn
, 0)
2176 MIPS_SYS(sys_rt_sigaction
, 4)
2177 MIPS_SYS(sys_rt_sigprocmask
, 4) /* 4195 */
2178 MIPS_SYS(sys_rt_sigpending
, 2)
2179 MIPS_SYS(sys_rt_sigtimedwait
, 4)
2180 MIPS_SYS(sys_rt_sigqueueinfo
, 3)
2181 MIPS_SYS(sys_rt_sigsuspend
, 0)
2182 MIPS_SYS(sys_pread64
, 6) /* 4200 */
2183 MIPS_SYS(sys_pwrite64
, 6)
2184 MIPS_SYS(sys_chown
, 3)
2185 MIPS_SYS(sys_getcwd
, 2)
2186 MIPS_SYS(sys_capget
, 2)
2187 MIPS_SYS(sys_capset
, 2) /* 4205 */
2188 MIPS_SYS(sys_sigaltstack
, 2)
2189 MIPS_SYS(sys_sendfile
, 4)
2190 MIPS_SYS(sys_ni_syscall
, 0)
2191 MIPS_SYS(sys_ni_syscall
, 0)
2192 MIPS_SYS(sys_mmap2
, 6) /* 4210 */
2193 MIPS_SYS(sys_truncate64
, 4)
2194 MIPS_SYS(sys_ftruncate64
, 4)
2195 MIPS_SYS(sys_stat64
, 2)
2196 MIPS_SYS(sys_lstat64
, 2)
2197 MIPS_SYS(sys_fstat64
, 2) /* 4215 */
2198 MIPS_SYS(sys_pivot_root
, 2)
2199 MIPS_SYS(sys_mincore
, 3)
2200 MIPS_SYS(sys_madvise
, 3)
2201 MIPS_SYS(sys_getdents64
, 3)
2202 MIPS_SYS(sys_fcntl64
, 3) /* 4220 */
2203 MIPS_SYS(sys_ni_syscall
, 0)
2204 MIPS_SYS(sys_gettid
, 0)
2205 MIPS_SYS(sys_readahead
, 5)
2206 MIPS_SYS(sys_setxattr
, 5)
2207 MIPS_SYS(sys_lsetxattr
, 5) /* 4225 */
2208 MIPS_SYS(sys_fsetxattr
, 5)
2209 MIPS_SYS(sys_getxattr
, 4)
2210 MIPS_SYS(sys_lgetxattr
, 4)
2211 MIPS_SYS(sys_fgetxattr
, 4)
2212 MIPS_SYS(sys_listxattr
, 3) /* 4230 */
2213 MIPS_SYS(sys_llistxattr
, 3)
2214 MIPS_SYS(sys_flistxattr
, 3)
2215 MIPS_SYS(sys_removexattr
, 2)
2216 MIPS_SYS(sys_lremovexattr
, 2)
2217 MIPS_SYS(sys_fremovexattr
, 2) /* 4235 */
2218 MIPS_SYS(sys_tkill
, 2)
2219 MIPS_SYS(sys_sendfile64
, 5)
2220 MIPS_SYS(sys_futex
, 6)
2221 MIPS_SYS(sys_sched_setaffinity
, 3)
2222 MIPS_SYS(sys_sched_getaffinity
, 3) /* 4240 */
2223 MIPS_SYS(sys_io_setup
, 2)
2224 MIPS_SYS(sys_io_destroy
, 1)
2225 MIPS_SYS(sys_io_getevents
, 5)
2226 MIPS_SYS(sys_io_submit
, 3)
2227 MIPS_SYS(sys_io_cancel
, 3) /* 4245 */
2228 MIPS_SYS(sys_exit_group
, 1)
2229 MIPS_SYS(sys_lookup_dcookie
, 3)
2230 MIPS_SYS(sys_epoll_create
, 1)
2231 MIPS_SYS(sys_epoll_ctl
, 4)
2232 MIPS_SYS(sys_epoll_wait
, 3) /* 4250 */
2233 MIPS_SYS(sys_remap_file_pages
, 5)
2234 MIPS_SYS(sys_set_tid_address
, 1)
2235 MIPS_SYS(sys_restart_syscall
, 0)
2236 MIPS_SYS(sys_fadvise64_64
, 7)
2237 MIPS_SYS(sys_statfs64
, 3) /* 4255 */
2238 MIPS_SYS(sys_fstatfs64
, 2)
2239 MIPS_SYS(sys_timer_create
, 3)
2240 MIPS_SYS(sys_timer_settime
, 4)
2241 MIPS_SYS(sys_timer_gettime
, 2)
2242 MIPS_SYS(sys_timer_getoverrun
, 1) /* 4260 */
2243 MIPS_SYS(sys_timer_delete
, 1)
2244 MIPS_SYS(sys_clock_settime
, 2)
2245 MIPS_SYS(sys_clock_gettime
, 2)
2246 MIPS_SYS(sys_clock_getres
, 2)
2247 MIPS_SYS(sys_clock_nanosleep
, 4) /* 4265 */
2248 MIPS_SYS(sys_tgkill
, 3)
2249 MIPS_SYS(sys_utimes
, 2)
2250 MIPS_SYS(sys_mbind
, 4)
2251 MIPS_SYS(sys_ni_syscall
, 0) /* sys_get_mempolicy */
2252 MIPS_SYS(sys_ni_syscall
, 0) /* 4270 sys_set_mempolicy */
2253 MIPS_SYS(sys_mq_open
, 4)
2254 MIPS_SYS(sys_mq_unlink
, 1)
2255 MIPS_SYS(sys_mq_timedsend
, 5)
2256 MIPS_SYS(sys_mq_timedreceive
, 5)
2257 MIPS_SYS(sys_mq_notify
, 2) /* 4275 */
2258 MIPS_SYS(sys_mq_getsetattr
, 3)
2259 MIPS_SYS(sys_ni_syscall
, 0) /* sys_vserver */
2260 MIPS_SYS(sys_waitid
, 4)
2261 MIPS_SYS(sys_ni_syscall
, 0) /* available, was setaltroot */
2262 MIPS_SYS(sys_add_key
, 5)
2263 MIPS_SYS(sys_request_key
, 4)
2264 MIPS_SYS(sys_keyctl
, 5)
2265 MIPS_SYS(sys_set_thread_area
, 1)
2266 MIPS_SYS(sys_inotify_init
, 0)
2267 MIPS_SYS(sys_inotify_add_watch
, 3) /* 4285 */
2268 MIPS_SYS(sys_inotify_rm_watch
, 2)
2269 MIPS_SYS(sys_migrate_pages
, 4)
2270 MIPS_SYS(sys_openat
, 4)
2271 MIPS_SYS(sys_mkdirat
, 3)
2272 MIPS_SYS(sys_mknodat
, 4) /* 4290 */
2273 MIPS_SYS(sys_fchownat
, 5)
2274 MIPS_SYS(sys_futimesat
, 3)
2275 MIPS_SYS(sys_fstatat64
, 4)
2276 MIPS_SYS(sys_unlinkat
, 3)
2277 MIPS_SYS(sys_renameat
, 4) /* 4295 */
2278 MIPS_SYS(sys_linkat
, 5)
2279 MIPS_SYS(sys_symlinkat
, 3)
2280 MIPS_SYS(sys_readlinkat
, 4)
2281 MIPS_SYS(sys_fchmodat
, 3)
2282 MIPS_SYS(sys_faccessat
, 3) /* 4300 */
2283 MIPS_SYS(sys_pselect6
, 6)
2284 MIPS_SYS(sys_ppoll
, 5)
2285 MIPS_SYS(sys_unshare
, 1)
2286 MIPS_SYS(sys_splice
, 6)
2287 MIPS_SYS(sys_sync_file_range
, 7) /* 4305 */
2288 MIPS_SYS(sys_tee
, 4)
2289 MIPS_SYS(sys_vmsplice
, 4)
2290 MIPS_SYS(sys_move_pages
, 6)
2291 MIPS_SYS(sys_set_robust_list
, 2)
2292 MIPS_SYS(sys_get_robust_list
, 3) /* 4310 */
2293 MIPS_SYS(sys_kexec_load
, 4)
2294 MIPS_SYS(sys_getcpu
, 3)
2295 MIPS_SYS(sys_epoll_pwait
, 6)
2296 MIPS_SYS(sys_ioprio_set
, 3)
2297 MIPS_SYS(sys_ioprio_get
, 2)
2298 MIPS_SYS(sys_utimensat
, 4)
2299 MIPS_SYS(sys_signalfd
, 3)
2300 MIPS_SYS(sys_ni_syscall
, 0) /* was timerfd */
2301 MIPS_SYS(sys_eventfd
, 1)
2302 MIPS_SYS(sys_fallocate
, 6) /* 4320 */
2303 MIPS_SYS(sys_timerfd_create
, 2)
2304 MIPS_SYS(sys_timerfd_gettime
, 2)
2305 MIPS_SYS(sys_timerfd_settime
, 4)
2306 MIPS_SYS(sys_signalfd4
, 4)
2307 MIPS_SYS(sys_eventfd2
, 2) /* 4325 */
2308 MIPS_SYS(sys_epoll_create1
, 1)
2309 MIPS_SYS(sys_dup3
, 3)
2310 MIPS_SYS(sys_pipe2
, 2)
2311 MIPS_SYS(sys_inotify_init1
, 1)
2312 MIPS_SYS(sys_preadv
, 6) /* 4330 */
2313 MIPS_SYS(sys_pwritev
, 6)
2314 MIPS_SYS(sys_rt_tgsigqueueinfo
, 4)
2315 MIPS_SYS(sys_perf_event_open
, 5)
2316 MIPS_SYS(sys_accept4
, 4)
2317 MIPS_SYS(sys_recvmmsg
, 5) /* 4335 */
2318 MIPS_SYS(sys_fanotify_init
, 2)
2319 MIPS_SYS(sys_fanotify_mark
, 6)
2320 MIPS_SYS(sys_prlimit64
, 4)
2321 MIPS_SYS(sys_name_to_handle_at
, 5)
2322 MIPS_SYS(sys_open_by_handle_at
, 3) /* 4340 */
2323 MIPS_SYS(sys_clock_adjtime
, 2)
2324 MIPS_SYS(sys_syncfs
, 1)
2329 static int do_store_exclusive(CPUMIPSState
*env
)
2332 target_ulong page_addr
;
2340 page_addr
= addr
& TARGET_PAGE_MASK
;
2343 flags
= page_get_flags(page_addr
);
2344 if ((flags
& PAGE_READ
) == 0) {
2347 reg
= env
->llreg
& 0x1f;
2348 d
= (env
->llreg
& 0x20) != 0;
2350 segv
= get_user_s64(val
, addr
);
2352 segv
= get_user_s32(val
, addr
);
2355 if (val
!= env
->llval
) {
2356 env
->active_tc
.gpr
[reg
] = 0;
2359 segv
= put_user_u64(env
->llnewval
, addr
);
2361 segv
= put_user_u32(env
->llnewval
, addr
);
2364 env
->active_tc
.gpr
[reg
] = 1;
2371 env
->active_tc
.PC
+= 4;
2384 static int do_break(CPUMIPSState
*env
, target_siginfo_t
*info
,
2392 info
->si_signo
= TARGET_SIGFPE
;
2394 info
->si_code
= (code
== BRK_OVERFLOW
) ? FPE_INTOVF
: FPE_INTDIV
;
2395 queue_signal(env
, info
->si_signo
, &*info
);
2399 info
->si_signo
= TARGET_SIGTRAP
;
2401 queue_signal(env
, info
->si_signo
, &*info
);
2409 void cpu_loop(CPUMIPSState
*env
)
2411 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2412 target_siginfo_t info
;
2415 # ifdef TARGET_ABI_MIPSO32
2416 unsigned int syscall_num
;
2421 trapnr
= cpu_mips_exec(env
);
2425 env
->active_tc
.PC
+= 4;
2426 # ifdef TARGET_ABI_MIPSO32
2427 syscall_num
= env
->active_tc
.gpr
[2] - 4000;
2428 if (syscall_num
>= sizeof(mips_syscall_args
)) {
2429 ret
= -TARGET_ENOSYS
;
2433 abi_ulong arg5
= 0, arg6
= 0, arg7
= 0, arg8
= 0;
2435 nb_args
= mips_syscall_args
[syscall_num
];
2436 sp_reg
= env
->active_tc
.gpr
[29];
2438 /* these arguments are taken from the stack */
2440 if ((ret
= get_user_ual(arg8
, sp_reg
+ 28)) != 0) {
2444 if ((ret
= get_user_ual(arg7
, sp_reg
+ 24)) != 0) {
2448 if ((ret
= get_user_ual(arg6
, sp_reg
+ 20)) != 0) {
2452 if ((ret
= get_user_ual(arg5
, sp_reg
+ 16)) != 0) {
2458 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
2459 env
->active_tc
.gpr
[4],
2460 env
->active_tc
.gpr
[5],
2461 env
->active_tc
.gpr
[6],
2462 env
->active_tc
.gpr
[7],
2463 arg5
, arg6
, arg7
, arg8
);
2467 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
2468 env
->active_tc
.gpr
[4], env
->active_tc
.gpr
[5],
2469 env
->active_tc
.gpr
[6], env
->active_tc
.gpr
[7],
2470 env
->active_tc
.gpr
[8], env
->active_tc
.gpr
[9],
2471 env
->active_tc
.gpr
[10], env
->active_tc
.gpr
[11]);
2473 if (ret
== -TARGET_QEMU_ESIGRETURN
) {
2474 /* Returning from a successful sigreturn syscall.
2475 Avoid clobbering register state. */
2478 if ((abi_ulong
)ret
>= (abi_ulong
)-1133) {
2479 env
->active_tc
.gpr
[7] = 1; /* error flag */
2482 env
->active_tc
.gpr
[7] = 0; /* error flag */
2484 env
->active_tc
.gpr
[2] = ret
;
2490 info
.si_signo
= TARGET_SIGSEGV
;
2492 /* XXX: check env->error_code */
2493 info
.si_code
= TARGET_SEGV_MAPERR
;
2494 info
._sifields
._sigfault
._addr
= env
->CP0_BadVAddr
;
2495 queue_signal(env
, info
.si_signo
, &info
);
2499 info
.si_signo
= TARGET_SIGILL
;
2502 queue_signal(env
, info
.si_signo
, &info
);
2504 case EXCP_INTERRUPT
:
2505 /* just indicate that signals should be handled asap */
2511 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2514 info
.si_signo
= sig
;
2516 info
.si_code
= TARGET_TRAP_BRKPT
;
2517 queue_signal(env
, info
.si_signo
, &info
);
2522 if (do_store_exclusive(env
)) {
2523 info
.si_signo
= TARGET_SIGSEGV
;
2525 info
.si_code
= TARGET_SEGV_MAPERR
;
2526 info
._sifields
._sigfault
._addr
= env
->active_tc
.PC
;
2527 queue_signal(env
, info
.si_signo
, &info
);
2531 info
.si_signo
= TARGET_SIGILL
;
2533 info
.si_code
= TARGET_ILL_ILLOPC
;
2534 queue_signal(env
, info
.si_signo
, &info
);
2536 /* The code below was inspired by the MIPS Linux kernel trap
2537 * handling code in arch/mips/kernel/traps.c.
2541 abi_ulong trap_instr
;
2544 if (env
->hflags
& MIPS_HFLAG_M16
) {
2545 if (env
->insn_flags
& ASE_MICROMIPS
) {
2546 /* microMIPS mode */
2547 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
2552 if ((trap_instr
>> 10) == 0x11) {
2553 /* 16-bit instruction */
2554 code
= trap_instr
& 0xf;
2556 /* 32-bit instruction */
2559 ret
= get_user_u16(instr_lo
,
2560 env
->active_tc
.PC
+ 2);
2564 trap_instr
= (trap_instr
<< 16) | instr_lo
;
2565 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
2566 /* Unfortunately, microMIPS also suffers from
2567 the old assembler bug... */
2568 if (code
>= (1 << 10)) {
2574 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
2578 code
= (trap_instr
>> 6) & 0x3f;
2581 ret
= get_user_ual(trap_instr
, env
->active_tc
.PC
);
2586 /* As described in the original Linux kernel code, the
2587 * below checks on 'code' are to work around an old
2590 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
2591 if (code
>= (1 << 10)) {
2596 if (do_break(env
, &info
, code
) != 0) {
2603 abi_ulong trap_instr
;
2604 unsigned int code
= 0;
2606 if (env
->hflags
& MIPS_HFLAG_M16
) {
2607 /* microMIPS mode */
2610 ret
= get_user_u16(instr
[0], env
->active_tc
.PC
) ||
2611 get_user_u16(instr
[1], env
->active_tc
.PC
+ 2);
2613 trap_instr
= (instr
[0] << 16) | instr
[1];
2615 ret
= get_user_ual(trap_instr
, env
->active_tc
.PC
);
2622 /* The immediate versions don't provide a code. */
2623 if (!(trap_instr
& 0xFC000000)) {
2624 if (env
->hflags
& MIPS_HFLAG_M16
) {
2625 /* microMIPS mode */
2626 code
= ((trap_instr
>> 12) & ((1 << 4) - 1));
2628 code
= ((trap_instr
>> 6) & ((1 << 10) - 1));
2632 if (do_break(env
, &info
, code
) != 0) {
2639 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n",
2641 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2644 process_pending_signals(env
);
2649 #ifdef TARGET_OPENRISC
2651 void cpu_loop(CPUOpenRISCState
*env
)
2653 CPUState
*cs
= CPU(openrisc_env_get_cpu(env
));
2658 trapnr
= cpu_exec(env
);
2664 qemu_log("\nReset request, exit, pc is %#x\n", env
->pc
);
2668 qemu_log("\nBus error, exit, pc is %#x\n", env
->pc
);
2669 gdbsig
= TARGET_SIGBUS
;
2673 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2674 gdbsig
= TARGET_SIGSEGV
;
2677 qemu_log("\nTick time interrupt pc is %#x\n", env
->pc
);
2680 qemu_log("\nAlignment pc is %#x\n", env
->pc
);
2681 gdbsig
= TARGET_SIGBUS
;
2684 qemu_log("\nIllegal instructionpc is %#x\n", env
->pc
);
2685 gdbsig
= TARGET_SIGILL
;
2688 qemu_log("\nExternal interruptpc is %#x\n", env
->pc
);
2692 qemu_log("\nTLB miss\n");
2695 qemu_log("\nRange\n");
2696 gdbsig
= TARGET_SIGSEGV
;
2699 env
->pc
+= 4; /* 0xc00; */
2700 env
->gpr
[11] = do_syscall(env
,
2701 env
->gpr
[11], /* return value */
2702 env
->gpr
[3], /* r3 - r7 are params */
2710 qemu_log("\nFloating point error\n");
2713 qemu_log("\nTrap\n");
2714 gdbsig
= TARGET_SIGTRAP
;
2720 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2722 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2723 gdbsig
= TARGET_SIGILL
;
2727 gdb_handlesig(cs
, gdbsig
);
2728 if (gdbsig
!= TARGET_SIGTRAP
) {
2733 process_pending_signals(env
);
2737 #endif /* TARGET_OPENRISC */
2740 void cpu_loop(CPUSH4State
*env
)
2742 CPUState
*cs
= CPU(sh_env_get_cpu(env
));
2744 target_siginfo_t info
;
2748 trapnr
= cpu_sh4_exec (env
);
2754 ret
= do_syscall(env
,
2763 env
->gregs
[0] = ret
;
2765 case EXCP_INTERRUPT
:
2766 /* just indicate that signals should be handled asap */
2772 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2775 info
.si_signo
= sig
;
2777 info
.si_code
= TARGET_TRAP_BRKPT
;
2778 queue_signal(env
, info
.si_signo
, &info
);
2784 info
.si_signo
= TARGET_SIGSEGV
;
2786 info
.si_code
= TARGET_SEGV_MAPERR
;
2787 info
._sifields
._sigfault
._addr
= env
->tea
;
2788 queue_signal(env
, info
.si_signo
, &info
);
2792 printf ("Unhandled trap: 0x%x\n", trapnr
);
2793 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2796 process_pending_signals (env
);
2802 void cpu_loop(CPUCRISState
*env
)
2804 CPUState
*cs
= CPU(cris_env_get_cpu(env
));
2806 target_siginfo_t info
;
2810 trapnr
= cpu_cris_exec (env
);
2815 info
.si_signo
= TARGET_SIGSEGV
;
2817 /* XXX: check env->error_code */
2818 info
.si_code
= TARGET_SEGV_MAPERR
;
2819 info
._sifields
._sigfault
._addr
= env
->pregs
[PR_EDA
];
2820 queue_signal(env
, info
.si_signo
, &info
);
2823 case EXCP_INTERRUPT
:
2824 /* just indicate that signals should be handled asap */
2827 ret
= do_syscall(env
,
2836 env
->regs
[10] = ret
;
2842 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2845 info
.si_signo
= sig
;
2847 info
.si_code
= TARGET_TRAP_BRKPT
;
2848 queue_signal(env
, info
.si_signo
, &info
);
2853 printf ("Unhandled trap: 0x%x\n", trapnr
);
2854 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2857 process_pending_signals (env
);
2862 #ifdef TARGET_MICROBLAZE
2863 void cpu_loop(CPUMBState
*env
)
2865 CPUState
*cs
= CPU(mb_env_get_cpu(env
));
2867 target_siginfo_t info
;
2871 trapnr
= cpu_mb_exec (env
);
2876 info
.si_signo
= TARGET_SIGSEGV
;
2878 /* XXX: check env->error_code */
2879 info
.si_code
= TARGET_SEGV_MAPERR
;
2880 info
._sifields
._sigfault
._addr
= 0;
2881 queue_signal(env
, info
.si_signo
, &info
);
2884 case EXCP_INTERRUPT
:
2885 /* just indicate that signals should be handled asap */
2888 /* Return address is 4 bytes after the call. */
2890 env
->sregs
[SR_PC
] = env
->regs
[14];
2891 ret
= do_syscall(env
,
2903 env
->regs
[17] = env
->sregs
[SR_PC
] + 4;
2904 if (env
->iflags
& D_FLAG
) {
2905 env
->sregs
[SR_ESR
] |= 1 << 12;
2906 env
->sregs
[SR_PC
] -= 4;
2907 /* FIXME: if branch was immed, replay the imm as well. */
2910 env
->iflags
&= ~(IMM_FLAG
| D_FLAG
);
2912 switch (env
->sregs
[SR_ESR
] & 31) {
2913 case ESR_EC_DIVZERO
:
2914 info
.si_signo
= TARGET_SIGFPE
;
2916 info
.si_code
= TARGET_FPE_FLTDIV
;
2917 info
._sifields
._sigfault
._addr
= 0;
2918 queue_signal(env
, info
.si_signo
, &info
);
2921 info
.si_signo
= TARGET_SIGFPE
;
2923 if (env
->sregs
[SR_FSR
] & FSR_IO
) {
2924 info
.si_code
= TARGET_FPE_FLTINV
;
2926 if (env
->sregs
[SR_FSR
] & FSR_DZ
) {
2927 info
.si_code
= TARGET_FPE_FLTDIV
;
2929 info
._sifields
._sigfault
._addr
= 0;
2930 queue_signal(env
, info
.si_signo
, &info
);
2933 printf ("Unhandled hw-exception: 0x%x\n",
2934 env
->sregs
[SR_ESR
] & ESR_EC_MASK
);
2935 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2944 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2947 info
.si_signo
= sig
;
2949 info
.si_code
= TARGET_TRAP_BRKPT
;
2950 queue_signal(env
, info
.si_signo
, &info
);
2955 printf ("Unhandled trap: 0x%x\n", trapnr
);
2956 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2959 process_pending_signals (env
);
2966 void cpu_loop(CPUM68KState
*env
)
2968 CPUState
*cs
= CPU(m68k_env_get_cpu(env
));
2971 target_siginfo_t info
;
2972 TaskState
*ts
= cs
->opaque
;
2976 trapnr
= cpu_m68k_exec(env
);
2981 if (ts
->sim_syscalls
) {
2983 get_user_u16(nr
, env
->pc
+ 2);
2985 do_m68k_simcall(env
, nr
);
2991 case EXCP_HALT_INSN
:
2992 /* Semihosing syscall. */
2994 do_m68k_semihosting(env
, env
->dregs
[0]);
2998 case EXCP_UNSUPPORTED
:
3000 info
.si_signo
= TARGET_SIGILL
;
3002 info
.si_code
= TARGET_ILL_ILLOPN
;
3003 info
._sifields
._sigfault
._addr
= env
->pc
;
3004 queue_signal(env
, info
.si_signo
, &info
);
3008 ts
->sim_syscalls
= 0;
3011 env
->dregs
[0] = do_syscall(env
,
3022 case EXCP_INTERRUPT
:
3023 /* just indicate that signals should be handled asap */
3027 info
.si_signo
= TARGET_SIGSEGV
;
3029 /* XXX: check env->error_code */
3030 info
.si_code
= TARGET_SEGV_MAPERR
;
3031 info
._sifields
._sigfault
._addr
= env
->mmu
.ar
;
3032 queue_signal(env
, info
.si_signo
, &info
);
3039 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
3042 info
.si_signo
= sig
;
3044 info
.si_code
= TARGET_TRAP_BRKPT
;
3045 queue_signal(env
, info
.si_signo
, &info
);
3050 fprintf(stderr
, "qemu: unhandled CPU exception 0x%x - aborting\n",
3052 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3055 process_pending_signals(env
);
3058 #endif /* TARGET_M68K */
3061 static void do_store_exclusive(CPUAlphaState
*env
, int reg
, int quad
)
3063 target_ulong addr
, val
, tmp
;
3064 target_siginfo_t info
;
3067 addr
= env
->lock_addr
;
3068 tmp
= env
->lock_st_addr
;
3069 env
->lock_addr
= -1;
3070 env
->lock_st_addr
= 0;
3076 if (quad
? get_user_s64(val
, addr
) : get_user_s32(val
, addr
)) {
3080 if (val
== env
->lock_value
) {
3082 if (quad
? put_user_u64(tmp
, addr
) : put_user_u32(tmp
, addr
)) {
3099 info
.si_signo
= TARGET_SIGSEGV
;
3101 info
.si_code
= TARGET_SEGV_MAPERR
;
3102 info
._sifields
._sigfault
._addr
= addr
;
3103 queue_signal(env
, TARGET_SIGSEGV
, &info
);
3106 void cpu_loop(CPUAlphaState
*env
)
3108 CPUState
*cs
= CPU(alpha_env_get_cpu(env
));
3110 target_siginfo_t info
;
3115 trapnr
= cpu_alpha_exec (env
);
3118 /* All of the traps imply a transition through PALcode, which
3119 implies an REI instruction has been executed. Which means
3120 that the intr_flag should be cleared. */
3125 fprintf(stderr
, "Reset requested. Exit\n");
3129 fprintf(stderr
, "Machine check exception. Exit\n");
3132 case EXCP_SMP_INTERRUPT
:
3133 case EXCP_CLK_INTERRUPT
:
3134 case EXCP_DEV_INTERRUPT
:
3135 fprintf(stderr
, "External interrupt. Exit\n");
3139 env
->lock_addr
= -1;
3140 info
.si_signo
= TARGET_SIGSEGV
;
3142 info
.si_code
= (page_get_flags(env
->trap_arg0
) & PAGE_VALID
3143 ? TARGET_SEGV_ACCERR
: TARGET_SEGV_MAPERR
);
3144 info
._sifields
._sigfault
._addr
= env
->trap_arg0
;
3145 queue_signal(env
, info
.si_signo
, &info
);
3148 env
->lock_addr
= -1;
3149 info
.si_signo
= TARGET_SIGBUS
;
3151 info
.si_code
= TARGET_BUS_ADRALN
;
3152 info
._sifields
._sigfault
._addr
= env
->trap_arg0
;
3153 queue_signal(env
, info
.si_signo
, &info
);
3157 env
->lock_addr
= -1;
3158 info
.si_signo
= TARGET_SIGILL
;
3160 info
.si_code
= TARGET_ILL_ILLOPC
;
3161 info
._sifields
._sigfault
._addr
= env
->pc
;
3162 queue_signal(env
, info
.si_signo
, &info
);
3165 env
->lock_addr
= -1;
3166 info
.si_signo
= TARGET_SIGFPE
;
3168 info
.si_code
= TARGET_FPE_FLTINV
;
3169 info
._sifields
._sigfault
._addr
= env
->pc
;
3170 queue_signal(env
, info
.si_signo
, &info
);
3173 /* No-op. Linux simply re-enables the FPU. */
3176 env
->lock_addr
= -1;
3177 switch (env
->error_code
) {
3180 info
.si_signo
= TARGET_SIGTRAP
;
3182 info
.si_code
= TARGET_TRAP_BRKPT
;
3183 info
._sifields
._sigfault
._addr
= env
->pc
;
3184 queue_signal(env
, info
.si_signo
, &info
);
3188 info
.si_signo
= TARGET_SIGTRAP
;
3191 info
._sifields
._sigfault
._addr
= env
->pc
;
3192 queue_signal(env
, info
.si_signo
, &info
);
3196 trapnr
= env
->ir
[IR_V0
];
3197 sysret
= do_syscall(env
, trapnr
,
3198 env
->ir
[IR_A0
], env
->ir
[IR_A1
],
3199 env
->ir
[IR_A2
], env
->ir
[IR_A3
],
3200 env
->ir
[IR_A4
], env
->ir
[IR_A5
],
3202 if (trapnr
== TARGET_NR_sigreturn
3203 || trapnr
== TARGET_NR_rt_sigreturn
) {
3206 /* Syscall writes 0 to V0 to bypass error check, similar
3207 to how this is handled internal to Linux kernel.
3208 (Ab)use trapnr temporarily as boolean indicating error. */
3209 trapnr
= (env
->ir
[IR_V0
] != 0 && sysret
< 0);
3210 env
->ir
[IR_V0
] = (trapnr
? -sysret
: sysret
);
3211 env
->ir
[IR_A3
] = trapnr
;
3215 /* ??? We can probably elide the code using page_unprotect
3216 that is checking for self-modifying code. Instead we
3217 could simply call tb_flush here. Until we work out the
3218 changes required to turn off the extra write protection,
3219 this can be a no-op. */
3223 /* Handled in the translator for usermode. */
3227 /* Handled in the translator for usermode. */
3231 info
.si_signo
= TARGET_SIGFPE
;
3232 switch (env
->ir
[IR_A0
]) {
3233 case TARGET_GEN_INTOVF
:
3234 info
.si_code
= TARGET_FPE_INTOVF
;
3236 case TARGET_GEN_INTDIV
:
3237 info
.si_code
= TARGET_FPE_INTDIV
;
3239 case TARGET_GEN_FLTOVF
:
3240 info
.si_code
= TARGET_FPE_FLTOVF
;
3242 case TARGET_GEN_FLTUND
:
3243 info
.si_code
= TARGET_FPE_FLTUND
;
3245 case TARGET_GEN_FLTINV
:
3246 info
.si_code
= TARGET_FPE_FLTINV
;
3248 case TARGET_GEN_FLTINE
:
3249 info
.si_code
= TARGET_FPE_FLTRES
;
3251 case TARGET_GEN_ROPRAND
:
3255 info
.si_signo
= TARGET_SIGTRAP
;
3260 info
._sifields
._sigfault
._addr
= env
->pc
;
3261 queue_signal(env
, info
.si_signo
, &info
);
3268 info
.si_signo
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
3269 if (info
.si_signo
) {
3270 env
->lock_addr
= -1;
3272 info
.si_code
= TARGET_TRAP_BRKPT
;
3273 queue_signal(env
, info
.si_signo
, &info
);
3278 do_store_exclusive(env
, env
->error_code
, trapnr
- EXCP_STL_C
);
3280 case EXCP_INTERRUPT
:
3281 /* Just indicate that signals should be handled asap. */
3284 printf ("Unhandled trap: 0x%x\n", trapnr
);
3285 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3288 process_pending_signals (env
);
3291 #endif /* TARGET_ALPHA */
3294 void cpu_loop(CPUS390XState
*env
)
3296 CPUState
*cs
= CPU(s390_env_get_cpu(env
));
3298 target_siginfo_t info
;
3303 trapnr
= cpu_s390x_exec(env
);
3306 case EXCP_INTERRUPT
:
3307 /* Just indicate that signals should be handled asap. */
3311 n
= env
->int_svc_code
;
3313 /* syscalls > 255 */
3316 env
->psw
.addr
+= env
->int_svc_ilen
;
3317 env
->regs
[2] = do_syscall(env
, n
, env
->regs
[2], env
->regs
[3],
3318 env
->regs
[4], env
->regs
[5],
3319 env
->regs
[6], env
->regs
[7], 0, 0);
3323 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
3325 n
= TARGET_TRAP_BRKPT
;
3330 n
= env
->int_pgm_code
;
3333 case PGM_PRIVILEGED
:
3334 sig
= TARGET_SIGILL
;
3335 n
= TARGET_ILL_ILLOPC
;
3337 case PGM_PROTECTION
:
3338 case PGM_ADDRESSING
:
3339 sig
= TARGET_SIGSEGV
;
3340 /* XXX: check env->error_code */
3341 n
= TARGET_SEGV_MAPERR
;
3342 addr
= env
->__excp_addr
;
3345 case PGM_SPECIFICATION
:
3346 case PGM_SPECIAL_OP
:
3349 sig
= TARGET_SIGILL
;
3350 n
= TARGET_ILL_ILLOPN
;
3353 case PGM_FIXPT_OVERFLOW
:
3354 sig
= TARGET_SIGFPE
;
3355 n
= TARGET_FPE_INTOVF
;
3357 case PGM_FIXPT_DIVIDE
:
3358 sig
= TARGET_SIGFPE
;
3359 n
= TARGET_FPE_INTDIV
;
3363 n
= (env
->fpc
>> 8) & 0xff;
3365 /* compare-and-trap */
3368 /* An IEEE exception, simulated or otherwise. */
3370 n
= TARGET_FPE_FLTINV
;
3371 } else if (n
& 0x40) {
3372 n
= TARGET_FPE_FLTDIV
;
3373 } else if (n
& 0x20) {
3374 n
= TARGET_FPE_FLTOVF
;
3375 } else if (n
& 0x10) {
3376 n
= TARGET_FPE_FLTUND
;
3377 } else if (n
& 0x08) {
3378 n
= TARGET_FPE_FLTRES
;
3380 /* ??? Quantum exception; BFP, DFP error. */
3383 sig
= TARGET_SIGFPE
;
3388 fprintf(stderr
, "Unhandled program exception: %#x\n", n
);
3389 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3395 addr
= env
->psw
.addr
;
3397 info
.si_signo
= sig
;
3400 info
._sifields
._sigfault
._addr
= addr
;
3401 queue_signal(env
, info
.si_signo
, &info
);
3405 fprintf(stderr
, "Unhandled trap: 0x%x\n", trapnr
);
3406 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3409 process_pending_signals (env
);
3413 #endif /* TARGET_S390X */
3415 THREAD CPUState
*thread_cpu
;
3417 void task_settid(TaskState
*ts
)
3419 if (ts
->ts_tid
== 0) {
3420 ts
->ts_tid
= (pid_t
)syscall(SYS_gettid
);
3424 void stop_all_tasks(void)
3427 * We trust that when using NPTL, start_exclusive()
3428 * handles thread stopping correctly.
3433 /* Assumes contents are already zeroed. */
3434 void init_task_state(TaskState
*ts
)
3439 ts
->first_free
= ts
->sigqueue_table
;
3440 for (i
= 0; i
< MAX_SIGQUEUE_SIZE
- 1; i
++) {
3441 ts
->sigqueue_table
[i
].next
= &ts
->sigqueue_table
[i
+ 1];
3443 ts
->sigqueue_table
[i
].next
= NULL
;
3446 CPUArchState
*cpu_copy(CPUArchState
*env
)
3448 CPUState
*cpu
= ENV_GET_CPU(env
);
3449 CPUState
*new_cpu
= cpu_init(cpu_model
);
3450 CPUArchState
*new_env
= new_cpu
->env_ptr
;
3454 /* Reset non arch specific state */
3457 memcpy(new_env
, env
, sizeof(CPUArchState
));
3459 /* Clone all break/watchpoints.
3460 Note: Once we support ptrace with hw-debug register access, make sure
3461 BP_CPU break/watchpoints are handled correctly on clone. */
3462 QTAILQ_INIT(&cpu
->breakpoints
);
3463 QTAILQ_INIT(&cpu
->watchpoints
);
3464 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
3465 cpu_breakpoint_insert(new_cpu
, bp
->pc
, bp
->flags
, NULL
);
3467 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
3468 cpu_watchpoint_insert(new_cpu
, wp
->vaddr
, wp
->len
, wp
->flags
, NULL
);
3474 static void handle_arg_help(const char *arg
)
3479 static void handle_arg_log(const char *arg
)
3483 mask
= qemu_str_to_log_mask(arg
);
3485 qemu_print_log_usage(stdout
);
3491 static void handle_arg_log_filename(const char *arg
)
3493 qemu_set_log_filename(arg
);
3496 static void handle_arg_set_env(const char *arg
)
3498 char *r
, *p
, *token
;
3499 r
= p
= strdup(arg
);
3500 while ((token
= strsep(&p
, ",")) != NULL
) {
3501 if (envlist_setenv(envlist
, token
) != 0) {
3508 static void handle_arg_unset_env(const char *arg
)
3510 char *r
, *p
, *token
;
3511 r
= p
= strdup(arg
);
3512 while ((token
= strsep(&p
, ",")) != NULL
) {
3513 if (envlist_unsetenv(envlist
, token
) != 0) {
3520 static void handle_arg_argv0(const char *arg
)
3522 argv0
= strdup(arg
);
3525 static void handle_arg_stack_size(const char *arg
)
3528 guest_stack_size
= strtoul(arg
, &p
, 0);
3529 if (guest_stack_size
== 0) {
3534 guest_stack_size
*= 1024 * 1024;
3535 } else if (*p
== 'k' || *p
== 'K') {
3536 guest_stack_size
*= 1024;
3540 static void handle_arg_ld_prefix(const char *arg
)
3542 interp_prefix
= strdup(arg
);
3545 static void handle_arg_pagesize(const char *arg
)
3547 qemu_host_page_size
= atoi(arg
);
3548 if (qemu_host_page_size
== 0 ||
3549 (qemu_host_page_size
& (qemu_host_page_size
- 1)) != 0) {
3550 fprintf(stderr
, "page size must be a power of two\n");
3555 static void handle_arg_randseed(const char *arg
)
3557 unsigned long long seed
;
3559 if (parse_uint_full(arg
, &seed
, 0) != 0 || seed
> UINT_MAX
) {
3560 fprintf(stderr
, "Invalid seed number: %s\n", arg
);
3566 static void handle_arg_gdb(const char *arg
)
3568 gdbstub_port
= atoi(arg
);
3571 static void handle_arg_uname(const char *arg
)
3573 qemu_uname_release
= strdup(arg
);
3576 static void handle_arg_cpu(const char *arg
)
3578 cpu_model
= strdup(arg
);
3579 if (cpu_model
== NULL
|| is_help_option(cpu_model
)) {
3580 /* XXX: implement xxx_cpu_list for targets that still miss it */
3581 #if defined(cpu_list)
3582 cpu_list(stdout
, &fprintf
);
3588 #if defined(CONFIG_USE_GUEST_BASE)
3589 static void handle_arg_guest_base(const char *arg
)
3591 guest_base
= strtol(arg
, NULL
, 0);
3592 have_guest_base
= 1;
3595 static void handle_arg_reserved_va(const char *arg
)
3599 reserved_va
= strtoul(arg
, &p
, 0);
3613 unsigned long unshifted
= reserved_va
;
3615 reserved_va
<<= shift
;
3616 if (((reserved_va
>> shift
) != unshifted
)
3617 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3618 || (reserved_va
> (1ul << TARGET_VIRT_ADDR_SPACE_BITS
))
3621 fprintf(stderr
, "Reserved virtual address too big\n");
3626 fprintf(stderr
, "Unrecognised -R size suffix '%s'\n", p
);
3632 static void handle_arg_singlestep(const char *arg
)
3637 static void handle_arg_strace(const char *arg
)
3642 static void handle_arg_version(const char *arg
)
3644 printf("qemu-" TARGET_NAME
" version " QEMU_VERSION QEMU_PKGVERSION
3645 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3649 struct qemu_argument
{
3653 void (*handle_opt
)(const char *arg
);
3654 const char *example
;
3658 static const struct qemu_argument arg_table
[] = {
3659 {"h", "", false, handle_arg_help
,
3660 "", "print this help"},
3661 {"g", "QEMU_GDB", true, handle_arg_gdb
,
3662 "port", "wait gdb connection to 'port'"},
3663 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix
,
3664 "path", "set the elf interpreter prefix to 'path'"},
3665 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size
,
3666 "size", "set the stack size to 'size' bytes"},
3667 {"cpu", "QEMU_CPU", true, handle_arg_cpu
,
3668 "model", "select CPU (-cpu help for list)"},
3669 {"E", "QEMU_SET_ENV", true, handle_arg_set_env
,
3670 "var=value", "sets targets environment variable (see below)"},
3671 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env
,
3672 "var", "unsets targets environment variable (see below)"},
3673 {"0", "QEMU_ARGV0", true, handle_arg_argv0
,
3674 "argv0", "forces target process argv[0] to be 'argv0'"},
3675 {"r", "QEMU_UNAME", true, handle_arg_uname
,
3676 "uname", "set qemu uname release string to 'uname'"},
3677 #if defined(CONFIG_USE_GUEST_BASE)
3678 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base
,
3679 "address", "set guest_base address to 'address'"},
3680 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va
,
3681 "size", "reserve 'size' bytes for guest virtual address space"},
3683 {"d", "QEMU_LOG", true, handle_arg_log
,
3684 "item[,...]", "enable logging of specified items "
3685 "(use '-d help' for a list of items)"},
3686 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename
,
3687 "logfile", "write logs to 'logfile' (default stderr)"},
3688 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize
,
3689 "pagesize", "set the host page size to 'pagesize'"},
3690 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep
,
3691 "", "run in singlestep mode"},
3692 {"strace", "QEMU_STRACE", false, handle_arg_strace
,
3693 "", "log system calls"},
3694 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed
,
3695 "", "Seed for pseudo-random number generator"},
3696 {"version", "QEMU_VERSION", false, handle_arg_version
,
3697 "", "display version information and exit"},
3698 {NULL
, NULL
, false, NULL
, NULL
, NULL
}
3701 static void usage(void)
3703 const struct qemu_argument
*arginfo
;
3707 printf("usage: qemu-" TARGET_NAME
" [options] program [arguments...]\n"
3708 "Linux CPU emulator (compiled for " TARGET_NAME
" emulation)\n"
3710 "Options and associated environment variables:\n"
3713 /* Calculate column widths. We must always have at least enough space
3714 * for the column header.
3716 maxarglen
= strlen("Argument");
3717 maxenvlen
= strlen("Env-variable");
3719 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
3720 int arglen
= strlen(arginfo
->argv
);
3721 if (arginfo
->has_arg
) {
3722 arglen
+= strlen(arginfo
->example
) + 1;
3724 if (strlen(arginfo
->env
) > maxenvlen
) {
3725 maxenvlen
= strlen(arginfo
->env
);
3727 if (arglen
> maxarglen
) {
3732 printf("%-*s %-*s Description\n", maxarglen
+1, "Argument",
3733 maxenvlen
, "Env-variable");
3735 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
3736 if (arginfo
->has_arg
) {
3737 printf("-%s %-*s %-*s %s\n", arginfo
->argv
,
3738 (int)(maxarglen
- strlen(arginfo
->argv
) - 1),
3739 arginfo
->example
, maxenvlen
, arginfo
->env
, arginfo
->help
);
3741 printf("-%-*s %-*s %s\n", maxarglen
, arginfo
->argv
,
3742 maxenvlen
, arginfo
->env
,
3749 "QEMU_LD_PREFIX = %s\n"
3750 "QEMU_STACK_SIZE = %ld byte\n",
3755 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3756 "QEMU_UNSET_ENV environment variables to set and unset\n"
3757 "environment variables for the target process.\n"
3758 "It is possible to provide several variables by separating them\n"
3759 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3760 "provide the -E and -U options multiple times.\n"
3761 "The following lines are equivalent:\n"
3762 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3763 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3764 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3765 "Note that if you provide several changes to a single variable\n"
3766 "the last change will stay in effect.\n");
3771 static int parse_args(int argc
, char **argv
)
3775 const struct qemu_argument
*arginfo
;
3777 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
3778 if (arginfo
->env
== NULL
) {
3782 r
= getenv(arginfo
->env
);
3784 arginfo
->handle_opt(r
);
3790 if (optind
>= argc
) {
3799 if (!strcmp(r
, "-")) {
3803 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
3804 if (!strcmp(r
, arginfo
->argv
)) {
3805 if (arginfo
->has_arg
) {
3806 if (optind
>= argc
) {
3809 arginfo
->handle_opt(argv
[optind
]);
3812 arginfo
->handle_opt(NULL
);
3818 /* no option matched the current argv */
3819 if (arginfo
->handle_opt
== NULL
) {
3824 if (optind
>= argc
) {
3828 filename
= argv
[optind
];
3829 exec_path
= argv
[optind
];
3834 int main(int argc
, char **argv
, char **envp
)
3836 struct target_pt_regs regs1
, *regs
= ®s1
;
3837 struct image_info info1
, *info
= &info1
;
3838 struct linux_binprm bprm
;
3843 char **target_environ
, **wrk
;
3850 module_call_init(MODULE_INIT_QOM
);
3852 if ((envlist
= envlist_create()) == NULL
) {
3853 (void) fprintf(stderr
, "Unable to allocate envlist\n");
3857 /* add current environment into the list */
3858 for (wrk
= environ
; *wrk
!= NULL
; wrk
++) {
3859 (void) envlist_setenv(envlist
, *wrk
);
3862 /* Read the stack limit from the kernel. If it's "unlimited",
3863 then we can do little else besides use the default. */
3866 if (getrlimit(RLIMIT_STACK
, &lim
) == 0
3867 && lim
.rlim_cur
!= RLIM_INFINITY
3868 && lim
.rlim_cur
== (target_long
)lim
.rlim_cur
) {
3869 guest_stack_size
= lim
.rlim_cur
;
3874 #if defined(cpudef_setup)
3875 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3880 optind
= parse_args(argc
, argv
);
3883 memset(regs
, 0, sizeof(struct target_pt_regs
));
3885 /* Zero out image_info */
3886 memset(info
, 0, sizeof(struct image_info
));
3888 memset(&bprm
, 0, sizeof (bprm
));
3890 /* Scan interp_prefix dir for replacement files. */
3891 init_paths(interp_prefix
);
3893 init_qemu_uname_release();
3895 if (cpu_model
== NULL
) {
3896 #if defined(TARGET_I386)
3897 #ifdef TARGET_X86_64
3898 cpu_model
= "qemu64";
3900 cpu_model
= "qemu32";
3902 #elif defined(TARGET_ARM)
3904 #elif defined(TARGET_UNICORE32)
3906 #elif defined(TARGET_M68K)
3908 #elif defined(TARGET_SPARC)
3909 #ifdef TARGET_SPARC64
3910 cpu_model
= "TI UltraSparc II";
3912 cpu_model
= "Fujitsu MB86904";
3914 #elif defined(TARGET_MIPS)
3915 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3920 #elif defined TARGET_OPENRISC
3921 cpu_model
= "or1200";
3922 #elif defined(TARGET_PPC)
3923 # ifdef TARGET_PPC64
3924 cpu_model
= "POWER7";
3933 /* NOTE: we need to init the CPU at this stage to get
3934 qemu_host_page_size */
3935 cpu
= cpu_init(cpu_model
);
3937 fprintf(stderr
, "Unable to find CPU definition\n");
3945 if (getenv("QEMU_STRACE")) {
3949 if (getenv("QEMU_RAND_SEED")) {
3950 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
3953 target_environ
= envlist_to_environ(envlist
, NULL
);
3954 envlist_free(envlist
);
3956 #if defined(CONFIG_USE_GUEST_BASE)
3958 * Now that page sizes are configured in cpu_init() we can do
3959 * proper page alignment for guest_base.
3961 guest_base
= HOST_PAGE_ALIGN(guest_base
);
3963 if (reserved_va
|| have_guest_base
) {
3964 guest_base
= init_guest_space(guest_base
, reserved_va
, 0,
3966 if (guest_base
== (unsigned long)-1) {
3967 fprintf(stderr
, "Unable to reserve 0x%lx bytes of virtual address "
3968 "space for use as guest address space (check your virtual "
3969 "memory ulimit setting or reserve less using -R option)\n",
3975 mmap_next_start
= reserved_va
;
3978 #endif /* CONFIG_USE_GUEST_BASE */
3981 * Read in mmap_min_addr kernel parameter. This value is used
3982 * When loading the ELF image to determine whether guest_base
3983 * is needed. It is also used in mmap_find_vma.
3988 if ((fp
= fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL
) {
3990 if (fscanf(fp
, "%lu", &tmp
) == 1) {
3991 mmap_min_addr
= tmp
;
3992 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr
);
3999 * Prepare copy of argv vector for target.
4001 target_argc
= argc
- optind
;
4002 target_argv
= calloc(target_argc
+ 1, sizeof (char *));
4003 if (target_argv
== NULL
) {
4004 (void) fprintf(stderr
, "Unable to allocate memory for target_argv\n");
4009 * If argv0 is specified (using '-0' switch) we replace
4010 * argv[0] pointer with the given one.
4013 if (argv0
!= NULL
) {
4014 target_argv
[i
++] = strdup(argv0
);
4016 for (; i
< target_argc
; i
++) {
4017 target_argv
[i
] = strdup(argv
[optind
+ i
]);
4019 target_argv
[target_argc
] = NULL
;
4021 ts
= g_malloc0 (sizeof(TaskState
));
4022 init_task_state(ts
);
4023 /* build Task State */
4029 execfd
= qemu_getauxval(AT_EXECFD
);
4031 execfd
= open(filename
, O_RDONLY
);
4033 printf("Error while loading %s: %s\n", filename
, strerror(errno
));
4038 ret
= loader_exec(execfd
, filename
, target_argv
, target_environ
, regs
,
4041 printf("Error while loading %s: %s\n", filename
, strerror(-ret
));
4045 for (wrk
= target_environ
; *wrk
; wrk
++) {
4049 free(target_environ
);
4051 if (qemu_log_enabled()) {
4052 #if defined(CONFIG_USE_GUEST_BASE)
4053 qemu_log("guest_base 0x%lx\n", guest_base
);
4057 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx
"\n", info
->start_brk
);
4058 qemu_log("end_code 0x" TARGET_ABI_FMT_lx
"\n", info
->end_code
);
4059 qemu_log("start_code 0x" TARGET_ABI_FMT_lx
"\n",
4061 qemu_log("start_data 0x" TARGET_ABI_FMT_lx
"\n",
4063 qemu_log("end_data 0x" TARGET_ABI_FMT_lx
"\n", info
->end_data
);
4064 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx
"\n",
4066 qemu_log("brk 0x" TARGET_ABI_FMT_lx
"\n", info
->brk
);
4067 qemu_log("entry 0x" TARGET_ABI_FMT_lx
"\n", info
->entry
);
4070 target_set_brk(info
->brk
);
4074 #if defined(CONFIG_USE_GUEST_BASE)
4075 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4076 generating the prologue until now so that the prologue can take
4077 the real value of GUEST_BASE into account. */
4078 tcg_prologue_init(&tcg_ctx
);
4081 #if defined(TARGET_I386)
4082 env
->cr
[0] = CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
;
4083 env
->hflags
|= HF_PE_MASK
| HF_CPL_MASK
;
4084 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
4085 env
->cr
[4] |= CR4_OSFXSR_MASK
;
4086 env
->hflags
|= HF_OSFXSR_MASK
;
4088 #ifndef TARGET_ABI32
4089 /* enable 64 bit mode if possible */
4090 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
)) {
4091 fprintf(stderr
, "The selected x86 CPU does not support 64 bit mode\n");
4094 env
->cr
[4] |= CR4_PAE_MASK
;
4095 env
->efer
|= MSR_EFER_LMA
| MSR_EFER_LME
;
4096 env
->hflags
|= HF_LMA_MASK
;
4099 /* flags setup : we activate the IRQs by default as in user mode */
4100 env
->eflags
|= IF_MASK
;
4102 /* linux register setup */
4103 #ifndef TARGET_ABI32
4104 env
->regs
[R_EAX
] = regs
->rax
;
4105 env
->regs
[R_EBX
] = regs
->rbx
;
4106 env
->regs
[R_ECX
] = regs
->rcx
;
4107 env
->regs
[R_EDX
] = regs
->rdx
;
4108 env
->regs
[R_ESI
] = regs
->rsi
;
4109 env
->regs
[R_EDI
] = regs
->rdi
;
4110 env
->regs
[R_EBP
] = regs
->rbp
;
4111 env
->regs
[R_ESP
] = regs
->rsp
;
4112 env
->eip
= regs
->rip
;
4114 env
->regs
[R_EAX
] = regs
->eax
;
4115 env
->regs
[R_EBX
] = regs
->ebx
;
4116 env
->regs
[R_ECX
] = regs
->ecx
;
4117 env
->regs
[R_EDX
] = regs
->edx
;
4118 env
->regs
[R_ESI
] = regs
->esi
;
4119 env
->regs
[R_EDI
] = regs
->edi
;
4120 env
->regs
[R_EBP
] = regs
->ebp
;
4121 env
->regs
[R_ESP
] = regs
->esp
;
4122 env
->eip
= regs
->eip
;
4125 /* linux interrupt setup */
4126 #ifndef TARGET_ABI32
4127 env
->idt
.limit
= 511;
4129 env
->idt
.limit
= 255;
4131 env
->idt
.base
= target_mmap(0, sizeof(uint64_t) * (env
->idt
.limit
+ 1),
4132 PROT_READ
|PROT_WRITE
,
4133 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
4134 idt_table
= g2h(env
->idt
.base
);
4157 /* linux segment setup */
4159 uint64_t *gdt_table
;
4160 env
->gdt
.base
= target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES
,
4161 PROT_READ
|PROT_WRITE
,
4162 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
4163 env
->gdt
.limit
= sizeof(uint64_t) * TARGET_GDT_ENTRIES
- 1;
4164 gdt_table
= g2h(env
->gdt
.base
);
4166 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
4167 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
4168 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
4170 /* 64 bit code segment */
4171 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
4172 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
4174 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
4176 write_dt(&gdt_table
[__USER_DS
>> 3], 0, 0xfffff,
4177 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
4178 (3 << DESC_DPL_SHIFT
) | (0x2 << DESC_TYPE_SHIFT
));
4180 cpu_x86_load_seg(env
, R_CS
, __USER_CS
);
4181 cpu_x86_load_seg(env
, R_SS
, __USER_DS
);
4183 cpu_x86_load_seg(env
, R_DS
, __USER_DS
);
4184 cpu_x86_load_seg(env
, R_ES
, __USER_DS
);
4185 cpu_x86_load_seg(env
, R_FS
, __USER_DS
);
4186 cpu_x86_load_seg(env
, R_GS
, __USER_DS
);
4187 /* This hack makes Wine work... */
4188 env
->segs
[R_FS
].selector
= 0;
4190 cpu_x86_load_seg(env
, R_DS
, 0);
4191 cpu_x86_load_seg(env
, R_ES
, 0);
4192 cpu_x86_load_seg(env
, R_FS
, 0);
4193 cpu_x86_load_seg(env
, R_GS
, 0);
4195 #elif defined(TARGET_AARCH64)
4199 if (!(arm_feature(env
, ARM_FEATURE_AARCH64
))) {
4201 "The selected ARM CPU does not support 64 bit mode\n");
4205 for (i
= 0; i
< 31; i
++) {
4206 env
->xregs
[i
] = regs
->regs
[i
];
4209 env
->xregs
[31] = regs
->sp
;
4211 #elif defined(TARGET_ARM)
4214 cpsr_write(env
, regs
->uregs
[16], 0xffffffff);
4215 for(i
= 0; i
< 16; i
++) {
4216 env
->regs
[i
] = regs
->uregs
[i
];
4219 if (EF_ARM_EABI_VERSION(info
->elf_flags
) >= EF_ARM_EABI_VER4
4220 && (info
->elf_flags
& EF_ARM_BE8
)) {
4221 env
->bswap_code
= 1;
4224 #elif defined(TARGET_UNICORE32)
4227 cpu_asr_write(env
, regs
->uregs
[32], 0xffffffff);
4228 for (i
= 0; i
< 32; i
++) {
4229 env
->regs
[i
] = regs
->uregs
[i
];
4232 #elif defined(TARGET_SPARC)
4236 env
->npc
= regs
->npc
;
4238 for(i
= 0; i
< 8; i
++)
4239 env
->gregs
[i
] = regs
->u_regs
[i
];
4240 for(i
= 0; i
< 8; i
++)
4241 env
->regwptr
[i
] = regs
->u_regs
[i
+ 8];
4243 #elif defined(TARGET_PPC)
4247 #if defined(TARGET_PPC64)
4248 #if defined(TARGET_ABI32)
4249 env
->msr
&= ~((target_ulong
)1 << MSR_SF
);
4251 env
->msr
|= (target_ulong
)1 << MSR_SF
;
4254 env
->nip
= regs
->nip
;
4255 for(i
= 0; i
< 32; i
++) {
4256 env
->gpr
[i
] = regs
->gpr
[i
];
4259 #elif defined(TARGET_M68K)
4262 env
->dregs
[0] = regs
->d0
;
4263 env
->dregs
[1] = regs
->d1
;
4264 env
->dregs
[2] = regs
->d2
;
4265 env
->dregs
[3] = regs
->d3
;
4266 env
->dregs
[4] = regs
->d4
;
4267 env
->dregs
[5] = regs
->d5
;
4268 env
->dregs
[6] = regs
->d6
;
4269 env
->dregs
[7] = regs
->d7
;
4270 env
->aregs
[0] = regs
->a0
;
4271 env
->aregs
[1] = regs
->a1
;
4272 env
->aregs
[2] = regs
->a2
;
4273 env
->aregs
[3] = regs
->a3
;
4274 env
->aregs
[4] = regs
->a4
;
4275 env
->aregs
[5] = regs
->a5
;
4276 env
->aregs
[6] = regs
->a6
;
4277 env
->aregs
[7] = regs
->usp
;
4279 ts
->sim_syscalls
= 1;
4281 #elif defined(TARGET_MICROBLAZE)
4283 env
->regs
[0] = regs
->r0
;
4284 env
->regs
[1] = regs
->r1
;
4285 env
->regs
[2] = regs
->r2
;
4286 env
->regs
[3] = regs
->r3
;
4287 env
->regs
[4] = regs
->r4
;
4288 env
->regs
[5] = regs
->r5
;
4289 env
->regs
[6] = regs
->r6
;
4290 env
->regs
[7] = regs
->r7
;
4291 env
->regs
[8] = regs
->r8
;
4292 env
->regs
[9] = regs
->r9
;
4293 env
->regs
[10] = regs
->r10
;
4294 env
->regs
[11] = regs
->r11
;
4295 env
->regs
[12] = regs
->r12
;
4296 env
->regs
[13] = regs
->r13
;
4297 env
->regs
[14] = regs
->r14
;
4298 env
->regs
[15] = regs
->r15
;
4299 env
->regs
[16] = regs
->r16
;
4300 env
->regs
[17] = regs
->r17
;
4301 env
->regs
[18] = regs
->r18
;
4302 env
->regs
[19] = regs
->r19
;
4303 env
->regs
[20] = regs
->r20
;
4304 env
->regs
[21] = regs
->r21
;
4305 env
->regs
[22] = regs
->r22
;
4306 env
->regs
[23] = regs
->r23
;
4307 env
->regs
[24] = regs
->r24
;
4308 env
->regs
[25] = regs
->r25
;
4309 env
->regs
[26] = regs
->r26
;
4310 env
->regs
[27] = regs
->r27
;
4311 env
->regs
[28] = regs
->r28
;
4312 env
->regs
[29] = regs
->r29
;
4313 env
->regs
[30] = regs
->r30
;
4314 env
->regs
[31] = regs
->r31
;
4315 env
->sregs
[SR_PC
] = regs
->pc
;
4317 #elif defined(TARGET_MIPS)
4321 for(i
= 0; i
< 32; i
++) {
4322 env
->active_tc
.gpr
[i
] = regs
->regs
[i
];
4324 env
->active_tc
.PC
= regs
->cp0_epc
& ~(target_ulong
)1;
4325 if (regs
->cp0_epc
& 1) {
4326 env
->hflags
|= MIPS_HFLAG_M16
;
4329 #elif defined(TARGET_OPENRISC)
4333 for (i
= 0; i
< 32; i
++) {
4334 env
->gpr
[i
] = regs
->gpr
[i
];
4340 #elif defined(TARGET_SH4)
4344 for(i
= 0; i
< 16; i
++) {
4345 env
->gregs
[i
] = regs
->regs
[i
];
4349 #elif defined(TARGET_ALPHA)
4353 for(i
= 0; i
< 28; i
++) {
4354 env
->ir
[i
] = ((abi_ulong
*)regs
)[i
];
4356 env
->ir
[IR_SP
] = regs
->usp
;
4359 #elif defined(TARGET_CRIS)
4361 env
->regs
[0] = regs
->r0
;
4362 env
->regs
[1] = regs
->r1
;
4363 env
->regs
[2] = regs
->r2
;
4364 env
->regs
[3] = regs
->r3
;
4365 env
->regs
[4] = regs
->r4
;
4366 env
->regs
[5] = regs
->r5
;
4367 env
->regs
[6] = regs
->r6
;
4368 env
->regs
[7] = regs
->r7
;
4369 env
->regs
[8] = regs
->r8
;
4370 env
->regs
[9] = regs
->r9
;
4371 env
->regs
[10] = regs
->r10
;
4372 env
->regs
[11] = regs
->r11
;
4373 env
->regs
[12] = regs
->r12
;
4374 env
->regs
[13] = regs
->r13
;
4375 env
->regs
[14] = info
->start_stack
;
4376 env
->regs
[15] = regs
->acr
;
4377 env
->pc
= regs
->erp
;
4379 #elif defined(TARGET_S390X)
4382 for (i
= 0; i
< 16; i
++) {
4383 env
->regs
[i
] = regs
->gprs
[i
];
4385 env
->psw
.mask
= regs
->psw
.mask
;
4386 env
->psw
.addr
= regs
->psw
.addr
;
4389 #error unsupported target CPU
4392 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4393 ts
->stack_base
= info
->start_stack
;
4394 ts
->heap_base
= info
->brk
;
4395 /* This will be filled in on the first SYS_HEAPINFO call. */
4400 if (gdbserver_start(gdbstub_port
) < 0) {
4401 fprintf(stderr
, "qemu: could not open gdbserver on port %d\n",
4405 gdb_handlesig(cpu
, 0);