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ppc: Add real mode CI load/store instructions for P7 and P8
[qemu.git] / target-ppc / cpu.h
blob61a24b19ffceff3b3bd12b780263f8cbc1fbffac
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "qemu-common.h"
23
24 //#define PPC_EMULATE_32BITS_HYPV
25
26 #if defined (TARGET_PPC64)
27 /* PowerPC 64 definitions */
28 #define TARGET_LONG_BITS 64
29 #define TARGET_PAGE_BITS 12
30
31 /* Note that the official physical address space bits is 62-M where M
32 is implementation dependent. I've not looked up M for the set of
33 cpus we emulate at the system level. */
34 #define TARGET_PHYS_ADDR_SPACE_BITS 62
35
36 /* Note that the PPC environment architecture talks about 80 bit virtual
37 addresses, with segmentation. Obviously that's not all visible to a
38 single process, which is all we're concerned with here. */
39 #ifdef TARGET_ABI32
40 # define TARGET_VIRT_ADDR_SPACE_BITS 32
41 #else
42 # define TARGET_VIRT_ADDR_SPACE_BITS 64
43 #endif
44
45 #define TARGET_PAGE_BITS_64K 16
46 #define TARGET_PAGE_BITS_16M 24
47
48 #else /* defined (TARGET_PPC64) */
49 /* PowerPC 32 definitions */
50 #define TARGET_LONG_BITS 32
51
52 #if defined(TARGET_PPCEMB)
53 /* Specific definitions for PowerPC embedded */
54 /* BookE have 36 bits physical address space */
55 #if defined(CONFIG_USER_ONLY)
56 /* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
59 #define TARGET_PAGE_BITS 12
60 #else /* defined(CONFIG_USER_ONLY) */
61 /* Pages can be 1 kB small */
62 #define TARGET_PAGE_BITS 10
63 #endif /* defined(CONFIG_USER_ONLY) */
64 #else /* defined(TARGET_PPCEMB) */
65 /* "standard" PowerPC 32 definitions */
66 #define TARGET_PAGE_BITS 12
67 #endif /* defined(TARGET_PPCEMB) */
68
69 #define TARGET_PHYS_ADDR_SPACE_BITS 36
70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
71
72 #endif /* defined (TARGET_PPC64) */
73
74 #define CPUArchState struct CPUPPCState
75
76 #include "exec/cpu-defs.h"
77 #include "cpu-qom.h"
78 #include "fpu/softfloat.h"
79
80 #if defined (TARGET_PPC64)
81 #define PPC_ELF_MACHINE EM_PPC64
82 #else
83 #define PPC_ELF_MACHINE EM_PPC
84 #endif
85
86 /*****************************************************************************/
87 /* Exception vectors definitions */
88 enum {
89 POWERPC_EXCP_NONE = -1,
90 /* The 64 first entries are used by the PowerPC embedded specification */
91 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
92 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
93 POWERPC_EXCP_DSI = 2, /* Data storage exception */
94 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
95 POWERPC_EXCP_EXTERNAL = 4, /* External input */
96 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
97 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
98 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
99 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
100 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
101 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
102 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
103 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
104 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
105 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
106 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
107 /* Vectors 16 to 31 are reserved */
108 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
109 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
110 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
111 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
112 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
113 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
114 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
115 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
116 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
117 /* Vectors 42 to 63 are reserved */
118 /* Exceptions defined in the PowerPC server specification */
119 /* Server doorbell variants */
120 #define POWERPC_EXCP_SDOOR POWERPC_EXCP_GDOORI
121 #define POWERPC_EXCP_SDOOR_HV POWERPC_EXCP_DOORI
122 POWERPC_EXCP_RESET = 64, /* System reset exception */
123 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
124 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
125 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
126 POWERPC_EXCP_TRACE = 68, /* Trace exception */
127 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
128 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
129 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
130 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
131 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
132 /* 40x specific exceptions */
133 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
134 /* 601 specific exceptions */
135 POWERPC_EXCP_IO = 75, /* IO error exception */
136 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
137 /* 602 specific exceptions */
138 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
139 /* 602/603 specific exceptions */
140 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
141 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
142 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
143 /* Exceptions available on most PowerPC */
144 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
145 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
146 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
147 POWERPC_EXCP_SMI = 84, /* System management interrupt */
148 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
149 /* 7xx/74xx specific exceptions */
150 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
151 /* 74xx specific exceptions */
152 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
153 /* 970FX specific exceptions */
154 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
155 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
156 /* Freescale embedded cores specific exceptions */
157 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
158 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
159 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
160 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
161 /* VSX Unavailable (Power ISA 2.06 and later) */
162 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
163 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
164 /* Additional ISA 2.06 and later server exceptions */
165 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
166 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
167 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
168 /* EOL */
169 POWERPC_EXCP_NB = 99,
170 /* QEMU exceptions: used internally during code translation */
171 POWERPC_EXCP_STOP = 0x200, /* stop translation */
172 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
173 /* QEMU exceptions: special cases we want to stop translation */
174 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
175 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
176 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
177 };
178
179 /* Exceptions error codes */
180 enum {
181 /* Exception subtypes for POWERPC_EXCP_ALIGN */
182 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
183 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
184 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
185 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
186 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
187 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
188 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
189 /* FP exceptions */
190 POWERPC_EXCP_FP = 0x10,
191 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
192 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
193 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
194 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
195 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
196 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
197 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
198 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
199 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
200 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
201 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
202 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
203 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
204 /* Invalid instruction */
205 POWERPC_EXCP_INVAL = 0x20,
206 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
207 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
208 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
209 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
210 /* Privileged instruction */
211 POWERPC_EXCP_PRIV = 0x30,
212 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
213 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
214 /* Trap */
215 POWERPC_EXCP_TRAP = 0x40,
216 };
217
218 #define PPC_INPUT(env) (env->bus_model)
219
220 /*****************************************************************************/
221 typedef struct opc_handler_t opc_handler_t;
222
223 /*****************************************************************************/
224 /* Types used to describe some PowerPC registers */
225 typedef struct DisasContext DisasContext;
226 typedef struct ppc_spr_t ppc_spr_t;
227 typedef union ppc_avr_t ppc_avr_t;
228 typedef union ppc_tlb_t ppc_tlb_t;
229
230 /* SPR access micro-ops generations callbacks */
231 struct ppc_spr_t {
232 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
233 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
234 #if !defined(CONFIG_USER_ONLY)
235 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
236 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
237 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
238 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
239 #endif
240 const char *name;
241 target_ulong default_value;
242 #ifdef CONFIG_KVM
243 /* We (ab)use the fact that all the SPRs will have ids for the
244 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
245 * don't sync this */
246 uint64_t one_reg_id;
247 #endif
248 };
249
250 /* Altivec registers (128 bits) */
251 union ppc_avr_t {
252 float32 f[4];
253 uint8_t u8[16];
254 uint16_t u16[8];
255 uint32_t u32[4];
256 int8_t s8[16];
257 int16_t s16[8];
258 int32_t s32[4];
259 uint64_t u64[2];
260 int64_t s64[2];
261 #ifdef CONFIG_INT128
262 __uint128_t u128;
263 #endif
264 };
265
266 #if !defined(CONFIG_USER_ONLY)
267 /* Software TLB cache */
268 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
269 struct ppc6xx_tlb_t {
270 target_ulong pte0;
271 target_ulong pte1;
272 target_ulong EPN;
273 };
274
275 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
276 struct ppcemb_tlb_t {
277 uint64_t RPN;
278 target_ulong EPN;
279 target_ulong PID;
280 target_ulong size;
281 uint32_t prot;
282 uint32_t attr; /* Storage attributes */
283 };
284
285 typedef struct ppcmas_tlb_t {
286 uint32_t mas8;
287 uint32_t mas1;
288 uint64_t mas2;
289 uint64_t mas7_3;
290 } ppcmas_tlb_t;
291
292 union ppc_tlb_t {
293 ppc6xx_tlb_t *tlb6;
294 ppcemb_tlb_t *tlbe;
295 ppcmas_tlb_t *tlbm;
296 };
297
298 /* possible TLB variants */
299 #define TLB_NONE 0
300 #define TLB_6XX 1
301 #define TLB_EMB 2
302 #define TLB_MAS 3
303 #endif
304
305 #define SDR_32_HTABORG 0xFFFF0000UL
306 #define SDR_32_HTABMASK 0x000001FFUL
307
308 #if defined(TARGET_PPC64)
309 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
310 #define SDR_64_HTABSIZE 0x000000000000001FULL
311 #endif /* defined(TARGET_PPC64 */
312
313 typedef struct ppc_slb_t ppc_slb_t;
314 struct ppc_slb_t {
315 uint64_t esid;
316 uint64_t vsid;
317 const struct ppc_one_seg_page_size *sps;
318 };
319
320 #define MAX_SLB_ENTRIES 64
321 #define SEGMENT_SHIFT_256M 28
322 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
323
324 #define SEGMENT_SHIFT_1T 40
325 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
326
327
328 /*****************************************************************************/
329 /* Machine state register bits definition */
330 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
331 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
332 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
333 #define MSR_SHV 60 /* hypervisor state hflags */
334 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
335 #define MSR_TS1 33
336 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
337 #define MSR_CM 31 /* Computation mode for BookE hflags */
338 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
339 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
340 #define MSR_GS 28 /* guest state for BookE */
341 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
342 #define MSR_VR 25 /* altivec available x hflags */
343 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
344 #define MSR_AP 23 /* Access privilege state on 602 hflags */
345 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
346 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
347 #define MSR_KEY 19 /* key bit on 603e */
348 #define MSR_POW 18 /* Power management */
349 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
350 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
351 #define MSR_ILE 16 /* Interrupt little-endian mode */
352 #define MSR_EE 15 /* External interrupt enable */
353 #define MSR_PR 14 /* Problem state hflags */
354 #define MSR_FP 13 /* Floating point available hflags */
355 #define MSR_ME 12 /* Machine check interrupt enable */
356 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
357 #define MSR_SE 10 /* Single-step trace enable x hflags */
358 #define MSR_DWE 10 /* Debug wait enable on 405 x */
359 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
360 #define MSR_BE 9 /* Branch trace enable x hflags */
361 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
362 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
363 #define MSR_AL 7 /* AL bit on POWER */
364 #define MSR_EP 6 /* Exception prefix on 601 */
365 #define MSR_IR 5 /* Instruction relocate */
366 #define MSR_DR 4 /* Data relocate */
367 #define MSR_IS 5 /* Instruction address space (BookE) */
368 #define MSR_DS 4 /* Data address space (BookE) */
369 #define MSR_PE 3 /* Protection enable on 403 */
370 #define MSR_PX 2 /* Protection exclusive on 403 x */
371 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
372 #define MSR_RI 1 /* Recoverable interrupt 1 */
373 #define MSR_LE 0 /* Little-endian mode 1 hflags */
374
375 /* LPCR bits */
376 #define LPCR_VPM0 (1ull << (63 - 0))
377 #define LPCR_VPM1 (1ull << (63 - 1))
378 #define LPCR_ISL (1ull << (63 - 2))
379 #define LPCR_KBV (1ull << (63 - 3))
380 #define LPCR_ILE (1ull << (63 - 38))
381 #define LPCR_MER (1ull << (63 - 52))
382 #define LPCR_LPES0 (1ull << (63 - 60))
383 #define LPCR_LPES1 (1ull << (63 - 61))
384 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
385 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
386
387 #define msr_sf ((env->msr >> MSR_SF) & 1)
388 #define msr_isf ((env->msr >> MSR_ISF) & 1)
389 #define msr_shv ((env->msr >> MSR_SHV) & 1)
390 #define msr_cm ((env->msr >> MSR_CM) & 1)
391 #define msr_icm ((env->msr >> MSR_ICM) & 1)
392 #define msr_thv ((env->msr >> MSR_THV) & 1)
393 #define msr_gs ((env->msr >> MSR_GS) & 1)
394 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
395 #define msr_vr ((env->msr >> MSR_VR) & 1)
396 #define msr_spe ((env->msr >> MSR_SPE) & 1)
397 #define msr_ap ((env->msr >> MSR_AP) & 1)
398 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
399 #define msr_sa ((env->msr >> MSR_SA) & 1)
400 #define msr_key ((env->msr >> MSR_KEY) & 1)
401 #define msr_pow ((env->msr >> MSR_POW) & 1)
402 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
403 #define msr_ce ((env->msr >> MSR_CE) & 1)
404 #define msr_ile ((env->msr >> MSR_ILE) & 1)
405 #define msr_ee ((env->msr >> MSR_EE) & 1)
406 #define msr_pr ((env->msr >> MSR_PR) & 1)
407 #define msr_fp ((env->msr >> MSR_FP) & 1)
408 #define msr_me ((env->msr >> MSR_ME) & 1)
409 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
410 #define msr_se ((env->msr >> MSR_SE) & 1)
411 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
412 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
413 #define msr_be ((env->msr >> MSR_BE) & 1)
414 #define msr_de ((env->msr >> MSR_DE) & 1)
415 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
416 #define msr_al ((env->msr >> MSR_AL) & 1)
417 #define msr_ep ((env->msr >> MSR_EP) & 1)
418 #define msr_ir ((env->msr >> MSR_IR) & 1)
419 #define msr_dr ((env->msr >> MSR_DR) & 1)
420 #define msr_is ((env->msr >> MSR_IS) & 1)
421 #define msr_ds ((env->msr >> MSR_DS) & 1)
422 #define msr_pe ((env->msr >> MSR_PE) & 1)
423 #define msr_px ((env->msr >> MSR_PX) & 1)
424 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
425 #define msr_ri ((env->msr >> MSR_RI) & 1)
426 #define msr_le ((env->msr >> MSR_LE) & 1)
427 #define msr_ts ((env->msr >> MSR_TS1) & 3)
428 #define msr_tm ((env->msr >> MSR_TM) & 1)
429
430 /* Hypervisor bit is more specific */
431 #if defined(TARGET_PPC64)
432 #define MSR_HVB (1ULL << MSR_SHV)
433 #define msr_hv msr_shv
434 #else
435 #if defined(PPC_EMULATE_32BITS_HYPV)
436 #define MSR_HVB (1ULL << MSR_THV)
437 #define msr_hv msr_thv
438 #else
439 #define MSR_HVB (0ULL)
440 #define msr_hv (0)
441 #endif
442 #endif
443
444 /* Facility Status and Control (FSCR) bits */
445 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
446 #define FSCR_TAR (63 - 55) /* Target Address Register */
447 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
448 #define FSCR_IC_MASK (0xFFULL)
449 #define FSCR_IC_POS (63 - 7)
450 #define FSCR_IC_DSCR_SPR3 2
451 #define FSCR_IC_PMU 3
452 #define FSCR_IC_BHRB 4
453 #define FSCR_IC_TM 5
454 #define FSCR_IC_EBB 7
455 #define FSCR_IC_TAR 8
456
457 /* Exception state register bits definition */
458 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
459 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
460 #define ESR_PTR (1 << (63 - 38)) /* Trap */
461 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
462 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
463 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
464 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
465 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
466 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
467 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
468 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
469 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
470 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
471 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
472 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
473 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
474
475 /* Transaction EXception And Summary Register bits */
476 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
477 #define TEXASR_DISALLOWED (63 - 8)
478 #define TEXASR_NESTING_OVERFLOW (63 - 9)
479 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
480 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
481 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
482 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
483 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
484 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
485 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
486 #define TEXASR_ABORT (63 - 31)
487 #define TEXASR_SUSPENDED (63 - 32)
488 #define TEXASR_PRIVILEGE_HV (63 - 34)
489 #define TEXASR_PRIVILEGE_PR (63 - 35)
490 #define TEXASR_FAILURE_SUMMARY (63 - 36)
491 #define TEXASR_TFIAR_EXACT (63 - 37)
492 #define TEXASR_ROT (63 - 38)
493 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
494
495 enum {
496 POWERPC_FLAG_NONE = 0x00000000,
497 /* Flag for MSR bit 25 signification (VRE/SPE) */
498 POWERPC_FLAG_SPE = 0x00000001,
499 POWERPC_FLAG_VRE = 0x00000002,
500 /* Flag for MSR bit 17 signification (TGPR/CE) */
501 POWERPC_FLAG_TGPR = 0x00000004,
502 POWERPC_FLAG_CE = 0x00000008,
503 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
504 POWERPC_FLAG_SE = 0x00000010,
505 POWERPC_FLAG_DWE = 0x00000020,
506 POWERPC_FLAG_UBLE = 0x00000040,
507 /* Flag for MSR bit 9 signification (BE/DE) */
508 POWERPC_FLAG_BE = 0x00000080,
509 POWERPC_FLAG_DE = 0x00000100,
510 /* Flag for MSR bit 2 signification (PX/PMM) */
511 POWERPC_FLAG_PX = 0x00000200,
512 POWERPC_FLAG_PMM = 0x00000400,
513 /* Flag for special features */
514 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
515 POWERPC_FLAG_RTC_CLK = 0x00010000,
516 POWERPC_FLAG_BUS_CLK = 0x00020000,
517 /* Has CFAR */
518 POWERPC_FLAG_CFAR = 0x00040000,
519 /* Has VSX */
520 POWERPC_FLAG_VSX = 0x00080000,
521 /* Has Transaction Memory (ISA 2.07) */
522 POWERPC_FLAG_TM = 0x00100000,
523 };
524
525 /*****************************************************************************/
526 /* Floating point status and control register */
527 #define FPSCR_FX 31 /* Floating-point exception summary */
528 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
529 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
530 #define FPSCR_OX 28 /* Floating-point overflow exception */
531 #define FPSCR_UX 27 /* Floating-point underflow exception */
532 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
533 #define FPSCR_XX 25 /* Floating-point inexact exception */
534 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
535 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
536 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
537 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
538 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
539 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
540 #define FPSCR_FR 18 /* Floating-point fraction rounded */
541 #define FPSCR_FI 17 /* Floating-point fraction inexact */
542 #define FPSCR_C 16 /* Floating-point result class descriptor */
543 #define FPSCR_FL 15 /* Floating-point less than or negative */
544 #define FPSCR_FG 14 /* Floating-point greater than or negative */
545 #define FPSCR_FE 13 /* Floating-point equal or zero */
546 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
547 #define FPSCR_FPCC 12 /* Floating-point condition code */
548 #define FPSCR_FPRF 12 /* Floating-point result flags */
549 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
550 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
551 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
552 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
553 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
554 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
555 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
556 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
557 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
558 #define FPSCR_RN1 1
559 #define FPSCR_RN 0 /* Floating-point rounding control */
560 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
561 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
562 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
563 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
564 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
565 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
566 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
567 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
568 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
569 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
570 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
571 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
572 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
573 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
574 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
575 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
576 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
577 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
578 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
579 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
580 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
581 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
582 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
583 /* Invalid operation exception summary */
584 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
585 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
586 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
587 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
588 (1 << FPSCR_VXCVI)))
589 /* exception summary */
590 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
591 /* enabled exception summary */
592 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
593 0x1F)
594
595 #define FP_FX (1ull << FPSCR_FX)
596 #define FP_FEX (1ull << FPSCR_FEX)
597 #define FP_VX (1ull << FPSCR_VX)
598 #define FP_OX (1ull << FPSCR_OX)
599 #define FP_UX (1ull << FPSCR_UX)
600 #define FP_ZX (1ull << FPSCR_ZX)
601 #define FP_XX (1ull << FPSCR_XX)
602 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
603 #define FP_VXISI (1ull << FPSCR_VXISI)
604 #define FP_VXIDI (1ull << FPSCR_VXIDI)
605 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
606 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
607 #define FP_VXVC (1ull << FPSCR_VXVC)
608 #define FP_FR (1ull << FSPCR_FR)
609 #define FP_FI (1ull << FPSCR_FI)
610 #define FP_C (1ull << FPSCR_C)
611 #define FP_FL (1ull << FPSCR_FL)
612 #define FP_FG (1ull << FPSCR_FG)
613 #define FP_FE (1ull << FPSCR_FE)
614 #define FP_FU (1ull << FPSCR_FU)
615 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
616 #define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
617 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
618 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
619 #define FP_VXCVI (1ull << FPSCR_VXCVI)
620 #define FP_VE (1ull << FPSCR_VE)
621 #define FP_OE (1ull << FPSCR_OE)
622 #define FP_UE (1ull << FPSCR_UE)
623 #define FP_ZE (1ull << FPSCR_ZE)
624 #define FP_XE (1ull << FPSCR_XE)
625 #define FP_NI (1ull << FPSCR_NI)
626 #define FP_RN1 (1ull << FPSCR_RN1)
627 #define FP_RN (1ull << FPSCR_RN)
628
629 /* the exception bits which can be cleared by mcrfs - includes FX */
630 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
631 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
632 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
633 FP_VXSQRT | FP_VXCVI)
634
635 /*****************************************************************************/
636 /* Vector status and control register */
637 #define VSCR_NJ 16 /* Vector non-java */
638 #define VSCR_SAT 0 /* Vector saturation */
639 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
640 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
641
642 /*****************************************************************************/
643 /* BookE e500 MMU registers */
644
645 #define MAS0_NV_SHIFT 0
646 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
647
648 #define MAS0_WQ_SHIFT 12
649 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
650 /* Write TLB entry regardless of reservation */
651 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
652 /* Write TLB entry only already in use */
653 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
654 /* Clear TLB entry */
655 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
656
657 #define MAS0_HES_SHIFT 14
658 #define MAS0_HES (1 << MAS0_HES_SHIFT)
659
660 #define MAS0_ESEL_SHIFT 16
661 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
662
663 #define MAS0_TLBSEL_SHIFT 28
664 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
665 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
666 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
667 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
668 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
669
670 #define MAS0_ATSEL_SHIFT 31
671 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
672 #define MAS0_ATSEL_TLB 0
673 #define MAS0_ATSEL_LRAT MAS0_ATSEL
674
675 #define MAS1_TSIZE_SHIFT 7
676 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
677
678 #define MAS1_TS_SHIFT 12
679 #define MAS1_TS (1 << MAS1_TS_SHIFT)
680
681 #define MAS1_IND_SHIFT 13
682 #define MAS1_IND (1 << MAS1_IND_SHIFT)
683
684 #define MAS1_TID_SHIFT 16
685 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
686
687 #define MAS1_IPROT_SHIFT 30
688 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
689
690 #define MAS1_VALID_SHIFT 31
691 #define MAS1_VALID 0x80000000
692
693 #define MAS2_EPN_SHIFT 12
694 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
695
696 #define MAS2_ACM_SHIFT 6
697 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
698
699 #define MAS2_VLE_SHIFT 5
700 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
701
702 #define MAS2_W_SHIFT 4
703 #define MAS2_W (1 << MAS2_W_SHIFT)
704
705 #define MAS2_I_SHIFT 3
706 #define MAS2_I (1 << MAS2_I_SHIFT)
707
708 #define MAS2_M_SHIFT 2
709 #define MAS2_M (1 << MAS2_M_SHIFT)
710
711 #define MAS2_G_SHIFT 1
712 #define MAS2_G (1 << MAS2_G_SHIFT)
713
714 #define MAS2_E_SHIFT 0
715 #define MAS2_E (1 << MAS2_E_SHIFT)
716
717 #define MAS3_RPN_SHIFT 12
718 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
719
720 #define MAS3_U0 0x00000200
721 #define MAS3_U1 0x00000100
722 #define MAS3_U2 0x00000080
723 #define MAS3_U3 0x00000040
724 #define MAS3_UX 0x00000020
725 #define MAS3_SX 0x00000010
726 #define MAS3_UW 0x00000008
727 #define MAS3_SW 0x00000004
728 #define MAS3_UR 0x00000002
729 #define MAS3_SR 0x00000001
730 #define MAS3_SPSIZE_SHIFT 1
731 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
732
733 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
734 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
735 #define MAS4_TIDSELD_MASK 0x00030000
736 #define MAS4_TIDSELD_PID0 0x00000000
737 #define MAS4_TIDSELD_PID1 0x00010000
738 #define MAS4_TIDSELD_PID2 0x00020000
739 #define MAS4_TIDSELD_PIDZ 0x00030000
740 #define MAS4_INDD 0x00008000 /* Default IND */
741 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
742 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
743 #define MAS4_ACMD 0x00000040
744 #define MAS4_VLED 0x00000020
745 #define MAS4_WD 0x00000010
746 #define MAS4_ID 0x00000008
747 #define MAS4_MD 0x00000004
748 #define MAS4_GD 0x00000002
749 #define MAS4_ED 0x00000001
750 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
751 #define MAS4_WIMGED_SHIFT 0
752
753 #define MAS5_SGS 0x80000000
754 #define MAS5_SLPID_MASK 0x00000fff
755
756 #define MAS6_SPID0 0x3fff0000
757 #define MAS6_SPID1 0x00007ffe
758 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
759 #define MAS6_SAS 0x00000001
760 #define MAS6_SPID MAS6_SPID0
761 #define MAS6_SIND 0x00000002 /* Indirect page */
762 #define MAS6_SIND_SHIFT 1
763 #define MAS6_SPID_MASK 0x3fff0000
764 #define MAS6_SPID_SHIFT 16
765 #define MAS6_ISIZE_MASK 0x00000f80
766 #define MAS6_ISIZE_SHIFT 7
767
768 #define MAS7_RPN 0xffffffff
769
770 #define MAS8_TGS 0x80000000
771 #define MAS8_VF 0x40000000
772 #define MAS8_TLBPID 0x00000fff
773
774 /* Bit definitions for MMUCFG */
775 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
776 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
777 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
778 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
779 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
780 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
781 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
782 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
783 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
784
785 /* Bit definitions for MMUCSR0 */
786 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
787 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
788 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
789 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
790 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
791 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
792 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
793 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
794 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
795 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
796
797 /* TLBnCFG encoding */
798 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
799 #define TLBnCFG_HES 0x00002000 /* HW select supported */
800 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
801 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
802 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
803 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
804 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
805 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
806 #define TLBnCFG_MINSIZE_SHIFT 20
807 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
808 #define TLBnCFG_MAXSIZE_SHIFT 16
809 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
810 #define TLBnCFG_ASSOC_SHIFT 24
811
812 /* TLBnPS encoding */
813 #define TLBnPS_4K 0x00000004
814 #define TLBnPS_8K 0x00000008
815 #define TLBnPS_16K 0x00000010
816 #define TLBnPS_32K 0x00000020
817 #define TLBnPS_64K 0x00000040
818 #define TLBnPS_128K 0x00000080
819 #define TLBnPS_256K 0x00000100
820 #define TLBnPS_512K 0x00000200
821 #define TLBnPS_1M 0x00000400
822 #define TLBnPS_2M 0x00000800
823 #define TLBnPS_4M 0x00001000
824 #define TLBnPS_8M 0x00002000
825 #define TLBnPS_16M 0x00004000
826 #define TLBnPS_32M 0x00008000
827 #define TLBnPS_64M 0x00010000
828 #define TLBnPS_128M 0x00020000
829 #define TLBnPS_256M 0x00040000
830 #define TLBnPS_512M 0x00080000
831 #define TLBnPS_1G 0x00100000
832 #define TLBnPS_2G 0x00200000
833 #define TLBnPS_4G 0x00400000
834 #define TLBnPS_8G 0x00800000
835 #define TLBnPS_16G 0x01000000
836 #define TLBnPS_32G 0x02000000
837 #define TLBnPS_64G 0x04000000
838 #define TLBnPS_128G 0x08000000
839 #define TLBnPS_256G 0x10000000
840
841 /* tlbilx action encoding */
842 #define TLBILX_T_ALL 0
843 #define TLBILX_T_TID 1
844 #define TLBILX_T_FULLMATCH 3
845 #define TLBILX_T_CLASS0 4
846 #define TLBILX_T_CLASS1 5
847 #define TLBILX_T_CLASS2 6
848 #define TLBILX_T_CLASS3 7
849
850 /* BookE 2.06 helper defines */
851
852 #define BOOKE206_FLUSH_TLB0 (1 << 0)
853 #define BOOKE206_FLUSH_TLB1 (1 << 1)
854 #define BOOKE206_FLUSH_TLB2 (1 << 2)
855 #define BOOKE206_FLUSH_TLB3 (1 << 3)
856
857 /* number of possible TLBs */
858 #define BOOKE206_MAX_TLBN 4
859
860 /*****************************************************************************/
861 /* Embedded.Processor Control */
862
863 #define DBELL_TYPE_SHIFT 27
864 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
865 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
866 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
867 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
868 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
869 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
870
871 #define DBELL_BRDCAST (1 << 26)
872 #define DBELL_LPIDTAG_SHIFT 14
873 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
874 #define DBELL_PIRTAG_MASK 0x3fff
875
876 /*****************************************************************************/
877 /* Segment page size information, used by recent hash MMUs
878 * The format of this structure mirrors kvm_ppc_smmu_info
879 */
880
881 #define PPC_PAGE_SIZES_MAX_SZ 8
882
883 struct ppc_one_page_size {
884 uint32_t page_shift; /* Page shift (or 0) */
885 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
886 };
887
888 struct ppc_one_seg_page_size {
889 uint32_t page_shift; /* Base page shift of segment (or 0) */
890 uint32_t slb_enc; /* SLB encoding for BookS */
891 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
892 };
893
894 struct ppc_segment_page_sizes {
895 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
896 };
897
898
899 /*****************************************************************************/
900 /* The whole PowerPC CPU context */
901 #define NB_MMU_MODES 8
902
903 #define PPC_CPU_OPCODES_LEN 0x40
904 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
905
906 struct CPUPPCState {
907 /* First are the most commonly used resources
908 * during translated code execution
909 */
910 /* general purpose registers */
911 target_ulong gpr[32];
912 /* Storage for GPR MSB, used by the SPE extension */
913 target_ulong gprh[32];
914 /* LR */
915 target_ulong lr;
916 /* CTR */
917 target_ulong ctr;
918 /* condition register */
919 uint32_t crf[8];
920 #if defined(TARGET_PPC64)
921 /* CFAR */
922 target_ulong cfar;
923 #endif
924 /* XER (with SO, OV, CA split out) */
925 target_ulong xer;
926 target_ulong so;
927 target_ulong ov;
928 target_ulong ca;
929 /* Reservation address */
930 target_ulong reserve_addr;
931 /* Reservation value */
932 target_ulong reserve_val;
933 target_ulong reserve_val2;
934 /* Reservation store address */
935 target_ulong reserve_ea;
936 /* Reserved store source register and size */
937 target_ulong reserve_info;
938
939 /* Those ones are used in supervisor mode only */
940 /* machine state register */
941 target_ulong msr;
942 /* temporary general purpose registers */
943 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
944
945 /* Floating point execution context */
946 float_status fp_status;
947 /* floating point registers */
948 float64 fpr[32];
949 /* floating point status and control register */
950 target_ulong fpscr;
951
952 /* Next instruction pointer */
953 target_ulong nip;
954
955 int access_type; /* when a memory exception occurs, the access
956 type is stored here */
957
958 CPU_COMMON
959
960 /* MMU context - only relevant for full system emulation */
961 #if !defined(CONFIG_USER_ONLY)
962 #if defined(TARGET_PPC64)
963 /* PowerPC 64 SLB area */
964 ppc_slb_t slb[MAX_SLB_ENTRIES];
965 int32_t slb_nr;
966 /* tcg TLB needs flush (deferred slb inval instruction typically) */
967 #endif
968 /* segment registers */
969 hwaddr htab_base;
970 /* mask used to normalize hash value to PTEG index */
971 hwaddr htab_mask;
972 target_ulong sr[32];
973 /* externally stored hash table */
974 uint8_t *external_htab;
975 /* BATs */
976 uint32_t nb_BATs;
977 target_ulong DBAT[2][8];
978 target_ulong IBAT[2][8];
979 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
980 int32_t nb_tlb; /* Total number of TLB */
981 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
982 int nb_ways; /* Number of ways in the TLB set */
983 int last_way; /* Last used way used to allocate TLB in a LRU way */
984 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
985 int nb_pids; /* Number of available PID registers */
986 int tlb_type; /* Type of TLB we're dealing with */
987 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
988 /* 403 dedicated access protection registers */
989 target_ulong pb[4];
990 bool tlb_dirty; /* Set to non-zero when modifying TLB */
991 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
992 uint32_t tlb_need_flush; /* Delayed flush needed */
993 #endif
994
995 /* Other registers */
996 /* Special purpose registers */
997 target_ulong spr[1024];
998 ppc_spr_t spr_cb[1024];
999 /* Altivec registers */
1000 ppc_avr_t avr[32];
1001 uint32_t vscr;
1002 /* VSX registers */
1003 uint64_t vsr[32];
1004 /* SPE registers */
1005 uint64_t spe_acc;
1006 uint32_t spe_fscr;
1007 /* SPE and Altivec can share a status since they will never be used
1008 * simultaneously */
1009 float_status vec_status;
1010
1011 /* Internal devices resources */
1012 /* Time base and decrementer */
1013 ppc_tb_t *tb_env;
1014 /* Device control registers */
1015 ppc_dcr_t *dcr_env;
1016
1017 int dcache_line_size;
1018 int icache_line_size;
1019
1020 /* Those resources are used during exception processing */
1021 /* CPU model definition */
1022 target_ulong msr_mask;
1023 powerpc_mmu_t mmu_model;
1024 powerpc_excp_t excp_model;
1025 powerpc_input_t bus_model;
1026 int bfd_mach;
1027 uint32_t flags;
1028 uint64_t insns_flags;
1029 uint64_t insns_flags2;
1030 #if defined(TARGET_PPC64)
1031 struct ppc_segment_page_sizes sps;
1032 bool ci_large_pages;
1033 #endif
1034
1035 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1036 uint64_t vpa_addr;
1037 uint64_t slb_shadow_addr, slb_shadow_size;
1038 uint64_t dtl_addr, dtl_size;
1039 #endif /* TARGET_PPC64 */
1040
1041 int error_code;
1042 uint32_t pending_interrupts;
1043 #if !defined(CONFIG_USER_ONLY)
1044 /* This is the IRQ controller, which is implementation dependent
1045 * and only relevant when emulating a complete machine.
1046 */
1047 uint32_t irq_input_state;
1048 void **irq_inputs;
1049 /* Exception vectors */
1050 target_ulong excp_vectors[POWERPC_EXCP_NB];
1051 target_ulong excp_prefix;
1052 target_ulong ivor_mask;
1053 target_ulong ivpr_mask;
1054 target_ulong hreset_vector;
1055 hwaddr mpic_iack;
1056 /* true when the external proxy facility mode is enabled */
1057 bool mpic_proxy;
1058 /* set when the processor has an HV mode, thus HV priv
1059 * instructions and SPRs are diallowed if MSR:HV is 0
1060 */
1061 bool has_hv_mode;
1062 #endif
1063
1064 /* Those resources are used only during code translation */
1065 /* opcode handlers */
1066 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1067
1068 /* Those resources are used only in QEMU core */
1069 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1070 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1071 int immu_idx; /* precomputed MMU index to speed up insn access */
1072 int dmmu_idx; /* precomputed MMU index to speed up data accesses */
1073
1074 /* Power management */
1075 int (*check_pow)(CPUPPCState *env);
1076
1077 #if !defined(CONFIG_USER_ONLY)
1078 void *load_info; /* Holds boot loading state. */
1079 #endif
1080
1081 /* booke timers */
1082
1083 /* Specifies bit locations of the Time Base used to signal a fixed timer
1084 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1085 *
1086 * 0 selects the least significant bit.
1087 * 63 selects the most significant bit.
1088 */
1089 uint8_t fit_period[4];
1090 uint8_t wdt_period[4];
1091
1092 /* Transactional memory state */
1093 target_ulong tm_gpr[32];
1094 ppc_avr_t tm_vsr[64];
1095 uint64_t tm_cr;
1096 uint64_t tm_lr;
1097 uint64_t tm_ctr;
1098 uint64_t tm_fpscr;
1099 uint64_t tm_amr;
1100 uint64_t tm_ppr;
1101 uint64_t tm_vrsave;
1102 uint32_t tm_vscr;
1103 uint64_t tm_dscr;
1104 uint64_t tm_tar;
1105 };
1106
1107 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1108 do { \
1109 env->fit_period[0] = (a_); \
1110 env->fit_period[1] = (b_); \
1111 env->fit_period[2] = (c_); \
1112 env->fit_period[3] = (d_); \
1113 } while (0)
1114
1115 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1116 do { \
1117 env->wdt_period[0] = (a_); \
1118 env->wdt_period[1] = (b_); \
1119 env->wdt_period[2] = (c_); \
1120 env->wdt_period[3] = (d_); \
1121 } while (0)
1122
1123 /**
1124 * PowerPCCPU:
1125 * @env: #CPUPPCState
1126 * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
1127 * @max_compat: Maximal supported logical PVR from the command line
1128 * @cpu_version: Current logical PVR, zero if in "raw" mode
1129 *
1130 * A PowerPC CPU.
1131 */
1132 struct PowerPCCPU {
1133 /*< private >*/
1134 CPUState parent_obj;
1135 /*< public >*/
1136
1137 CPUPPCState env;
1138 int cpu_dt_id;
1139 uint32_t max_compat;
1140 uint32_t cpu_version;
1141 };
1142
1143 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1144 {
1145 return container_of(env, PowerPCCPU, env);
1146 }
1147
1148 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1149
1150 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1151
1152 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1153 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1154
1155 void ppc_cpu_do_interrupt(CPUState *cpu);
1156 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1157 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1158 int flags);
1159 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1160 fprintf_function cpu_fprintf, int flags);
1161 int ppc_cpu_get_monitor_def(CPUState *cs, const char *name,
1162 uint64_t *pval);
1163 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1164 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1165 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1166 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1167 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1168 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1169 int cpuid, void *opaque);
1170 #ifndef CONFIG_USER_ONLY
1171 void ppc_cpu_do_system_reset(CPUState *cs);
1172 extern const struct VMStateDescription vmstate_ppc_cpu;
1173 #endif
1174
1175 /*****************************************************************************/
1176 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1177 void ppc_translate_init(void);
1178 void gen_update_current_nip(void *opaque);
1179 int cpu_ppc_exec (CPUState *s);
1180 /* you can call this signal handler from your SIGBUS and SIGSEGV
1181 signal handlers to inform the virtual CPU of exceptions. non zero
1182 is returned if the signal was handled by the virtual CPU. */
1183 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1184 void *puc);
1185 #if defined(CONFIG_USER_ONLY)
1186 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1187 int mmu_idx);
1188 #endif
1189
1190 #if !defined(CONFIG_USER_ONLY)
1191 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1192 #endif /* !defined(CONFIG_USER_ONLY) */
1193 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1194
1195 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1196 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1197 #if defined(TARGET_PPC64)
1198 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
1199 #endif
1200
1201 /* Time-base and decrementer management */
1202 #ifndef NO_CPU_IO_DEFS
1203 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1204 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1205 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1206 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1207 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1208 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1209 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1210 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1211 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1212 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1213 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1214 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1215 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1216 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1217 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1218 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1219 #if !defined(CONFIG_USER_ONLY)
1220 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1221 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1222 target_ulong load_40x_pit (CPUPPCState *env);
1223 void store_40x_pit (CPUPPCState *env, target_ulong val);
1224 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1225 void store_40x_sler (CPUPPCState *env, uint32_t val);
1226 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1227 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1228 void ppc_tlb_invalidate_all (CPUPPCState *env);
1229 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1230 void cpu_ppc_set_papr(PowerPCCPU *cpu);
1231 #endif
1232 #endif
1233
1234 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1235
1236 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1237 {
1238 uint64_t gprv;
1239
1240 gprv = env->gpr[gprn];
1241 if (env->flags & POWERPC_FLAG_SPE) {
1242 /* If the CPU implements the SPE extension, we have to get the
1243 * high bits of the GPR from the gprh storage area
1244 */
1245 gprv &= 0xFFFFFFFFULL;
1246 gprv |= (uint64_t)env->gprh[gprn] << 32;
1247 }
1248
1249 return gprv;
1250 }
1251
1252 /* Device control registers */
1253 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1254 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1255
1256 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1257
1258 #define cpu_exec cpu_ppc_exec
1259 #define cpu_signal_handler cpu_ppc_signal_handler
1260 #define cpu_list ppc_cpu_list
1261
1262 /* MMU modes definitions */
1263 #define MMU_USER_IDX 0
1264 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1265 {
1266 return ifetch ? env->immu_idx : env->dmmu_idx;
1267 }
1268
1269 #include "exec/cpu-all.h"
1270
1271 /*****************************************************************************/
1272 /* CRF definitions */
1273 #define CRF_LT 3
1274 #define CRF_GT 2
1275 #define CRF_EQ 1
1276 #define CRF_SO 0
1277 #define CRF_CH (1 << CRF_LT)
1278 #define CRF_CL (1 << CRF_GT)
1279 #define CRF_CH_OR_CL (1 << CRF_EQ)
1280 #define CRF_CH_AND_CL (1 << CRF_SO)
1281
1282 /* XER definitions */
1283 #define XER_SO 31
1284 #define XER_OV 30
1285 #define XER_CA 29
1286 #define XER_CMP 8
1287 #define XER_BC 0
1288 #define xer_so (env->so)
1289 #define xer_ov (env->ov)
1290 #define xer_ca (env->ca)
1291 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1292 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1293
1294 /* SPR definitions */
1295 #define SPR_MQ (0x000)
1296 #define SPR_XER (0x001)
1297 #define SPR_601_VRTCU (0x004)
1298 #define SPR_601_VRTCL (0x005)
1299 #define SPR_601_UDECR (0x006)
1300 #define SPR_LR (0x008)
1301 #define SPR_CTR (0x009)
1302 #define SPR_UAMR (0x00C)
1303 #define SPR_DSCR (0x011)
1304 #define SPR_DSISR (0x012)
1305 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1306 #define SPR_601_RTCU (0x014)
1307 #define SPR_601_RTCL (0x015)
1308 #define SPR_DECR (0x016)
1309 #define SPR_SDR1 (0x019)
1310 #define SPR_SRR0 (0x01A)
1311 #define SPR_SRR1 (0x01B)
1312 #define SPR_CFAR (0x01C)
1313 #define SPR_AMR (0x01D)
1314 #define SPR_ACOP (0x01F)
1315 #define SPR_BOOKE_PID (0x030)
1316 #define SPR_BOOKS_PID (0x030)
1317 #define SPR_BOOKE_DECAR (0x036)
1318 #define SPR_BOOKE_CSRR0 (0x03A)
1319 #define SPR_BOOKE_CSRR1 (0x03B)
1320 #define SPR_BOOKE_DEAR (0x03D)
1321 #define SPR_IAMR (0x03D)
1322 #define SPR_BOOKE_ESR (0x03E)
1323 #define SPR_BOOKE_IVPR (0x03F)
1324 #define SPR_MPC_EIE (0x050)
1325 #define SPR_MPC_EID (0x051)
1326 #define SPR_MPC_NRI (0x052)
1327 #define SPR_TFHAR (0x080)
1328 #define SPR_TFIAR (0x081)
1329 #define SPR_TEXASR (0x082)
1330 #define SPR_TEXASRU (0x083)
1331 #define SPR_UCTRL (0x088)
1332 #define SPR_MPC_CMPA (0x090)
1333 #define SPR_MPC_CMPB (0x091)
1334 #define SPR_MPC_CMPC (0x092)
1335 #define SPR_MPC_CMPD (0x093)
1336 #define SPR_MPC_ECR (0x094)
1337 #define SPR_MPC_DER (0x095)
1338 #define SPR_MPC_COUNTA (0x096)
1339 #define SPR_MPC_COUNTB (0x097)
1340 #define SPR_CTRL (0x098)
1341 #define SPR_MPC_CMPE (0x098)
1342 #define SPR_MPC_CMPF (0x099)
1343 #define SPR_FSCR (0x099)
1344 #define SPR_MPC_CMPG (0x09A)
1345 #define SPR_MPC_CMPH (0x09B)
1346 #define SPR_MPC_LCTRL1 (0x09C)
1347 #define SPR_MPC_LCTRL2 (0x09D)
1348 #define SPR_UAMOR (0x09D)
1349 #define SPR_MPC_ICTRL (0x09E)
1350 #define SPR_MPC_BAR (0x09F)
1351 #define SPR_PSPB (0x09F)
1352 #define SPR_DAWR (0x0B4)
1353 #define SPR_RPR (0x0BA)
1354 #define SPR_CIABR (0x0BB)
1355 #define SPR_DAWRX (0x0BC)
1356 #define SPR_HFSCR (0x0BE)
1357 #define SPR_VRSAVE (0x100)
1358 #define SPR_USPRG0 (0x100)
1359 #define SPR_USPRG1 (0x101)
1360 #define SPR_USPRG2 (0x102)
1361 #define SPR_USPRG3 (0x103)
1362 #define SPR_USPRG4 (0x104)
1363 #define SPR_USPRG5 (0x105)
1364 #define SPR_USPRG6 (0x106)
1365 #define SPR_USPRG7 (0x107)
1366 #define SPR_VTBL (0x10C)
1367 #define SPR_VTBU (0x10D)
1368 #define SPR_SPRG0 (0x110)
1369 #define SPR_SPRG1 (0x111)
1370 #define SPR_SPRG2 (0x112)
1371 #define SPR_SPRG3 (0x113)
1372 #define SPR_SPRG4 (0x114)
1373 #define SPR_SCOMC (0x114)
1374 #define SPR_SPRG5 (0x115)
1375 #define SPR_SCOMD (0x115)
1376 #define SPR_SPRG6 (0x116)
1377 #define SPR_SPRG7 (0x117)
1378 #define SPR_ASR (0x118)
1379 #define SPR_EAR (0x11A)
1380 #define SPR_TBL (0x11C)
1381 #define SPR_TBU (0x11D)
1382 #define SPR_TBU40 (0x11E)
1383 #define SPR_SVR (0x11E)
1384 #define SPR_BOOKE_PIR (0x11E)
1385 #define SPR_PVR (0x11F)
1386 #define SPR_HSPRG0 (0x130)
1387 #define SPR_BOOKE_DBSR (0x130)
1388 #define SPR_HSPRG1 (0x131)
1389 #define SPR_HDSISR (0x132)
1390 #define SPR_HDAR (0x133)
1391 #define SPR_BOOKE_EPCR (0x133)
1392 #define SPR_SPURR (0x134)
1393 #define SPR_BOOKE_DBCR0 (0x134)
1394 #define SPR_IBCR (0x135)
1395 #define SPR_PURR (0x135)
1396 #define SPR_BOOKE_DBCR1 (0x135)
1397 #define SPR_DBCR (0x136)
1398 #define SPR_HDEC (0x136)
1399 #define SPR_BOOKE_DBCR2 (0x136)
1400 #define SPR_HIOR (0x137)
1401 #define SPR_MBAR (0x137)
1402 #define SPR_RMOR (0x138)
1403 #define SPR_BOOKE_IAC1 (0x138)
1404 #define SPR_HRMOR (0x139)
1405 #define SPR_BOOKE_IAC2 (0x139)
1406 #define SPR_HSRR0 (0x13A)
1407 #define SPR_BOOKE_IAC3 (0x13A)
1408 #define SPR_HSRR1 (0x13B)
1409 #define SPR_BOOKE_IAC4 (0x13B)
1410 #define SPR_BOOKE_DAC1 (0x13C)
1411 #define SPR_MMCRH (0x13C)
1412 #define SPR_DABR2 (0x13D)
1413 #define SPR_BOOKE_DAC2 (0x13D)
1414 #define SPR_TFMR (0x13D)
1415 #define SPR_BOOKE_DVC1 (0x13E)
1416 #define SPR_LPCR (0x13E)
1417 #define SPR_BOOKE_DVC2 (0x13F)
1418 #define SPR_LPIDR (0x13F)
1419 #define SPR_BOOKE_TSR (0x150)
1420 #define SPR_HMER (0x150)
1421 #define SPR_HMEER (0x151)
1422 #define SPR_PCR (0x152)
1423 #define SPR_BOOKE_LPIDR (0x152)
1424 #define SPR_BOOKE_TCR (0x154)
1425 #define SPR_BOOKE_TLB0PS (0x158)
1426 #define SPR_BOOKE_TLB1PS (0x159)
1427 #define SPR_BOOKE_TLB2PS (0x15A)
1428 #define SPR_BOOKE_TLB3PS (0x15B)
1429 #define SPR_AMOR (0x15D)
1430 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1431 #define SPR_BOOKE_IVOR0 (0x190)
1432 #define SPR_BOOKE_IVOR1 (0x191)
1433 #define SPR_BOOKE_IVOR2 (0x192)
1434 #define SPR_BOOKE_IVOR3 (0x193)
1435 #define SPR_BOOKE_IVOR4 (0x194)
1436 #define SPR_BOOKE_IVOR5 (0x195)
1437 #define SPR_BOOKE_IVOR6 (0x196)
1438 #define SPR_BOOKE_IVOR7 (0x197)
1439 #define SPR_BOOKE_IVOR8 (0x198)
1440 #define SPR_BOOKE_IVOR9 (0x199)
1441 #define SPR_BOOKE_IVOR10 (0x19A)
1442 #define SPR_BOOKE_IVOR11 (0x19B)
1443 #define SPR_BOOKE_IVOR12 (0x19C)
1444 #define SPR_BOOKE_IVOR13 (0x19D)
1445 #define SPR_BOOKE_IVOR14 (0x19E)
1446 #define SPR_BOOKE_IVOR15 (0x19F)
1447 #define SPR_BOOKE_IVOR38 (0x1B0)
1448 #define SPR_BOOKE_IVOR39 (0x1B1)
1449 #define SPR_BOOKE_IVOR40 (0x1B2)
1450 #define SPR_BOOKE_IVOR41 (0x1B3)
1451 #define SPR_BOOKE_IVOR42 (0x1B4)
1452 #define SPR_BOOKE_GIVOR2 (0x1B8)
1453 #define SPR_BOOKE_GIVOR3 (0x1B9)
1454 #define SPR_BOOKE_GIVOR4 (0x1BA)
1455 #define SPR_BOOKE_GIVOR8 (0x1BB)
1456 #define SPR_BOOKE_GIVOR13 (0x1BC)
1457 #define SPR_BOOKE_GIVOR14 (0x1BD)
1458 #define SPR_TIR (0x1BE)
1459 #define SPR_BOOKE_SPEFSCR (0x200)
1460 #define SPR_Exxx_BBEAR (0x201)
1461 #define SPR_Exxx_BBTAR (0x202)
1462 #define SPR_Exxx_L1CFG0 (0x203)
1463 #define SPR_Exxx_L1CFG1 (0x204)
1464 #define SPR_Exxx_NPIDR (0x205)
1465 #define SPR_ATBL (0x20E)
1466 #define SPR_ATBU (0x20F)
1467 #define SPR_IBAT0U (0x210)
1468 #define SPR_BOOKE_IVOR32 (0x210)
1469 #define SPR_RCPU_MI_GRA (0x210)
1470 #define SPR_IBAT0L (0x211)
1471 #define SPR_BOOKE_IVOR33 (0x211)
1472 #define SPR_IBAT1U (0x212)
1473 #define SPR_BOOKE_IVOR34 (0x212)
1474 #define SPR_IBAT1L (0x213)
1475 #define SPR_BOOKE_IVOR35 (0x213)
1476 #define SPR_IBAT2U (0x214)
1477 #define SPR_BOOKE_IVOR36 (0x214)
1478 #define SPR_IBAT2L (0x215)
1479 #define SPR_BOOKE_IVOR37 (0x215)
1480 #define SPR_IBAT3U (0x216)
1481 #define SPR_IBAT3L (0x217)
1482 #define SPR_DBAT0U (0x218)
1483 #define SPR_RCPU_L2U_GRA (0x218)
1484 #define SPR_DBAT0L (0x219)
1485 #define SPR_DBAT1U (0x21A)
1486 #define SPR_DBAT1L (0x21B)
1487 #define SPR_DBAT2U (0x21C)
1488 #define SPR_DBAT2L (0x21D)
1489 #define SPR_DBAT3U (0x21E)
1490 #define SPR_DBAT3L (0x21F)
1491 #define SPR_IBAT4U (0x230)
1492 #define SPR_RPCU_BBCMCR (0x230)
1493 #define SPR_MPC_IC_CST (0x230)
1494 #define SPR_Exxx_CTXCR (0x230)
1495 #define SPR_IBAT4L (0x231)
1496 #define SPR_MPC_IC_ADR (0x231)
1497 #define SPR_Exxx_DBCR3 (0x231)
1498 #define SPR_IBAT5U (0x232)
1499 #define SPR_MPC_IC_DAT (0x232)
1500 #define SPR_Exxx_DBCNT (0x232)
1501 #define SPR_IBAT5L (0x233)
1502 #define SPR_IBAT6U (0x234)
1503 #define SPR_IBAT6L (0x235)
1504 #define SPR_IBAT7U (0x236)
1505 #define SPR_IBAT7L (0x237)
1506 #define SPR_DBAT4U (0x238)
1507 #define SPR_RCPU_L2U_MCR (0x238)
1508 #define SPR_MPC_DC_CST (0x238)
1509 #define SPR_Exxx_ALTCTXCR (0x238)
1510 #define SPR_DBAT4L (0x239)
1511 #define SPR_MPC_DC_ADR (0x239)
1512 #define SPR_DBAT5U (0x23A)
1513 #define SPR_BOOKE_MCSRR0 (0x23A)
1514 #define SPR_MPC_DC_DAT (0x23A)
1515 #define SPR_DBAT5L (0x23B)
1516 #define SPR_BOOKE_MCSRR1 (0x23B)
1517 #define SPR_DBAT6U (0x23C)
1518 #define SPR_BOOKE_MCSR (0x23C)
1519 #define SPR_DBAT6L (0x23D)
1520 #define SPR_Exxx_MCAR (0x23D)
1521 #define SPR_DBAT7U (0x23E)
1522 #define SPR_BOOKE_DSRR0 (0x23E)
1523 #define SPR_DBAT7L (0x23F)
1524 #define SPR_BOOKE_DSRR1 (0x23F)
1525 #define SPR_BOOKE_SPRG8 (0x25C)
1526 #define SPR_BOOKE_SPRG9 (0x25D)
1527 #define SPR_BOOKE_MAS0 (0x270)
1528 #define SPR_BOOKE_MAS1 (0x271)
1529 #define SPR_BOOKE_MAS2 (0x272)
1530 #define SPR_BOOKE_MAS3 (0x273)
1531 #define SPR_BOOKE_MAS4 (0x274)
1532 #define SPR_BOOKE_MAS5 (0x275)
1533 #define SPR_BOOKE_MAS6 (0x276)
1534 #define SPR_BOOKE_PID1 (0x279)
1535 #define SPR_BOOKE_PID2 (0x27A)
1536 #define SPR_MPC_DPDR (0x280)
1537 #define SPR_MPC_IMMR (0x288)
1538 #define SPR_BOOKE_TLB0CFG (0x2B0)
1539 #define SPR_BOOKE_TLB1CFG (0x2B1)
1540 #define SPR_BOOKE_TLB2CFG (0x2B2)
1541 #define SPR_BOOKE_TLB3CFG (0x2B3)
1542 #define SPR_BOOKE_EPR (0x2BE)
1543 #define SPR_PERF0 (0x300)
1544 #define SPR_RCPU_MI_RBA0 (0x300)
1545 #define SPR_MPC_MI_CTR (0x300)
1546 #define SPR_POWER_USIER (0x300)
1547 #define SPR_PERF1 (0x301)
1548 #define SPR_RCPU_MI_RBA1 (0x301)
1549 #define SPR_POWER_UMMCR2 (0x301)
1550 #define SPR_PERF2 (0x302)
1551 #define SPR_RCPU_MI_RBA2 (0x302)
1552 #define SPR_MPC_MI_AP (0x302)
1553 #define SPR_POWER_UMMCRA (0x302)
1554 #define SPR_PERF3 (0x303)
1555 #define SPR_RCPU_MI_RBA3 (0x303)
1556 #define SPR_MPC_MI_EPN (0x303)
1557 #define SPR_POWER_UPMC1 (0x303)
1558 #define SPR_PERF4 (0x304)
1559 #define SPR_POWER_UPMC2 (0x304)
1560 #define SPR_PERF5 (0x305)
1561 #define SPR_MPC_MI_TWC (0x305)
1562 #define SPR_POWER_UPMC3 (0x305)
1563 #define SPR_PERF6 (0x306)
1564 #define SPR_MPC_MI_RPN (0x306)
1565 #define SPR_POWER_UPMC4 (0x306)
1566 #define SPR_PERF7 (0x307)
1567 #define SPR_POWER_UPMC5 (0x307)
1568 #define SPR_PERF8 (0x308)
1569 #define SPR_RCPU_L2U_RBA0 (0x308)
1570 #define SPR_MPC_MD_CTR (0x308)
1571 #define SPR_POWER_UPMC6 (0x308)
1572 #define SPR_PERF9 (0x309)
1573 #define SPR_RCPU_L2U_RBA1 (0x309)
1574 #define SPR_MPC_MD_CASID (0x309)
1575 #define SPR_970_UPMC7 (0X309)
1576 #define SPR_PERFA (0x30A)
1577 #define SPR_RCPU_L2U_RBA2 (0x30A)
1578 #define SPR_MPC_MD_AP (0x30A)
1579 #define SPR_970_UPMC8 (0X30A)
1580 #define SPR_PERFB (0x30B)
1581 #define SPR_RCPU_L2U_RBA3 (0x30B)
1582 #define SPR_MPC_MD_EPN (0x30B)
1583 #define SPR_POWER_UMMCR0 (0X30B)
1584 #define SPR_PERFC (0x30C)
1585 #define SPR_MPC_MD_TWB (0x30C)
1586 #define SPR_POWER_USIAR (0X30C)
1587 #define SPR_PERFD (0x30D)
1588 #define SPR_MPC_MD_TWC (0x30D)
1589 #define SPR_POWER_USDAR (0X30D)
1590 #define SPR_PERFE (0x30E)
1591 #define SPR_MPC_MD_RPN (0x30E)
1592 #define SPR_POWER_UMMCR1 (0X30E)
1593 #define SPR_PERFF (0x30F)
1594 #define SPR_MPC_MD_TW (0x30F)
1595 #define SPR_UPERF0 (0x310)
1596 #define SPR_POWER_SIER (0x310)
1597 #define SPR_UPERF1 (0x311)
1598 #define SPR_POWER_MMCR2 (0x311)
1599 #define SPR_UPERF2 (0x312)
1600 #define SPR_POWER_MMCRA (0X312)
1601 #define SPR_UPERF3 (0x313)
1602 #define SPR_POWER_PMC1 (0X313)
1603 #define SPR_UPERF4 (0x314)
1604 #define SPR_POWER_PMC2 (0X314)
1605 #define SPR_UPERF5 (0x315)
1606 #define SPR_POWER_PMC3 (0X315)
1607 #define SPR_UPERF6 (0x316)
1608 #define SPR_POWER_PMC4 (0X316)
1609 #define SPR_UPERF7 (0x317)
1610 #define SPR_POWER_PMC5 (0X317)
1611 #define SPR_UPERF8 (0x318)
1612 #define SPR_POWER_PMC6 (0X318)
1613 #define SPR_UPERF9 (0x319)
1614 #define SPR_970_PMC7 (0X319)
1615 #define SPR_UPERFA (0x31A)
1616 #define SPR_970_PMC8 (0X31A)
1617 #define SPR_UPERFB (0x31B)
1618 #define SPR_POWER_MMCR0 (0X31B)
1619 #define SPR_UPERFC (0x31C)
1620 #define SPR_POWER_SIAR (0X31C)
1621 #define SPR_UPERFD (0x31D)
1622 #define SPR_POWER_SDAR (0X31D)
1623 #define SPR_UPERFE (0x31E)
1624 #define SPR_POWER_MMCR1 (0X31E)
1625 #define SPR_UPERFF (0x31F)
1626 #define SPR_RCPU_MI_RA0 (0x320)
1627 #define SPR_MPC_MI_DBCAM (0x320)
1628 #define SPR_BESCRS (0x320)
1629 #define SPR_RCPU_MI_RA1 (0x321)
1630 #define SPR_MPC_MI_DBRAM0 (0x321)
1631 #define SPR_BESCRSU (0x321)
1632 #define SPR_RCPU_MI_RA2 (0x322)
1633 #define SPR_MPC_MI_DBRAM1 (0x322)
1634 #define SPR_BESCRR (0x322)
1635 #define SPR_RCPU_MI_RA3 (0x323)
1636 #define SPR_BESCRRU (0x323)
1637 #define SPR_EBBHR (0x324)
1638 #define SPR_EBBRR (0x325)
1639 #define SPR_BESCR (0x326)
1640 #define SPR_RCPU_L2U_RA0 (0x328)
1641 #define SPR_MPC_MD_DBCAM (0x328)
1642 #define SPR_RCPU_L2U_RA1 (0x329)
1643 #define SPR_MPC_MD_DBRAM0 (0x329)
1644 #define SPR_RCPU_L2U_RA2 (0x32A)
1645 #define SPR_MPC_MD_DBRAM1 (0x32A)
1646 #define SPR_RCPU_L2U_RA3 (0x32B)
1647 #define SPR_TAR (0x32F)
1648 #define SPR_IC (0x350)
1649 #define SPR_VTB (0x351)
1650 #define SPR_MMCRC (0x353)
1651 #define SPR_440_INV0 (0x370)
1652 #define SPR_440_INV1 (0x371)
1653 #define SPR_440_INV2 (0x372)
1654 #define SPR_440_INV3 (0x373)
1655 #define SPR_440_ITV0 (0x374)
1656 #define SPR_440_ITV1 (0x375)
1657 #define SPR_440_ITV2 (0x376)
1658 #define SPR_440_ITV3 (0x377)
1659 #define SPR_440_CCR1 (0x378)
1660 #define SPR_TACR (0x378)
1661 #define SPR_TCSCR (0x379)
1662 #define SPR_CSIGR (0x37a)
1663 #define SPR_DCRIPR (0x37B)
1664 #define SPR_POWER_SPMC1 (0x37C)
1665 #define SPR_POWER_SPMC2 (0x37D)
1666 #define SPR_POWER_MMCRS (0x37E)
1667 #define SPR_WORT (0x37F)
1668 #define SPR_PPR (0x380)
1669 #define SPR_750_GQR0 (0x390)
1670 #define SPR_440_DNV0 (0x390)
1671 #define SPR_750_GQR1 (0x391)
1672 #define SPR_440_DNV1 (0x391)
1673 #define SPR_750_GQR2 (0x392)
1674 #define SPR_440_DNV2 (0x392)
1675 #define SPR_750_GQR3 (0x393)
1676 #define SPR_440_DNV3 (0x393)
1677 #define SPR_750_GQR4 (0x394)
1678 #define SPR_440_DTV0 (0x394)
1679 #define SPR_750_GQR5 (0x395)
1680 #define SPR_440_DTV1 (0x395)
1681 #define SPR_750_GQR6 (0x396)
1682 #define SPR_440_DTV2 (0x396)
1683 #define SPR_750_GQR7 (0x397)
1684 #define SPR_440_DTV3 (0x397)
1685 #define SPR_750_THRM4 (0x398)
1686 #define SPR_750CL_HID2 (0x398)
1687 #define SPR_440_DVLIM (0x398)
1688 #define SPR_750_WPAR (0x399)
1689 #define SPR_440_IVLIM (0x399)
1690 #define SPR_TSCR (0x399)
1691 #define SPR_750_DMAU (0x39A)
1692 #define SPR_750_DMAL (0x39B)
1693 #define SPR_440_RSTCFG (0x39B)
1694 #define SPR_BOOKE_DCDBTRL (0x39C)
1695 #define SPR_BOOKE_DCDBTRH (0x39D)
1696 #define SPR_BOOKE_ICDBTRL (0x39E)
1697 #define SPR_BOOKE_ICDBTRH (0x39F)
1698 #define SPR_74XX_UMMCR2 (0x3A0)
1699 #define SPR_7XX_UPMC5 (0x3A1)
1700 #define SPR_7XX_UPMC6 (0x3A2)
1701 #define SPR_UBAMR (0x3A7)
1702 #define SPR_7XX_UMMCR0 (0x3A8)
1703 #define SPR_7XX_UPMC1 (0x3A9)
1704 #define SPR_7XX_UPMC2 (0x3AA)
1705 #define SPR_7XX_USIAR (0x3AB)
1706 #define SPR_7XX_UMMCR1 (0x3AC)
1707 #define SPR_7XX_UPMC3 (0x3AD)
1708 #define SPR_7XX_UPMC4 (0x3AE)
1709 #define SPR_USDA (0x3AF)
1710 #define SPR_40x_ZPR (0x3B0)
1711 #define SPR_BOOKE_MAS7 (0x3B0)
1712 #define SPR_74XX_MMCR2 (0x3B0)
1713 #define SPR_7XX_PMC5 (0x3B1)
1714 #define SPR_40x_PID (0x3B1)
1715 #define SPR_7XX_PMC6 (0x3B2)
1716 #define SPR_440_MMUCR (0x3B2)
1717 #define SPR_4xx_CCR0 (0x3B3)
1718 #define SPR_BOOKE_EPLC (0x3B3)
1719 #define SPR_405_IAC3 (0x3B4)
1720 #define SPR_BOOKE_EPSC (0x3B4)
1721 #define SPR_405_IAC4 (0x3B5)
1722 #define SPR_405_DVC1 (0x3B6)
1723 #define SPR_405_DVC2 (0x3B7)
1724 #define SPR_BAMR (0x3B7)
1725 #define SPR_7XX_MMCR0 (0x3B8)
1726 #define SPR_7XX_PMC1 (0x3B9)
1727 #define SPR_40x_SGR (0x3B9)
1728 #define SPR_7XX_PMC2 (0x3BA)
1729 #define SPR_40x_DCWR (0x3BA)
1730 #define SPR_7XX_SIAR (0x3BB)
1731 #define SPR_405_SLER (0x3BB)
1732 #define SPR_7XX_MMCR1 (0x3BC)
1733 #define SPR_405_SU0R (0x3BC)
1734 #define SPR_401_SKR (0x3BC)
1735 #define SPR_7XX_PMC3 (0x3BD)
1736 #define SPR_405_DBCR1 (0x3BD)
1737 #define SPR_7XX_PMC4 (0x3BE)
1738 #define SPR_SDA (0x3BF)
1739 #define SPR_403_VTBL (0x3CC)
1740 #define SPR_403_VTBU (0x3CD)
1741 #define SPR_DMISS (0x3D0)
1742 #define SPR_DCMP (0x3D1)
1743 #define SPR_HASH1 (0x3D2)
1744 #define SPR_HASH2 (0x3D3)
1745 #define SPR_BOOKE_ICDBDR (0x3D3)
1746 #define SPR_TLBMISS (0x3D4)
1747 #define SPR_IMISS (0x3D4)
1748 #define SPR_40x_ESR (0x3D4)
1749 #define SPR_PTEHI (0x3D5)
1750 #define SPR_ICMP (0x3D5)
1751 #define SPR_40x_DEAR (0x3D5)
1752 #define SPR_PTELO (0x3D6)
1753 #define SPR_RPA (0x3D6)
1754 #define SPR_40x_EVPR (0x3D6)
1755 #define SPR_L3PM (0x3D7)
1756 #define SPR_403_CDBCR (0x3D7)
1757 #define SPR_L3ITCR0 (0x3D8)
1758 #define SPR_TCR (0x3D8)
1759 #define SPR_40x_TSR (0x3D8)
1760 #define SPR_IBR (0x3DA)
1761 #define SPR_40x_TCR (0x3DA)
1762 #define SPR_ESASRR (0x3DB)
1763 #define SPR_40x_PIT (0x3DB)
1764 #define SPR_403_TBL (0x3DC)
1765 #define SPR_403_TBU (0x3DD)
1766 #define SPR_SEBR (0x3DE)
1767 #define SPR_40x_SRR2 (0x3DE)
1768 #define SPR_SER (0x3DF)
1769 #define SPR_40x_SRR3 (0x3DF)
1770 #define SPR_L3OHCR (0x3E8)
1771 #define SPR_L3ITCR1 (0x3E9)
1772 #define SPR_L3ITCR2 (0x3EA)
1773 #define SPR_L3ITCR3 (0x3EB)
1774 #define SPR_HID0 (0x3F0)
1775 #define SPR_40x_DBSR (0x3F0)
1776 #define SPR_HID1 (0x3F1)
1777 #define SPR_IABR (0x3F2)
1778 #define SPR_40x_DBCR0 (0x3F2)
1779 #define SPR_601_HID2 (0x3F2)
1780 #define SPR_Exxx_L1CSR0 (0x3F2)
1781 #define SPR_ICTRL (0x3F3)
1782 #define SPR_HID2 (0x3F3)
1783 #define SPR_750CL_HID4 (0x3F3)
1784 #define SPR_Exxx_L1CSR1 (0x3F3)
1785 #define SPR_440_DBDR (0x3F3)
1786 #define SPR_LDSTDB (0x3F4)
1787 #define SPR_750_TDCL (0x3F4)
1788 #define SPR_40x_IAC1 (0x3F4)
1789 #define SPR_MMUCSR0 (0x3F4)
1790 #define SPR_970_HID4 (0x3F4)
1791 #define SPR_DABR (0x3F5)
1792 #define DABR_MASK (~(target_ulong)0x7)
1793 #define SPR_Exxx_BUCSR (0x3F5)
1794 #define SPR_40x_IAC2 (0x3F5)
1795 #define SPR_601_HID5 (0x3F5)
1796 #define SPR_40x_DAC1 (0x3F6)
1797 #define SPR_MSSCR0 (0x3F6)
1798 #define SPR_970_HID5 (0x3F6)
1799 #define SPR_MSSSR0 (0x3F7)
1800 #define SPR_MSSCR1 (0x3F7)
1801 #define SPR_DABRX (0x3F7)
1802 #define SPR_40x_DAC2 (0x3F7)
1803 #define SPR_MMUCFG (0x3F7)
1804 #define SPR_LDSTCR (0x3F8)
1805 #define SPR_L2PMCR (0x3F8)
1806 #define SPR_750FX_HID2 (0x3F8)
1807 #define SPR_Exxx_L1FINV0 (0x3F8)
1808 #define SPR_L2CR (0x3F9)
1809 #define SPR_L3CR (0x3FA)
1810 #define SPR_750_TDCH (0x3FA)
1811 #define SPR_IABR2 (0x3FA)
1812 #define SPR_40x_DCCR (0x3FA)
1813 #define SPR_ICTC (0x3FB)
1814 #define SPR_40x_ICCR (0x3FB)
1815 #define SPR_THRM1 (0x3FC)
1816 #define SPR_403_PBL1 (0x3FC)
1817 #define SPR_SP (0x3FD)
1818 #define SPR_THRM2 (0x3FD)
1819 #define SPR_403_PBU1 (0x3FD)
1820 #define SPR_604_HID13 (0x3FD)
1821 #define SPR_LT (0x3FE)
1822 #define SPR_THRM3 (0x3FE)
1823 #define SPR_RCPU_FPECR (0x3FE)
1824 #define SPR_403_PBL2 (0x3FE)
1825 #define SPR_PIR (0x3FF)
1826 #define SPR_403_PBU2 (0x3FF)
1827 #define SPR_601_HID15 (0x3FF)
1828 #define SPR_604_HID15 (0x3FF)
1829 #define SPR_E500_SVR (0x3FF)
1830
1831 /* Disable MAS Interrupt Updates for Hypervisor */
1832 #define EPCR_DMIUH (1 << 22)
1833 /* Disable Guest TLB Management Instructions */
1834 #define EPCR_DGTMI (1 << 23)
1835 /* Guest Interrupt Computation Mode */
1836 #define EPCR_GICM (1 << 24)
1837 /* Interrupt Computation Mode */
1838 #define EPCR_ICM (1 << 25)
1839 /* Disable Embedded Hypervisor Debug */
1840 #define EPCR_DUVD (1 << 26)
1841 /* Instruction Storage Interrupt Directed to Guest State */
1842 #define EPCR_ISIGS (1 << 27)
1843 /* Data Storage Interrupt Directed to Guest State */
1844 #define EPCR_DSIGS (1 << 28)
1845 /* Instruction TLB Error Interrupt Directed to Guest State */
1846 #define EPCR_ITLBGS (1 << 29)
1847 /* Data TLB Error Interrupt Directed to Guest State */
1848 #define EPCR_DTLBGS (1 << 30)
1849 /* External Input Interrupt Directed to Guest State */
1850 #define EPCR_EXTGS (1 << 31)
1851
1852 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1853 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1854 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1855 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1856 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1857
1858 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1859 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1860 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1861 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1862 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1863
1864 /* HID0 bits */
1865 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
1866 #define HID0_DOZE (1 << 23) /* pre-2.06 */
1867 #define HID0_NAP (1 << 22) /* pre-2.06 */
1868 #define HID0_HILE (1ull << (63 - 19)) /* POWER8 */
1869
1870 /*****************************************************************************/
1871 /* PowerPC Instructions types definitions */
1872 enum {
1873 PPC_NONE = 0x0000000000000000ULL,
1874 /* PowerPC base instructions set */
1875 PPC_INSNS_BASE = 0x0000000000000001ULL,
1876 /* integer operations instructions */
1877 #define PPC_INTEGER PPC_INSNS_BASE
1878 /* flow control instructions */
1879 #define PPC_FLOW PPC_INSNS_BASE
1880 /* virtual memory instructions */
1881 #define PPC_MEM PPC_INSNS_BASE
1882 /* ld/st with reservation instructions */
1883 #define PPC_RES PPC_INSNS_BASE
1884 /* spr/msr access instructions */
1885 #define PPC_MISC PPC_INSNS_BASE
1886 /* Deprecated instruction sets */
1887 /* Original POWER instruction set */
1888 PPC_POWER = 0x0000000000000002ULL,
1889 /* POWER2 instruction set extension */
1890 PPC_POWER2 = 0x0000000000000004ULL,
1891 /* Power RTC support */
1892 PPC_POWER_RTC = 0x0000000000000008ULL,
1893 /* Power-to-PowerPC bridge (601) */
1894 PPC_POWER_BR = 0x0000000000000010ULL,
1895 /* 64 bits PowerPC instruction set */
1896 PPC_64B = 0x0000000000000020ULL,
1897 /* New 64 bits extensions (PowerPC 2.0x) */
1898 PPC_64BX = 0x0000000000000040ULL,
1899 /* 64 bits hypervisor extensions */
1900 PPC_64H = 0x0000000000000080ULL,
1901 /* New wait instruction (PowerPC 2.0x) */
1902 PPC_WAIT = 0x0000000000000100ULL,
1903 /* Time base mftb instruction */
1904 PPC_MFTB = 0x0000000000000200ULL,
1905
1906 /* Fixed-point unit extensions */
1907 /* PowerPC 602 specific */
1908 PPC_602_SPEC = 0x0000000000000400ULL,
1909 /* isel instruction */
1910 PPC_ISEL = 0x0000000000000800ULL,
1911 /* popcntb instruction */
1912 PPC_POPCNTB = 0x0000000000001000ULL,
1913 /* string load / store */
1914 PPC_STRING = 0x0000000000002000ULL,
1915 /* real mode cache inhibited load / store */
1916 PPC_CILDST = 0x0000000000004000ULL,
1917
1918 /* Floating-point unit extensions */
1919 /* Optional floating point instructions */
1920 PPC_FLOAT = 0x0000000000010000ULL,
1921 /* New floating-point extensions (PowerPC 2.0x) */
1922 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1923 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1924 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1925 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1926 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1927 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1928 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1929
1930 /* Vector/SIMD extensions */
1931 /* Altivec support */
1932 PPC_ALTIVEC = 0x0000000001000000ULL,
1933 /* PowerPC 2.03 SPE extension */
1934 PPC_SPE = 0x0000000002000000ULL,
1935 /* PowerPC 2.03 SPE single-precision floating-point extension */
1936 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1937 /* PowerPC 2.03 SPE double-precision floating-point extension */
1938 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1939
1940 /* Optional memory control instructions */
1941 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1942 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1943 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1944 /* sync instruction */
1945 PPC_MEM_SYNC = 0x0000000080000000ULL,
1946 /* eieio instruction */
1947 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1948
1949 /* Cache control instructions */
1950 PPC_CACHE = 0x0000000200000000ULL,
1951 /* icbi instruction */
1952 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1953 /* dcbz instruction */
1954 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1955 /* dcba instruction */
1956 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1957 /* Freescale cache locking instructions */
1958 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1959
1960 /* MMU related extensions */
1961 /* external control instructions */
1962 PPC_EXTERN = 0x0000010000000000ULL,
1963 /* segment register access instructions */
1964 PPC_SEGMENT = 0x0000020000000000ULL,
1965 /* PowerPC 6xx TLB management instructions */
1966 PPC_6xx_TLB = 0x0000040000000000ULL,
1967 /* PowerPC 74xx TLB management instructions */
1968 PPC_74xx_TLB = 0x0000080000000000ULL,
1969 /* PowerPC 40x TLB management instructions */
1970 PPC_40x_TLB = 0x0000100000000000ULL,
1971 /* segment register access instructions for PowerPC 64 "bridge" */
1972 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1973 /* SLB management */
1974 PPC_SLBI = 0x0000400000000000ULL,
1975
1976 /* Embedded PowerPC dedicated instructions */
1977 PPC_WRTEE = 0x0001000000000000ULL,
1978 /* PowerPC 40x exception model */
1979 PPC_40x_EXCP = 0x0002000000000000ULL,
1980 /* PowerPC 405 Mac instructions */
1981 PPC_405_MAC = 0x0004000000000000ULL,
1982 /* PowerPC 440 specific instructions */
1983 PPC_440_SPEC = 0x0008000000000000ULL,
1984 /* BookE (embedded) PowerPC specification */
1985 PPC_BOOKE = 0x0010000000000000ULL,
1986 /* mfapidi instruction */
1987 PPC_MFAPIDI = 0x0020000000000000ULL,
1988 /* tlbiva instruction */
1989 PPC_TLBIVA = 0x0040000000000000ULL,
1990 /* tlbivax instruction */
1991 PPC_TLBIVAX = 0x0080000000000000ULL,
1992 /* PowerPC 4xx dedicated instructions */
1993 PPC_4xx_COMMON = 0x0100000000000000ULL,
1994 /* PowerPC 40x ibct instructions */
1995 PPC_40x_ICBT = 0x0200000000000000ULL,
1996 /* rfmci is not implemented in all BookE PowerPC */
1997 PPC_RFMCI = 0x0400000000000000ULL,
1998 /* rfdi instruction */
1999 PPC_RFDI = 0x0800000000000000ULL,
2000 /* DCR accesses */
2001 PPC_DCR = 0x1000000000000000ULL,
2002 /* DCR extended accesse */
2003 PPC_DCRX = 0x2000000000000000ULL,
2004 /* user-mode DCR access, implemented in PowerPC 460 */
2005 PPC_DCRUX = 0x4000000000000000ULL,
2006 /* popcntw and popcntd instructions */
2007 PPC_POPCNTWD = 0x8000000000000000ULL,
2008
2009 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2010 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2011 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2012 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2013 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2014 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2015 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2016 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2017 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2018 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2019 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2020 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2021 | PPC_CACHE | PPC_CACHE_ICBI \
2022 | PPC_CACHE_DCBZ \
2023 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2024 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2025 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2026 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2027 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2028 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2029 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2030 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2031 | PPC_POPCNTWD | PPC_CILDST)
2032
2033 /* extended type values */
2034
2035 /* BookE 2.06 PowerPC specification */
2036 PPC2_BOOKE206 = 0x0000000000000001ULL,
2037 /* VSX (extensions to Altivec / VMX) */
2038 PPC2_VSX = 0x0000000000000002ULL,
2039 /* Decimal Floating Point (DFP) */
2040 PPC2_DFP = 0x0000000000000004ULL,
2041 /* Embedded.Processor Control */
2042 PPC2_PRCNTL = 0x0000000000000008ULL,
2043 /* Byte-reversed, indexed, double-word load and store */
2044 PPC2_DBRX = 0x0000000000000010ULL,
2045 /* Book I 2.05 PowerPC specification */
2046 PPC2_ISA205 = 0x0000000000000020ULL,
2047 /* VSX additions in ISA 2.07 */
2048 PPC2_VSX207 = 0x0000000000000040ULL,
2049 /* ISA 2.06B bpermd */
2050 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2051 /* ISA 2.06B divide extended variants */
2052 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2053 /* ISA 2.06B larx/stcx. instructions */
2054 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2055 /* ISA 2.06B floating point integer conversion */
2056 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2057 /* ISA 2.06B floating point test instructions */
2058 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2059 /* ISA 2.07 bctar instruction */
2060 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2061 /* ISA 2.07 load/store quadword */
2062 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2063 /* ISA 2.07 Altivec */
2064 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2065 /* PowerISA 2.07 Book3s specification */
2066 PPC2_ISA207S = 0x0000000000008000ULL,
2067 /* Double precision floating point conversion for signed integer 64 */
2068 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2069 /* Transactional Memory (ISA 2.07, Book II) */
2070 PPC2_TM = 0x0000000000020000ULL,
2071
2072 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2073 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2074 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2075 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2076 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2077 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2078 PPC2_FP_CVT_S64 | PPC2_TM)
2079 };
2080
2081 /*****************************************************************************/
2082 /* Memory access type :
2083 * may be needed for precise access rights control and precise exceptions.
2084 */
2085 enum {
2086 /* 1 bit to define user level / supervisor access */
2087 ACCESS_USER = 0x00,
2088 ACCESS_SUPER = 0x01,
2089 /* Type of instruction that generated the access */
2090 ACCESS_CODE = 0x10, /* Code fetch access */
2091 ACCESS_INT = 0x20, /* Integer load/store access */
2092 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2093 ACCESS_RES = 0x40, /* load/store with reservation */
2094 ACCESS_EXT = 0x50, /* external access */
2095 ACCESS_CACHE = 0x60, /* Cache manipulation */
2096 };
2097
2098 /* Hardware interruption sources:
2099 * all those exception can be raised simulteaneously
2100 */
2101 /* Input pins definitions */
2102 enum {
2103 /* 6xx bus input pins */
2104 PPC6xx_INPUT_HRESET = 0,
2105 PPC6xx_INPUT_SRESET = 1,
2106 PPC6xx_INPUT_CKSTP_IN = 2,
2107 PPC6xx_INPUT_MCP = 3,
2108 PPC6xx_INPUT_SMI = 4,
2109 PPC6xx_INPUT_INT = 5,
2110 PPC6xx_INPUT_TBEN = 6,
2111 PPC6xx_INPUT_WAKEUP = 7,
2112 PPC6xx_INPUT_NB,
2113 };
2114
2115 enum {
2116 /* Embedded PowerPC input pins */
2117 PPCBookE_INPUT_HRESET = 0,
2118 PPCBookE_INPUT_SRESET = 1,
2119 PPCBookE_INPUT_CKSTP_IN = 2,
2120 PPCBookE_INPUT_MCP = 3,
2121 PPCBookE_INPUT_SMI = 4,
2122 PPCBookE_INPUT_INT = 5,
2123 PPCBookE_INPUT_CINT = 6,
2124 PPCBookE_INPUT_NB,
2125 };
2126
2127 enum {
2128 /* PowerPC E500 input pins */
2129 PPCE500_INPUT_RESET_CORE = 0,
2130 PPCE500_INPUT_MCK = 1,
2131 PPCE500_INPUT_CINT = 3,
2132 PPCE500_INPUT_INT = 4,
2133 PPCE500_INPUT_DEBUG = 6,
2134 PPCE500_INPUT_NB,
2135 };
2136
2137 enum {
2138 /* PowerPC 40x input pins */
2139 PPC40x_INPUT_RESET_CORE = 0,
2140 PPC40x_INPUT_RESET_CHIP = 1,
2141 PPC40x_INPUT_RESET_SYS = 2,
2142 PPC40x_INPUT_CINT = 3,
2143 PPC40x_INPUT_INT = 4,
2144 PPC40x_INPUT_HALT = 5,
2145 PPC40x_INPUT_DEBUG = 6,
2146 PPC40x_INPUT_NB,
2147 };
2148
2149 enum {
2150 /* RCPU input pins */
2151 PPCRCPU_INPUT_PORESET = 0,
2152 PPCRCPU_INPUT_HRESET = 1,
2153 PPCRCPU_INPUT_SRESET = 2,
2154 PPCRCPU_INPUT_IRQ0 = 3,
2155 PPCRCPU_INPUT_IRQ1 = 4,
2156 PPCRCPU_INPUT_IRQ2 = 5,
2157 PPCRCPU_INPUT_IRQ3 = 6,
2158 PPCRCPU_INPUT_IRQ4 = 7,
2159 PPCRCPU_INPUT_IRQ5 = 8,
2160 PPCRCPU_INPUT_IRQ6 = 9,
2161 PPCRCPU_INPUT_IRQ7 = 10,
2162 PPCRCPU_INPUT_NB,
2163 };
2164
2165 #if defined(TARGET_PPC64)
2166 enum {
2167 /* PowerPC 970 input pins */
2168 PPC970_INPUT_HRESET = 0,
2169 PPC970_INPUT_SRESET = 1,
2170 PPC970_INPUT_CKSTP = 2,
2171 PPC970_INPUT_TBEN = 3,
2172 PPC970_INPUT_MCP = 4,
2173 PPC970_INPUT_INT = 5,
2174 PPC970_INPUT_THINT = 6,
2175 PPC970_INPUT_NB,
2176 };
2177
2178 enum {
2179 /* POWER7 input pins */
2180 POWER7_INPUT_INT = 0,
2181 /* POWER7 probably has other inputs, but we don't care about them
2182 * for any existing machine. We can wire these up when we need
2183 * them */
2184 POWER7_INPUT_NB,
2185 };
2186 #endif
2187
2188 /* Hardware exceptions definitions */
2189 enum {
2190 /* External hardware exception sources */
2191 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2192 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2193 PPC_INTERRUPT_MCK, /* Machine check exception */
2194 PPC_INTERRUPT_EXT, /* External interrupt */
2195 PPC_INTERRUPT_SMI, /* System management interrupt */
2196 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2197 PPC_INTERRUPT_DEBUG, /* External debug exception */
2198 PPC_INTERRUPT_THERM, /* Thermal exception */
2199 /* Internal hardware exception sources */
2200 PPC_INTERRUPT_DECR, /* Decrementer exception */
2201 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2202 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2203 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2204 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2205 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2206 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2207 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2208 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
2209 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
2210 };
2211
2212 /* Processor Compatibility mask (PCR) */
2213 enum {
2214 PCR_COMPAT_2_05 = 1ull << (63-62),
2215 PCR_COMPAT_2_06 = 1ull << (63-61),
2216 PCR_COMPAT_2_07 = 1ull << (63-60),
2217 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2218 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2219 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2220 };
2221
2222 /* HMER/HMEER */
2223 enum {
2224 HMER_MALFUNCTION_ALERT = 1ull << (63 - 0),
2225 HMER_PROC_RECV_DONE = 1ull << (63 - 2),
2226 HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2227 HMER_TFAC_ERROR = 1ull << (63 - 4),
2228 HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5),
2229 HMER_XSCOM_FAIL = 1ull << (63 - 8),
2230 HMER_XSCOM_DONE = 1ull << (63 - 9),
2231 HMER_PROC_RECV_AGAIN = 1ull << (63 - 11),
2232 HMER_WARN_RISE = 1ull << (63 - 14),
2233 HMER_WARN_FALL = 1ull << (63 - 15),
2234 HMER_SCOM_FIR_HMI = 1ull << (63 - 16),
2235 HMER_TRIG_FIR_HMI = 1ull << (63 - 17),
2236 HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20),
2237 HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23),
2238 HMER_XSCOM_STATUS_LSH = (63 - 23),
2239 };
2240
2241 /* Alternate Interrupt Location (AIL) */
2242 enum {
2243 AIL_NONE = 0,
2244 AIL_RESERVED = 1,
2245 AIL_0001_8000 = 2,
2246 AIL_C000_0000_0000_4000 = 3,
2247 };
2248
2249 /*****************************************************************************/
2250
2251 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2252 {
2253 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2254 }
2255
2256 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2257 {
2258 env->so = (xer >> XER_SO) & 1;
2259 env->ov = (xer >> XER_OV) & 1;
2260 env->ca = (xer >> XER_CA) & 1;
2261 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2262 }
2263
2264 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2265 target_ulong *cs_base, uint32_t *flags)
2266 {
2267 *pc = env->nip;
2268 *cs_base = 0;
2269 *flags = env->hflags;
2270 }
2271
2272 #if !defined(CONFIG_USER_ONLY)
2273 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2274 {
2275 uintptr_t tlbml = (uintptr_t)tlbm;
2276 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2277
2278 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2279 }
2280
2281 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2282 {
2283 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2284 int r = tlbncfg & TLBnCFG_N_ENTRY;
2285 return r;
2286 }
2287
2288 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2289 {
2290 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2291 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2292 return r;
2293 }
2294
2295 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2296 {
2297 int id = booke206_tlbm_id(env, tlbm);
2298 int end = 0;
2299 int i;
2300
2301 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2302 end += booke206_tlb_size(env, i);
2303 if (id < end) {
2304 return i;
2305 }
2306 }
2307
2308 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2309 return 0;
2310 }
2311
2312 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2313 {
2314 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2315 int tlbid = booke206_tlbm_id(env, tlb);
2316 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2317 }
2318
2319 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2320 target_ulong ea, int way)
2321 {
2322 int r;
2323 uint32_t ways = booke206_tlb_ways(env, tlbn);
2324 int ways_bits = ctz32(ways);
2325 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2326 int i;
2327
2328 way &= ways - 1;
2329 ea >>= MAS2_EPN_SHIFT;
2330 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2331 r = (ea << ways_bits) | way;
2332
2333 if (r >= booke206_tlb_size(env, tlbn)) {
2334 return NULL;
2335 }
2336
2337 /* bump up to tlbn index */
2338 for (i = 0; i < tlbn; i++) {
2339 r += booke206_tlb_size(env, i);
2340 }
2341
2342 return &env->tlb.tlbm[r];
2343 }
2344
2345 /* returns bitmap of supported page sizes for a given TLB */
2346 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2347 {
2348 bool mav2 = false;
2349 uint32_t ret = 0;
2350
2351 if (mav2) {
2352 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2353 } else {
2354 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2355 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2356 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2357 int i;
2358 for (i = min; i <= max; i++) {
2359 ret |= (1 << (i << 1));
2360 }
2361 }
2362
2363 return ret;
2364 }
2365
2366 #endif
2367
2368 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2369 {
2370 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2371 return msr & (1ULL << MSR_CM);
2372 }
2373
2374 return msr & (1ULL << MSR_SF);
2375 }
2376
2377 /**
2378 * Check whether register rx is in the range between start and
2379 * start + nregs (as needed by the LSWX and LSWI instructions)
2380 */
2381 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2382 {
2383 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2384 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2385 }
2386
2387 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2388
2389 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2390
2391 /**
2392 * ppc_get_vcpu_dt_id:
2393 * @cs: a PowerPCCPU struct.
2394 *
2395 * Returns a device-tree ID for a CPU.
2396 */
2397 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2398
2399 /**
2400 * ppc_get_vcpu_by_dt_id:
2401 * @cpu_dt_id: a device tree id
2402 *
2403 * Searches for a CPU by @cpu_dt_id.
2404 *
2405 * Returns: a PowerPCCPU struct
2406 */
2407 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2408
2409 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2410 #endif /* !defined (__CPU_PPC_H__) */
QEmu