2 * ARM GICv3 emulation: Redistributor
4 * Copyright (c) 2015 Huawei.
5 * Copyright (c) 2016 Linaro Limited.
6 * Written by Shlomo Pongratz, Peter Maydell
8 * This code is licensed under the GPL, version 2 or (at your option)
12 #include "qemu/osdep.h"
15 #include "gicv3_internal.h"
17 static uint32_t mask_group(GICv3CPUState
*cs
, MemTxAttrs attrs
)
19 /* Return a 32-bit mask which should be applied for this set of 32
20 * interrupts; each bit is 1 if access is permitted by the
21 * combination of attrs.secure and GICR_GROUPR. (GICR_NSACR does
22 * not affect config register accesses, unlike GICD_NSACR.)
24 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
25 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI */
26 return cs
->gicr_igroupr0
;
31 static int gicr_ns_access(GICv3CPUState
*cs
, int irq
)
33 /* Return the 2 bit NSACR.NS_access field for this SGI */
35 return extract32(cs
->gicr_nsacr
, irq
* 2, 2);
38 static void gicr_write_set_bitmap_reg(GICv3CPUState
*cs
, MemTxAttrs attrs
,
39 uint32_t *reg
, uint32_t val
)
41 /* Helper routine to implement writing to a "set-bitmap" register */
42 val
&= mask_group(cs
, attrs
);
44 gicv3_redist_update(cs
);
47 static void gicr_write_clear_bitmap_reg(GICv3CPUState
*cs
, MemTxAttrs attrs
,
48 uint32_t *reg
, uint32_t val
)
50 /* Helper routine to implement writing to a "clear-bitmap" register */
51 val
&= mask_group(cs
, attrs
);
53 gicv3_redist_update(cs
);
56 static uint32_t gicr_read_bitmap_reg(GICv3CPUState
*cs
, MemTxAttrs attrs
,
59 reg
&= mask_group(cs
, attrs
);
64 * update_for_one_lpi: Update pending information if this LPI is better
67 * @irq: interrupt to look up in the LPI Configuration table
68 * @ctbase: physical address of the LPI Configuration table to use
69 * @ds: true if priority value should not be shifted
70 * @hpp: points to pending information to update
72 * Look up @irq in the Configuration table specified by @ctbase
73 * to see if it is enabled and what its priority is. If it is an
74 * enabled interrupt with a higher priority than that currently
75 * recorded in @hpp, update @hpp.
77 static void update_for_one_lpi(GICv3CPUState
*cs
, int irq
,
78 uint64_t ctbase
, bool ds
, PendingIrq
*hpp
)
83 address_space_read(&cs
->gic
->dma_as
,
84 ctbase
+ ((irq
- GICV3_LPI_INTID_START
) * sizeof(lpite
)),
85 MEMTXATTRS_UNSPECIFIED
, &lpite
, sizeof(lpite
));
87 if (!(lpite
& LPI_CTE_ENABLED
)) {
92 prio
= lpite
& LPI_PRIORITY_MASK
;
94 prio
= ((lpite
& LPI_PRIORITY_MASK
) >> 1) | 0x80;
97 if ((prio
< hpp
->prio
) ||
98 ((prio
== hpp
->prio
) && (irq
<= hpp
->irq
))) {
101 /* LPIs and vLPIs are always non-secure Grp1 interrupts */
102 hpp
->grp
= GICV3_G1NS
;
107 * update_for_all_lpis: Fully scan LPI tables and find best pending LPI
110 * @ptbase: physical address of LPI Pending table
111 * @ctbase: physical address of LPI Configuration table
112 * @ptsizebits: size of tables, specified as number of interrupt ID bits minus 1
113 * @ds: true if priority value should not be shifted
114 * @hpp: points to pending information to set
116 * Recalculate the highest priority pending enabled LPI from scratch,
117 * and set @hpp accordingly.
119 * We scan the LPI pending table @ptbase; for each pending LPI, we read the
120 * corresponding entry in the LPI configuration table @ctbase to extract
121 * the priority and enabled information.
123 * We take @ptsizebits in the form idbits-1 because this is the way that
124 * LPI table sizes are architecturally specified in GICR_PROPBASER.IDBits
125 * and in the VMAPP command's VPT_size field.
127 static void update_for_all_lpis(GICv3CPUState
*cs
, uint64_t ptbase
,
128 uint64_t ctbase
, unsigned ptsizebits
,
129 bool ds
, PendingIrq
*hpp
)
131 AddressSpace
*as
= &cs
->gic
->dma_as
;
133 uint32_t pendt_size
= (1ULL << (ptsizebits
+ 1));
138 for (i
= GICV3_LPI_INTID_START
/ 8; i
< pendt_size
/ 8; i
++) {
139 address_space_read(as
, ptbase
+ i
, MEMTXATTRS_UNSPECIFIED
, &pend
, 1);
142 update_for_one_lpi(cs
, i
* 8 + bit
, ctbase
, ds
, hpp
);
149 * set_lpi_pending_bit: Set or clear pending bit for an LPI
152 * @ptbase: physical address of LPI Pending table
153 * @irq: LPI to change pending state for
154 * @level: false to clear pending state, true to set
156 * Returns true if we needed to do something, false if the pending bit
157 * was already at @level.
159 static bool set_pending_table_bit(GICv3CPUState
*cs
, uint64_t ptbase
,
162 AddressSpace
*as
= &cs
->gic
->dma_as
;
163 uint64_t addr
= ptbase
+ irq
/ 8;
166 address_space_read(as
, addr
, MEMTXATTRS_UNSPECIFIED
, &pend
, 1);
167 if (extract32(pend
, irq
% 8, 1) == level
) {
168 /* Bit already at requested state, no action required */
171 pend
= deposit32(pend
, irq
% 8, 1, level
? 1 : 0);
172 address_space_write(as
, addr
, MEMTXATTRS_UNSPECIFIED
, &pend
, 1);
176 static uint8_t gicr_read_ipriorityr(GICv3CPUState
*cs
, MemTxAttrs attrs
,
179 /* Read the value of GICR_IPRIORITYR<n> for the specified interrupt,
180 * honouring security state (these are RAZ/WI for Group 0 or Secure
181 * Group 1 interrupts).
185 prio
= cs
->gicr_ipriorityr
[irq
];
187 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
188 if (!(cs
->gicr_igroupr0
& (1U << irq
))) {
189 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
192 /* NS view of the interrupt priority */
193 prio
= (prio
<< 1) & 0xff;
198 static void gicr_write_ipriorityr(GICv3CPUState
*cs
, MemTxAttrs attrs
, int irq
,
201 /* Write the value of GICD_IPRIORITYR<n> for the specified interrupt,
202 * honouring security state (these are RAZ/WI for Group 0 or Secure
203 * Group 1 interrupts).
205 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
206 if (!(cs
->gicr_igroupr0
& (1U << irq
))) {
207 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
210 /* NS view of the interrupt priority */
211 value
= 0x80 | (value
>> 1);
213 cs
->gicr_ipriorityr
[irq
] = value
;
216 static void gicv3_redist_update_vlpi_only(GICv3CPUState
*cs
)
218 uint64_t ptbase
, ctbase
, idbits
;
220 if (!FIELD_EX64(cs
->gicr_vpendbaser
, GICR_VPENDBASER
, VALID
)) {
221 cs
->hppvlpi
.prio
= 0xff;
225 ptbase
= cs
->gicr_vpendbaser
& R_GICR_VPENDBASER_PHYADDR_MASK
;
226 ctbase
= cs
->gicr_vpropbaser
& R_GICR_VPROPBASER_PHYADDR_MASK
;
227 idbits
= FIELD_EX64(cs
->gicr_vpropbaser
, GICR_VPROPBASER
, IDBITS
);
229 update_for_all_lpis(cs
, ptbase
, ctbase
, idbits
, true, &cs
->hppvlpi
);
232 static void gicv3_redist_update_vlpi(GICv3CPUState
*cs
)
234 gicv3_redist_update_vlpi_only(cs
);
235 gicv3_cpuif_virt_irq_fiq_update(cs
);
238 static void gicr_write_vpendbaser(GICv3CPUState
*cs
, uint64_t newval
)
240 /* Write @newval to GICR_VPENDBASER, handling its effects */
241 bool oldvalid
= FIELD_EX64(cs
->gicr_vpendbaser
, GICR_VPENDBASER
, VALID
);
242 bool newvalid
= FIELD_EX64(newval
, GICR_VPENDBASER
, VALID
);
246 * The DIRTY bit is read-only and for us is always zero;
247 * other fields are writeable.
249 newval
&= R_GICR_VPENDBASER_INNERCACHE_MASK
|
250 R_GICR_VPENDBASER_SHAREABILITY_MASK
|
251 R_GICR_VPENDBASER_PHYADDR_MASK
|
252 R_GICR_VPENDBASER_OUTERCACHE_MASK
|
253 R_GICR_VPENDBASER_PENDINGLAST_MASK
|
254 R_GICR_VPENDBASER_IDAI_MASK
|
255 R_GICR_VPENDBASER_VALID_MASK
;
257 if (oldvalid
&& newvalid
) {
259 * Changing other fields while VALID is 1 is UNPREDICTABLE;
260 * we choose to log and ignore the write.
262 if (cs
->gicr_vpendbaser
^ newval
) {
263 qemu_log_mask(LOG_GUEST_ERROR
,
264 "%s: Changing GICR_VPENDBASER when VALID=1 "
265 "is UNPREDICTABLE\n", __func__
);
269 if (!oldvalid
&& !newvalid
) {
270 cs
->gicr_vpendbaser
= newval
;
276 * Valid going from 0 to 1: update hppvlpi from tables.
277 * If IDAI is 0 we are allowed to use the info we cached in
278 * the IMPDEF area of the table.
279 * PendingLast is RES1 when we make this transition.
284 * Valid going from 1 to 0:
285 * Set PendingLast if there was a pending enabled interrupt
286 * for the vPE that was just descheduled.
287 * If we cache info in the IMPDEF area, write it out here.
289 pendinglast
= cs
->hppvlpi
.prio
!= 0xff;
292 newval
= FIELD_DP64(newval
, GICR_VPENDBASER
, PENDINGLAST
, pendinglast
);
293 cs
->gicr_vpendbaser
= newval
;
294 gicv3_redist_update_vlpi(cs
);
297 static MemTxResult
gicr_readb(GICv3CPUState
*cs
, hwaddr offset
,
298 uint64_t *data
, MemTxAttrs attrs
)
301 case GICR_IPRIORITYR
... GICR_IPRIORITYR
+ 0x1f:
302 *data
= gicr_read_ipriorityr(cs
, attrs
, offset
- GICR_IPRIORITYR
);
309 static MemTxResult
gicr_writeb(GICv3CPUState
*cs
, hwaddr offset
,
310 uint64_t value
, MemTxAttrs attrs
)
313 case GICR_IPRIORITYR
... GICR_IPRIORITYR
+ 0x1f:
314 gicr_write_ipriorityr(cs
, attrs
, offset
- GICR_IPRIORITYR
, value
);
315 gicv3_redist_update(cs
);
322 static MemTxResult
gicr_readl(GICv3CPUState
*cs
, hwaddr offset
,
323 uint64_t *data
, MemTxAttrs attrs
)
327 *data
= cs
->gicr_ctlr
;
330 *data
= gicv3_iidr();
333 *data
= extract64(cs
->gicr_typer
, 0, 32);
336 *data
= extract64(cs
->gicr_typer
, 32, 32);
339 /* RAZ/WI for us (this is an optional register and our implementation
340 * does not track RO/WO/reserved violations to report them to the guest)
345 *data
= cs
->gicr_waker
;
348 *data
= extract64(cs
->gicr_propbaser
, 0, 32);
350 case GICR_PROPBASER
+ 4:
351 *data
= extract64(cs
->gicr_propbaser
, 32, 32);
354 *data
= extract64(cs
->gicr_pendbaser
, 0, 32);
356 case GICR_PENDBASER
+ 4:
357 *data
= extract64(cs
->gicr_pendbaser
, 32, 32);
360 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
364 *data
= cs
->gicr_igroupr0
;
366 case GICR_ISENABLER0
:
367 case GICR_ICENABLER0
:
368 *data
= gicr_read_bitmap_reg(cs
, attrs
, cs
->gicr_ienabler0
);
373 /* The pending register reads as the logical OR of the pending
374 * latch and the input line level for level-triggered interrupts.
376 uint32_t val
= cs
->gicr_ipendr0
| (~cs
->edge_trigger
& cs
->level
);
377 *data
= gicr_read_bitmap_reg(cs
, attrs
, val
);
380 case GICR_ISACTIVER0
:
381 case GICR_ICACTIVER0
:
382 *data
= gicr_read_bitmap_reg(cs
, attrs
, cs
->gicr_iactiver0
);
384 case GICR_IPRIORITYR
... GICR_IPRIORITYR
+ 0x1f:
386 int i
, irq
= offset
- GICR_IPRIORITYR
;
389 for (i
= irq
+ 3; i
>= irq
; i
--) {
391 value
|= gicr_read_ipriorityr(cs
, attrs
, i
);
399 /* Our edge_trigger bitmap is one bit per irq; take the correct
400 * half of it, and spread it out into the odd bits.
404 value
= cs
->edge_trigger
& mask_group(cs
, attrs
);
405 value
= extract32(value
, (offset
== GICR_ICFGR1
) ? 16 : 0, 16);
406 value
= half_shuffle32(value
) << 1;
411 if ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) || !attrs
.secure
) {
412 /* RAZ/WI if security disabled, or if
413 * security enabled and this is an NS access
418 *data
= cs
->gicr_igrpmodr0
;
421 if ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) || !attrs
.secure
) {
422 /* RAZ/WI if security disabled, or if
423 * security enabled and this is an NS access
428 *data
= cs
->gicr_nsacr
;
430 case GICR_IDREGS
... GICR_IDREGS
+ 0x2f:
431 *data
= gicv3_idreg(offset
- GICR_IDREGS
, GICV3_PIDR0_REDIST
);
434 * VLPI frame registers. We don't need a version check for
435 * VPROPBASER and VPENDBASER because gicv3_redist_size() will
436 * prevent pre-v4 GIC from passing us offsets this high.
438 case GICR_VPROPBASER
:
439 *data
= extract64(cs
->gicr_vpropbaser
, 0, 32);
441 case GICR_VPROPBASER
+ 4:
442 *data
= extract64(cs
->gicr_vpropbaser
, 32, 32);
444 case GICR_VPENDBASER
:
445 *data
= extract64(cs
->gicr_vpendbaser
, 0, 32);
447 case GICR_VPENDBASER
+ 4:
448 *data
= extract64(cs
->gicr_vpendbaser
, 32, 32);
455 static MemTxResult
gicr_writel(GICv3CPUState
*cs
, hwaddr offset
,
456 uint64_t value
, MemTxAttrs attrs
)
460 /* For our implementation, GICR_TYPER.DPGS is 0 and so all
461 * the DPG bits are RAZ/WI. We don't do anything asynchronously,
462 * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
463 * implement LPIs) so Enable_LPIs is programmable.
465 if (cs
->gicr_typer
& GICR_TYPER_PLPIS
) {
466 if (value
& GICR_CTLR_ENABLE_LPIS
) {
467 cs
->gicr_ctlr
|= GICR_CTLR_ENABLE_LPIS
;
468 /* Check for any pending interr in pending table */
469 gicv3_redist_update_lpi(cs
);
471 cs
->gicr_ctlr
&= ~GICR_CTLR_ENABLE_LPIS
;
472 /* cs->hppi might have been an LPI; recalculate */
473 gicv3_redist_update(cs
);
478 /* RAZ/WI for our implementation */
481 /* Only the ProcessorSleep bit is writeable. When the guest sets
482 * it it requests that we transition the channel between the
483 * redistributor and the cpu interface to quiescent, and that
484 * we set the ChildrenAsleep bit once the inteface has reached the
486 * Setting the ProcessorSleep to 0 reverses the quiescing, and
487 * ChildrenAsleep is cleared once the transition is complete.
488 * Since our interface is not asynchronous, we complete these
489 * transitions instantaneously, so we set ChildrenAsleep to the
490 * same value as ProcessorSleep here.
492 value
&= GICR_WAKER_ProcessorSleep
;
493 if (value
& GICR_WAKER_ProcessorSleep
) {
494 value
|= GICR_WAKER_ChildrenAsleep
;
496 cs
->gicr_waker
= value
;
499 cs
->gicr_propbaser
= deposit64(cs
->gicr_propbaser
, 0, 32, value
);
501 case GICR_PROPBASER
+ 4:
502 cs
->gicr_propbaser
= deposit64(cs
->gicr_propbaser
, 32, 32, value
);
505 cs
->gicr_pendbaser
= deposit64(cs
->gicr_pendbaser
, 0, 32, value
);
507 case GICR_PENDBASER
+ 4:
508 cs
->gicr_pendbaser
= deposit64(cs
->gicr_pendbaser
, 32, 32, value
);
511 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
514 cs
->gicr_igroupr0
= value
;
515 gicv3_redist_update(cs
);
517 case GICR_ISENABLER0
:
518 gicr_write_set_bitmap_reg(cs
, attrs
, &cs
->gicr_ienabler0
, value
);
520 case GICR_ICENABLER0
:
521 gicr_write_clear_bitmap_reg(cs
, attrs
, &cs
->gicr_ienabler0
, value
);
524 gicr_write_set_bitmap_reg(cs
, attrs
, &cs
->gicr_ipendr0
, value
);
527 gicr_write_clear_bitmap_reg(cs
, attrs
, &cs
->gicr_ipendr0
, value
);
529 case GICR_ISACTIVER0
:
530 gicr_write_set_bitmap_reg(cs
, attrs
, &cs
->gicr_iactiver0
, value
);
532 case GICR_ICACTIVER0
:
533 gicr_write_clear_bitmap_reg(cs
, attrs
, &cs
->gicr_iactiver0
, value
);
535 case GICR_IPRIORITYR
... GICR_IPRIORITYR
+ 0x1f:
537 int i
, irq
= offset
- GICR_IPRIORITYR
;
539 for (i
= irq
; i
< irq
+ 4; i
++, value
>>= 8) {
540 gicr_write_ipriorityr(cs
, attrs
, i
, value
);
542 gicv3_redist_update(cs
);
546 /* Register is all RAZ/WI or RAO/WI bits */
552 /* Since our edge_trigger bitmap is one bit per irq, our input
553 * 32-bits will compress down into 16 bits which we need
554 * to write into the bitmap.
556 value
= half_unshuffle32(value
>> 1) << 16;
557 mask
= mask_group(cs
, attrs
) & 0xffff0000U
;
559 cs
->edge_trigger
&= ~mask
;
560 cs
->edge_trigger
|= (value
& mask
);
562 gicv3_redist_update(cs
);
566 if ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) || !attrs
.secure
) {
567 /* RAZ/WI if security disabled, or if
568 * security enabled and this is an NS access
572 cs
->gicr_igrpmodr0
= value
;
573 gicv3_redist_update(cs
);
576 if ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) || !attrs
.secure
) {
577 /* RAZ/WI if security disabled, or if
578 * security enabled and this is an NS access
582 cs
->gicr_nsacr
= value
;
583 /* no update required as this only affects access permission checks */
587 case GICR_IDREGS
... GICR_IDREGS
+ 0x2f:
588 /* RO registers, ignore the write */
589 qemu_log_mask(LOG_GUEST_ERROR
,
590 "%s: invalid guest write to RO register at offset "
591 TARGET_FMT_plx
"\n", __func__
, offset
);
594 * VLPI frame registers. We don't need a version check for
595 * VPROPBASER and VPENDBASER because gicv3_redist_size() will
596 * prevent pre-v4 GIC from passing us offsets this high.
598 case GICR_VPROPBASER
:
599 cs
->gicr_vpropbaser
= deposit64(cs
->gicr_vpropbaser
, 0, 32, value
);
601 case GICR_VPROPBASER
+ 4:
602 cs
->gicr_vpropbaser
= deposit64(cs
->gicr_vpropbaser
, 32, 32, value
);
604 case GICR_VPENDBASER
:
605 gicr_write_vpendbaser(cs
, deposit64(cs
->gicr_vpendbaser
, 0, 32, value
));
607 case GICR_VPENDBASER
+ 4:
608 gicr_write_vpendbaser(cs
, deposit64(cs
->gicr_vpendbaser
, 32, 32, value
));
615 static MemTxResult
gicr_readll(GICv3CPUState
*cs
, hwaddr offset
,
616 uint64_t *data
, MemTxAttrs attrs
)
620 *data
= cs
->gicr_typer
;
623 *data
= cs
->gicr_propbaser
;
626 *data
= cs
->gicr_pendbaser
;
629 * VLPI frame registers. We don't need a version check for
630 * VPROPBASER and VPENDBASER because gicv3_redist_size() will
631 * prevent pre-v4 GIC from passing us offsets this high.
633 case GICR_VPROPBASER
:
634 *data
= cs
->gicr_vpropbaser
;
636 case GICR_VPENDBASER
:
637 *data
= cs
->gicr_vpendbaser
;
644 static MemTxResult
gicr_writell(GICv3CPUState
*cs
, hwaddr offset
,
645 uint64_t value
, MemTxAttrs attrs
)
649 cs
->gicr_propbaser
= value
;
652 cs
->gicr_pendbaser
= value
;
655 /* RO register, ignore the write */
656 qemu_log_mask(LOG_GUEST_ERROR
,
657 "%s: invalid guest write to RO register at offset "
658 TARGET_FMT_plx
"\n", __func__
, offset
);
661 * VLPI frame registers. We don't need a version check for
662 * VPROPBASER and VPENDBASER because gicv3_redist_size() will
663 * prevent pre-v4 GIC from passing us offsets this high.
665 case GICR_VPROPBASER
:
666 cs
->gicr_vpropbaser
= value
;
668 case GICR_VPENDBASER
:
669 gicr_write_vpendbaser(cs
, value
);
676 MemTxResult
gicv3_redist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
677 unsigned size
, MemTxAttrs attrs
)
679 GICv3RedistRegion
*region
= opaque
;
680 GICv3State
*s
= region
->gic
;
685 assert((offset
& (size
- 1)) == 0);
688 * There are (for GICv3) two 64K redistributor pages per CPU.
689 * In some cases the redistributor pages for all CPUs are not
690 * contiguous (eg on the virt board they are split into two
691 * parts if there are too many CPUs to all fit in the same place
692 * in the memory map); if so then the GIC has multiple MemoryRegions
693 * for the redistributors.
695 cpuidx
= region
->cpuidx
+ offset
/ gicv3_redist_size(s
);
696 offset
%= gicv3_redist_size(s
);
698 cs
= &s
->cpu
[cpuidx
];
702 r
= gicr_readb(cs
, offset
, data
, attrs
);
705 r
= gicr_readl(cs
, offset
, data
, attrs
);
708 r
= gicr_readll(cs
, offset
, data
, attrs
);
716 qemu_log_mask(LOG_GUEST_ERROR
,
717 "%s: invalid guest read at offset " TARGET_FMT_plx
718 " size %u\n", __func__
, offset
, size
);
719 trace_gicv3_redist_badread(gicv3_redist_affid(cs
), offset
,
721 /* The spec requires that reserved registers are RAZ/WI;
722 * so use MEMTX_ERROR returns from leaf functions as a way to
723 * trigger the guest-error logging but don't return it to
724 * the caller, or we'll cause a spurious guest data abort.
729 trace_gicv3_redist_read(gicv3_redist_affid(cs
), offset
, *data
,
735 MemTxResult
gicv3_redist_write(void *opaque
, hwaddr offset
, uint64_t data
,
736 unsigned size
, MemTxAttrs attrs
)
738 GICv3RedistRegion
*region
= opaque
;
739 GICv3State
*s
= region
->gic
;
744 assert((offset
& (size
- 1)) == 0);
747 * There are (for GICv3) two 64K redistributor pages per CPU.
748 * In some cases the redistributor pages for all CPUs are not
749 * contiguous (eg on the virt board they are split into two
750 * parts if there are too many CPUs to all fit in the same place
751 * in the memory map); if so then the GIC has multiple MemoryRegions
752 * for the redistributors.
754 cpuidx
= region
->cpuidx
+ offset
/ gicv3_redist_size(s
);
755 offset
%= gicv3_redist_size(s
);
757 cs
= &s
->cpu
[cpuidx
];
761 r
= gicr_writeb(cs
, offset
, data
, attrs
);
764 r
= gicr_writel(cs
, offset
, data
, attrs
);
767 r
= gicr_writell(cs
, offset
, data
, attrs
);
775 qemu_log_mask(LOG_GUEST_ERROR
,
776 "%s: invalid guest write at offset " TARGET_FMT_plx
777 " size %u\n", __func__
, offset
, size
);
778 trace_gicv3_redist_badwrite(gicv3_redist_affid(cs
), offset
, data
,
780 /* The spec requires that reserved registers are RAZ/WI;
781 * so use MEMTX_ERROR returns from leaf functions as a way to
782 * trigger the guest-error logging but don't return it to
783 * the caller, or we'll cause a spurious guest data abort.
787 trace_gicv3_redist_write(gicv3_redist_affid(cs
), offset
, data
,
793 static void gicv3_redist_check_lpi_priority(GICv3CPUState
*cs
, int irq
)
795 uint64_t lpict_baddr
= cs
->gicr_propbaser
& R_GICR_PROPBASER_PHYADDR_MASK
;
797 update_for_one_lpi(cs
, irq
, lpict_baddr
,
798 cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
,
802 void gicv3_redist_update_lpi_only(GICv3CPUState
*cs
)
805 * This function scans the LPI pending table and for each pending
806 * LPI, reads the corresponding entry from LPI configuration table
807 * to extract the priority info and determine if the current LPI
808 * priority is lower than the last computed high priority lpi interrupt.
809 * If yes, replace current LPI as the new high priority lpi interrupt.
811 uint64_t lpipt_baddr
, lpict_baddr
;
814 idbits
= MIN(FIELD_EX64(cs
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
817 if (!(cs
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
)) {
821 lpipt_baddr
= cs
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
822 lpict_baddr
= cs
->gicr_propbaser
& R_GICR_PROPBASER_PHYADDR_MASK
;
824 update_for_all_lpis(cs
, lpipt_baddr
, lpict_baddr
, idbits
,
825 cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
, &cs
->hpplpi
);
828 void gicv3_redist_update_lpi(GICv3CPUState
*cs
)
830 gicv3_redist_update_lpi_only(cs
);
831 gicv3_redist_update(cs
);
834 void gicv3_redist_lpi_pending(GICv3CPUState
*cs
, int irq
, int level
)
837 * This function updates the pending bit in lpi pending table for
838 * the irq being activated or deactivated.
840 uint64_t lpipt_baddr
;
842 lpipt_baddr
= cs
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
843 if (!set_pending_table_bit(cs
, lpipt_baddr
, irq
, level
)) {
844 /* no change in the value of pending bit, return */
849 * check if this LPI is better than the current hpplpi, if yes
850 * just set hpplpi.prio and .irq without doing a full rescan
853 gicv3_redist_check_lpi_priority(cs
, irq
);
854 gicv3_redist_update(cs
);
856 if (irq
== cs
->hpplpi
.irq
) {
857 gicv3_redist_update_lpi(cs
);
862 void gicv3_redist_process_lpi(GICv3CPUState
*cs
, int irq
, int level
)
866 idbits
= MIN(FIELD_EX64(cs
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
869 if (!(cs
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
) ||
870 (irq
> (1ULL << (idbits
+ 1)) - 1) || irq
< GICV3_LPI_INTID_START
) {
874 /* set/clear the pending bit for this irq */
875 gicv3_redist_lpi_pending(cs
, irq
, level
);
878 void gicv3_redist_inv_lpi(GICv3CPUState
*cs
, int irq
)
881 * The only cached information for LPIs we have is the HPPLPI.
882 * We could be cleverer about identifying when we don't need
883 * to do a full rescan of the pending table, but until we find
884 * this is a performance issue, just always recalculate.
886 gicv3_redist_update_lpi(cs
);
889 void gicv3_redist_mov_lpi(GICv3CPUState
*src
, GICv3CPUState
*dest
, int irq
)
892 * Move the specified LPI's pending state from the source redistributor
893 * to the destination.
895 * If LPIs are disabled on dest this is CONSTRAINED UNPREDICTABLE:
896 * we choose to NOP. If LPIs are disabled on source there's nothing
897 * to be transferred anyway.
899 AddressSpace
*as
= &src
->gic
->dma_as
;
905 if (!(src
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
) ||
906 !(dest
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
)) {
910 idbits
= MIN(FIELD_EX64(src
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
912 idbits
= MIN(FIELD_EX64(dest
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
915 pendt_size
= 1ULL << (idbits
+ 1);
916 if ((irq
/ 8) >= pendt_size
) {
920 src_baddr
= src
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
922 address_space_read(as
, src_baddr
+ (irq
/ 8),
923 MEMTXATTRS_UNSPECIFIED
, &src_pend
, sizeof(src_pend
));
924 if (!extract32(src_pend
, irq
% 8, 1)) {
925 /* Not pending on source, nothing to do */
928 src_pend
&= ~(1 << (irq
% 8));
929 address_space_write(as
, src_baddr
+ (irq
/ 8),
930 MEMTXATTRS_UNSPECIFIED
, &src_pend
, sizeof(src_pend
));
931 if (irq
== src
->hpplpi
.irq
) {
933 * We just made this LPI not-pending so only need to update
934 * if it was previously the highest priority pending LPI
936 gicv3_redist_update_lpi(src
);
938 /* Mark it pending on the destination */
939 gicv3_redist_lpi_pending(dest
, irq
, 1);
942 void gicv3_redist_movall_lpis(GICv3CPUState
*src
, GICv3CPUState
*dest
)
945 * We must move all pending LPIs from the source redistributor
946 * to the destination. That is, for every pending LPI X on
947 * src, we must set it not-pending on src and pending on dest.
948 * LPIs that are already pending on dest are not cleared.
950 * If LPIs are disabled on dest this is CONSTRAINED UNPREDICTABLE:
951 * we choose to NOP. If LPIs are disabled on source there's nothing
952 * to be transferred anyway.
954 AddressSpace
*as
= &src
->gic
->dma_as
;
957 uint64_t src_baddr
, dest_baddr
;
960 if (!(src
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
) ||
961 !(dest
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
)) {
965 idbits
= MIN(FIELD_EX64(src
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
967 idbits
= MIN(FIELD_EX64(dest
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
970 pendt_size
= 1ULL << (idbits
+ 1);
971 src_baddr
= src
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
972 dest_baddr
= dest
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
974 for (i
= GICV3_LPI_INTID_START
/ 8; i
< pendt_size
/ 8; i
++) {
975 uint8_t src_pend
, dest_pend
;
977 address_space_read(as
, src_baddr
+ i
, MEMTXATTRS_UNSPECIFIED
,
978 &src_pend
, sizeof(src_pend
));
982 address_space_read(as
, dest_baddr
+ i
, MEMTXATTRS_UNSPECIFIED
,
983 &dest_pend
, sizeof(dest_pend
));
984 dest_pend
|= src_pend
;
986 address_space_write(as
, src_baddr
+ i
, MEMTXATTRS_UNSPECIFIED
,
987 &src_pend
, sizeof(src_pend
));
988 address_space_write(as
, dest_baddr
+ i
, MEMTXATTRS_UNSPECIFIED
,
989 &dest_pend
, sizeof(dest_pend
));
992 gicv3_redist_update_lpi(src
);
993 gicv3_redist_update_lpi(dest
);
996 void gicv3_redist_vlpi_pending(GICv3CPUState
*cs
, int irq
, int level
)
999 * The redistributor handling for changing the pending state
1000 * of a vLPI will be added in a subsequent commit.
1004 void gicv3_redist_process_vlpi(GICv3CPUState
*cs
, int irq
, uint64_t vptaddr
,
1005 int doorbell
, int level
)
1008 * The redistributor handling for being handed a VLPI by the ITS
1009 * will be added in a subsequent commit.
1013 void gicv3_redist_mov_vlpi(GICv3CPUState
*src
, uint64_t src_vptaddr
,
1014 GICv3CPUState
*dest
, uint64_t dest_vptaddr
,
1015 int irq
, int doorbell
)
1018 * The redistributor handling for moving a VLPI will be added
1019 * in a subsequent commit.
1023 void gicv3_redist_vinvall(GICv3CPUState
*cs
, uint64_t vptaddr
)
1025 /* The redistributor handling will be added in a subsequent commit */
1028 void gicv3_redist_inv_vlpi(GICv3CPUState
*cs
, int irq
, uint64_t vptaddr
)
1031 * The redistributor handling for invalidating cached information
1032 * about a VLPI will be added in a subsequent commit.
1036 void gicv3_redist_set_irq(GICv3CPUState
*cs
, int irq
, int level
)
1038 /* Update redistributor state for a change in an external PPI input line */
1039 if (level
== extract32(cs
->level
, irq
, 1)) {
1043 trace_gicv3_redist_set_irq(gicv3_redist_affid(cs
), irq
, level
);
1045 cs
->level
= deposit32(cs
->level
, irq
, 1, level
);
1048 /* 0->1 edges latch the pending bit for edge-triggered interrupts */
1049 if (extract32(cs
->edge_trigger
, irq
, 1)) {
1050 cs
->gicr_ipendr0
= deposit32(cs
->gicr_ipendr0
, irq
, 1, 1);
1054 gicv3_redist_update(cs
);
1057 void gicv3_redist_send_sgi(GICv3CPUState
*cs
, int grp
, int irq
, bool ns
)
1059 /* Update redistributor state for a generated SGI */
1060 int irqgrp
= gicv3_irq_group(cs
->gic
, cs
, irq
);
1062 /* If we are asked for a Secure Group 1 SGI and it's actually
1063 * configured as Secure Group 0 this is OK (subject to the usual
1066 if (grp
== GICV3_G1
&& irqgrp
== GICV3_G0
) {
1070 if (grp
!= irqgrp
) {
1074 if (ns
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
1075 /* If security is enabled we must test the NSACR bits */
1076 int nsaccess
= gicr_ns_access(cs
, irq
);
1078 if ((irqgrp
== GICV3_G0
&& nsaccess
< 1) ||
1079 (irqgrp
== GICV3_G1
&& nsaccess
< 2)) {
1084 /* OK, we can accept the SGI */
1085 trace_gicv3_redist_send_sgi(gicv3_redist_affid(cs
), irq
);
1086 cs
->gicr_ipendr0
= deposit32(cs
->gicr_ipendr0
, irq
, 1, 1);
1087 gicv3_redist_update(cs
);