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target-tricore: Add instructions of BIT opcode format
[qemu.git] / target-tricore / translate.c
blobddbabc40faf8685cc1df6012a0d469b3a0b80d04
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "exec/cpu_ldst.h"
25
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28
29 #include "tricore-opcodes.h"
30
31 /*
32 * TCG registers
33 */
34 static TCGv cpu_PC;
35 static TCGv cpu_PCXI;
36 static TCGv cpu_PSW;
37 static TCGv cpu_ICR;
38 /* GPR registers */
39 static TCGv cpu_gpr_a[16];
40 static TCGv cpu_gpr_d[16];
41 /* PSW Flag cache */
42 static TCGv cpu_PSW_C;
43 static TCGv cpu_PSW_V;
44 static TCGv cpu_PSW_SV;
45 static TCGv cpu_PSW_AV;
46 static TCGv cpu_PSW_SAV;
47 /* CPU env */
48 static TCGv_ptr cpu_env;
49
50 #include "exec/gen-icount.h"
51
52 static const char *regnames_a[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
56 };
57
58 static const char *regnames_d[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
62 };
63
64 typedef struct DisasContext {
65 struct TranslationBlock *tb;
66 target_ulong pc, saved_pc, next_pc;
67 uint32_t opcode;
68 int singlestep_enabled;
69 /* Routine used to access memory */
70 int mem_idx;
71 uint32_t hflags, saved_hflags;
72 int bstate;
73 } DisasContext;
74
75 enum {
76
77 BS_NONE = 0,
78 BS_STOP = 1,
79 BS_BRANCH = 2,
80 BS_EXCP = 3,
81 };
82
83 void tricore_cpu_dump_state(CPUState *cs, FILE *f,
84 fprintf_function cpu_fprintf, int flags)
85 {
86 TriCoreCPU *cpu = TRICORE_CPU(cs);
87 CPUTriCoreState *env = &cpu->env;
88 int i;
89
90 cpu_fprintf(f, "PC=%08x\n", env->PC);
91 for (i = 0; i < 16; ++i) {
92 if ((i & 3) == 0) {
93 cpu_fprintf(f, "GPR A%02d:", i);
94 }
95 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
96 }
97 for (i = 0; i < 16; ++i) {
98 if ((i & 3) == 0) {
99 cpu_fprintf(f, "GPR D%02d:", i);
100 }
101 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
102 }
103
104 }
105
106 /*
107 * Functions to generate micro-ops
108 */
109
110 /* Makros for generating helpers */
111
112 #define gen_helper_1arg(name, arg) do { \
113 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
114 gen_helper_##name(cpu_env, helper_tmp); \
115 tcg_temp_free_i32(helper_tmp); \
116 } while (0)
117
118 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
119 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
120 ((offset & 0x0fffff) << 1))
121
122 /* Functions for load/save to/from memory */
123
124 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
125 int16_t con, TCGMemOp mop)
126 {
127 TCGv temp = tcg_temp_new();
128 tcg_gen_addi_tl(temp, r2, con);
129 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
130 tcg_temp_free(temp);
131 }
132
133 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
134 int16_t con, TCGMemOp mop)
135 {
136 TCGv temp = tcg_temp_new();
137 tcg_gen_addi_tl(temp, r2, con);
138 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
139 tcg_temp_free(temp);
140 }
141
142 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
143 {
144 TCGv_i64 temp = tcg_temp_new_i64();
145
146 tcg_gen_concat_i32_i64(temp, rl, rh);
147 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
148
149 tcg_temp_free_i64(temp);
150 }
151
152 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
153 {
154 TCGv_i64 temp = tcg_temp_new_i64();
155
156 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
157 /* write back to two 32 bit regs */
158 tcg_gen_extr_i64_i32(rl, rh, temp);
159
160 tcg_temp_free_i64(temp);
161 }
162
163 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
164 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
165 {
166 TCGv temp = tcg_temp_new();
167 TCGv temp2 = tcg_temp_new();
168
169 /* temp = (M(EA, word) */
170 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
171 /* temp = temp & ~E[a][63:32]) */
172 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
173 /* temp2 = (E[a][31:0] & E[a][63:32]); */
174 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
175 /* temp = temp | temp2; */
176 tcg_gen_or_tl(temp, temp, temp2);
177 /* M(EA, word) = temp; */
178 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
179
180 tcg_temp_free(temp);
181 tcg_temp_free(temp2);
182 }
183
184 /* tmp = M(EA, word);
185 M(EA, word) = D[a];
186 D[a] = tmp[31:0];*/
187 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
188 {
189 TCGv temp = tcg_temp_new();
190
191 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
192 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
193 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
194
195 tcg_temp_free(temp);
196 }
197
198 /* Functions for arithmetic instructions */
199
200 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
201 {
202 TCGv t0 = tcg_temp_new_i32();
203 TCGv result = tcg_temp_new_i32();
204 /* Addition and set V/SV bits */
205 tcg_gen_add_tl(result, r1, r2);
206 /* calc V bit */
207 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
208 tcg_gen_xor_tl(t0, r1, r2);
209 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
210 /* Calc SV bit */
211 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
212 /* Calc AV/SAV bits */
213 tcg_gen_add_tl(cpu_PSW_AV, result, result);
214 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
215 /* calc SAV */
216 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
217 /* write back result */
218 tcg_gen_mov_tl(ret, result);
219
220 tcg_temp_free(result);
221 tcg_temp_free(t0);
222 }
223
224 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
225 {
226 TCGv temp = tcg_const_i32(r2);
227 gen_add_d(ret, r1, temp);
228 tcg_temp_free(temp);
229 }
230
231 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
232 TCGv r4)
233 {
234 TCGv temp = tcg_temp_new();
235 TCGv temp2 = tcg_temp_new();
236 TCGv result = tcg_temp_new();
237 TCGv mask = tcg_temp_new();
238 TCGv t0 = tcg_const_i32(0);
239
240 /* create mask for sticky bits */
241 tcg_gen_setcond_tl(cond, mask, r4, t0);
242 tcg_gen_shli_tl(mask, mask, 31);
243
244 tcg_gen_add_tl(result, r1, r2);
245 /* Calc PSW_V */
246 tcg_gen_xor_tl(temp, result, r1);
247 tcg_gen_xor_tl(temp2, r1, r2);
248 tcg_gen_andc_tl(temp, temp, temp2);
249 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
250 /* Set PSW_SV */
251 tcg_gen_and_tl(temp, temp, mask);
252 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
253 /* calc AV bit */
254 tcg_gen_add_tl(temp, result, result);
255 tcg_gen_xor_tl(temp, temp, result);
256 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
257 /* calc SAV bit */
258 tcg_gen_and_tl(temp, temp, mask);
259 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
260 /* write back result */
261 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
262
263 tcg_temp_free(t0);
264 tcg_temp_free(temp);
265 tcg_temp_free(temp2);
266 tcg_temp_free(result);
267 tcg_temp_free(mask);
268 }
269
270 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
271 TCGv r3, TCGv r4)
272 {
273 TCGv temp = tcg_const_i32(r2);
274 gen_cond_add(cond, r1, temp, r3, r4);
275 tcg_temp_free(temp);
276 }
277
278 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
279 {
280 TCGv temp = tcg_temp_new_i32();
281 TCGv result = tcg_temp_new_i32();
282
283 tcg_gen_sub_tl(result, r1, r2);
284 /* calc V bit */
285 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
286 tcg_gen_xor_tl(temp, r1, r2);
287 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
288 /* calc SV bit */
289 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
290 /* Calc AV bit */
291 tcg_gen_add_tl(cpu_PSW_AV, result, result);
292 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
293 /* calc SAV bit */
294 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
295 /* write back result */
296 tcg_gen_mov_tl(ret, result);
297
298 tcg_temp_free(temp);
299 tcg_temp_free(result);
300 }
301
302 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
303 {
304 TCGv high = tcg_temp_new();
305 TCGv low = tcg_temp_new();
306
307 tcg_gen_muls2_tl(low, high, r1, r2);
308 tcg_gen_mov_tl(ret, low);
309 /* calc V bit */
310 tcg_gen_sari_tl(low, low, 31);
311 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
312 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
313 /* calc SV bit */
314 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
315 /* Calc AV bit */
316 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
317 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
318 /* calc SAV bit */
319 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
320
321 tcg_temp_free(high);
322 tcg_temp_free(low);
323 }
324
325 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
326 {
327 TCGv sat_neg = tcg_const_i32(low);
328 TCGv temp = tcg_const_i32(up);
329
330 /* sat_neg = (arg < low ) ? low : arg; */
331 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
332
333 /* ret = (sat_neg > up ) ? up : sat_neg; */
334 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
335
336 tcg_temp_free(sat_neg);
337 tcg_temp_free(temp);
338 }
339
340 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
341 {
342 TCGv temp = tcg_const_i32(up);
343 /* sat_neg = (arg > up ) ? up : arg; */
344 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
345 tcg_temp_free(temp);
346 }
347
348 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
349 {
350 if (shift_count == -32) {
351 tcg_gen_movi_tl(ret, 0);
352 } else if (shift_count >= 0) {
353 tcg_gen_shli_tl(ret, r1, shift_count);
354 } else {
355 tcg_gen_shri_tl(ret, r1, -shift_count);
356 }
357 }
358
359 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
360 {
361 uint32_t msk, msk_start;
362 TCGv temp = tcg_temp_new();
363 TCGv temp2 = tcg_temp_new();
364 TCGv t_0 = tcg_const_i32(0);
365
366 if (shift_count == 0) {
367 /* Clear PSW.C and PSW.V */
368 tcg_gen_movi_tl(cpu_PSW_C, 0);
369 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
370 tcg_gen_mov_tl(ret, r1);
371 } else if (shift_count == -32) {
372 /* set PSW.C */
373 tcg_gen_mov_tl(cpu_PSW_C, r1);
374 /* fill ret completly with sign bit */
375 tcg_gen_sari_tl(ret, r1, 31);
376 /* clear PSW.V */
377 tcg_gen_movi_tl(cpu_PSW_V, 0);
378 } else if (shift_count > 0) {
379 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
380 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
381
382 /* calc carry */
383 msk_start = 32 - shift_count;
384 msk = ((1 << shift_count) - 1) << msk_start;
385 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
386 /* calc v/sv bits */
387 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
388 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
389 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
390 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
391 /* calc sv */
392 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
393 /* do shift */
394 tcg_gen_shli_tl(ret, r1, shift_count);
395
396 tcg_temp_free(t_max);
397 tcg_temp_free(t_min);
398 } else {
399 /* clear PSW.V */
400 tcg_gen_movi_tl(cpu_PSW_V, 0);
401 /* calc carry */
402 msk = (1 << -shift_count) - 1;
403 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
404 /* do shift */
405 tcg_gen_sari_tl(ret, r1, -shift_count);
406 }
407 /* calc av overflow bit */
408 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
409 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
410 /* calc sav overflow bit */
411 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
412
413 tcg_temp_free(temp);
414 tcg_temp_free(temp2);
415 tcg_temp_free(t_0);
416 }
417
418 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
419 {
420 gen_helper_add_ssov(ret, cpu_env, r1, r2);
421 }
422
423 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
424 {
425 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
426 }
427
428 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
429 int pos1, int pos2,
430 void(*op1)(TCGv, TCGv, TCGv),
431 void(*op2)(TCGv, TCGv, TCGv))
432 {
433 TCGv temp1, temp2;
434
435 temp1 = tcg_temp_new();
436 temp2 = tcg_temp_new();
437
438 tcg_gen_shri_tl(temp2, r2, pos2);
439 tcg_gen_shri_tl(temp1, r1, pos1);
440
441 (*op1)(temp1, temp1, temp2);
442 (*op2)(temp1 , ret, temp1);
443
444 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
445
446 tcg_temp_free(temp1);
447 tcg_temp_free(temp2);
448 }
449
450 /* ret = r1[pos1] op1 r2[pos2]; */
451 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
452 int pos1, int pos2,
453 void(*op1)(TCGv, TCGv, TCGv))
454 {
455 TCGv temp1, temp2;
456
457 temp1 = tcg_temp_new();
458 temp2 = tcg_temp_new();
459
460 tcg_gen_shri_tl(temp2, r2, pos2);
461 tcg_gen_shri_tl(temp1, r1, pos1);
462
463 (*op1)(ret, temp1, temp2);
464
465 tcg_gen_andi_tl(ret, ret, 0x1);
466
467 tcg_temp_free(temp1);
468 tcg_temp_free(temp2);
469 }
470
471 /* helpers for generating program flow micro-ops */
472
473 static inline void gen_save_pc(target_ulong pc)
474 {
475 tcg_gen_movi_tl(cpu_PC, pc);
476 }
477
478 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
479 {
480 TranslationBlock *tb;
481 tb = ctx->tb;
482 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
483 likely(!ctx->singlestep_enabled)) {
484 tcg_gen_goto_tb(n);
485 gen_save_pc(dest);
486 tcg_gen_exit_tb((uintptr_t)tb + n);
487 } else {
488 gen_save_pc(dest);
489 if (ctx->singlestep_enabled) {
490 /* raise exception debug */
491 }
492 tcg_gen_exit_tb(0);
493 }
494 }
495
496 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
497 TCGv r2, int16_t address)
498 {
499 int jumpLabel;
500 jumpLabel = gen_new_label();
501 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
502
503 gen_goto_tb(ctx, 1, ctx->next_pc);
504
505 gen_set_label(jumpLabel);
506 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
507 }
508
509 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
510 int r2, int16_t address)
511 {
512 TCGv temp = tcg_const_i32(r2);
513 gen_branch_cond(ctx, cond, r1, temp, address);
514 tcg_temp_free(temp);
515 }
516
517 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
518 {
519 int l1;
520 l1 = gen_new_label();
521
522 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
523 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
524 gen_goto_tb(ctx, 1, ctx->pc + offset);
525 gen_set_label(l1);
526 gen_goto_tb(ctx, 0, ctx->next_pc);
527 }
528
529 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
530 int r2 , int32_t constant , int32_t offset)
531 {
532 TCGv temp;
533
534 switch (opc) {
535 /* SB-format jumps */
536 case OPC1_16_SB_J:
537 case OPC1_32_B_J:
538 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
539 break;
540 case OPC1_32_B_CALL:
541 case OPC1_16_SB_CALL:
542 gen_helper_1arg(call, ctx->next_pc);
543 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
544 break;
545 case OPC1_16_SB_JZ:
546 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
547 break;
548 case OPC1_16_SB_JNZ:
549 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
550 break;
551 /* SBC-format jumps */
552 case OPC1_16_SBC_JEQ:
553 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
554 break;
555 case OPC1_16_SBC_JNE:
556 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
557 break;
558 /* SBRN-format jumps */
559 case OPC1_16_SBRN_JZ_T:
560 temp = tcg_temp_new();
561 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
562 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
563 tcg_temp_free(temp);
564 break;
565 case OPC1_16_SBRN_JNZ_T:
566 temp = tcg_temp_new();
567 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
568 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
569 tcg_temp_free(temp);
570 break;
571 /* SBR-format jumps */
572 case OPC1_16_SBR_JEQ:
573 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
574 offset);
575 break;
576 case OPC1_16_SBR_JNE:
577 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
578 offset);
579 break;
580 case OPC1_16_SBR_JNZ:
581 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
582 break;
583 case OPC1_16_SBR_JNZ_A:
584 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
585 break;
586 case OPC1_16_SBR_JGEZ:
587 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
588 break;
589 case OPC1_16_SBR_JGTZ:
590 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
591 break;
592 case OPC1_16_SBR_JLEZ:
593 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
594 break;
595 case OPC1_16_SBR_JLTZ:
596 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
597 break;
598 case OPC1_16_SBR_JZ:
599 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
600 break;
601 case OPC1_16_SBR_JZ_A:
602 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
603 break;
604 case OPC1_16_SBR_LOOP:
605 gen_loop(ctx, r1, offset * 2 - 32);
606 break;
607 /* SR-format jumps */
608 case OPC1_16_SR_JI:
609 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
610 tcg_gen_exit_tb(0);
611 break;
612 case OPC2_16_SR_RET:
613 gen_helper_ret(cpu_env);
614 tcg_gen_exit_tb(0);
615 break;
616 /* B-format */
617 case OPC1_32_B_CALLA:
618 gen_helper_1arg(call, ctx->next_pc);
619 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
620 break;
621 case OPC1_32_B_JLA:
622 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
623 case OPC1_32_B_JA:
624 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
625 break;
626 case OPC1_32_B_JL:
627 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
628 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
629 break;
630 default:
631 printf("Branch Error at %x\n", ctx->pc);
632 }
633 ctx->bstate = BS_BRANCH;
634 }
635
636
637 /*
638 * Functions for decoding instructions
639 */
640
641 static void decode_src_opc(DisasContext *ctx, int op1)
642 {
643 int r1;
644 int32_t const4;
645 TCGv temp, temp2;
646
647 r1 = MASK_OP_SRC_S1D(ctx->opcode);
648 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
649
650 switch (op1) {
651 case OPC1_16_SRC_ADD:
652 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
653 break;
654 case OPC1_16_SRC_ADD_A15:
655 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
656 break;
657 case OPC1_16_SRC_ADD_15A:
658 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
659 break;
660 case OPC1_16_SRC_ADD_A:
661 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
662 break;
663 case OPC1_16_SRC_CADD:
664 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
665 cpu_gpr_d[15]);
666 break;
667 case OPC1_16_SRC_CADDN:
668 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
669 cpu_gpr_d[15]);
670 break;
671 case OPC1_16_SRC_CMOV:
672 temp = tcg_const_tl(0);
673 temp2 = tcg_const_tl(const4);
674 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
675 temp2, cpu_gpr_d[r1]);
676 tcg_temp_free(temp);
677 tcg_temp_free(temp2);
678 break;
679 case OPC1_16_SRC_CMOVN:
680 temp = tcg_const_tl(0);
681 temp2 = tcg_const_tl(const4);
682 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
683 temp2, cpu_gpr_d[r1]);
684 tcg_temp_free(temp);
685 tcg_temp_free(temp2);
686 break;
687 case OPC1_16_SRC_EQ:
688 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
689 const4);
690 break;
691 case OPC1_16_SRC_LT:
692 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
693 const4);
694 break;
695 case OPC1_16_SRC_MOV:
696 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
697 break;
698 case OPC1_16_SRC_MOV_A:
699 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
700 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
701 break;
702 case OPC1_16_SRC_SH:
703 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
704 break;
705 case OPC1_16_SRC_SHA:
706 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
707 break;
708 }
709 }
710
711 static void decode_srr_opc(DisasContext *ctx, int op1)
712 {
713 int r1, r2;
714 TCGv temp;
715
716 r1 = MASK_OP_SRR_S1D(ctx->opcode);
717 r2 = MASK_OP_SRR_S2(ctx->opcode);
718
719 switch (op1) {
720 case OPC1_16_SRR_ADD:
721 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
722 break;
723 case OPC1_16_SRR_ADD_A15:
724 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
725 break;
726 case OPC1_16_SRR_ADD_15A:
727 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
728 break;
729 case OPC1_16_SRR_ADD_A:
730 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
731 break;
732 case OPC1_16_SRR_ADDS:
733 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
734 break;
735 case OPC1_16_SRR_AND:
736 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
737 break;
738 case OPC1_16_SRR_CMOV:
739 temp = tcg_const_tl(0);
740 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
741 cpu_gpr_d[r2], cpu_gpr_d[r1]);
742 tcg_temp_free(temp);
743 break;
744 case OPC1_16_SRR_CMOVN:
745 temp = tcg_const_tl(0);
746 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
747 cpu_gpr_d[r2], cpu_gpr_d[r1]);
748 tcg_temp_free(temp);
749 break;
750 case OPC1_16_SRR_EQ:
751 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
752 cpu_gpr_d[r2]);
753 break;
754 case OPC1_16_SRR_LT:
755 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
756 cpu_gpr_d[r2]);
757 break;
758 case OPC1_16_SRR_MOV:
759 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
760 break;
761 case OPC1_16_SRR_MOV_A:
762 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
763 break;
764 case OPC1_16_SRR_MOV_AA:
765 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
766 break;
767 case OPC1_16_SRR_MOV_D:
768 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
769 break;
770 case OPC1_16_SRR_MUL:
771 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
772 break;
773 case OPC1_16_SRR_OR:
774 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
775 break;
776 case OPC1_16_SRR_SUB:
777 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
778 break;
779 case OPC1_16_SRR_SUB_A15B:
780 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
781 break;
782 case OPC1_16_SRR_SUB_15AB:
783 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
784 break;
785 case OPC1_16_SRR_SUBS:
786 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
787 break;
788 case OPC1_16_SRR_XOR:
789 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
790 break;
791 }
792 }
793
794 static void decode_ssr_opc(DisasContext *ctx, int op1)
795 {
796 int r1, r2;
797
798 r1 = MASK_OP_SSR_S1(ctx->opcode);
799 r2 = MASK_OP_SSR_S2(ctx->opcode);
800
801 switch (op1) {
802 case OPC1_16_SSR_ST_A:
803 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
804 break;
805 case OPC1_16_SSR_ST_A_POSTINC:
806 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
807 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
808 break;
809 case OPC1_16_SSR_ST_B:
810 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
811 break;
812 case OPC1_16_SSR_ST_B_POSTINC:
813 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
814 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
815 break;
816 case OPC1_16_SSR_ST_H:
817 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
818 break;
819 case OPC1_16_SSR_ST_H_POSTINC:
820 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
821 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
822 break;
823 case OPC1_16_SSR_ST_W:
824 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
825 break;
826 case OPC1_16_SSR_ST_W_POSTINC:
827 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
828 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
829 break;
830 }
831 }
832
833 static void decode_sc_opc(DisasContext *ctx, int op1)
834 {
835 int32_t const16;
836
837 const16 = MASK_OP_SC_CONST8(ctx->opcode);
838
839 switch (op1) {
840 case OPC1_16_SC_AND:
841 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
842 break;
843 case OPC1_16_SC_BISR:
844 gen_helper_1arg(bisr, const16 & 0xff);
845 break;
846 case OPC1_16_SC_LD_A:
847 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
848 break;
849 case OPC1_16_SC_LD_W:
850 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
851 break;
852 case OPC1_16_SC_MOV:
853 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
854 break;
855 case OPC1_16_SC_OR:
856 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
857 break;
858 case OPC1_16_SC_ST_A:
859 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
860 break;
861 case OPC1_16_SC_ST_W:
862 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
863 break;
864 case OPC1_16_SC_SUB_A:
865 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
866 break;
867 }
868 }
869
870 static void decode_slr_opc(DisasContext *ctx, int op1)
871 {
872 int r1, r2;
873
874 r1 = MASK_OP_SLR_D(ctx->opcode);
875 r2 = MASK_OP_SLR_S2(ctx->opcode);
876
877 switch (op1) {
878 /* SLR-format */
879 case OPC1_16_SLR_LD_A:
880 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
881 break;
882 case OPC1_16_SLR_LD_A_POSTINC:
883 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
884 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
885 break;
886 case OPC1_16_SLR_LD_BU:
887 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
888 break;
889 case OPC1_16_SLR_LD_BU_POSTINC:
890 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
891 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
892 break;
893 case OPC1_16_SLR_LD_H:
894 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
895 break;
896 case OPC1_16_SLR_LD_H_POSTINC:
897 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
898 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
899 break;
900 case OPC1_16_SLR_LD_W:
901 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
902 break;
903 case OPC1_16_SLR_LD_W_POSTINC:
904 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
905 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
906 break;
907 }
908 }
909
910 static void decode_sro_opc(DisasContext *ctx, int op1)
911 {
912 int r2;
913 int32_t address;
914
915 r2 = MASK_OP_SRO_S2(ctx->opcode);
916 address = MASK_OP_SRO_OFF4(ctx->opcode);
917
918 /* SRO-format */
919 switch (op1) {
920 case OPC1_16_SRO_LD_A:
921 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
922 break;
923 case OPC1_16_SRO_LD_BU:
924 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
925 break;
926 case OPC1_16_SRO_LD_H:
927 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
928 break;
929 case OPC1_16_SRO_LD_W:
930 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
931 break;
932 case OPC1_16_SRO_ST_A:
933 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
934 break;
935 case OPC1_16_SRO_ST_B:
936 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
937 break;
938 case OPC1_16_SRO_ST_H:
939 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
940 break;
941 case OPC1_16_SRO_ST_W:
942 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
943 break;
944 }
945 }
946
947 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
948 {
949 uint32_t op2;
950 op2 = MASK_OP_SR_OP2(ctx->opcode);
951
952 switch (op2) {
953 case OPC2_16_SR_NOP:
954 break;
955 case OPC2_16_SR_RET:
956 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
957 break;
958 case OPC2_16_SR_RFE:
959 gen_helper_rfe(cpu_env);
960 tcg_gen_exit_tb(0);
961 ctx->bstate = BS_BRANCH;
962 break;
963 case OPC2_16_SR_DEBUG:
964 /* raise EXCP_DEBUG */
965 break;
966 }
967 }
968
969 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
970 {
971 uint32_t op2;
972 uint32_t r1;
973 TCGv temp;
974
975 r1 = MASK_OP_SR_S1D(ctx->opcode);
976 op2 = MASK_OP_SR_OP2(ctx->opcode);
977
978 switch (op2) {
979 case OPC2_16_SR_RSUB:
980 /* overflow only if r1 = -0x80000000 */
981 temp = tcg_const_i32(-0x80000000);
982 /* calc V bit */
983 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
984 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
985 /* calc SV bit */
986 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
987 /* sub */
988 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
989 /* calc av */
990 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
991 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
992 /* calc sav */
993 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
994 tcg_temp_free(temp);
995 break;
996 case OPC2_16_SR_SAT_B:
997 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
998 break;
999 case OPC2_16_SR_SAT_BU:
1000 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
1001 break;
1002 case OPC2_16_SR_SAT_H:
1003 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
1004 break;
1005 case OPC2_16_SR_SAT_HU:
1006 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
1007 break;
1008 }
1009 }
1010
1011 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
1012 {
1013 int op1;
1014 int r1, r2;
1015 int32_t const16;
1016 int32_t address;
1017 TCGv temp;
1018
1019 op1 = MASK_OP_MAJOR(ctx->opcode);
1020
1021 /* handle ADDSC.A opcode only being 6 bit long */
1022 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
1023 op1 = OPC1_16_SRRS_ADDSC_A;
1024 }
1025
1026 switch (op1) {
1027 case OPC1_16_SRC_ADD:
1028 case OPC1_16_SRC_ADD_A15:
1029 case OPC1_16_SRC_ADD_15A:
1030 case OPC1_16_SRC_ADD_A:
1031 case OPC1_16_SRC_CADD:
1032 case OPC1_16_SRC_CADDN:
1033 case OPC1_16_SRC_CMOV:
1034 case OPC1_16_SRC_CMOVN:
1035 case OPC1_16_SRC_EQ:
1036 case OPC1_16_SRC_LT:
1037 case OPC1_16_SRC_MOV:
1038 case OPC1_16_SRC_MOV_A:
1039 case OPC1_16_SRC_SH:
1040 case OPC1_16_SRC_SHA:
1041 decode_src_opc(ctx, op1);
1042 break;
1043 /* SRR-format */
1044 case OPC1_16_SRR_ADD:
1045 case OPC1_16_SRR_ADD_A15:
1046 case OPC1_16_SRR_ADD_15A:
1047 case OPC1_16_SRR_ADD_A:
1048 case OPC1_16_SRR_ADDS:
1049 case OPC1_16_SRR_AND:
1050 case OPC1_16_SRR_CMOV:
1051 case OPC1_16_SRR_CMOVN:
1052 case OPC1_16_SRR_EQ:
1053 case OPC1_16_SRR_LT:
1054 case OPC1_16_SRR_MOV:
1055 case OPC1_16_SRR_MOV_A:
1056 case OPC1_16_SRR_MOV_AA:
1057 case OPC1_16_SRR_MOV_D:
1058 case OPC1_16_SRR_MUL:
1059 case OPC1_16_SRR_OR:
1060 case OPC1_16_SRR_SUB:
1061 case OPC1_16_SRR_SUB_A15B:
1062 case OPC1_16_SRR_SUB_15AB:
1063 case OPC1_16_SRR_SUBS:
1064 case OPC1_16_SRR_XOR:
1065 decode_srr_opc(ctx, op1);
1066 break;
1067 /* SSR-format */
1068 case OPC1_16_SSR_ST_A:
1069 case OPC1_16_SSR_ST_A_POSTINC:
1070 case OPC1_16_SSR_ST_B:
1071 case OPC1_16_SSR_ST_B_POSTINC:
1072 case OPC1_16_SSR_ST_H:
1073 case OPC1_16_SSR_ST_H_POSTINC:
1074 case OPC1_16_SSR_ST_W:
1075 case OPC1_16_SSR_ST_W_POSTINC:
1076 decode_ssr_opc(ctx, op1);
1077 break;
1078 /* SRRS-format */
1079 case OPC1_16_SRRS_ADDSC_A:
1080 r2 = MASK_OP_SRRS_S2(ctx->opcode);
1081 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
1082 const16 = MASK_OP_SRRS_N(ctx->opcode);
1083 temp = tcg_temp_new();
1084 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
1085 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
1086 tcg_temp_free(temp);
1087 break;
1088 /* SLRO-format */
1089 case OPC1_16_SLRO_LD_A:
1090 r1 = MASK_OP_SLRO_D(ctx->opcode);
1091 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1092 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1093 break;
1094 case OPC1_16_SLRO_LD_BU:
1095 r1 = MASK_OP_SLRO_D(ctx->opcode);
1096 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1097 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
1098 break;
1099 case OPC1_16_SLRO_LD_H:
1100 r1 = MASK_OP_SLRO_D(ctx->opcode);
1101 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1102 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
1103 break;
1104 case OPC1_16_SLRO_LD_W:
1105 r1 = MASK_OP_SLRO_D(ctx->opcode);
1106 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
1107 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1108 break;
1109 /* SB-format */
1110 case OPC1_16_SB_CALL:
1111 case OPC1_16_SB_J:
1112 case OPC1_16_SB_JNZ:
1113 case OPC1_16_SB_JZ:
1114 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
1115 gen_compute_branch(ctx, op1, 0, 0, 0, address);
1116 break;
1117 /* SBC-format */
1118 case OPC1_16_SBC_JEQ:
1119 case OPC1_16_SBC_JNE:
1120 address = MASK_OP_SBC_DISP4(ctx->opcode);
1121 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
1122 gen_compute_branch(ctx, op1, 0, 0, const16, address);
1123 break;
1124 /* SBRN-format */
1125 case OPC1_16_SBRN_JNZ_T:
1126 case OPC1_16_SBRN_JZ_T:
1127 address = MASK_OP_SBRN_DISP4(ctx->opcode);
1128 const16 = MASK_OP_SBRN_N(ctx->opcode);
1129 gen_compute_branch(ctx, op1, 0, 0, const16, address);
1130 break;
1131 /* SBR-format */
1132 case OPC1_16_SBR_JEQ:
1133 case OPC1_16_SBR_JGEZ:
1134 case OPC1_16_SBR_JGTZ:
1135 case OPC1_16_SBR_JLEZ:
1136 case OPC1_16_SBR_JLTZ:
1137 case OPC1_16_SBR_JNE:
1138 case OPC1_16_SBR_JNZ:
1139 case OPC1_16_SBR_JNZ_A:
1140 case OPC1_16_SBR_JZ:
1141 case OPC1_16_SBR_JZ_A:
1142 case OPC1_16_SBR_LOOP:
1143 r1 = MASK_OP_SBR_S2(ctx->opcode);
1144 address = MASK_OP_SBR_DISP4(ctx->opcode);
1145 gen_compute_branch(ctx, op1, r1, 0, 0, address);
1146 break;
1147 /* SC-format */
1148 case OPC1_16_SC_AND:
1149 case OPC1_16_SC_BISR:
1150 case OPC1_16_SC_LD_A:
1151 case OPC1_16_SC_LD_W:
1152 case OPC1_16_SC_MOV:
1153 case OPC1_16_SC_OR:
1154 case OPC1_16_SC_ST_A:
1155 case OPC1_16_SC_ST_W:
1156 case OPC1_16_SC_SUB_A:
1157 decode_sc_opc(ctx, op1);
1158 break;
1159 /* SLR-format */
1160 case OPC1_16_SLR_LD_A:
1161 case OPC1_16_SLR_LD_A_POSTINC:
1162 case OPC1_16_SLR_LD_BU:
1163 case OPC1_16_SLR_LD_BU_POSTINC:
1164 case OPC1_16_SLR_LD_H:
1165 case OPC1_16_SLR_LD_H_POSTINC:
1166 case OPC1_16_SLR_LD_W:
1167 case OPC1_16_SLR_LD_W_POSTINC:
1168 decode_slr_opc(ctx, op1);
1169 break;
1170 /* SRO-format */
1171 case OPC1_16_SRO_LD_A:
1172 case OPC1_16_SRO_LD_BU:
1173 case OPC1_16_SRO_LD_H:
1174 case OPC1_16_SRO_LD_W:
1175 case OPC1_16_SRO_ST_A:
1176 case OPC1_16_SRO_ST_B:
1177 case OPC1_16_SRO_ST_H:
1178 case OPC1_16_SRO_ST_W:
1179 decode_sro_opc(ctx, op1);
1180 break;
1181 /* SSRO-format */
1182 case OPC1_16_SSRO_ST_A:
1183 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1184 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1185 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1186 break;
1187 case OPC1_16_SSRO_ST_B:
1188 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1189 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1190 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
1191 break;
1192 case OPC1_16_SSRO_ST_H:
1193 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1194 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1195 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
1196 break;
1197 case OPC1_16_SSRO_ST_W:
1198 r1 = MASK_OP_SSRO_S1(ctx->opcode);
1199 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
1200 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
1201 break;
1202 /* SR-format */
1203 case OPCM_16_SR_SYSTEM:
1204 decode_sr_system(env, ctx);
1205 break;
1206 case OPCM_16_SR_ACCU:
1207 decode_sr_accu(env, ctx);
1208 break;
1209 case OPC1_16_SR_JI:
1210 r1 = MASK_OP_SR_S1D(ctx->opcode);
1211 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
1212 break;
1213 case OPC1_16_SR_NOT:
1214 r1 = MASK_OP_SR_S1D(ctx->opcode);
1215 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
1216 break;
1217 }
1218 }
1219
1220 /*
1221 * 32 bit instructions
1222 */
1223
1224 /* ABS-format */
1225 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
1226 {
1227 int32_t op2;
1228 int32_t r1;
1229 uint32_t address;
1230 TCGv temp;
1231
1232 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1233 address = MASK_OP_ABS_OFF18(ctx->opcode);
1234 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1235
1236 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1237
1238 switch (op2) {
1239 case OPC2_32_ABS_LD_A:
1240 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
1241 break;
1242 case OPC2_32_ABS_LD_D:
1243 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
1244 break;
1245 case OPC2_32_ABS_LD_DA:
1246 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
1247 break;
1248 case OPC2_32_ABS_LD_W:
1249 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
1250 break;
1251 }
1252
1253 tcg_temp_free(temp);
1254 }
1255
1256 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
1257 {
1258 int32_t op2;
1259 int32_t r1;
1260 uint32_t address;
1261 TCGv temp;
1262
1263 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1264 address = MASK_OP_ABS_OFF18(ctx->opcode);
1265 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1266
1267 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1268
1269 switch (op2) {
1270 case OPC2_32_ABS_LD_B:
1271 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
1272 break;
1273 case OPC2_32_ABS_LD_BU:
1274 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
1275 break;
1276 case OPC2_32_ABS_LD_H:
1277 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
1278 break;
1279 case OPC2_32_ABS_LD_HU:
1280 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
1281 break;
1282 }
1283
1284 tcg_temp_free(temp);
1285 }
1286
1287 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
1288 {
1289 int32_t op2;
1290 int32_t r1;
1291 uint32_t address;
1292 TCGv temp;
1293
1294 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1295 address = MASK_OP_ABS_OFF18(ctx->opcode);
1296 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1297
1298 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1299
1300 switch (op2) {
1301 case OPC2_32_ABS_LDMST:
1302 gen_ldmst(ctx, r1, temp);
1303 break;
1304 case OPC2_32_ABS_SWAP_W:
1305 gen_swap(ctx, r1, temp);
1306 break;
1307 }
1308
1309 tcg_temp_free(temp);
1310 }
1311
1312 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
1313 {
1314 uint32_t op2;
1315 int32_t off18;
1316
1317 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
1318 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1319
1320 switch (op2) {
1321 case OPC2_32_ABS_LDLCX:
1322 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
1323 break;
1324 case OPC2_32_ABS_LDUCX:
1325 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
1326 break;
1327 case OPC2_32_ABS_STLCX:
1328 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
1329 break;
1330 case OPC2_32_ABS_STUCX:
1331 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
1332 break;
1333 }
1334 }
1335
1336 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
1337 {
1338 int32_t op2;
1339 int32_t r1;
1340 uint32_t address;
1341 TCGv temp;
1342
1343 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1344 address = MASK_OP_ABS_OFF18(ctx->opcode);
1345 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1346
1347 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1348
1349 switch (op2) {
1350 case OPC2_32_ABS_ST_A:
1351 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
1352 break;
1353 case OPC2_32_ABS_ST_D:
1354 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
1355 break;
1356 case OPC2_32_ABS_ST_DA:
1357 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
1358 break;
1359 case OPC2_32_ABS_ST_W:
1360 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
1361 break;
1362
1363 }
1364 tcg_temp_free(temp);
1365 }
1366
1367 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
1368 {
1369 int32_t op2;
1370 int32_t r1;
1371 uint32_t address;
1372 TCGv temp;
1373
1374 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1375 address = MASK_OP_ABS_OFF18(ctx->opcode);
1376 op2 = MASK_OP_ABS_OP2(ctx->opcode);
1377
1378 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1379
1380 switch (op2) {
1381 case OPC2_32_ABS_ST_B:
1382 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
1383 break;
1384 case OPC2_32_ABS_ST_H:
1385 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
1386 break;
1387 }
1388 tcg_temp_free(temp);
1389 }
1390
1391 /* Bit-format */
1392
1393 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
1394 {
1395 uint32_t op2;
1396 int r1, r2, r3;
1397 int pos1, pos2;
1398
1399 r1 = MASK_OP_BIT_S1(ctx->opcode);
1400 r2 = MASK_OP_BIT_S2(ctx->opcode);
1401 r3 = MASK_OP_BIT_D(ctx->opcode);
1402 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1403 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1404 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1405
1406
1407 switch (op2) {
1408 case OPC2_32_BIT_AND_AND_T:
1409 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1410 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
1411 break;
1412 case OPC2_32_BIT_AND_ANDN_T:
1413 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1414 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
1415 break;
1416 case OPC2_32_BIT_AND_NOR_T:
1417 if (TCG_TARGET_HAS_andc_i32) {
1418 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1419 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
1420 } else {
1421 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1422 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
1423 }
1424 break;
1425 case OPC2_32_BIT_AND_OR_T:
1426 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1427 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
1428 break;
1429 }
1430 }
1431
1432 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
1433 {
1434 uint32_t op2;
1435 int r1, r2, r3;
1436 int pos1, pos2;
1437 r1 = MASK_OP_BIT_S1(ctx->opcode);
1438 r2 = MASK_OP_BIT_S2(ctx->opcode);
1439 r3 = MASK_OP_BIT_D(ctx->opcode);
1440 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1441 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1442 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1443
1444 switch (op2) {
1445 case OPC2_32_BIT_AND_T:
1446 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1447 pos1, pos2, &tcg_gen_and_tl);
1448 break;
1449 case OPC2_32_BIT_ANDN_T:
1450 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1451 pos1, pos2, &tcg_gen_andc_tl);
1452 break;
1453 case OPC2_32_BIT_NOR_T:
1454 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1455 pos1, pos2, &tcg_gen_nor_tl);
1456 break;
1457 case OPC2_32_BIT_OR_T:
1458 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1459 pos1, pos2, &tcg_gen_or_tl);
1460 break;
1461 }
1462 }
1463
1464 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
1465 {
1466 uint32_t op2;
1467 int r1, r2, r3;
1468 int pos1, pos2;
1469 TCGv temp;
1470 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1471 r1 = MASK_OP_BIT_S1(ctx->opcode);
1472 r2 = MASK_OP_BIT_S2(ctx->opcode);
1473 r3 = MASK_OP_BIT_D(ctx->opcode);
1474 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1475 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1476
1477 temp = tcg_temp_new();
1478
1479 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
1480 if (op2 == OPC2_32_BIT_INSN_T) {
1481 tcg_gen_not_tl(temp, temp);
1482 }
1483 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
1484 tcg_temp_free(temp);
1485 }
1486
1487 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
1488 {
1489 uint32_t op2;
1490
1491 int r1, r2, r3;
1492 int pos1, pos2;
1493
1494 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1495 r1 = MASK_OP_BIT_S1(ctx->opcode);
1496 r2 = MASK_OP_BIT_S2(ctx->opcode);
1497 r3 = MASK_OP_BIT_D(ctx->opcode);
1498 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1499 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1500
1501 switch (op2) {
1502 case OPC2_32_BIT_NAND_T:
1503 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1504 pos1, pos2, &tcg_gen_nand_tl);
1505 break;
1506 case OPC2_32_BIT_ORN_T:
1507 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1508 pos1, pos2, &tcg_gen_orc_tl);
1509 break;
1510 case OPC2_32_BIT_XNOR_T:
1511 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1512 pos1, pos2, &tcg_gen_eqv_tl);
1513 break;
1514 case OPC2_32_BIT_XOR_T:
1515 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1516 pos1, pos2, &tcg_gen_xor_tl);
1517 break;
1518 }
1519 }
1520
1521 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
1522 {
1523 uint32_t op2;
1524
1525 int r1, r2, r3;
1526 int pos1, pos2;
1527
1528 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1529 r1 = MASK_OP_BIT_S1(ctx->opcode);
1530 r2 = MASK_OP_BIT_S2(ctx->opcode);
1531 r3 = MASK_OP_BIT_D(ctx->opcode);
1532 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1533 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1534
1535 switch (op2) {
1536 case OPC2_32_BIT_OR_AND_T:
1537 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1538 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
1539 break;
1540 case OPC2_32_BIT_OR_ANDN_T:
1541 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1542 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
1543 break;
1544 case OPC2_32_BIT_OR_NOR_T:
1545 if (TCG_TARGET_HAS_orc_i32) {
1546 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1547 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
1548 } else {
1549 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1550 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
1551 }
1552 break;
1553 case OPC2_32_BIT_OR_OR_T:
1554 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
1555 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
1556 break;
1557 }
1558 }
1559
1560 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
1561 {
1562 uint32_t op2;
1563 int r1, r2, r3;
1564 int pos1, pos2;
1565 TCGv temp;
1566
1567 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1568 r1 = MASK_OP_BIT_S1(ctx->opcode);
1569 r2 = MASK_OP_BIT_S2(ctx->opcode);
1570 r3 = MASK_OP_BIT_D(ctx->opcode);
1571 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1572 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1573
1574 temp = tcg_temp_new();
1575
1576 switch (op2) {
1577 case OPC2_32_BIT_SH_AND_T:
1578 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1579 pos1, pos2, &tcg_gen_and_tl);
1580 break;
1581 case OPC2_32_BIT_SH_ANDN_T:
1582 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1583 pos1, pos2, &tcg_gen_andc_tl);
1584 break;
1585 case OPC2_32_BIT_SH_NOR_T:
1586 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1587 pos1, pos2, &tcg_gen_nor_tl);
1588 break;
1589 case OPC2_32_BIT_SH_OR_T:
1590 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1591 pos1, pos2, &tcg_gen_or_tl);
1592 break;
1593 }
1594 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
1595 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
1596 tcg_temp_free(temp);
1597 }
1598
1599 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
1600 {
1601 uint32_t op2;
1602 int r1, r2, r3;
1603 int pos1, pos2;
1604 TCGv temp;
1605
1606 op2 = MASK_OP_BIT_OP2(ctx->opcode);
1607 r1 = MASK_OP_BIT_S1(ctx->opcode);
1608 r2 = MASK_OP_BIT_S2(ctx->opcode);
1609 r3 = MASK_OP_BIT_D(ctx->opcode);
1610 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
1611 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
1612
1613 temp = tcg_temp_new();
1614
1615 switch (op2) {
1616 case OPC2_32_BIT_SH_NAND_T:
1617 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
1618 pos1, pos2, &tcg_gen_nand_tl);
1619 break;
1620 case OPC2_32_BIT_SH_ORN_T:
1621 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1622 pos1, pos2, &tcg_gen_orc_tl);
1623 break;
1624 case OPC2_32_BIT_SH_XNOR_T:
1625 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1626 pos1, pos2, &tcg_gen_eqv_tl);
1627 break;
1628 case OPC2_32_BIT_SH_XOR_T:
1629 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
1630 pos1, pos2, &tcg_gen_xor_tl);
1631 break;
1632 }
1633 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
1634 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
1635 tcg_temp_free(temp);
1636 }
1637
1638 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
1639 {
1640 int op1;
1641 int32_t r1;
1642 int32_t address;
1643 int8_t b;
1644 int32_t bpos;
1645 TCGv temp, temp2;
1646
1647 op1 = MASK_OP_MAJOR(ctx->opcode);
1648
1649 switch (op1) {
1650 /* ABS-format */
1651 case OPCM_32_ABS_LDW:
1652 decode_abs_ldw(env, ctx);
1653 break;
1654 case OPCM_32_ABS_LDB:
1655 decode_abs_ldb(env, ctx);
1656 break;
1657 case OPCM_32_ABS_LDMST_SWAP:
1658 decode_abs_ldst_swap(env, ctx);
1659 break;
1660 case OPCM_32_ABS_LDST_CONTEXT:
1661 decode_abs_ldst_context(env, ctx);
1662 break;
1663 case OPCM_32_ABS_STORE:
1664 decode_abs_store(env, ctx);
1665 break;
1666 case OPCM_32_ABS_STOREB_H:
1667 decode_abs_storeb_h(env, ctx);
1668 break;
1669 case OPC1_32_ABS_STOREQ:
1670 address = MASK_OP_ABS_OFF18(ctx->opcode);
1671 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1672 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1673 temp2 = tcg_temp_new();
1674
1675 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
1676 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
1677
1678 tcg_temp_free(temp2);
1679 tcg_temp_free(temp);
1680 break;
1681 case OPC1_32_ABS_LD_Q:
1682 address = MASK_OP_ABS_OFF18(ctx->opcode);
1683 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1684 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1685
1686 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
1687 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
1688
1689 tcg_temp_free(temp);
1690 break;
1691 case OPC1_32_ABS_LEA:
1692 address = MASK_OP_ABS_OFF18(ctx->opcode);
1693 r1 = MASK_OP_ABS_S1D(ctx->opcode);
1694 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
1695 break;
1696 /* ABSB-format */
1697 case OPC1_32_ABSB_ST_T:
1698 address = MASK_OP_ABS_OFF18(ctx->opcode);
1699 b = MASK_OP_ABSB_B(ctx->opcode);
1700 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
1701
1702 temp = tcg_const_i32(EA_ABS_FORMAT(address));
1703 temp2 = tcg_temp_new();
1704
1705 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
1706 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
1707 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
1708 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
1709
1710 tcg_temp_free(temp);
1711 tcg_temp_free(temp2);
1712 break;
1713 /* B-format */
1714 case OPC1_32_B_CALL:
1715 case OPC1_32_B_CALLA:
1716 case OPC1_32_B_J:
1717 case OPC1_32_B_JA:
1718 case OPC1_32_B_JL:
1719 case OPC1_32_B_JLA:
1720 address = MASK_OP_B_DISP24(ctx->opcode);
1721 gen_compute_branch(ctx, op1, 0, 0, 0, address);
1722 break;
1723 /* Bit-format */
1724 case OPCM_32_BIT_ANDACC:
1725 decode_bit_andacc(env, ctx);
1726 break;
1727 case OPCM_32_BIT_LOGICAL_T1:
1728 decode_bit_logical_t(env, ctx);
1729 break;
1730 case OPCM_32_BIT_INSERT:
1731 decode_bit_insert(env, ctx);
1732 break;
1733 case OPCM_32_BIT_LOGICAL_T2:
1734 decode_bit_logical_t2(env, ctx);
1735 break;
1736 case OPCM_32_BIT_ORAND:
1737 decode_bit_orand(env, ctx);
1738 break;
1739 case OPCM_32_BIT_SH_LOGIC1:
1740 decode_bit_sh_logic1(env, ctx);
1741 break;
1742 case OPCM_32_BIT_SH_LOGIC2:
1743 decode_bit_sh_logic2(env, ctx);
1744 break;
1745 }
1746 }
1747
1748 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
1749 {
1750 /* 16-Bit Instruction */
1751 if ((ctx->opcode & 0x1) == 0) {
1752 ctx->next_pc = ctx->pc + 2;
1753 decode_16Bit_opc(env, ctx);
1754 /* 32-Bit Instruction */
1755 } else {
1756 ctx->next_pc = ctx->pc + 4;
1757 decode_32Bit_opc(env, ctx);
1758 }
1759 }
1760
1761 static inline void
1762 gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
1763 int search_pc)
1764 {
1765 CPUState *cs = CPU(cpu);
1766 CPUTriCoreState *env = &cpu->env;
1767 DisasContext ctx;
1768 target_ulong pc_start;
1769 int num_insns;
1770 uint16_t *gen_opc_end;
1771
1772 if (search_pc) {
1773 qemu_log("search pc %d\n", search_pc);
1774 }
1775
1776 num_insns = 0;
1777 pc_start = tb->pc;
1778 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
1779 ctx.pc = pc_start;
1780 ctx.saved_pc = -1;
1781 ctx.tb = tb;
1782 ctx.singlestep_enabled = cs->singlestep_enabled;
1783 ctx.bstate = BS_NONE;
1784 ctx.mem_idx = cpu_mmu_index(env);
1785
1786 tcg_clear_temp_count();
1787 gen_tb_start();
1788 while (ctx.bstate == BS_NONE) {
1789 ctx.opcode = cpu_ldl_code(env, ctx.pc);
1790 decode_opc(env, &ctx, 0);
1791
1792 num_insns++;
1793
1794 if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
1795 gen_save_pc(ctx.next_pc);
1796 tcg_gen_exit_tb(0);
1797 break;
1798 }
1799 if (singlestep) {
1800 gen_save_pc(ctx.next_pc);
1801 tcg_gen_exit_tb(0);
1802 break;
1803 }
1804 ctx.pc = ctx.next_pc;
1805 }
1806
1807 gen_tb_end(tb, num_insns);
1808 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
1809 if (search_pc) {
1810 printf("done_generating search pc\n");
1811 } else {
1812 tb->size = ctx.pc - pc_start;
1813 tb->icount = num_insns;
1814 }
1815 if (tcg_check_temp_count()) {
1816 printf("LEAK at %08x\n", env->PC);
1817 }
1818
1819 #ifdef DEBUG_DISAS
1820 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1821 qemu_log("IN: %s\n", lookup_symbol(pc_start));
1822 log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
1823 qemu_log("\n");
1824 }
1825 #endif
1826 }
1827
1828 void
1829 gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
1830 {
1831 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
1832 }
1833
1834 void
1835 gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
1836 {
1837 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
1838 }
1839
1840 void
1841 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
1842 {
1843 env->PC = tcg_ctx.gen_opc_pc[pc_pos];
1844 }
1845 /*
1846 *
1847 * Initialization
1848 *
1849 */
1850
1851 void cpu_state_reset(CPUTriCoreState *env)
1852 {
1853 /* Reset Regs to Default Value */
1854 env->PSW = 0xb80;
1855 }
1856
1857 static void tricore_tcg_init_csfr(void)
1858 {
1859 cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
1860 offsetof(CPUTriCoreState, PCXI), "PCXI");
1861 cpu_PSW = tcg_global_mem_new(TCG_AREG0,
1862 offsetof(CPUTriCoreState, PSW), "PSW");
1863 cpu_PC = tcg_global_mem_new(TCG_AREG0,
1864 offsetof(CPUTriCoreState, PC), "PC");
1865 cpu_ICR = tcg_global_mem_new(TCG_AREG0,
1866 offsetof(CPUTriCoreState, ICR), "ICR");
1867 }
1868
1869 void tricore_tcg_init(void)
1870 {
1871 int i;
1872 static int inited;
1873 if (inited) {
1874 return;
1875 }
1876 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1877 /* reg init */
1878 for (i = 0 ; i < 16 ; i++) {
1879 cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
1880 offsetof(CPUTriCoreState, gpr_a[i]),
1881 regnames_a[i]);
1882 }
1883 for (i = 0 ; i < 16 ; i++) {
1884 cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
1885 offsetof(CPUTriCoreState, gpr_d[i]),
1886 regnames_d[i]);
1887 }
1888 tricore_tcg_init_csfr();
1889 /* init PSW flag cache */
1890 cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
1891 offsetof(CPUTriCoreState, PSW_USB_C),
1892 "PSW_C");
1893 cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
1894 offsetof(CPUTriCoreState, PSW_USB_V),
1895 "PSW_V");
1896 cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
1897 offsetof(CPUTriCoreState, PSW_USB_SV),
1898 "PSW_SV");
1899 cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
1900 offsetof(CPUTriCoreState, PSW_USB_AV),
1901 "PSW_AV");
1902 cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
1903 offsetof(CPUTriCoreState, PSW_USB_SAV),
1904 "PSW_SAV");
1905 }
QEmu