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nbd: Improve server handling of shutdown requests
[qemu.git] / target-ppc / translate.c
blob43505a936c14688c0604c692118982a3e05f6015
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 bool need_access_type;
199 int mem_idx;
200 int access_type;
201 /* Translation flags */
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 bool sf_mode;
205 bool has_cfar;
206 #endif
207 bool fpu_enabled;
208 bool altivec_enabled;
209 bool vsx_enabled;
210 bool spe_enabled;
211 bool tm_enabled;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->nip - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->nip);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->nip);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
380 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
381
382 typedef struct opcode_t {
383 unsigned char opc1, opc2, opc3, opc4;
384 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
385 unsigned char pad[4];
386 #endif
387 opc_handler_t handler;
388 const char *oname;
389 } opcode_t;
390
391 /* Helpers for priv. check */
392 #define GEN_PRIV \
393 do { \
394 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
395 } while (0)
396
397 #if defined(CONFIG_USER_ONLY)
398 #define CHK_HV GEN_PRIV
399 #define CHK_SV GEN_PRIV
400 #define CHK_HVRM GEN_PRIV
401 #else
402 #define CHK_HV \
403 do { \
404 if (unlikely(ctx->pr || !ctx->hv)) { \
405 GEN_PRIV; \
406 } \
407 } while (0)
408 #define CHK_SV \
409 do { \
410 if (unlikely(ctx->pr)) { \
411 GEN_PRIV; \
412 } \
413 } while (0)
414 #define CHK_HVRM \
415 do { \
416 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
417 GEN_PRIV; \
418 } \
419 } while (0)
420 #endif
421
422 #define CHK_NONE
423
424
425 /*****************************************************************************/
426 /*** Instruction decoding ***/
427 #define EXTRACT_HELPER(name, shift, nb) \
428 static inline uint32_t name(uint32_t opcode) \
429 { \
430 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
431 }
432
433 #define EXTRACT_SHELPER(name, shift, nb) \
434 static inline int32_t name(uint32_t opcode) \
435 { \
436 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
437 }
438
439 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
440 static inline uint32_t name(uint32_t opcode) \
441 { \
442 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
443 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
444 }
445
446 #define EXTRACT_HELPER_DXFORM(name, \
447 d0_bits, shift_op_d0, shift_d0, \
448 d1_bits, shift_op_d1, shift_d1, \
449 d2_bits, shift_op_d2, shift_d2) \
450 static inline int16_t name(uint32_t opcode) \
451 { \
452 return \
453 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
454 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
455 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
456 }
457
458
459 /* Opcode part 1 */
460 EXTRACT_HELPER(opc1, 26, 6);
461 /* Opcode part 2 */
462 EXTRACT_HELPER(opc2, 1, 5);
463 /* Opcode part 3 */
464 EXTRACT_HELPER(opc3, 6, 5);
465 /* Opcode part 4 */
466 EXTRACT_HELPER(opc4, 16, 5);
467 /* Update Cr0 flags */
468 EXTRACT_HELPER(Rc, 0, 1);
469 /* Update Cr6 flags (Altivec) */
470 EXTRACT_HELPER(Rc21, 10, 1);
471 /* Destination */
472 EXTRACT_HELPER(rD, 21, 5);
473 /* Source */
474 EXTRACT_HELPER(rS, 21, 5);
475 /* First operand */
476 EXTRACT_HELPER(rA, 16, 5);
477 /* Second operand */
478 EXTRACT_HELPER(rB, 11, 5);
479 /* Third operand */
480 EXTRACT_HELPER(rC, 6, 5);
481 /*** Get CRn ***/
482 EXTRACT_HELPER(crfD, 23, 3);
483 EXTRACT_HELPER(crfS, 18, 3);
484 EXTRACT_HELPER(crbD, 21, 5);
485 EXTRACT_HELPER(crbA, 16, 5);
486 EXTRACT_HELPER(crbB, 11, 5);
487 /* SPR / TBL */
488 EXTRACT_HELPER(_SPR, 11, 10);
489 static inline uint32_t SPR(uint32_t opcode)
490 {
491 uint32_t sprn = _SPR(opcode);
492
493 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
494 }
495 /*** Get constants ***/
496 /* 16 bits signed immediate value */
497 EXTRACT_SHELPER(SIMM, 0, 16);
498 /* 16 bits unsigned immediate value */
499 EXTRACT_HELPER(UIMM, 0, 16);
500 /* 5 bits signed immediate value */
501 EXTRACT_HELPER(SIMM5, 16, 5);
502 /* 5 bits signed immediate value */
503 EXTRACT_HELPER(UIMM5, 16, 5);
504 /* 4 bits unsigned immediate value */
505 EXTRACT_HELPER(UIMM4, 16, 4);
506 /* Bit count */
507 EXTRACT_HELPER(NB, 11, 5);
508 /* Shift count */
509 EXTRACT_HELPER(SH, 11, 5);
510 /* Vector shift count */
511 EXTRACT_HELPER(VSH, 6, 4);
512 /* Mask start */
513 EXTRACT_HELPER(MB, 6, 5);
514 /* Mask end */
515 EXTRACT_HELPER(ME, 1, 5);
516 /* Trap operand */
517 EXTRACT_HELPER(TO, 21, 5);
518
519 EXTRACT_HELPER(CRM, 12, 8);
520
521 #ifndef CONFIG_USER_ONLY
522 EXTRACT_HELPER(SR, 16, 4);
523 #endif
524
525 /* mtfsf/mtfsfi */
526 EXTRACT_HELPER(FPBF, 23, 3);
527 EXTRACT_HELPER(FPIMM, 12, 4);
528 EXTRACT_HELPER(FPL, 25, 1);
529 EXTRACT_HELPER(FPFLM, 17, 8);
530 EXTRACT_HELPER(FPW, 16, 1);
531
532 /* addpcis */
533 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
534 #if defined(TARGET_PPC64)
535 /* darn */
536 EXTRACT_HELPER(L, 16, 2);
537 #endif
538
539 /*** Jump target decoding ***/
540 /* Immediate address */
541 static inline target_ulong LI(uint32_t opcode)
542 {
543 return (opcode >> 0) & 0x03FFFFFC;
544 }
545
546 static inline uint32_t BD(uint32_t opcode)
547 {
548 return (opcode >> 0) & 0xFFFC;
549 }
550
551 EXTRACT_HELPER(BO, 21, 5);
552 EXTRACT_HELPER(BI, 16, 5);
553 /* Absolute/relative address */
554 EXTRACT_HELPER(AA, 1, 1);
555 /* Link */
556 EXTRACT_HELPER(LK, 0, 1);
557
558 /* DFP Z22-form */
559 EXTRACT_HELPER(DCM, 10, 6)
560
561 /* DFP Z23-form */
562 EXTRACT_HELPER(RMC, 9, 2)
563
564 /* Create a mask between <start> and <end> bits */
565 static inline target_ulong MASK(uint32_t start, uint32_t end)
566 {
567 target_ulong ret;
568
569 #if defined(TARGET_PPC64)
570 if (likely(start == 0)) {
571 ret = UINT64_MAX << (63 - end);
572 } else if (likely(end == 63)) {
573 ret = UINT64_MAX >> start;
574 }
575 #else
576 if (likely(start == 0)) {
577 ret = UINT32_MAX << (31 - end);
578 } else if (likely(end == 31)) {
579 ret = UINT32_MAX >> start;
580 }
581 #endif
582 else {
583 ret = (((target_ulong)(-1ULL)) >> (start)) ^
584 (((target_ulong)(-1ULL) >> (end)) >> 1);
585 if (unlikely(start > end))
586 return ~ret;
587 }
588
589 return ret;
590 }
591
592 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
593 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
594 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
595 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
596 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
597 EXTRACT_HELPER(DM, 8, 2);
598 EXTRACT_HELPER(UIM, 16, 2);
599 EXTRACT_HELPER(SHW, 8, 2);
600 EXTRACT_HELPER(SP, 19, 2);
601 EXTRACT_HELPER(IMM8, 11, 8);
602
603 /*****************************************************************************/
604 /* PowerPC instructions table */
605
606 #if defined(DO_PPC_STATISTICS)
607 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
608 { \
609 .opc1 = op1, \
610 .opc2 = op2, \
611 .opc3 = op3, \
612 .opc4 = 0xff, \
613 .handler = { \
614 .inval1 = invl, \
615 .type = _typ, \
616 .type2 = _typ2, \
617 .handler = &gen_##name, \
618 .oname = stringify(name), \
619 }, \
620 .oname = stringify(name), \
621 }
622 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
623 { \
624 .opc1 = op1, \
625 .opc2 = op2, \
626 .opc3 = op3, \
627 .opc4 = 0xff, \
628 .handler = { \
629 .inval1 = invl1, \
630 .inval2 = invl2, \
631 .type = _typ, \
632 .type2 = _typ2, \
633 .handler = &gen_##name, \
634 .oname = stringify(name), \
635 }, \
636 .oname = stringify(name), \
637 }
638 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
639 { \
640 .opc1 = op1, \
641 .opc2 = op2, \
642 .opc3 = op3, \
643 .opc4 = 0xff, \
644 .handler = { \
645 .inval1 = invl, \
646 .type = _typ, \
647 .type2 = _typ2, \
648 .handler = &gen_##name, \
649 .oname = onam, \
650 }, \
651 .oname = onam, \
652 }
653 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
654 { \
655 .opc1 = op1, \
656 .opc2 = op2, \
657 .opc3 = op3, \
658 .opc4 = op4, \
659 .handler = { \
660 .inval1 = invl, \
661 .type = _typ, \
662 .type2 = _typ2, \
663 .handler = &gen_##name, \
664 .oname = stringify(name), \
665 }, \
666 .oname = stringify(name), \
667 }
668 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
669 { \
670 .opc1 = op1, \
671 .opc2 = op2, \
672 .opc3 = op3, \
673 .opc4 = op4, \
674 .handler = { \
675 .inval1 = invl, \
676 .type = _typ, \
677 .type2 = _typ2, \
678 .handler = &gen_##name, \
679 .oname = onam, \
680 }, \
681 .oname = onam, \
682 }
683 #else
684 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
685 { \
686 .opc1 = op1, \
687 .opc2 = op2, \
688 .opc3 = op3, \
689 .opc4 = 0xff, \
690 .handler = { \
691 .inval1 = invl, \
692 .type = _typ, \
693 .type2 = _typ2, \
694 .handler = &gen_##name, \
695 }, \
696 .oname = stringify(name), \
697 }
698 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
699 { \
700 .opc1 = op1, \
701 .opc2 = op2, \
702 .opc3 = op3, \
703 .opc4 = 0xff, \
704 .handler = { \
705 .inval1 = invl1, \
706 .inval2 = invl2, \
707 .type = _typ, \
708 .type2 = _typ2, \
709 .handler = &gen_##name, \
710 }, \
711 .oname = stringify(name), \
712 }
713 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
714 { \
715 .opc1 = op1, \
716 .opc2 = op2, \
717 .opc3 = op3, \
718 .opc4 = 0xff, \
719 .handler = { \
720 .inval1 = invl, \
721 .type = _typ, \
722 .type2 = _typ2, \
723 .handler = &gen_##name, \
724 }, \
725 .oname = onam, \
726 }
727 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
728 { \
729 .opc1 = op1, \
730 .opc2 = op2, \
731 .opc3 = op3, \
732 .opc4 = op4, \
733 .handler = { \
734 .inval1 = invl, \
735 .type = _typ, \
736 .type2 = _typ2, \
737 .handler = &gen_##name, \
738 }, \
739 .oname = stringify(name), \
740 }
741 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
742 { \
743 .opc1 = op1, \
744 .opc2 = op2, \
745 .opc3 = op3, \
746 .opc4 = op4, \
747 .handler = { \
748 .inval1 = invl, \
749 .type = _typ, \
750 .type2 = _typ2, \
751 .handler = &gen_##name, \
752 }, \
753 .oname = onam, \
754 }
755 #endif
756
757 /* SPR load/store helpers */
758 static inline void gen_load_spr(TCGv t, int reg)
759 {
760 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
761 }
762
763 static inline void gen_store_spr(int reg, TCGv t)
764 {
765 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
766 }
767
768 /* Invalid instruction */
769 static void gen_invalid(DisasContext *ctx)
770 {
771 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
772 }
773
774 static opc_handler_t invalid_handler = {
775 .inval1 = 0xFFFFFFFF,
776 .inval2 = 0xFFFFFFFF,
777 .type = PPC_NONE,
778 .type2 = PPC_NONE,
779 .handler = gen_invalid,
780 };
781
782 /*** Integer comparison ***/
783
784 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
785 {
786 TCGv t0 = tcg_temp_new();
787 TCGv_i32 t1 = tcg_temp_new_i32();
788
789 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
790
791 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
792 tcg_gen_trunc_tl_i32(t1, t0);
793 tcg_gen_shli_i32(t1, t1, CRF_LT);
794 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
795
796 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
797 tcg_gen_trunc_tl_i32(t1, t0);
798 tcg_gen_shli_i32(t1, t1, CRF_GT);
799 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
800
801 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
802 tcg_gen_trunc_tl_i32(t1, t0);
803 tcg_gen_shli_i32(t1, t1, CRF_EQ);
804 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
805
806 tcg_temp_free(t0);
807 tcg_temp_free_i32(t1);
808 }
809
810 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
811 {
812 TCGv t0 = tcg_const_tl(arg1);
813 gen_op_cmp(arg0, t0, s, crf);
814 tcg_temp_free(t0);
815 }
816
817 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
818 {
819 TCGv t0, t1;
820 t0 = tcg_temp_new();
821 t1 = tcg_temp_new();
822 if (s) {
823 tcg_gen_ext32s_tl(t0, arg0);
824 tcg_gen_ext32s_tl(t1, arg1);
825 } else {
826 tcg_gen_ext32u_tl(t0, arg0);
827 tcg_gen_ext32u_tl(t1, arg1);
828 }
829 gen_op_cmp(t0, t1, s, crf);
830 tcg_temp_free(t1);
831 tcg_temp_free(t0);
832 }
833
834 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
835 {
836 TCGv t0 = tcg_const_tl(arg1);
837 gen_op_cmp32(arg0, t0, s, crf);
838 tcg_temp_free(t0);
839 }
840
841 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
842 {
843 if (NARROW_MODE(ctx)) {
844 gen_op_cmpi32(reg, 0, 1, 0);
845 } else {
846 gen_op_cmpi(reg, 0, 1, 0);
847 }
848 }
849
850 /* cmp */
851 static void gen_cmp(DisasContext *ctx)
852 {
853 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
854 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
855 1, crfD(ctx->opcode));
856 } else {
857 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
858 1, crfD(ctx->opcode));
859 }
860 }
861
862 /* cmpi */
863 static void gen_cmpi(DisasContext *ctx)
864 {
865 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
866 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
867 1, crfD(ctx->opcode));
868 } else {
869 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
870 1, crfD(ctx->opcode));
871 }
872 }
873
874 /* cmpl */
875 static void gen_cmpl(DisasContext *ctx)
876 {
877 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
878 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
879 0, crfD(ctx->opcode));
880 } else {
881 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
882 0, crfD(ctx->opcode));
883 }
884 }
885
886 /* cmpli */
887 static void gen_cmpli(DisasContext *ctx)
888 {
889 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
890 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
891 0, crfD(ctx->opcode));
892 } else {
893 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
894 0, crfD(ctx->opcode));
895 }
896 }
897
898 /* cmprb - range comparison: isupper, isaplha, islower*/
899 static void gen_cmprb(DisasContext *ctx)
900 {
901 TCGv_i32 src1 = tcg_temp_new_i32();
902 TCGv_i32 src2 = tcg_temp_new_i32();
903 TCGv_i32 src2lo = tcg_temp_new_i32();
904 TCGv_i32 src2hi = tcg_temp_new_i32();
905 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
906
907 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
908 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
909
910 tcg_gen_andi_i32(src1, src1, 0xFF);
911 tcg_gen_ext8u_i32(src2lo, src2);
912 tcg_gen_shri_i32(src2, src2, 8);
913 tcg_gen_ext8u_i32(src2hi, src2);
914
915 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
916 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
917 tcg_gen_and_i32(crf, src2lo, src2hi);
918
919 if (ctx->opcode & 0x00200000) {
920 tcg_gen_shri_i32(src2, src2, 8);
921 tcg_gen_ext8u_i32(src2lo, src2);
922 tcg_gen_shri_i32(src2, src2, 8);
923 tcg_gen_ext8u_i32(src2hi, src2);
924 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
925 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
926 tcg_gen_and_i32(src2lo, src2lo, src2hi);
927 tcg_gen_or_i32(crf, crf, src2lo);
928 }
929 tcg_gen_shli_i32(crf, crf, CRF_GT);
930 tcg_temp_free_i32(src1);
931 tcg_temp_free_i32(src2);
932 tcg_temp_free_i32(src2lo);
933 tcg_temp_free_i32(src2hi);
934 }
935
936 #if defined(TARGET_PPC64)
937 /* cmpeqb */
938 static void gen_cmpeqb(DisasContext *ctx)
939 {
940 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
941 cpu_gpr[rB(ctx->opcode)]);
942 }
943 #endif
944
945 /* isel (PowerPC 2.03 specification) */
946 static void gen_isel(DisasContext *ctx)
947 {
948 uint32_t bi = rC(ctx->opcode);
949 uint32_t mask = 0x08 >> (bi & 0x03);
950 TCGv t0 = tcg_temp_new();
951 TCGv zr;
952
953 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
954 tcg_gen_andi_tl(t0, t0, mask);
955
956 zr = tcg_const_tl(0);
957 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
958 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
959 cpu_gpr[rB(ctx->opcode)]);
960 tcg_temp_free(zr);
961 tcg_temp_free(t0);
962 }
963
964 /* cmpb: PowerPC 2.05 specification */
965 static void gen_cmpb(DisasContext *ctx)
966 {
967 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
968 cpu_gpr[rB(ctx->opcode)]);
969 }
970
971 /*** Integer arithmetic ***/
972
973 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
974 TCGv arg1, TCGv arg2, int sub)
975 {
976 TCGv t0 = tcg_temp_new();
977
978 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
979 tcg_gen_xor_tl(t0, arg1, arg2);
980 if (sub) {
981 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
982 } else {
983 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
984 }
985 tcg_temp_free(t0);
986 if (NARROW_MODE(ctx)) {
987 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
988 }
989 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
990 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
991 }
992
993 /* Common add function */
994 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
995 TCGv arg2, bool add_ca, bool compute_ca,
996 bool compute_ov, bool compute_rc0)
997 {
998 TCGv t0 = ret;
999
1000 if (compute_ca || compute_ov) {
1001 t0 = tcg_temp_new();
1002 }
1003
1004 if (compute_ca) {
1005 if (NARROW_MODE(ctx)) {
1006 /* Caution: a non-obvious corner case of the spec is that we
1007 must produce the *entire* 64-bit addition, but produce the
1008 carry into bit 32. */
1009 TCGv t1 = tcg_temp_new();
1010 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
1011 tcg_gen_add_tl(t0, arg1, arg2);
1012 if (add_ca) {
1013 tcg_gen_add_tl(t0, t0, cpu_ca);
1014 }
1015 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
1016 tcg_temp_free(t1);
1017 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1018 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1019 } else {
1020 TCGv zero = tcg_const_tl(0);
1021 if (add_ca) {
1022 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
1023 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
1024 } else {
1025 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
1026 }
1027 tcg_temp_free(zero);
1028 }
1029 } else {
1030 tcg_gen_add_tl(t0, arg1, arg2);
1031 if (add_ca) {
1032 tcg_gen_add_tl(t0, t0, cpu_ca);
1033 }
1034 }
1035
1036 if (compute_ov) {
1037 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1038 }
1039 if (unlikely(compute_rc0)) {
1040 gen_set_Rc0(ctx, t0);
1041 }
1042
1043 if (!TCGV_EQUAL(t0, ret)) {
1044 tcg_gen_mov_tl(ret, t0);
1045 tcg_temp_free(t0);
1046 }
1047 }
1048 /* Add functions with two operands */
1049 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1050 static void glue(gen_, name)(DisasContext *ctx) \
1051 { \
1052 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1053 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1054 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1055 }
1056 /* Add functions with one operand and one immediate */
1057 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1058 add_ca, compute_ca, compute_ov) \
1059 static void glue(gen_, name)(DisasContext *ctx) \
1060 { \
1061 TCGv t0 = tcg_const_tl(const_val); \
1062 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1063 cpu_gpr[rA(ctx->opcode)], t0, \
1064 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1065 tcg_temp_free(t0); \
1066 }
1067
1068 /* add add. addo addo. */
1069 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1070 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1071 /* addc addc. addco addco. */
1072 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1073 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1074 /* adde adde. addeo addeo. */
1075 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1076 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1077 /* addme addme. addmeo addmeo. */
1078 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1079 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1080 /* addze addze. addzeo addzeo.*/
1081 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1082 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1083 /* addi */
1084 static void gen_addi(DisasContext *ctx)
1085 {
1086 target_long simm = SIMM(ctx->opcode);
1087
1088 if (rA(ctx->opcode) == 0) {
1089 /* li case */
1090 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1091 } else {
1092 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1093 cpu_gpr[rA(ctx->opcode)], simm);
1094 }
1095 }
1096 /* addic addic.*/
1097 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1098 {
1099 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1100 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1101 c, 0, 1, 0, compute_rc0);
1102 tcg_temp_free(c);
1103 }
1104
1105 static void gen_addic(DisasContext *ctx)
1106 {
1107 gen_op_addic(ctx, 0);
1108 }
1109
1110 static void gen_addic_(DisasContext *ctx)
1111 {
1112 gen_op_addic(ctx, 1);
1113 }
1114
1115 /* addis */
1116 static void gen_addis(DisasContext *ctx)
1117 {
1118 target_long simm = SIMM(ctx->opcode);
1119
1120 if (rA(ctx->opcode) == 0) {
1121 /* lis case */
1122 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1123 } else {
1124 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1125 cpu_gpr[rA(ctx->opcode)], simm << 16);
1126 }
1127 }
1128
1129 /* addpcis */
1130 static void gen_addpcis(DisasContext *ctx)
1131 {
1132 target_long d = DX(ctx->opcode);
1133
1134 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1135 }
1136
1137 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1138 TCGv arg2, int sign, int compute_ov)
1139 {
1140 TCGv_i32 t0 = tcg_temp_new_i32();
1141 TCGv_i32 t1 = tcg_temp_new_i32();
1142 TCGv_i32 t2 = tcg_temp_new_i32();
1143 TCGv_i32 t3 = tcg_temp_new_i32();
1144
1145 tcg_gen_trunc_tl_i32(t0, arg1);
1146 tcg_gen_trunc_tl_i32(t1, arg2);
1147 if (sign) {
1148 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1149 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1150 tcg_gen_and_i32(t2, t2, t3);
1151 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1152 tcg_gen_or_i32(t2, t2, t3);
1153 tcg_gen_movi_i32(t3, 0);
1154 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1155 tcg_gen_div_i32(t3, t0, t1);
1156 tcg_gen_extu_i32_tl(ret, t3);
1157 } else {
1158 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1159 tcg_gen_movi_i32(t3, 0);
1160 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1161 tcg_gen_divu_i32(t3, t0, t1);
1162 tcg_gen_extu_i32_tl(ret, t3);
1163 }
1164 if (compute_ov) {
1165 tcg_gen_extu_i32_tl(cpu_ov, t2);
1166 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1167 }
1168 tcg_temp_free_i32(t0);
1169 tcg_temp_free_i32(t1);
1170 tcg_temp_free_i32(t2);
1171 tcg_temp_free_i32(t3);
1172
1173 if (unlikely(Rc(ctx->opcode) != 0))
1174 gen_set_Rc0(ctx, ret);
1175 }
1176 /* Div functions */
1177 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1178 static void glue(gen_, name)(DisasContext *ctx) \
1179 { \
1180 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1181 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1182 sign, compute_ov); \
1183 }
1184 /* divwu divwu. divwuo divwuo. */
1185 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1186 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1187 /* divw divw. divwo divwo. */
1188 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1189 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1190
1191 /* div[wd]eu[o][.] */
1192 #define GEN_DIVE(name, hlpr, compute_ov) \
1193 static void gen_##name(DisasContext *ctx) \
1194 { \
1195 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1196 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1197 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1198 tcg_temp_free_i32(t0); \
1199 if (unlikely(Rc(ctx->opcode) != 0)) { \
1200 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1201 } \
1202 }
1203
1204 GEN_DIVE(divweu, divweu, 0);
1205 GEN_DIVE(divweuo, divweu, 1);
1206 GEN_DIVE(divwe, divwe, 0);
1207 GEN_DIVE(divweo, divwe, 1);
1208
1209 #if defined(TARGET_PPC64)
1210 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1211 TCGv arg2, int sign, int compute_ov)
1212 {
1213 TCGv_i64 t0 = tcg_temp_new_i64();
1214 TCGv_i64 t1 = tcg_temp_new_i64();
1215 TCGv_i64 t2 = tcg_temp_new_i64();
1216 TCGv_i64 t3 = tcg_temp_new_i64();
1217
1218 tcg_gen_mov_i64(t0, arg1);
1219 tcg_gen_mov_i64(t1, arg2);
1220 if (sign) {
1221 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1222 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1223 tcg_gen_and_i64(t2, t2, t3);
1224 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1225 tcg_gen_or_i64(t2, t2, t3);
1226 tcg_gen_movi_i64(t3, 0);
1227 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1228 tcg_gen_div_i64(ret, t0, t1);
1229 } else {
1230 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1231 tcg_gen_movi_i64(t3, 0);
1232 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1233 tcg_gen_divu_i64(ret, t0, t1);
1234 }
1235 if (compute_ov) {
1236 tcg_gen_mov_tl(cpu_ov, t2);
1237 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1238 }
1239 tcg_temp_free_i64(t0);
1240 tcg_temp_free_i64(t1);
1241 tcg_temp_free_i64(t2);
1242 tcg_temp_free_i64(t3);
1243
1244 if (unlikely(Rc(ctx->opcode) != 0))
1245 gen_set_Rc0(ctx, ret);
1246 }
1247
1248 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1249 static void glue(gen_, name)(DisasContext *ctx) \
1250 { \
1251 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1252 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1253 sign, compute_ov); \
1254 }
1255 /* divwu divwu. divwuo divwuo. */
1256 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1257 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1258 /* divw divw. divwo divwo. */
1259 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1260 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1261
1262 GEN_DIVE(divdeu, divdeu, 0);
1263 GEN_DIVE(divdeuo, divdeu, 1);
1264 GEN_DIVE(divde, divde, 0);
1265 GEN_DIVE(divdeo, divde, 1);
1266 #endif
1267
1268 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1269 TCGv arg2, int sign)
1270 {
1271 TCGv_i32 t0 = tcg_temp_new_i32();
1272 TCGv_i32 t1 = tcg_temp_new_i32();
1273
1274 tcg_gen_trunc_tl_i32(t0, arg1);
1275 tcg_gen_trunc_tl_i32(t1, arg2);
1276 if (sign) {
1277 TCGv_i32 t2 = tcg_temp_new_i32();
1278 TCGv_i32 t3 = tcg_temp_new_i32();
1279 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1280 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1281 tcg_gen_and_i32(t2, t2, t3);
1282 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1283 tcg_gen_or_i32(t2, t2, t3);
1284 tcg_gen_movi_i32(t3, 0);
1285 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1286 tcg_gen_rem_i32(t3, t0, t1);
1287 tcg_gen_ext_i32_tl(ret, t3);
1288 tcg_temp_free_i32(t2);
1289 tcg_temp_free_i32(t3);
1290 } else {
1291 TCGv_i32 t2 = tcg_const_i32(1);
1292 TCGv_i32 t3 = tcg_const_i32(0);
1293 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1294 tcg_gen_remu_i32(t3, t0, t1);
1295 tcg_gen_extu_i32_tl(ret, t3);
1296 tcg_temp_free_i32(t2);
1297 tcg_temp_free_i32(t3);
1298 }
1299 tcg_temp_free_i32(t0);
1300 tcg_temp_free_i32(t1);
1301 }
1302
1303 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1304 static void glue(gen_, name)(DisasContext *ctx) \
1305 { \
1306 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1307 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1308 sign); \
1309 }
1310
1311 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1312 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1313
1314 #if defined(TARGET_PPC64)
1315 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1316 TCGv arg2, int sign)
1317 {
1318 TCGv_i64 t0 = tcg_temp_new_i64();
1319 TCGv_i64 t1 = tcg_temp_new_i64();
1320
1321 tcg_gen_mov_i64(t0, arg1);
1322 tcg_gen_mov_i64(t1, arg2);
1323 if (sign) {
1324 TCGv_i64 t2 = tcg_temp_new_i64();
1325 TCGv_i64 t3 = tcg_temp_new_i64();
1326 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1327 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1328 tcg_gen_and_i64(t2, t2, t3);
1329 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1330 tcg_gen_or_i64(t2, t2, t3);
1331 tcg_gen_movi_i64(t3, 0);
1332 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1333 tcg_gen_rem_i64(ret, t0, t1);
1334 tcg_temp_free_i64(t2);
1335 tcg_temp_free_i64(t3);
1336 } else {
1337 TCGv_i64 t2 = tcg_const_i64(1);
1338 TCGv_i64 t3 = tcg_const_i64(0);
1339 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1340 tcg_gen_remu_i64(ret, t0, t1);
1341 tcg_temp_free_i64(t2);
1342 tcg_temp_free_i64(t3);
1343 }
1344 tcg_temp_free_i64(t0);
1345 tcg_temp_free_i64(t1);
1346 }
1347
1348 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1349 static void glue(gen_, name)(DisasContext *ctx) \
1350 { \
1351 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1352 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1353 sign); \
1354 }
1355
1356 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1357 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1358 #endif
1359
1360 /* mulhw mulhw. */
1361 static void gen_mulhw(DisasContext *ctx)
1362 {
1363 TCGv_i32 t0 = tcg_temp_new_i32();
1364 TCGv_i32 t1 = tcg_temp_new_i32();
1365
1366 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1367 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1368 tcg_gen_muls2_i32(t0, t1, t0, t1);
1369 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1370 tcg_temp_free_i32(t0);
1371 tcg_temp_free_i32(t1);
1372 if (unlikely(Rc(ctx->opcode) != 0))
1373 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1374 }
1375
1376 /* mulhwu mulhwu. */
1377 static void gen_mulhwu(DisasContext *ctx)
1378 {
1379 TCGv_i32 t0 = tcg_temp_new_i32();
1380 TCGv_i32 t1 = tcg_temp_new_i32();
1381
1382 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1383 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1384 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1385 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1386 tcg_temp_free_i32(t0);
1387 tcg_temp_free_i32(t1);
1388 if (unlikely(Rc(ctx->opcode) != 0))
1389 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1390 }
1391
1392 /* mullw mullw. */
1393 static void gen_mullw(DisasContext *ctx)
1394 {
1395 #if defined(TARGET_PPC64)
1396 TCGv_i64 t0, t1;
1397 t0 = tcg_temp_new_i64();
1398 t1 = tcg_temp_new_i64();
1399 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1400 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1401 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1402 tcg_temp_free(t0);
1403 tcg_temp_free(t1);
1404 #else
1405 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1406 cpu_gpr[rB(ctx->opcode)]);
1407 #endif
1408 if (unlikely(Rc(ctx->opcode) != 0))
1409 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1410 }
1411
1412 /* mullwo mullwo. */
1413 static void gen_mullwo(DisasContext *ctx)
1414 {
1415 TCGv_i32 t0 = tcg_temp_new_i32();
1416 TCGv_i32 t1 = tcg_temp_new_i32();
1417
1418 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1419 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1420 tcg_gen_muls2_i32(t0, t1, t0, t1);
1421 #if defined(TARGET_PPC64)
1422 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1423 #else
1424 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1425 #endif
1426
1427 tcg_gen_sari_i32(t0, t0, 31);
1428 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1429 tcg_gen_extu_i32_tl(cpu_ov, t0);
1430 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1431
1432 tcg_temp_free_i32(t0);
1433 tcg_temp_free_i32(t1);
1434 if (unlikely(Rc(ctx->opcode) != 0))
1435 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1436 }
1437
1438 /* mulli */
1439 static void gen_mulli(DisasContext *ctx)
1440 {
1441 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1442 SIMM(ctx->opcode));
1443 }
1444
1445 #if defined(TARGET_PPC64)
1446 /* mulhd mulhd. */
1447 static void gen_mulhd(DisasContext *ctx)
1448 {
1449 TCGv lo = tcg_temp_new();
1450 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1451 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1452 tcg_temp_free(lo);
1453 if (unlikely(Rc(ctx->opcode) != 0)) {
1454 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1455 }
1456 }
1457
1458 /* mulhdu mulhdu. */
1459 static void gen_mulhdu(DisasContext *ctx)
1460 {
1461 TCGv lo = tcg_temp_new();
1462 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1463 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1464 tcg_temp_free(lo);
1465 if (unlikely(Rc(ctx->opcode) != 0)) {
1466 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1467 }
1468 }
1469
1470 /* mulld mulld. */
1471 static void gen_mulld(DisasContext *ctx)
1472 {
1473 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1474 cpu_gpr[rB(ctx->opcode)]);
1475 if (unlikely(Rc(ctx->opcode) != 0))
1476 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1477 }
1478
1479 /* mulldo mulldo. */
1480 static void gen_mulldo(DisasContext *ctx)
1481 {
1482 TCGv_i64 t0 = tcg_temp_new_i64();
1483 TCGv_i64 t1 = tcg_temp_new_i64();
1484
1485 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1486 cpu_gpr[rB(ctx->opcode)]);
1487 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1488
1489 tcg_gen_sari_i64(t0, t0, 63);
1490 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1491 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1492
1493 tcg_temp_free_i64(t0);
1494 tcg_temp_free_i64(t1);
1495
1496 if (unlikely(Rc(ctx->opcode) != 0)) {
1497 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1498 }
1499 }
1500 #endif
1501
1502 /* Common subf function */
1503 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1504 TCGv arg2, bool add_ca, bool compute_ca,
1505 bool compute_ov, bool compute_rc0)
1506 {
1507 TCGv t0 = ret;
1508
1509 if (compute_ca || compute_ov) {
1510 t0 = tcg_temp_new();
1511 }
1512
1513 if (compute_ca) {
1514 /* dest = ~arg1 + arg2 [+ ca]. */
1515 if (NARROW_MODE(ctx)) {
1516 /* Caution: a non-obvious corner case of the spec is that we
1517 must produce the *entire* 64-bit addition, but produce the
1518 carry into bit 32. */
1519 TCGv inv1 = tcg_temp_new();
1520 TCGv t1 = tcg_temp_new();
1521 tcg_gen_not_tl(inv1, arg1);
1522 if (add_ca) {
1523 tcg_gen_add_tl(t0, arg2, cpu_ca);
1524 } else {
1525 tcg_gen_addi_tl(t0, arg2, 1);
1526 }
1527 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1528 tcg_gen_add_tl(t0, t0, inv1);
1529 tcg_temp_free(inv1);
1530 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1531 tcg_temp_free(t1);
1532 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1533 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1534 } else if (add_ca) {
1535 TCGv zero, inv1 = tcg_temp_new();
1536 tcg_gen_not_tl(inv1, arg1);
1537 zero = tcg_const_tl(0);
1538 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1539 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1540 tcg_temp_free(zero);
1541 tcg_temp_free(inv1);
1542 } else {
1543 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1544 tcg_gen_sub_tl(t0, arg2, arg1);
1545 }
1546 } else if (add_ca) {
1547 /* Since we're ignoring carry-out, we can simplify the
1548 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1549 tcg_gen_sub_tl(t0, arg2, arg1);
1550 tcg_gen_add_tl(t0, t0, cpu_ca);
1551 tcg_gen_subi_tl(t0, t0, 1);
1552 } else {
1553 tcg_gen_sub_tl(t0, arg2, arg1);
1554 }
1555
1556 if (compute_ov) {
1557 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1558 }
1559 if (unlikely(compute_rc0)) {
1560 gen_set_Rc0(ctx, t0);
1561 }
1562
1563 if (!TCGV_EQUAL(t0, ret)) {
1564 tcg_gen_mov_tl(ret, t0);
1565 tcg_temp_free(t0);
1566 }
1567 }
1568 /* Sub functions with Two operands functions */
1569 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1570 static void glue(gen_, name)(DisasContext *ctx) \
1571 { \
1572 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1573 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1574 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1575 }
1576 /* Sub functions with one operand and one immediate */
1577 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1578 add_ca, compute_ca, compute_ov) \
1579 static void glue(gen_, name)(DisasContext *ctx) \
1580 { \
1581 TCGv t0 = tcg_const_tl(const_val); \
1582 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1583 cpu_gpr[rA(ctx->opcode)], t0, \
1584 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1585 tcg_temp_free(t0); \
1586 }
1587 /* subf subf. subfo subfo. */
1588 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1589 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1590 /* subfc subfc. subfco subfco. */
1591 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1592 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1593 /* subfe subfe. subfeo subfo. */
1594 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1595 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1596 /* subfme subfme. subfmeo subfmeo. */
1597 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1598 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1599 /* subfze subfze. subfzeo subfzeo.*/
1600 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1601 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1602
1603 /* subfic */
1604 static void gen_subfic(DisasContext *ctx)
1605 {
1606 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1607 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1608 c, 0, 1, 0, 0);
1609 tcg_temp_free(c);
1610 }
1611
1612 /* neg neg. nego nego. */
1613 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1614 {
1615 TCGv zero = tcg_const_tl(0);
1616 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1617 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1618 tcg_temp_free(zero);
1619 }
1620
1621 static void gen_neg(DisasContext *ctx)
1622 {
1623 gen_op_arith_neg(ctx, 0);
1624 }
1625
1626 static void gen_nego(DisasContext *ctx)
1627 {
1628 gen_op_arith_neg(ctx, 1);
1629 }
1630
1631 /*** Integer logical ***/
1632 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1633 static void glue(gen_, name)(DisasContext *ctx) \
1634 { \
1635 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1636 cpu_gpr[rB(ctx->opcode)]); \
1637 if (unlikely(Rc(ctx->opcode) != 0)) \
1638 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1639 }
1640
1641 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1642 static void glue(gen_, name)(DisasContext *ctx) \
1643 { \
1644 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1645 if (unlikely(Rc(ctx->opcode) != 0)) \
1646 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1647 }
1648
1649 /* and & and. */
1650 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1651 /* andc & andc. */
1652 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1653
1654 /* andi. */
1655 static void gen_andi_(DisasContext *ctx)
1656 {
1657 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1659 }
1660
1661 /* andis. */
1662 static void gen_andis_(DisasContext *ctx)
1663 {
1664 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1665 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1666 }
1667
1668 /* cntlzw */
1669 static void gen_cntlzw(DisasContext *ctx)
1670 {
1671 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1672 if (unlikely(Rc(ctx->opcode) != 0))
1673 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1674 }
1675
1676 /* cnttzw */
1677 static void gen_cnttzw(DisasContext *ctx)
1678 {
1679 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1680 if (unlikely(Rc(ctx->opcode) != 0)) {
1681 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1682 }
1683 }
1684
1685 /* eqv & eqv. */
1686 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1687 /* extsb & extsb. */
1688 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1689 /* extsh & extsh. */
1690 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1691 /* nand & nand. */
1692 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1693 /* nor & nor. */
1694 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1695
1696 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1697 static void gen_pause(DisasContext *ctx)
1698 {
1699 TCGv_i32 t0 = tcg_const_i32(0);
1700 tcg_gen_st_i32(t0, cpu_env,
1701 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1702 tcg_temp_free_i32(t0);
1703
1704 /* Stop translation, this gives other CPUs a chance to run */
1705 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1706 }
1707 #endif /* defined(TARGET_PPC64) */
1708
1709 /* or & or. */
1710 static void gen_or(DisasContext *ctx)
1711 {
1712 int rs, ra, rb;
1713
1714 rs = rS(ctx->opcode);
1715 ra = rA(ctx->opcode);
1716 rb = rB(ctx->opcode);
1717 /* Optimisation for mr. ri case */
1718 if (rs != ra || rs != rb) {
1719 if (rs != rb)
1720 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1721 else
1722 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1723 if (unlikely(Rc(ctx->opcode) != 0))
1724 gen_set_Rc0(ctx, cpu_gpr[ra]);
1725 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1726 gen_set_Rc0(ctx, cpu_gpr[rs]);
1727 #if defined(TARGET_PPC64)
1728 } else if (rs != 0) { /* 0 is nop */
1729 int prio = 0;
1730
1731 switch (rs) {
1732 case 1:
1733 /* Set process priority to low */
1734 prio = 2;
1735 break;
1736 case 6:
1737 /* Set process priority to medium-low */
1738 prio = 3;
1739 break;
1740 case 2:
1741 /* Set process priority to normal */
1742 prio = 4;
1743 break;
1744 #if !defined(CONFIG_USER_ONLY)
1745 case 31:
1746 if (!ctx->pr) {
1747 /* Set process priority to very low */
1748 prio = 1;
1749 }
1750 break;
1751 case 5:
1752 if (!ctx->pr) {
1753 /* Set process priority to medium-hight */
1754 prio = 5;
1755 }
1756 break;
1757 case 3:
1758 if (!ctx->pr) {
1759 /* Set process priority to high */
1760 prio = 6;
1761 }
1762 break;
1763 case 7:
1764 if (ctx->hv && !ctx->pr) {
1765 /* Set process priority to very high */
1766 prio = 7;
1767 }
1768 break;
1769 #endif
1770 default:
1771 break;
1772 }
1773 if (prio) {
1774 TCGv t0 = tcg_temp_new();
1775 gen_load_spr(t0, SPR_PPR);
1776 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1777 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1778 gen_store_spr(SPR_PPR, t0);
1779 tcg_temp_free(t0);
1780 }
1781 #if !defined(CONFIG_USER_ONLY)
1782 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1783 * CPU and the kernel hangs. This applies to all encodings other
1784 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1785 * and all currently undefined.
1786 */
1787 gen_pause(ctx);
1788 #endif
1789 #endif
1790 }
1791 }
1792 /* orc & orc. */
1793 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1794
1795 /* xor & xor. */
1796 static void gen_xor(DisasContext *ctx)
1797 {
1798 /* Optimisation for "set to zero" case */
1799 if (rS(ctx->opcode) != rB(ctx->opcode))
1800 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1801 else
1802 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1803 if (unlikely(Rc(ctx->opcode) != 0))
1804 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1805 }
1806
1807 /* ori */
1808 static void gen_ori(DisasContext *ctx)
1809 {
1810 target_ulong uimm = UIMM(ctx->opcode);
1811
1812 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1813 return;
1814 }
1815 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1816 }
1817
1818 /* oris */
1819 static void gen_oris(DisasContext *ctx)
1820 {
1821 target_ulong uimm = UIMM(ctx->opcode);
1822
1823 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1824 /* NOP */
1825 return;
1826 }
1827 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1828 }
1829
1830 /* xori */
1831 static void gen_xori(DisasContext *ctx)
1832 {
1833 target_ulong uimm = UIMM(ctx->opcode);
1834
1835 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1836 /* NOP */
1837 return;
1838 }
1839 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1840 }
1841
1842 /* xoris */
1843 static void gen_xoris(DisasContext *ctx)
1844 {
1845 target_ulong uimm = UIMM(ctx->opcode);
1846
1847 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1848 /* NOP */
1849 return;
1850 }
1851 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1852 }
1853
1854 /* popcntb : PowerPC 2.03 specification */
1855 static void gen_popcntb(DisasContext *ctx)
1856 {
1857 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1858 }
1859
1860 static void gen_popcntw(DisasContext *ctx)
1861 {
1862 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1863 }
1864
1865 #if defined(TARGET_PPC64)
1866 /* popcntd: PowerPC 2.06 specification */
1867 static void gen_popcntd(DisasContext *ctx)
1868 {
1869 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1870 }
1871 #endif
1872
1873 /* prtyw: PowerPC 2.05 specification */
1874 static void gen_prtyw(DisasContext *ctx)
1875 {
1876 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1877 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1878 TCGv t0 = tcg_temp_new();
1879 tcg_gen_shri_tl(t0, rs, 16);
1880 tcg_gen_xor_tl(ra, rs, t0);
1881 tcg_gen_shri_tl(t0, ra, 8);
1882 tcg_gen_xor_tl(ra, ra, t0);
1883 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1884 tcg_temp_free(t0);
1885 }
1886
1887 #if defined(TARGET_PPC64)
1888 /* prtyd: PowerPC 2.05 specification */
1889 static void gen_prtyd(DisasContext *ctx)
1890 {
1891 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1892 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1893 TCGv t0 = tcg_temp_new();
1894 tcg_gen_shri_tl(t0, rs, 32);
1895 tcg_gen_xor_tl(ra, rs, t0);
1896 tcg_gen_shri_tl(t0, ra, 16);
1897 tcg_gen_xor_tl(ra, ra, t0);
1898 tcg_gen_shri_tl(t0, ra, 8);
1899 tcg_gen_xor_tl(ra, ra, t0);
1900 tcg_gen_andi_tl(ra, ra, 1);
1901 tcg_temp_free(t0);
1902 }
1903 #endif
1904
1905 #if defined(TARGET_PPC64)
1906 /* bpermd */
1907 static void gen_bpermd(DisasContext *ctx)
1908 {
1909 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1910 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1911 }
1912 #endif
1913
1914 #if defined(TARGET_PPC64)
1915 /* extsw & extsw. */
1916 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1917
1918 /* cntlzd */
1919 static void gen_cntlzd(DisasContext *ctx)
1920 {
1921 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1922 if (unlikely(Rc(ctx->opcode) != 0))
1923 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1924 }
1925
1926 /* cnttzd */
1927 static void gen_cnttzd(DisasContext *ctx)
1928 {
1929 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1930 if (unlikely(Rc(ctx->opcode) != 0)) {
1931 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1932 }
1933 }
1934
1935 /* darn */
1936 static void gen_darn(DisasContext *ctx)
1937 {
1938 int l = L(ctx->opcode);
1939
1940 if (l == 0) {
1941 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1942 } else if (l <= 2) {
1943 /* Return 64-bit random for both CRN and RRN */
1944 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1945 } else {
1946 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1947 }
1948 }
1949 #endif
1950
1951 /*** Integer rotate ***/
1952
1953 /* rlwimi & rlwimi. */
1954 static void gen_rlwimi(DisasContext *ctx)
1955 {
1956 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1957 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1958 uint32_t sh = SH(ctx->opcode);
1959 uint32_t mb = MB(ctx->opcode);
1960 uint32_t me = ME(ctx->opcode);
1961
1962 if (sh == (31-me) && mb <= me) {
1963 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1964 } else {
1965 target_ulong mask;
1966 TCGv t1;
1967
1968 #if defined(TARGET_PPC64)
1969 mb += 32;
1970 me += 32;
1971 #endif
1972 mask = MASK(mb, me);
1973
1974 t1 = tcg_temp_new();
1975 if (mask <= 0xffffffffu) {
1976 TCGv_i32 t0 = tcg_temp_new_i32();
1977 tcg_gen_trunc_tl_i32(t0, t_rs);
1978 tcg_gen_rotli_i32(t0, t0, sh);
1979 tcg_gen_extu_i32_tl(t1, t0);
1980 tcg_temp_free_i32(t0);
1981 } else {
1982 #if defined(TARGET_PPC64)
1983 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1984 tcg_gen_rotli_i64(t1, t1, sh);
1985 #else
1986 g_assert_not_reached();
1987 #endif
1988 }
1989
1990 tcg_gen_andi_tl(t1, t1, mask);
1991 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1992 tcg_gen_or_tl(t_ra, t_ra, t1);
1993 tcg_temp_free(t1);
1994 }
1995 if (unlikely(Rc(ctx->opcode) != 0)) {
1996 gen_set_Rc0(ctx, t_ra);
1997 }
1998 }
1999
2000 /* rlwinm & rlwinm. */
2001 static void gen_rlwinm(DisasContext *ctx)
2002 {
2003 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2004 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2005 uint32_t sh = SH(ctx->opcode);
2006 uint32_t mb = MB(ctx->opcode);
2007 uint32_t me = ME(ctx->opcode);
2008
2009 if (mb == 0 && me == (31 - sh)) {
2010 tcg_gen_shli_tl(t_ra, t_rs, sh);
2011 tcg_gen_ext32u_tl(t_ra, t_ra);
2012 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
2013 tcg_gen_ext32u_tl(t_ra, t_rs);
2014 tcg_gen_shri_tl(t_ra, t_ra, mb);
2015 } else {
2016 target_ulong mask;
2017 #if defined(TARGET_PPC64)
2018 mb += 32;
2019 me += 32;
2020 #endif
2021 mask = MASK(mb, me);
2022
2023 if (mask <= 0xffffffffu) {
2024 TCGv_i32 t0 = tcg_temp_new_i32();
2025 tcg_gen_trunc_tl_i32(t0, t_rs);
2026 tcg_gen_rotli_i32(t0, t0, sh);
2027 tcg_gen_andi_i32(t0, t0, mask);
2028 tcg_gen_extu_i32_tl(t_ra, t0);
2029 tcg_temp_free_i32(t0);
2030 } else {
2031 #if defined(TARGET_PPC64)
2032 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2033 tcg_gen_rotli_i64(t_ra, t_ra, sh);
2034 tcg_gen_andi_i64(t_ra, t_ra, mask);
2035 #else
2036 g_assert_not_reached();
2037 #endif
2038 }
2039 }
2040 if (unlikely(Rc(ctx->opcode) != 0)) {
2041 gen_set_Rc0(ctx, t_ra);
2042 }
2043 }
2044
2045 /* rlwnm & rlwnm. */
2046 static void gen_rlwnm(DisasContext *ctx)
2047 {
2048 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2049 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2050 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2051 uint32_t mb = MB(ctx->opcode);
2052 uint32_t me = ME(ctx->opcode);
2053 target_ulong mask;
2054
2055 #if defined(TARGET_PPC64)
2056 mb += 32;
2057 me += 32;
2058 #endif
2059 mask = MASK(mb, me);
2060
2061 if (mask <= 0xffffffffu) {
2062 TCGv_i32 t0 = tcg_temp_new_i32();
2063 TCGv_i32 t1 = tcg_temp_new_i32();
2064 tcg_gen_trunc_tl_i32(t0, t_rb);
2065 tcg_gen_trunc_tl_i32(t1, t_rs);
2066 tcg_gen_andi_i32(t0, t0, 0x1f);
2067 tcg_gen_rotl_i32(t1, t1, t0);
2068 tcg_gen_extu_i32_tl(t_ra, t1);
2069 tcg_temp_free_i32(t0);
2070 tcg_temp_free_i32(t1);
2071 } else {
2072 #if defined(TARGET_PPC64)
2073 TCGv_i64 t0 = tcg_temp_new_i64();
2074 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2075 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2076 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2077 tcg_temp_free_i64(t0);
2078 #else
2079 g_assert_not_reached();
2080 #endif
2081 }
2082
2083 tcg_gen_andi_tl(t_ra, t_ra, mask);
2084
2085 if (unlikely(Rc(ctx->opcode) != 0)) {
2086 gen_set_Rc0(ctx, t_ra);
2087 }
2088 }
2089
2090 #if defined(TARGET_PPC64)
2091 #define GEN_PPC64_R2(name, opc1, opc2) \
2092 static void glue(gen_, name##0)(DisasContext *ctx) \
2093 { \
2094 gen_##name(ctx, 0); \
2095 } \
2096 \
2097 static void glue(gen_, name##1)(DisasContext *ctx) \
2098 { \
2099 gen_##name(ctx, 1); \
2100 }
2101 #define GEN_PPC64_R4(name, opc1, opc2) \
2102 static void glue(gen_, name##0)(DisasContext *ctx) \
2103 { \
2104 gen_##name(ctx, 0, 0); \
2105 } \
2106 \
2107 static void glue(gen_, name##1)(DisasContext *ctx) \
2108 { \
2109 gen_##name(ctx, 0, 1); \
2110 } \
2111 \
2112 static void glue(gen_, name##2)(DisasContext *ctx) \
2113 { \
2114 gen_##name(ctx, 1, 0); \
2115 } \
2116 \
2117 static void glue(gen_, name##3)(DisasContext *ctx) \
2118 { \
2119 gen_##name(ctx, 1, 1); \
2120 }
2121
2122 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2123 {
2124 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2125 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2126
2127 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2128 tcg_gen_shli_tl(t_ra, t_rs, sh);
2129 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2130 tcg_gen_shri_tl(t_ra, t_rs, mb);
2131 } else {
2132 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2133 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2134 }
2135 if (unlikely(Rc(ctx->opcode) != 0)) {
2136 gen_set_Rc0(ctx, t_ra);
2137 }
2138 }
2139
2140 /* rldicl - rldicl. */
2141 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2142 {
2143 uint32_t sh, mb;
2144
2145 sh = SH(ctx->opcode) | (shn << 5);
2146 mb = MB(ctx->opcode) | (mbn << 5);
2147 gen_rldinm(ctx, mb, 63, sh);
2148 }
2149 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2150
2151 /* rldicr - rldicr. */
2152 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2153 {
2154 uint32_t sh, me;
2155
2156 sh = SH(ctx->opcode) | (shn << 5);
2157 me = MB(ctx->opcode) | (men << 5);
2158 gen_rldinm(ctx, 0, me, sh);
2159 }
2160 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2161
2162 /* rldic - rldic. */
2163 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2164 {
2165 uint32_t sh, mb;
2166
2167 sh = SH(ctx->opcode) | (shn << 5);
2168 mb = MB(ctx->opcode) | (mbn << 5);
2169 gen_rldinm(ctx, mb, 63 - sh, sh);
2170 }
2171 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2172
2173 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2174 {
2175 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2176 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2177 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2178 TCGv t0;
2179
2180 t0 = tcg_temp_new();
2181 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2182 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2183 tcg_temp_free(t0);
2184
2185 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2186 if (unlikely(Rc(ctx->opcode) != 0)) {
2187 gen_set_Rc0(ctx, t_ra);
2188 }
2189 }
2190
2191 /* rldcl - rldcl. */
2192 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2193 {
2194 uint32_t mb;
2195
2196 mb = MB(ctx->opcode) | (mbn << 5);
2197 gen_rldnm(ctx, mb, 63);
2198 }
2199 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2200
2201 /* rldcr - rldcr. */
2202 static inline void gen_rldcr(DisasContext *ctx, int men)
2203 {
2204 uint32_t me;
2205
2206 me = MB(ctx->opcode) | (men << 5);
2207 gen_rldnm(ctx, 0, me);
2208 }
2209 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2210
2211 /* rldimi - rldimi. */
2212 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2213 {
2214 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2215 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2216 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2217 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2218 uint32_t me = 63 - sh;
2219
2220 if (mb <= me) {
2221 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2222 } else {
2223 target_ulong mask = MASK(mb, me);
2224 TCGv t1 = tcg_temp_new();
2225
2226 tcg_gen_rotli_tl(t1, t_rs, sh);
2227 tcg_gen_andi_tl(t1, t1, mask);
2228 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2229 tcg_gen_or_tl(t_ra, t_ra, t1);
2230 tcg_temp_free(t1);
2231 }
2232 if (unlikely(Rc(ctx->opcode) != 0)) {
2233 gen_set_Rc0(ctx, t_ra);
2234 }
2235 }
2236 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2237 #endif
2238
2239 /*** Integer shift ***/
2240
2241 /* slw & slw. */
2242 static void gen_slw(DisasContext *ctx)
2243 {
2244 TCGv t0, t1;
2245
2246 t0 = tcg_temp_new();
2247 /* AND rS with a mask that is 0 when rB >= 0x20 */
2248 #if defined(TARGET_PPC64)
2249 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2250 tcg_gen_sari_tl(t0, t0, 0x3f);
2251 #else
2252 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2253 tcg_gen_sari_tl(t0, t0, 0x1f);
2254 #endif
2255 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2256 t1 = tcg_temp_new();
2257 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2258 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2259 tcg_temp_free(t1);
2260 tcg_temp_free(t0);
2261 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2262 if (unlikely(Rc(ctx->opcode) != 0))
2263 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2264 }
2265
2266 /* sraw & sraw. */
2267 static void gen_sraw(DisasContext *ctx)
2268 {
2269 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2270 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2271 if (unlikely(Rc(ctx->opcode) != 0))
2272 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2273 }
2274
2275 /* srawi & srawi. */
2276 static void gen_srawi(DisasContext *ctx)
2277 {
2278 int sh = SH(ctx->opcode);
2279 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2280 TCGv src = cpu_gpr[rS(ctx->opcode)];
2281 if (sh == 0) {
2282 tcg_gen_ext32s_tl(dst, src);
2283 tcg_gen_movi_tl(cpu_ca, 0);
2284 } else {
2285 TCGv t0;
2286 tcg_gen_ext32s_tl(dst, src);
2287 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2288 t0 = tcg_temp_new();
2289 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2290 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2291 tcg_temp_free(t0);
2292 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2293 tcg_gen_sari_tl(dst, dst, sh);
2294 }
2295 if (unlikely(Rc(ctx->opcode) != 0)) {
2296 gen_set_Rc0(ctx, dst);
2297 }
2298 }
2299
2300 /* srw & srw. */
2301 static void gen_srw(DisasContext *ctx)
2302 {
2303 TCGv t0, t1;
2304
2305 t0 = tcg_temp_new();
2306 /* AND rS with a mask that is 0 when rB >= 0x20 */
2307 #if defined(TARGET_PPC64)
2308 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2309 tcg_gen_sari_tl(t0, t0, 0x3f);
2310 #else
2311 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2312 tcg_gen_sari_tl(t0, t0, 0x1f);
2313 #endif
2314 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2315 tcg_gen_ext32u_tl(t0, t0);
2316 t1 = tcg_temp_new();
2317 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2318 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2319 tcg_temp_free(t1);
2320 tcg_temp_free(t0);
2321 if (unlikely(Rc(ctx->opcode) != 0))
2322 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2323 }
2324
2325 #if defined(TARGET_PPC64)
2326 /* sld & sld. */
2327 static void gen_sld(DisasContext *ctx)
2328 {
2329 TCGv t0, t1;
2330
2331 t0 = tcg_temp_new();
2332 /* AND rS with a mask that is 0 when rB >= 0x40 */
2333 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2334 tcg_gen_sari_tl(t0, t0, 0x3f);
2335 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2336 t1 = tcg_temp_new();
2337 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2338 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2339 tcg_temp_free(t1);
2340 tcg_temp_free(t0);
2341 if (unlikely(Rc(ctx->opcode) != 0))
2342 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2343 }
2344
2345 /* srad & srad. */
2346 static void gen_srad(DisasContext *ctx)
2347 {
2348 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2349 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2350 if (unlikely(Rc(ctx->opcode) != 0))
2351 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2352 }
2353 /* sradi & sradi. */
2354 static inline void gen_sradi(DisasContext *ctx, int n)
2355 {
2356 int sh = SH(ctx->opcode) + (n << 5);
2357 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2358 TCGv src = cpu_gpr[rS(ctx->opcode)];
2359 if (sh == 0) {
2360 tcg_gen_mov_tl(dst, src);
2361 tcg_gen_movi_tl(cpu_ca, 0);
2362 } else {
2363 TCGv t0;
2364 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2365 t0 = tcg_temp_new();
2366 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2367 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2368 tcg_temp_free(t0);
2369 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2370 tcg_gen_sari_tl(dst, src, sh);
2371 }
2372 if (unlikely(Rc(ctx->opcode) != 0)) {
2373 gen_set_Rc0(ctx, dst);
2374 }
2375 }
2376
2377 static void gen_sradi0(DisasContext *ctx)
2378 {
2379 gen_sradi(ctx, 0);
2380 }
2381
2382 static void gen_sradi1(DisasContext *ctx)
2383 {
2384 gen_sradi(ctx, 1);
2385 }
2386
2387 /* extswsli & extswsli. */
2388 static inline void gen_extswsli(DisasContext *ctx, int n)
2389 {
2390 int sh = SH(ctx->opcode) + (n << 5);
2391 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2392 TCGv src = cpu_gpr[rS(ctx->opcode)];
2393
2394 tcg_gen_ext32s_tl(dst, src);
2395 tcg_gen_shli_tl(dst, dst, sh);
2396 if (unlikely(Rc(ctx->opcode) != 0)) {
2397 gen_set_Rc0(ctx, dst);
2398 }
2399 }
2400
2401 static void gen_extswsli0(DisasContext *ctx)
2402 {
2403 gen_extswsli(ctx, 0);
2404 }
2405
2406 static void gen_extswsli1(DisasContext *ctx)
2407 {
2408 gen_extswsli(ctx, 1);
2409 }
2410
2411 /* srd & srd. */
2412 static void gen_srd(DisasContext *ctx)
2413 {
2414 TCGv t0, t1;
2415
2416 t0 = tcg_temp_new();
2417 /* AND rS with a mask that is 0 when rB >= 0x40 */
2418 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2419 tcg_gen_sari_tl(t0, t0, 0x3f);
2420 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2421 t1 = tcg_temp_new();
2422 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2423 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2424 tcg_temp_free(t1);
2425 tcg_temp_free(t0);
2426 if (unlikely(Rc(ctx->opcode) != 0))
2427 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2428 }
2429 #endif
2430
2431 /*** Addressing modes ***/
2432 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2433 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2434 target_long maskl)
2435 {
2436 target_long simm = SIMM(ctx->opcode);
2437
2438 simm &= ~maskl;
2439 if (rA(ctx->opcode) == 0) {
2440 if (NARROW_MODE(ctx)) {
2441 simm = (uint32_t)simm;
2442 }
2443 tcg_gen_movi_tl(EA, simm);
2444 } else if (likely(simm != 0)) {
2445 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2446 if (NARROW_MODE(ctx)) {
2447 tcg_gen_ext32u_tl(EA, EA);
2448 }
2449 } else {
2450 if (NARROW_MODE(ctx)) {
2451 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2452 } else {
2453 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2454 }
2455 }
2456 }
2457
2458 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2459 {
2460 if (rA(ctx->opcode) == 0) {
2461 if (NARROW_MODE(ctx)) {
2462 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2463 } else {
2464 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2465 }
2466 } else {
2467 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2468 if (NARROW_MODE(ctx)) {
2469 tcg_gen_ext32u_tl(EA, EA);
2470 }
2471 }
2472 }
2473
2474 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2475 {
2476 if (rA(ctx->opcode) == 0) {
2477 tcg_gen_movi_tl(EA, 0);
2478 } else if (NARROW_MODE(ctx)) {
2479 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2480 } else {
2481 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2482 }
2483 }
2484
2485 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2486 target_long val)
2487 {
2488 tcg_gen_addi_tl(ret, arg1, val);
2489 if (NARROW_MODE(ctx)) {
2490 tcg_gen_ext32u_tl(ret, ret);
2491 }
2492 }
2493
2494 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2495 {
2496 TCGLabel *l1 = gen_new_label();
2497 TCGv t0 = tcg_temp_new();
2498 TCGv_i32 t1, t2;
2499 tcg_gen_andi_tl(t0, EA, mask);
2500 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2501 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2502 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2503 gen_update_nip(ctx, ctx->nip - 4);
2504 gen_helper_raise_exception_err(cpu_env, t1, t2);
2505 tcg_temp_free_i32(t1);
2506 tcg_temp_free_i32(t2);
2507 gen_set_label(l1);
2508 tcg_temp_free(t0);
2509 }
2510
2511 static inline void gen_align_no_le(DisasContext *ctx)
2512 {
2513 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2514 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2515 }
2516
2517 /*** Integer load ***/
2518 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2519 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2520
2521 #define GEN_QEMU_LOAD_TL(ldop, op) \
2522 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2523 TCGv val, \
2524 TCGv addr) \
2525 { \
2526 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2527 }
2528
2529 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2530 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2531 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2532 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2533 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2534
2535 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2536 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2537
2538 #define GEN_QEMU_LOAD_64(ldop, op) \
2539 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2540 TCGv_i64 val, \
2541 TCGv addr) \
2542 { \
2543 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2544 }
2545
2546 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2547 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2548 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2549 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2550 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2551
2552 #if defined(TARGET_PPC64)
2553 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2554 #endif
2555
2556 #define GEN_QEMU_STORE_TL(stop, op) \
2557 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2558 TCGv val, \
2559 TCGv addr) \
2560 { \
2561 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2562 }
2563
2564 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2565 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2566 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2567
2568 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2569 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2570
2571 #define GEN_QEMU_STORE_64(stop, op) \
2572 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2573 TCGv_i64 val, \
2574 TCGv addr) \
2575 { \
2576 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2577 }
2578
2579 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2580 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2581 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2582 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2583
2584 #if defined(TARGET_PPC64)
2585 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2586 #endif
2587
2588 #define GEN_LD(name, ldop, opc, type) \
2589 static void glue(gen_, name)(DisasContext *ctx) \
2590 { \
2591 TCGv EA; \
2592 gen_set_access_type(ctx, ACCESS_INT); \
2593 EA = tcg_temp_new(); \
2594 gen_addr_imm_index(ctx, EA, 0); \
2595 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2596 tcg_temp_free(EA); \
2597 }
2598
2599 #define GEN_LDU(name, ldop, opc, type) \
2600 static void glue(gen_, name##u)(DisasContext *ctx) \
2601 { \
2602 TCGv EA; \
2603 if (unlikely(rA(ctx->opcode) == 0 || \
2604 rA(ctx->opcode) == rD(ctx->opcode))) { \
2605 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2606 return; \
2607 } \
2608 gen_set_access_type(ctx, ACCESS_INT); \
2609 EA = tcg_temp_new(); \
2610 if (type == PPC_64B) \
2611 gen_addr_imm_index(ctx, EA, 0x03); \
2612 else \
2613 gen_addr_imm_index(ctx, EA, 0); \
2614 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2615 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2616 tcg_temp_free(EA); \
2617 }
2618
2619 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2620 static void glue(gen_, name##ux)(DisasContext *ctx) \
2621 { \
2622 TCGv EA; \
2623 if (unlikely(rA(ctx->opcode) == 0 || \
2624 rA(ctx->opcode) == rD(ctx->opcode))) { \
2625 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2626 return; \
2627 } \
2628 gen_set_access_type(ctx, ACCESS_INT); \
2629 EA = tcg_temp_new(); \
2630 gen_addr_reg_index(ctx, EA); \
2631 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2632 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2633 tcg_temp_free(EA); \
2634 }
2635
2636 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2637 static void glue(gen_, name##x)(DisasContext *ctx) \
2638 { \
2639 TCGv EA; \
2640 chk; \
2641 gen_set_access_type(ctx, ACCESS_INT); \
2642 EA = tcg_temp_new(); \
2643 gen_addr_reg_index(ctx, EA); \
2644 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2645 tcg_temp_free(EA); \
2646 }
2647
2648 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2649 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2650
2651 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2652 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2653
2654 #define GEN_LDS(name, ldop, op, type) \
2655 GEN_LD(name, ldop, op | 0x20, type); \
2656 GEN_LDU(name, ldop, op | 0x21, type); \
2657 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2658 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2659
2660 /* lbz lbzu lbzux lbzx */
2661 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2662 /* lha lhau lhaux lhax */
2663 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2664 /* lhz lhzu lhzux lhzx */
2665 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2666 /* lwz lwzu lwzux lwzx */
2667 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2668 #if defined(TARGET_PPC64)
2669 /* lwaux */
2670 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2671 /* lwax */
2672 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2673 /* ldux */
2674 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2675 /* ldx */
2676 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2677
2678 /* CI load/store variants */
2679 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2680 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2681 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2682 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2683
2684 static void gen_ld(DisasContext *ctx)
2685 {
2686 TCGv EA;
2687 if (Rc(ctx->opcode)) {
2688 if (unlikely(rA(ctx->opcode) == 0 ||
2689 rA(ctx->opcode) == rD(ctx->opcode))) {
2690 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2691 return;
2692 }
2693 }
2694 gen_set_access_type(ctx, ACCESS_INT);
2695 EA = tcg_temp_new();
2696 gen_addr_imm_index(ctx, EA, 0x03);
2697 if (ctx->opcode & 0x02) {
2698 /* lwa (lwau is undefined) */
2699 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2700 } else {
2701 /* ld - ldu */
2702 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2703 }
2704 if (Rc(ctx->opcode))
2705 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2706 tcg_temp_free(EA);
2707 }
2708
2709 /* lq */
2710 static void gen_lq(DisasContext *ctx)
2711 {
2712 int ra, rd;
2713 TCGv EA;
2714
2715 /* lq is a legal user mode instruction starting in ISA 2.07 */
2716 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2717 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2718
2719 if (!legal_in_user_mode && ctx->pr) {
2720 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2721 return;
2722 }
2723
2724 if (!le_is_supported && ctx->le_mode) {
2725 gen_align_no_le(ctx);
2726 return;
2727 }
2728 ra = rA(ctx->opcode);
2729 rd = rD(ctx->opcode);
2730 if (unlikely((rd & 1) || rd == ra)) {
2731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2732 return;
2733 }
2734
2735 gen_set_access_type(ctx, ACCESS_INT);
2736 EA = tcg_temp_new();
2737 gen_addr_imm_index(ctx, EA, 0x0F);
2738
2739 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2740 necessary 64-bit byteswap already. */
2741 if (unlikely(ctx->le_mode)) {
2742 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2743 gen_addr_add(ctx, EA, EA, 8);
2744 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2745 } else {
2746 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2747 gen_addr_add(ctx, EA, EA, 8);
2748 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2749 }
2750 tcg_temp_free(EA);
2751 }
2752 #endif
2753
2754 /*** Integer store ***/
2755 #define GEN_ST(name, stop, opc, type) \
2756 static void glue(gen_, name)(DisasContext *ctx) \
2757 { \
2758 TCGv EA; \
2759 gen_set_access_type(ctx, ACCESS_INT); \
2760 EA = tcg_temp_new(); \
2761 gen_addr_imm_index(ctx, EA, 0); \
2762 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2763 tcg_temp_free(EA); \
2764 }
2765
2766 #define GEN_STU(name, stop, opc, type) \
2767 static void glue(gen_, stop##u)(DisasContext *ctx) \
2768 { \
2769 TCGv EA; \
2770 if (unlikely(rA(ctx->opcode) == 0)) { \
2771 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2772 return; \
2773 } \
2774 gen_set_access_type(ctx, ACCESS_INT); \
2775 EA = tcg_temp_new(); \
2776 if (type == PPC_64B) \
2777 gen_addr_imm_index(ctx, EA, 0x03); \
2778 else \
2779 gen_addr_imm_index(ctx, EA, 0); \
2780 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2781 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2782 tcg_temp_free(EA); \
2783 }
2784
2785 #define GEN_STUX(name, stop, opc2, opc3, type) \
2786 static void glue(gen_, name##ux)(DisasContext *ctx) \
2787 { \
2788 TCGv EA; \
2789 if (unlikely(rA(ctx->opcode) == 0)) { \
2790 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2791 return; \
2792 } \
2793 gen_set_access_type(ctx, ACCESS_INT); \
2794 EA = tcg_temp_new(); \
2795 gen_addr_reg_index(ctx, EA); \
2796 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2797 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2798 tcg_temp_free(EA); \
2799 }
2800
2801 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2802 static void glue(gen_, name##x)(DisasContext *ctx) \
2803 { \
2804 TCGv EA; \
2805 chk; \
2806 gen_set_access_type(ctx, ACCESS_INT); \
2807 EA = tcg_temp_new(); \
2808 gen_addr_reg_index(ctx, EA); \
2809 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2810 tcg_temp_free(EA); \
2811 }
2812 #define GEN_STX(name, stop, opc2, opc3, type) \
2813 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2814
2815 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2816 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2817
2818 #define GEN_STS(name, stop, op, type) \
2819 GEN_ST(name, stop, op | 0x20, type); \
2820 GEN_STU(name, stop, op | 0x21, type); \
2821 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2822 GEN_STX(name, stop, 0x17, op | 0x00, type)
2823
2824 /* stb stbu stbux stbx */
2825 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2826 /* sth sthu sthux sthx */
2827 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2828 /* stw stwu stwux stwx */
2829 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2830 #if defined(TARGET_PPC64)
2831 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2832 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2833 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2834 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2835 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2836 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2837
2838 static void gen_std(DisasContext *ctx)
2839 {
2840 int rs;
2841 TCGv EA;
2842
2843 rs = rS(ctx->opcode);
2844 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2845 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2846 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2847
2848 if (!(ctx->insns_flags & PPC_64BX)) {
2849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2850 }
2851
2852 if (!legal_in_user_mode && ctx->pr) {
2853 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2854 return;
2855 }
2856
2857 if (!le_is_supported && ctx->le_mode) {
2858 gen_align_no_le(ctx);
2859 return;
2860 }
2861
2862 if (unlikely(rs & 1)) {
2863 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2864 return;
2865 }
2866 gen_set_access_type(ctx, ACCESS_INT);
2867 EA = tcg_temp_new();
2868 gen_addr_imm_index(ctx, EA, 0x03);
2869
2870 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2871 necessary 64-bit byteswap already. */
2872 if (unlikely(ctx->le_mode)) {
2873 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2874 gen_addr_add(ctx, EA, EA, 8);
2875 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2876 } else {
2877 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2878 gen_addr_add(ctx, EA, EA, 8);
2879 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2880 }
2881 tcg_temp_free(EA);
2882 } else {
2883 /* std / stdu*/
2884 if (Rc(ctx->opcode)) {
2885 if (unlikely(rA(ctx->opcode) == 0)) {
2886 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2887 return;
2888 }
2889 }
2890 gen_set_access_type(ctx, ACCESS_INT);
2891 EA = tcg_temp_new();
2892 gen_addr_imm_index(ctx, EA, 0x03);
2893 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2894 if (Rc(ctx->opcode))
2895 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2896 tcg_temp_free(EA);
2897 }
2898 }
2899 #endif
2900 /*** Integer load and store with byte reverse ***/
2901
2902 /* lhbrx */
2903 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2904
2905 /* lwbrx */
2906 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2907
2908 #if defined(TARGET_PPC64)
2909 /* ldbrx */
2910 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2911 /* stdbrx */
2912 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2913 #endif /* TARGET_PPC64 */
2914
2915 /* sthbrx */
2916 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2917 /* stwbrx */
2918 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2919
2920 /*** Integer load and store multiple ***/
2921
2922 /* lmw */
2923 static void gen_lmw(DisasContext *ctx)
2924 {
2925 TCGv t0;
2926 TCGv_i32 t1;
2927
2928 if (ctx->le_mode) {
2929 gen_align_no_le(ctx);
2930 return;
2931 }
2932 gen_set_access_type(ctx, ACCESS_INT);
2933 t0 = tcg_temp_new();
2934 t1 = tcg_const_i32(rD(ctx->opcode));
2935 gen_addr_imm_index(ctx, t0, 0);
2936 gen_helper_lmw(cpu_env, t0, t1);
2937 tcg_temp_free(t0);
2938 tcg_temp_free_i32(t1);
2939 }
2940
2941 /* stmw */
2942 static void gen_stmw(DisasContext *ctx)
2943 {
2944 TCGv t0;
2945 TCGv_i32 t1;
2946
2947 if (ctx->le_mode) {
2948 gen_align_no_le(ctx);
2949 return;
2950 }
2951 gen_set_access_type(ctx, ACCESS_INT);
2952 t0 = tcg_temp_new();
2953 t1 = tcg_const_i32(rS(ctx->opcode));
2954 gen_addr_imm_index(ctx, t0, 0);
2955 gen_helper_stmw(cpu_env, t0, t1);
2956 tcg_temp_free(t0);
2957 tcg_temp_free_i32(t1);
2958 }
2959
2960 /*** Integer load and store strings ***/
2961
2962 /* lswi */
2963 /* PowerPC32 specification says we must generate an exception if
2964 * rA is in the range of registers to be loaded.
2965 * In an other hand, IBM says this is valid, but rA won't be loaded.
2966 * For now, I'll follow the spec...
2967 */
2968 static void gen_lswi(DisasContext *ctx)
2969 {
2970 TCGv t0;
2971 TCGv_i32 t1, t2;
2972 int nb = NB(ctx->opcode);
2973 int start = rD(ctx->opcode);
2974 int ra = rA(ctx->opcode);
2975 int nr;
2976
2977 if (ctx->le_mode) {
2978 gen_align_no_le(ctx);
2979 return;
2980 }
2981 if (nb == 0)
2982 nb = 32;
2983 nr = (nb + 3) / 4;
2984 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2985 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2986 return;
2987 }
2988 gen_set_access_type(ctx, ACCESS_INT);
2989 t0 = tcg_temp_new();
2990 gen_addr_register(ctx, t0);
2991 t1 = tcg_const_i32(nb);
2992 t2 = tcg_const_i32(start);
2993 gen_helper_lsw(cpu_env, t0, t1, t2);
2994 tcg_temp_free(t0);
2995 tcg_temp_free_i32(t1);
2996 tcg_temp_free_i32(t2);
2997 }
2998
2999 /* lswx */
3000 static void gen_lswx(DisasContext *ctx)
3001 {
3002 TCGv t0;
3003 TCGv_i32 t1, t2, t3;
3004
3005 if (ctx->le_mode) {
3006 gen_align_no_le(ctx);
3007 return;
3008 }
3009 gen_set_access_type(ctx, ACCESS_INT);
3010 t0 = tcg_temp_new();
3011 gen_addr_reg_index(ctx, t0);
3012 t1 = tcg_const_i32(rD(ctx->opcode));
3013 t2 = tcg_const_i32(rA(ctx->opcode));
3014 t3 = tcg_const_i32(rB(ctx->opcode));
3015 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3016 tcg_temp_free(t0);
3017 tcg_temp_free_i32(t1);
3018 tcg_temp_free_i32(t2);
3019 tcg_temp_free_i32(t3);
3020 }
3021
3022 /* stswi */
3023 static void gen_stswi(DisasContext *ctx)
3024 {
3025 TCGv t0;
3026 TCGv_i32 t1, t2;
3027 int nb = NB(ctx->opcode);
3028
3029 if (ctx->le_mode) {
3030 gen_align_no_le(ctx);
3031 return;
3032 }
3033 gen_set_access_type(ctx, ACCESS_INT);
3034 t0 = tcg_temp_new();
3035 gen_addr_register(ctx, t0);
3036 if (nb == 0)
3037 nb = 32;
3038 t1 = tcg_const_i32(nb);
3039 t2 = tcg_const_i32(rS(ctx->opcode));
3040 gen_helper_stsw(cpu_env, t0, t1, t2);
3041 tcg_temp_free(t0);
3042 tcg_temp_free_i32(t1);
3043 tcg_temp_free_i32(t2);
3044 }
3045
3046 /* stswx */
3047 static void gen_stswx(DisasContext *ctx)
3048 {
3049 TCGv t0;
3050 TCGv_i32 t1, t2;
3051
3052 if (ctx->le_mode) {
3053 gen_align_no_le(ctx);
3054 return;
3055 }
3056 gen_set_access_type(ctx, ACCESS_INT);
3057 t0 = tcg_temp_new();
3058 gen_addr_reg_index(ctx, t0);
3059 t1 = tcg_temp_new_i32();
3060 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3061 tcg_gen_andi_i32(t1, t1, 0x7F);
3062 t2 = tcg_const_i32(rS(ctx->opcode));
3063 gen_helper_stsw(cpu_env, t0, t1, t2);
3064 tcg_temp_free(t0);
3065 tcg_temp_free_i32(t1);
3066 tcg_temp_free_i32(t2);
3067 }
3068
3069 /*** Memory synchronisation ***/
3070 /* eieio */
3071 static void gen_eieio(DisasContext *ctx)
3072 {
3073 }
3074
3075 #if !defined(CONFIG_USER_ONLY)
3076 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3077 {
3078 TCGv_i32 t;
3079 TCGLabel *l;
3080
3081 if (!ctx->lazy_tlb_flush) {
3082 return;
3083 }
3084 l = gen_new_label();
3085 t = tcg_temp_new_i32();
3086 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3087 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3088 if (global) {
3089 gen_helper_check_tlb_flush_global(cpu_env);
3090 } else {
3091 gen_helper_check_tlb_flush_local(cpu_env);
3092 }
3093 gen_set_label(l);
3094 tcg_temp_free_i32(t);
3095 }
3096 #else
3097 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3098 #endif
3099
3100 /* isync */
3101 static void gen_isync(DisasContext *ctx)
3102 {
3103 /*
3104 * We need to check for a pending TLB flush. This can only happen in
3105 * kernel mode however so check MSR_PR
3106 */
3107 if (!ctx->pr) {
3108 gen_check_tlb_flush(ctx, false);
3109 }
3110 gen_stop_exception(ctx);
3111 }
3112
3113 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3114
3115 #define LARX(name, memop) \
3116 static void gen_##name(DisasContext *ctx) \
3117 { \
3118 TCGv t0; \
3119 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3120 int len = MEMOP_GET_SIZE(memop); \
3121 gen_set_access_type(ctx, ACCESS_RES); \
3122 t0 = tcg_temp_local_new(); \
3123 gen_addr_reg_index(ctx, t0); \
3124 if ((len) > 1) { \
3125 gen_check_align(ctx, t0, (len)-1); \
3126 } \
3127 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3128 tcg_gen_mov_tl(cpu_reserve, t0); \
3129 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3130 tcg_temp_free(t0); \
3131 }
3132
3133 /* lwarx */
3134 LARX(lbarx, DEF_MEMOP(MO_UB))
3135 LARX(lharx, DEF_MEMOP(MO_UW))
3136 LARX(lwarx, DEF_MEMOP(MO_UL))
3137
3138 #if defined(CONFIG_USER_ONLY)
3139 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3140 int reg, int memop)
3141 {
3142 TCGv t0 = tcg_temp_new();
3143
3144 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3145 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
3146 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3147 tcg_temp_free(t0);
3148 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3149 }
3150 #else
3151 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3152 int reg, int memop)
3153 {
3154 TCGLabel *l1;
3155
3156 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3157 l1 = gen_new_label();
3158 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3159 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3160 tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
3161 gen_set_label(l1);
3162 tcg_gen_movi_tl(cpu_reserve, -1);
3163 }
3164 #endif
3165
3166 #define STCX(name, memop) \
3167 static void gen_##name(DisasContext *ctx) \
3168 { \
3169 TCGv t0; \
3170 int len = MEMOP_GET_SIZE(memop); \
3171 gen_set_access_type(ctx, ACCESS_RES); \
3172 t0 = tcg_temp_local_new(); \
3173 gen_addr_reg_index(ctx, t0); \
3174 if (len > 1) { \
3175 gen_check_align(ctx, t0, (len) - 1); \
3176 } \
3177 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3178 tcg_temp_free(t0); \
3179 }
3180
3181 STCX(stbcx_, DEF_MEMOP(MO_UB))
3182 STCX(sthcx_, DEF_MEMOP(MO_UW))
3183 STCX(stwcx_, DEF_MEMOP(MO_UL))
3184
3185 #if defined(TARGET_PPC64)
3186 /* ldarx */
3187 LARX(ldarx, DEF_MEMOP(MO_Q))
3188 /* stdcx. */
3189 STCX(stdcx_, DEF_MEMOP(MO_Q))
3190
3191 /* lqarx */
3192 static void gen_lqarx(DisasContext *ctx)
3193 {
3194 TCGv EA;
3195 int rd = rD(ctx->opcode);
3196 TCGv gpr1, gpr2;
3197
3198 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3199 (rd == rB(ctx->opcode)))) {
3200 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3201 return;
3202 }
3203
3204 gen_set_access_type(ctx, ACCESS_RES);
3205 EA = tcg_temp_local_new();
3206 gen_addr_reg_index(ctx, EA);
3207 gen_check_align(ctx, EA, 15);
3208 if (unlikely(ctx->le_mode)) {
3209 gpr1 = cpu_gpr[rd+1];
3210 gpr2 = cpu_gpr[rd];
3211 } else {
3212 gpr1 = cpu_gpr[rd];
3213 gpr2 = cpu_gpr[rd+1];
3214 }
3215 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3216 tcg_gen_mov_tl(cpu_reserve, EA);
3217 gen_addr_add(ctx, EA, EA, 8);
3218 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3219
3220 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3221 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3222 tcg_temp_free(EA);
3223 }
3224
3225 /* stqcx. */
3226 static void gen_stqcx_(DisasContext *ctx)
3227 {
3228 TCGv EA;
3229 int reg = rS(ctx->opcode);
3230 int len = 16;
3231 #if !defined(CONFIG_USER_ONLY)
3232 TCGLabel *l1;
3233 TCGv gpr1, gpr2;
3234 #endif
3235
3236 if (unlikely((rD(ctx->opcode) & 1))) {
3237 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3238 return;
3239 }
3240 gen_set_access_type(ctx, ACCESS_RES);
3241 EA = tcg_temp_local_new();
3242 gen_addr_reg_index(ctx, EA);
3243 if (len > 1) {
3244 gen_check_align(ctx, EA, (len) - 1);
3245 }
3246
3247 #if defined(CONFIG_USER_ONLY)
3248 gen_conditional_store(ctx, EA, reg, 16);
3249 #else
3250 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3251 l1 = gen_new_label();
3252 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3253 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3254
3255 if (unlikely(ctx->le_mode)) {
3256 gpr1 = cpu_gpr[reg + 1];
3257 gpr2 = cpu_gpr[reg];
3258 } else {
3259 gpr1 = cpu_gpr[reg];
3260 gpr2 = cpu_gpr[reg + 1];
3261 }
3262 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3263 gen_addr_add(ctx, EA, EA, 8);
3264 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3265
3266 gen_set_label(l1);
3267 tcg_gen_movi_tl(cpu_reserve, -1);
3268 #endif
3269 tcg_temp_free(EA);
3270 }
3271
3272 #endif /* defined(TARGET_PPC64) */
3273
3274 /* sync */
3275 static void gen_sync(DisasContext *ctx)
3276 {
3277 uint32_t l = (ctx->opcode >> 21) & 3;
3278
3279 /*
3280 * We may need to check for a pending TLB flush.
3281 *
3282 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3283 *
3284 * Additionally, this can only happen in kernel mode however so
3285 * check MSR_PR as well.
3286 */
3287 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3288 gen_check_tlb_flush(ctx, true);
3289 }
3290 }
3291
3292 /* wait */
3293 static void gen_wait(DisasContext *ctx)
3294 {
3295 TCGv_i32 t0 = tcg_const_i32(1);
3296 tcg_gen_st_i32(t0, cpu_env,
3297 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3298 tcg_temp_free_i32(t0);
3299 /* Stop translation, as the CPU is supposed to sleep from now */
3300 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3301 }
3302
3303 #if defined(TARGET_PPC64)
3304 static void gen_doze(DisasContext *ctx)
3305 {
3306 #if defined(CONFIG_USER_ONLY)
3307 GEN_PRIV;
3308 #else
3309 TCGv_i32 t;
3310
3311 CHK_HV;
3312 t = tcg_const_i32(PPC_PM_DOZE);
3313 gen_helper_pminsn(cpu_env, t);
3314 tcg_temp_free_i32(t);
3315 gen_stop_exception(ctx);
3316 #endif /* defined(CONFIG_USER_ONLY) */
3317 }
3318
3319 static void gen_nap(DisasContext *ctx)
3320 {
3321 #if defined(CONFIG_USER_ONLY)
3322 GEN_PRIV;
3323 #else
3324 TCGv_i32 t;
3325
3326 CHK_HV;
3327 t = tcg_const_i32(PPC_PM_NAP);
3328 gen_helper_pminsn(cpu_env, t);
3329 tcg_temp_free_i32(t);
3330 gen_stop_exception(ctx);
3331 #endif /* defined(CONFIG_USER_ONLY) */
3332 }
3333
3334 static void gen_sleep(DisasContext *ctx)
3335 {
3336 #if defined(CONFIG_USER_ONLY)
3337 GEN_PRIV;
3338 #else
3339 TCGv_i32 t;
3340
3341 CHK_HV;
3342 t = tcg_const_i32(PPC_PM_SLEEP);
3343 gen_helper_pminsn(cpu_env, t);
3344 tcg_temp_free_i32(t);
3345 gen_stop_exception(ctx);
3346 #endif /* defined(CONFIG_USER_ONLY) */
3347 }
3348
3349 static void gen_rvwinkle(DisasContext *ctx)
3350 {
3351 #if defined(CONFIG_USER_ONLY)
3352 GEN_PRIV;
3353 #else
3354 TCGv_i32 t;
3355
3356 CHK_HV;
3357 t = tcg_const_i32(PPC_PM_RVWINKLE);
3358 gen_helper_pminsn(cpu_env, t);
3359 tcg_temp_free_i32(t);
3360 gen_stop_exception(ctx);
3361 #endif /* defined(CONFIG_USER_ONLY) */
3362 }
3363 #endif /* #if defined(TARGET_PPC64) */
3364
3365 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3366 {
3367 #if defined(TARGET_PPC64)
3368 if (ctx->has_cfar)
3369 tcg_gen_movi_tl(cpu_cfar, nip);
3370 #endif
3371 }
3372
3373 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3374 {
3375 if (unlikely(ctx->singlestep_enabled)) {
3376 return false;
3377 }
3378
3379 #ifndef CONFIG_USER_ONLY
3380 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3381 #else
3382 return true;
3383 #endif
3384 }
3385
3386 /*** Branch ***/
3387 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3388 {
3389 if (NARROW_MODE(ctx)) {
3390 dest = (uint32_t) dest;
3391 }
3392 if (use_goto_tb(ctx, dest)) {
3393 tcg_gen_goto_tb(n);
3394 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3395 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3396 } else {
3397 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3398 if (unlikely(ctx->singlestep_enabled)) {
3399 if ((ctx->singlestep_enabled &
3400 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3401 (ctx->exception == POWERPC_EXCP_BRANCH ||
3402 ctx->exception == POWERPC_EXCP_TRACE)) {
3403 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3404 }
3405 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3406 gen_debug_exception(ctx);
3407 }
3408 }
3409 tcg_gen_exit_tb(0);
3410 }
3411 }
3412
3413 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3414 {
3415 if (NARROW_MODE(ctx)) {
3416 nip = (uint32_t)nip;
3417 }
3418 tcg_gen_movi_tl(cpu_lr, nip);
3419 }
3420
3421 /* b ba bl bla */
3422 static void gen_b(DisasContext *ctx)
3423 {
3424 target_ulong li, target;
3425
3426 ctx->exception = POWERPC_EXCP_BRANCH;
3427 /* sign extend LI */
3428 li = LI(ctx->opcode);
3429 li = (li ^ 0x02000000) - 0x02000000;
3430 if (likely(AA(ctx->opcode) == 0)) {
3431 target = ctx->nip + li - 4;
3432 } else {
3433 target = li;
3434 }
3435 if (LK(ctx->opcode)) {
3436 gen_setlr(ctx, ctx->nip);
3437 }
3438 gen_update_cfar(ctx, ctx->nip - 4);
3439 gen_goto_tb(ctx, 0, target);
3440 }
3441
3442 #define BCOND_IM 0
3443 #define BCOND_LR 1
3444 #define BCOND_CTR 2
3445 #define BCOND_TAR 3
3446
3447 static inline void gen_bcond(DisasContext *ctx, int type)
3448 {
3449 uint32_t bo = BO(ctx->opcode);
3450 TCGLabel *l1;
3451 TCGv target;
3452
3453 ctx->exception = POWERPC_EXCP_BRANCH;
3454 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3455 target = tcg_temp_local_new();
3456 if (type == BCOND_CTR)
3457 tcg_gen_mov_tl(target, cpu_ctr);
3458 else if (type == BCOND_TAR)
3459 gen_load_spr(target, SPR_TAR);
3460 else
3461 tcg_gen_mov_tl(target, cpu_lr);
3462 } else {
3463 TCGV_UNUSED(target);
3464 }
3465 if (LK(ctx->opcode))
3466 gen_setlr(ctx, ctx->nip);
3467 l1 = gen_new_label();
3468 if ((bo & 0x4) == 0) {
3469 /* Decrement and test CTR */
3470 TCGv temp = tcg_temp_new();
3471 if (unlikely(type == BCOND_CTR)) {
3472 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3473 return;
3474 }
3475 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3476 if (NARROW_MODE(ctx)) {
3477 tcg_gen_ext32u_tl(temp, cpu_ctr);
3478 } else {
3479 tcg_gen_mov_tl(temp, cpu_ctr);
3480 }
3481 if (bo & 0x2) {
3482 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3483 } else {
3484 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3485 }
3486 tcg_temp_free(temp);
3487 }
3488 if ((bo & 0x10) == 0) {
3489 /* Test CR */
3490 uint32_t bi = BI(ctx->opcode);
3491 uint32_t mask = 0x08 >> (bi & 0x03);
3492 TCGv_i32 temp = tcg_temp_new_i32();
3493
3494 if (bo & 0x8) {
3495 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3496 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3497 } else {
3498 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3499 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3500 }
3501 tcg_temp_free_i32(temp);
3502 }
3503 gen_update_cfar(ctx, ctx->nip - 4);
3504 if (type == BCOND_IM) {
3505 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3506 if (likely(AA(ctx->opcode) == 0)) {
3507 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3508 } else {
3509 gen_goto_tb(ctx, 0, li);
3510 }
3511 if ((bo & 0x14) != 0x14) {
3512 gen_set_label(l1);
3513 gen_goto_tb(ctx, 1, ctx->nip);
3514 }
3515 } else {
3516 if (NARROW_MODE(ctx)) {
3517 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3518 } else {
3519 tcg_gen_andi_tl(cpu_nip, target, ~3);
3520 }
3521 tcg_gen_exit_tb(0);
3522 if ((bo & 0x14) != 0x14) {
3523 gen_set_label(l1);
3524 gen_update_nip(ctx, ctx->nip);
3525 tcg_gen_exit_tb(0);
3526 }
3527 }
3528 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3529 tcg_temp_free(target);
3530 }
3531 }
3532
3533 static void gen_bc(DisasContext *ctx)
3534 {
3535 gen_bcond(ctx, BCOND_IM);
3536 }
3537
3538 static void gen_bcctr(DisasContext *ctx)
3539 {
3540 gen_bcond(ctx, BCOND_CTR);
3541 }
3542
3543 static void gen_bclr(DisasContext *ctx)
3544 {
3545 gen_bcond(ctx, BCOND_LR);
3546 }
3547
3548 static void gen_bctar(DisasContext *ctx)
3549 {
3550 gen_bcond(ctx, BCOND_TAR);
3551 }
3552
3553 /*** Condition register logical ***/
3554 #define GEN_CRLOGIC(name, tcg_op, opc) \
3555 static void glue(gen_, name)(DisasContext *ctx) \
3556 { \
3557 uint8_t bitmask; \
3558 int sh; \
3559 TCGv_i32 t0, t1; \
3560 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3561 t0 = tcg_temp_new_i32(); \
3562 if (sh > 0) \
3563 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3564 else if (sh < 0) \
3565 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3566 else \
3567 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3568 t1 = tcg_temp_new_i32(); \
3569 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3570 if (sh > 0) \
3571 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3572 else if (sh < 0) \
3573 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3574 else \
3575 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3576 tcg_op(t0, t0, t1); \
3577 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3578 tcg_gen_andi_i32(t0, t0, bitmask); \
3579 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3580 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3581 tcg_temp_free_i32(t0); \
3582 tcg_temp_free_i32(t1); \
3583 }
3584
3585 /* crand */
3586 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3587 /* crandc */
3588 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3589 /* creqv */
3590 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3591 /* crnand */
3592 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3593 /* crnor */
3594 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3595 /* cror */
3596 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3597 /* crorc */
3598 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3599 /* crxor */
3600 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3601
3602 /* mcrf */
3603 static void gen_mcrf(DisasContext *ctx)
3604 {
3605 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3606 }
3607
3608 /*** System linkage ***/
3609
3610 /* rfi (supervisor only) */
3611 static void gen_rfi(DisasContext *ctx)
3612 {
3613 #if defined(CONFIG_USER_ONLY)
3614 GEN_PRIV;
3615 #else
3616 /* This instruction doesn't exist anymore on 64-bit server
3617 * processors compliant with arch 2.x
3618 */
3619 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3620 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3621 return;
3622 }
3623 /* Restore CPU state */
3624 CHK_SV;
3625 gen_update_cfar(ctx, ctx->nip - 4);
3626 gen_helper_rfi(cpu_env);
3627 gen_sync_exception(ctx);
3628 #endif
3629 }
3630
3631 #if defined(TARGET_PPC64)
3632 static void gen_rfid(DisasContext *ctx)
3633 {
3634 #if defined(CONFIG_USER_ONLY)
3635 GEN_PRIV;
3636 #else
3637 /* Restore CPU state */
3638 CHK_SV;
3639 gen_update_cfar(ctx, ctx->nip - 4);
3640 gen_helper_rfid(cpu_env);
3641 gen_sync_exception(ctx);
3642 #endif
3643 }
3644
3645 static void gen_hrfid(DisasContext *ctx)
3646 {
3647 #if defined(CONFIG_USER_ONLY)
3648 GEN_PRIV;
3649 #else
3650 /* Restore CPU state */
3651 CHK_HV;
3652 gen_helper_hrfid(cpu_env);
3653 gen_sync_exception(ctx);
3654 #endif
3655 }
3656 #endif
3657
3658 /* sc */
3659 #if defined(CONFIG_USER_ONLY)
3660 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3661 #else
3662 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3663 #endif
3664 static void gen_sc(DisasContext *ctx)
3665 {
3666 uint32_t lev;
3667
3668 lev = (ctx->opcode >> 5) & 0x7F;
3669 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3670 }
3671
3672 /*** Trap ***/
3673
3674 /* Check for unconditional traps (always or never) */
3675 static bool check_unconditional_trap(DisasContext *ctx)
3676 {
3677 /* Trap never */
3678 if (TO(ctx->opcode) == 0) {
3679 return true;
3680 }
3681 /* Trap always */
3682 if (TO(ctx->opcode) == 31) {
3683 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3684 return true;
3685 }
3686 return false;
3687 }
3688
3689 /* tw */
3690 static void gen_tw(DisasContext *ctx)
3691 {
3692 TCGv_i32 t0;
3693
3694 if (check_unconditional_trap(ctx)) {
3695 return;
3696 }
3697 t0 = tcg_const_i32(TO(ctx->opcode));
3698 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3699 t0);
3700 tcg_temp_free_i32(t0);
3701 }
3702
3703 /* twi */
3704 static void gen_twi(DisasContext *ctx)
3705 {
3706 TCGv t0;
3707 TCGv_i32 t1;
3708
3709 if (check_unconditional_trap(ctx)) {
3710 return;
3711 }
3712 t0 = tcg_const_tl(SIMM(ctx->opcode));
3713 t1 = tcg_const_i32(TO(ctx->opcode));
3714 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3715 tcg_temp_free(t0);
3716 tcg_temp_free_i32(t1);
3717 }
3718
3719 #if defined(TARGET_PPC64)
3720 /* td */
3721 static void gen_td(DisasContext *ctx)
3722 {
3723 TCGv_i32 t0;
3724
3725 if (check_unconditional_trap(ctx)) {
3726 return;
3727 }
3728 t0 = tcg_const_i32(TO(ctx->opcode));
3729 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3730 t0);
3731 tcg_temp_free_i32(t0);
3732 }
3733
3734 /* tdi */
3735 static void gen_tdi(DisasContext *ctx)
3736 {
3737 TCGv t0;
3738 TCGv_i32 t1;
3739
3740 if (check_unconditional_trap(ctx)) {
3741 return;
3742 }
3743 t0 = tcg_const_tl(SIMM(ctx->opcode));
3744 t1 = tcg_const_i32(TO(ctx->opcode));
3745 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3746 tcg_temp_free(t0);
3747 tcg_temp_free_i32(t1);
3748 }
3749 #endif
3750
3751 /*** Processor control ***/
3752
3753 static void gen_read_xer(TCGv dst)
3754 {
3755 TCGv t0 = tcg_temp_new();
3756 TCGv t1 = tcg_temp_new();
3757 TCGv t2 = tcg_temp_new();
3758 tcg_gen_mov_tl(dst, cpu_xer);
3759 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3760 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3761 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3762 tcg_gen_or_tl(t0, t0, t1);
3763 tcg_gen_or_tl(dst, dst, t2);
3764 tcg_gen_or_tl(dst, dst, t0);
3765 tcg_temp_free(t0);
3766 tcg_temp_free(t1);
3767 tcg_temp_free(t2);
3768 }
3769
3770 static void gen_write_xer(TCGv src)
3771 {
3772 tcg_gen_andi_tl(cpu_xer, src,
3773 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3774 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3775 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3776 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3777 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3778 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3779 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3780 }
3781
3782 /* mcrxr */
3783 static void gen_mcrxr(DisasContext *ctx)
3784 {
3785 TCGv_i32 t0 = tcg_temp_new_i32();
3786 TCGv_i32 t1 = tcg_temp_new_i32();
3787 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3788
3789 tcg_gen_trunc_tl_i32(t0, cpu_so);
3790 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3791 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3792 tcg_gen_shli_i32(t0, t0, 3);
3793 tcg_gen_shli_i32(t1, t1, 2);
3794 tcg_gen_shli_i32(dst, dst, 1);
3795 tcg_gen_or_i32(dst, dst, t0);
3796 tcg_gen_or_i32(dst, dst, t1);
3797 tcg_temp_free_i32(t0);
3798 tcg_temp_free_i32(t1);
3799
3800 tcg_gen_movi_tl(cpu_so, 0);
3801 tcg_gen_movi_tl(cpu_ov, 0);
3802 tcg_gen_movi_tl(cpu_ca, 0);
3803 }
3804
3805 /* mfcr mfocrf */
3806 static void gen_mfcr(DisasContext *ctx)
3807 {
3808 uint32_t crm, crn;
3809
3810 if (likely(ctx->opcode & 0x00100000)) {
3811 crm = CRM(ctx->opcode);
3812 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3813 crn = ctz32 (crm);
3814 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3815 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3816 cpu_gpr[rD(ctx->opcode)], crn * 4);
3817 }
3818 } else {
3819 TCGv_i32 t0 = tcg_temp_new_i32();
3820 tcg_gen_mov_i32(t0, cpu_crf[0]);
3821 tcg_gen_shli_i32(t0, t0, 4);
3822 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3823 tcg_gen_shli_i32(t0, t0, 4);
3824 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3825 tcg_gen_shli_i32(t0, t0, 4);
3826 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3827 tcg_gen_shli_i32(t0, t0, 4);
3828 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3829 tcg_gen_shli_i32(t0, t0, 4);
3830 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3831 tcg_gen_shli_i32(t0, t0, 4);
3832 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3833 tcg_gen_shli_i32(t0, t0, 4);
3834 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3835 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3836 tcg_temp_free_i32(t0);
3837 }
3838 }
3839
3840 /* mfmsr */
3841 static void gen_mfmsr(DisasContext *ctx)
3842 {
3843 CHK_SV;
3844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3845 }
3846
3847 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3848 {
3849 #if 0
3850 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3851 printf("ERROR: try to access SPR %d !\n", sprn);
3852 #endif
3853 }
3854 #define SPR_NOACCESS (&spr_noaccess)
3855
3856 /* mfspr */
3857 static inline void gen_op_mfspr(DisasContext *ctx)
3858 {
3859 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3860 uint32_t sprn = SPR(ctx->opcode);
3861
3862 #if defined(CONFIG_USER_ONLY)
3863 read_cb = ctx->spr_cb[sprn].uea_read;
3864 #else
3865 if (ctx->pr) {
3866 read_cb = ctx->spr_cb[sprn].uea_read;
3867 } else if (ctx->hv) {
3868 read_cb = ctx->spr_cb[sprn].hea_read;
3869 } else {
3870 read_cb = ctx->spr_cb[sprn].oea_read;
3871 }
3872 #endif
3873 if (likely(read_cb != NULL)) {
3874 if (likely(read_cb != SPR_NOACCESS)) {
3875 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3876 } else {
3877 /* Privilege exception */
3878 /* This is a hack to avoid warnings when running Linux:
3879 * this OS breaks the PowerPC virtualisation model,
3880 * allowing userland application to read the PVR
3881 */
3882 if (sprn != SPR_PVR) {
3883 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3884 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3885 if (qemu_log_separate()) {
3886 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3887 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3888 }
3889 }
3890 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3891 }
3892 } else {
3893 /* ISA 2.07 defines these as no-ops */
3894 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3895 (sprn >= 808 && sprn <= 811)) {
3896 /* This is a nop */
3897 return;
3898 }
3899 /* Not defined */
3900 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3901 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3902 if (qemu_log_separate()) {
3903 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3904 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3905 }
3906
3907 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3908 * it can generate a priv, a hv emu or a no-op
3909 */
3910 if (sprn & 0x10) {
3911 if (ctx->pr) {
3912 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3913 }
3914 } else {
3915 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3916 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3917 }
3918 }
3919 }
3920 }
3921
3922 static void gen_mfspr(DisasContext *ctx)
3923 {
3924 gen_op_mfspr(ctx);
3925 }
3926
3927 /* mftb */
3928 static void gen_mftb(DisasContext *ctx)
3929 {
3930 gen_op_mfspr(ctx);
3931 }
3932
3933 /* mtcrf mtocrf*/
3934 static void gen_mtcrf(DisasContext *ctx)
3935 {
3936 uint32_t crm, crn;
3937
3938 crm = CRM(ctx->opcode);
3939 if (likely((ctx->opcode & 0x00100000))) {
3940 if (crm && ((crm & (crm - 1)) == 0)) {
3941 TCGv_i32 temp = tcg_temp_new_i32();
3942 crn = ctz32 (crm);
3943 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3944 tcg_gen_shri_i32(temp, temp, crn * 4);
3945 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3946 tcg_temp_free_i32(temp);
3947 }
3948 } else {
3949 TCGv_i32 temp = tcg_temp_new_i32();
3950 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3951 for (crn = 0 ; crn < 8 ; crn++) {
3952 if (crm & (1 << crn)) {
3953 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3954 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3955 }
3956 }
3957 tcg_temp_free_i32(temp);
3958 }
3959 }
3960
3961 /* mtmsr */
3962 #if defined(TARGET_PPC64)
3963 static void gen_mtmsrd(DisasContext *ctx)
3964 {
3965 CHK_SV;
3966
3967 #if !defined(CONFIG_USER_ONLY)
3968 if (ctx->opcode & 0x00010000) {
3969 /* Special form that does not need any synchronisation */
3970 TCGv t0 = tcg_temp_new();
3971 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3972 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3973 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3974 tcg_temp_free(t0);
3975 } else {
3976 /* XXX: we need to update nip before the store
3977 * if we enter power saving mode, we will exit the loop
3978 * directly from ppc_store_msr
3979 */
3980 gen_update_nip(ctx, ctx->nip);
3981 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3982 /* Must stop the translation as machine state (may have) changed */
3983 /* Note that mtmsr is not always defined as context-synchronizing */
3984 gen_stop_exception(ctx);
3985 }
3986 #endif /* !defined(CONFIG_USER_ONLY) */
3987 }
3988 #endif /* defined(TARGET_PPC64) */
3989
3990 static void gen_mtmsr(DisasContext *ctx)
3991 {
3992 CHK_SV;
3993
3994 #if !defined(CONFIG_USER_ONLY)
3995 if (ctx->opcode & 0x00010000) {
3996 /* Special form that does not need any synchronisation */
3997 TCGv t0 = tcg_temp_new();
3998 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3999 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4000 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4001 tcg_temp_free(t0);
4002 } else {
4003 TCGv msr = tcg_temp_new();
4004
4005 /* XXX: we need to update nip before the store
4006 * if we enter power saving mode, we will exit the loop
4007 * directly from ppc_store_msr
4008 */
4009 gen_update_nip(ctx, ctx->nip);
4010 #if defined(TARGET_PPC64)
4011 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4012 #else
4013 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4014 #endif
4015 gen_helper_store_msr(cpu_env, msr);
4016 tcg_temp_free(msr);
4017 /* Must stop the translation as machine state (may have) changed */
4018 /* Note that mtmsr is not always defined as context-synchronizing */
4019 gen_stop_exception(ctx);
4020 }
4021 #endif
4022 }
4023
4024 /* mtspr */
4025 static void gen_mtspr(DisasContext *ctx)
4026 {
4027 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4028 uint32_t sprn = SPR(ctx->opcode);
4029
4030 #if defined(CONFIG_USER_ONLY)
4031 write_cb = ctx->spr_cb[sprn].uea_write;
4032 #else
4033 if (ctx->pr) {
4034 write_cb = ctx->spr_cb[sprn].uea_write;
4035 } else if (ctx->hv) {
4036 write_cb = ctx->spr_cb[sprn].hea_write;
4037 } else {
4038 write_cb = ctx->spr_cb[sprn].oea_write;
4039 }
4040 #endif
4041 if (likely(write_cb != NULL)) {
4042 if (likely(write_cb != SPR_NOACCESS)) {
4043 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4044 } else {
4045 /* Privilege exception */
4046 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4047 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4048 if (qemu_log_separate()) {
4049 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4050 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4051 }
4052 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4053 }
4054 } else {
4055 /* ISA 2.07 defines these as no-ops */
4056 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4057 (sprn >= 808 && sprn <= 811)) {
4058 /* This is a nop */
4059 return;
4060 }
4061
4062 /* Not defined */
4063 if (qemu_log_separate()) {
4064 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4065 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4066 }
4067 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4068 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4069
4070
4071 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4072 * it can generate a priv, a hv emu or a no-op
4073 */
4074 if (sprn & 0x10) {
4075 if (ctx->pr) {
4076 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4077 }
4078 } else {
4079 if (ctx->pr || sprn == 0) {
4080 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4081 }
4082 }
4083 }
4084 }
4085
4086 #if defined(TARGET_PPC64)
4087 /* setb */
4088 static void gen_setb(DisasContext *ctx)
4089 {
4090 TCGv_i32 t0 = tcg_temp_new_i32();
4091 TCGv_i32 t8 = tcg_temp_new_i32();
4092 TCGv_i32 tm1 = tcg_temp_new_i32();
4093 int crf = crfS(ctx->opcode);
4094
4095 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4096 tcg_gen_movi_i32(t8, 8);
4097 tcg_gen_movi_i32(tm1, -1);
4098 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4099 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4100
4101 tcg_temp_free_i32(t0);
4102 tcg_temp_free_i32(t8);
4103 tcg_temp_free_i32(tm1);
4104 }
4105 #endif
4106
4107 /*** Cache management ***/
4108
4109 /* dcbf */
4110 static void gen_dcbf(DisasContext *ctx)
4111 {
4112 /* XXX: specification says this is treated as a load by the MMU */
4113 TCGv t0;
4114 gen_set_access_type(ctx, ACCESS_CACHE);
4115 t0 = tcg_temp_new();
4116 gen_addr_reg_index(ctx, t0);
4117 gen_qemu_ld8u(ctx, t0, t0);
4118 tcg_temp_free(t0);
4119 }
4120
4121 /* dcbi (Supervisor only) */
4122 static void gen_dcbi(DisasContext *ctx)
4123 {
4124 #if defined(CONFIG_USER_ONLY)
4125 GEN_PRIV;
4126 #else
4127 TCGv EA, val;
4128
4129 CHK_SV;
4130 EA = tcg_temp_new();
4131 gen_set_access_type(ctx, ACCESS_CACHE);
4132 gen_addr_reg_index(ctx, EA);
4133 val = tcg_temp_new();
4134 /* XXX: specification says this should be treated as a store by the MMU */
4135 gen_qemu_ld8u(ctx, val, EA);
4136 gen_qemu_st8(ctx, val, EA);
4137 tcg_temp_free(val);
4138 tcg_temp_free(EA);
4139 #endif /* defined(CONFIG_USER_ONLY) */
4140 }
4141
4142 /* dcdst */
4143 static void gen_dcbst(DisasContext *ctx)
4144 {
4145 /* XXX: specification say this is treated as a load by the MMU */
4146 TCGv t0;
4147 gen_set_access_type(ctx, ACCESS_CACHE);
4148 t0 = tcg_temp_new();
4149 gen_addr_reg_index(ctx, t0);
4150 gen_qemu_ld8u(ctx, t0, t0);
4151 tcg_temp_free(t0);
4152 }
4153
4154 /* dcbt */
4155 static void gen_dcbt(DisasContext *ctx)
4156 {
4157 /* interpreted as no-op */
4158 /* XXX: specification say this is treated as a load by the MMU
4159 * but does not generate any exception
4160 */
4161 }
4162
4163 /* dcbtst */
4164 static void gen_dcbtst(DisasContext *ctx)
4165 {
4166 /* interpreted as no-op */
4167 /* XXX: specification say this is treated as a load by the MMU
4168 * but does not generate any exception
4169 */
4170 }
4171
4172 /* dcbtls */
4173 static void gen_dcbtls(DisasContext *ctx)
4174 {
4175 /* Always fails locking the cache */
4176 TCGv t0 = tcg_temp_new();
4177 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4178 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4179 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4180 tcg_temp_free(t0);
4181 }
4182
4183 /* dcbz */
4184 static void gen_dcbz(DisasContext *ctx)
4185 {
4186 TCGv tcgv_addr;
4187 TCGv_i32 tcgv_op;
4188
4189 gen_set_access_type(ctx, ACCESS_CACHE);
4190 tcgv_addr = tcg_temp_new();
4191 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4192 gen_addr_reg_index(ctx, tcgv_addr);
4193 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4194 tcg_temp_free(tcgv_addr);
4195 tcg_temp_free_i32(tcgv_op);
4196 }
4197
4198 /* dst / dstt */
4199 static void gen_dst(DisasContext *ctx)
4200 {
4201 if (rA(ctx->opcode) == 0) {
4202 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4203 } else {
4204 /* interpreted as no-op */
4205 }
4206 }
4207
4208 /* dstst /dststt */
4209 static void gen_dstst(DisasContext *ctx)
4210 {
4211 if (rA(ctx->opcode) == 0) {
4212 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4213 } else {
4214 /* interpreted as no-op */
4215 }
4216
4217 }
4218
4219 /* dss / dssall */
4220 static void gen_dss(DisasContext *ctx)
4221 {
4222 /* interpreted as no-op */
4223 }
4224
4225 /* icbi */
4226 static void gen_icbi(DisasContext *ctx)
4227 {
4228 TCGv t0;
4229 gen_set_access_type(ctx, ACCESS_CACHE);
4230 t0 = tcg_temp_new();
4231 gen_addr_reg_index(ctx, t0);
4232 gen_helper_icbi(cpu_env, t0);
4233 tcg_temp_free(t0);
4234 }
4235
4236 /* Optional: */
4237 /* dcba */
4238 static void gen_dcba(DisasContext *ctx)
4239 {
4240 /* interpreted as no-op */
4241 /* XXX: specification say this is treated as a store by the MMU
4242 * but does not generate any exception
4243 */
4244 }
4245
4246 /*** Segment register manipulation ***/
4247 /* Supervisor only: */
4248
4249 /* mfsr */
4250 static void gen_mfsr(DisasContext *ctx)
4251 {
4252 #if defined(CONFIG_USER_ONLY)
4253 GEN_PRIV;
4254 #else
4255 TCGv t0;
4256
4257 CHK_SV;
4258 t0 = tcg_const_tl(SR(ctx->opcode));
4259 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4260 tcg_temp_free(t0);
4261 #endif /* defined(CONFIG_USER_ONLY) */
4262 }
4263
4264 /* mfsrin */
4265 static void gen_mfsrin(DisasContext *ctx)
4266 {
4267 #if defined(CONFIG_USER_ONLY)
4268 GEN_PRIV;
4269 #else
4270 TCGv t0;
4271
4272 CHK_SV;
4273 t0 = tcg_temp_new();
4274 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4275 tcg_gen_andi_tl(t0, t0, 0xF);
4276 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4277 tcg_temp_free(t0);
4278 #endif /* defined(CONFIG_USER_ONLY) */
4279 }
4280
4281 /* mtsr */
4282 static void gen_mtsr(DisasContext *ctx)
4283 {
4284 #if defined(CONFIG_USER_ONLY)
4285 GEN_PRIV;
4286 #else
4287 TCGv t0;
4288
4289 CHK_SV;
4290 t0 = tcg_const_tl(SR(ctx->opcode));
4291 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4292 tcg_temp_free(t0);
4293 #endif /* defined(CONFIG_USER_ONLY) */
4294 }
4295
4296 /* mtsrin */
4297 static void gen_mtsrin(DisasContext *ctx)
4298 {
4299 #if defined(CONFIG_USER_ONLY)
4300 GEN_PRIV;
4301 #else
4302 TCGv t0;
4303 CHK_SV;
4304
4305 t0 = tcg_temp_new();
4306 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4307 tcg_gen_andi_tl(t0, t0, 0xF);
4308 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4309 tcg_temp_free(t0);
4310 #endif /* defined(CONFIG_USER_ONLY) */
4311 }
4312
4313 #if defined(TARGET_PPC64)
4314 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4315
4316 /* mfsr */
4317 static void gen_mfsr_64b(DisasContext *ctx)
4318 {
4319 #if defined(CONFIG_USER_ONLY)
4320 GEN_PRIV;
4321 #else
4322 TCGv t0;
4323
4324 CHK_SV;
4325 t0 = tcg_const_tl(SR(ctx->opcode));
4326 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4327 tcg_temp_free(t0);
4328 #endif /* defined(CONFIG_USER_ONLY) */
4329 }
4330
4331 /* mfsrin */
4332 static void gen_mfsrin_64b(DisasContext *ctx)
4333 {
4334 #if defined(CONFIG_USER_ONLY)
4335 GEN_PRIV;
4336 #else
4337 TCGv t0;
4338
4339 CHK_SV;
4340 t0 = tcg_temp_new();
4341 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4342 tcg_gen_andi_tl(t0, t0, 0xF);
4343 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4344 tcg_temp_free(t0);
4345 #endif /* defined(CONFIG_USER_ONLY) */
4346 }
4347
4348 /* mtsr */
4349 static void gen_mtsr_64b(DisasContext *ctx)
4350 {
4351 #if defined(CONFIG_USER_ONLY)
4352 GEN_PRIV;
4353 #else
4354 TCGv t0;
4355
4356 CHK_SV;
4357 t0 = tcg_const_tl(SR(ctx->opcode));
4358 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4359 tcg_temp_free(t0);
4360 #endif /* defined(CONFIG_USER_ONLY) */
4361 }
4362
4363 /* mtsrin */
4364 static void gen_mtsrin_64b(DisasContext *ctx)
4365 {
4366 #if defined(CONFIG_USER_ONLY)
4367 GEN_PRIV;
4368 #else
4369 TCGv t0;
4370
4371 CHK_SV;
4372 t0 = tcg_temp_new();
4373 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4374 tcg_gen_andi_tl(t0, t0, 0xF);
4375 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4376 tcg_temp_free(t0);
4377 #endif /* defined(CONFIG_USER_ONLY) */
4378 }
4379
4380 /* slbmte */
4381 static void gen_slbmte(DisasContext *ctx)
4382 {
4383 #if defined(CONFIG_USER_ONLY)
4384 GEN_PRIV;
4385 #else
4386 CHK_SV;
4387
4388 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4389 cpu_gpr[rS(ctx->opcode)]);
4390 #endif /* defined(CONFIG_USER_ONLY) */
4391 }
4392
4393 static void gen_slbmfee(DisasContext *ctx)
4394 {
4395 #if defined(CONFIG_USER_ONLY)
4396 GEN_PRIV;
4397 #else
4398 CHK_SV;
4399
4400 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4401 cpu_gpr[rB(ctx->opcode)]);
4402 #endif /* defined(CONFIG_USER_ONLY) */
4403 }
4404
4405 static void gen_slbmfev(DisasContext *ctx)
4406 {
4407 #if defined(CONFIG_USER_ONLY)
4408 GEN_PRIV;
4409 #else
4410 CHK_SV;
4411
4412 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4413 cpu_gpr[rB(ctx->opcode)]);
4414 #endif /* defined(CONFIG_USER_ONLY) */
4415 }
4416
4417 static void gen_slbfee_(DisasContext *ctx)
4418 {
4419 #if defined(CONFIG_USER_ONLY)
4420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4421 #else
4422 TCGLabel *l1, *l2;
4423
4424 if (unlikely(ctx->pr)) {
4425 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4426 return;
4427 }
4428 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4429 cpu_gpr[rB(ctx->opcode)]);
4430 l1 = gen_new_label();
4431 l2 = gen_new_label();
4432 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4433 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4434 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4435 tcg_gen_br(l2);
4436 gen_set_label(l1);
4437 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4438 gen_set_label(l2);
4439 #endif
4440 }
4441 #endif /* defined(TARGET_PPC64) */
4442
4443 /*** Lookaside buffer management ***/
4444 /* Optional & supervisor only: */
4445
4446 /* tlbia */
4447 static void gen_tlbia(DisasContext *ctx)
4448 {
4449 #if defined(CONFIG_USER_ONLY)
4450 GEN_PRIV;
4451 #else
4452 CHK_HV;
4453
4454 gen_helper_tlbia(cpu_env);
4455 #endif /* defined(CONFIG_USER_ONLY) */
4456 }
4457
4458 /* tlbiel */
4459 static void gen_tlbiel(DisasContext *ctx)
4460 {
4461 #if defined(CONFIG_USER_ONLY)
4462 GEN_PRIV;
4463 #else
4464 CHK_SV;
4465
4466 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4467 #endif /* defined(CONFIG_USER_ONLY) */
4468 }
4469
4470 /* tlbie */
4471 static void gen_tlbie(DisasContext *ctx)
4472 {
4473 #if defined(CONFIG_USER_ONLY)
4474 GEN_PRIV;
4475 #else
4476 TCGv_i32 t1;
4477 CHK_HV;
4478
4479 if (NARROW_MODE(ctx)) {
4480 TCGv t0 = tcg_temp_new();
4481 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4482 gen_helper_tlbie(cpu_env, t0);
4483 tcg_temp_free(t0);
4484 } else {
4485 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4486 }
4487 t1 = tcg_temp_new_i32();
4488 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4489 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4490 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4491 tcg_temp_free_i32(t1);
4492 #endif /* defined(CONFIG_USER_ONLY) */
4493 }
4494
4495 /* tlbsync */
4496 static void gen_tlbsync(DisasContext *ctx)
4497 {
4498 #if defined(CONFIG_USER_ONLY)
4499 GEN_PRIV;
4500 #else
4501 CHK_HV;
4502
4503 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4504 if (ctx->insns_flags & PPC_BOOKE) {
4505 gen_check_tlb_flush(ctx, true);
4506 }
4507 #endif /* defined(CONFIG_USER_ONLY) */
4508 }
4509
4510 #if defined(TARGET_PPC64)
4511 /* slbia */
4512 static void gen_slbia(DisasContext *ctx)
4513 {
4514 #if defined(CONFIG_USER_ONLY)
4515 GEN_PRIV;
4516 #else
4517 CHK_SV;
4518
4519 gen_helper_slbia(cpu_env);
4520 #endif /* defined(CONFIG_USER_ONLY) */
4521 }
4522
4523 /* slbie */
4524 static void gen_slbie(DisasContext *ctx)
4525 {
4526 #if defined(CONFIG_USER_ONLY)
4527 GEN_PRIV;
4528 #else
4529 CHK_SV;
4530
4531 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4532 #endif /* defined(CONFIG_USER_ONLY) */
4533 }
4534 #endif /* defined(TARGET_PPC64) */
4535
4536 /*** External control ***/
4537 /* Optional: */
4538
4539 /* eciwx */
4540 static void gen_eciwx(DisasContext *ctx)
4541 {
4542 TCGv t0;
4543 /* Should check EAR[E] ! */
4544 gen_set_access_type(ctx, ACCESS_EXT);
4545 t0 = tcg_temp_new();
4546 gen_addr_reg_index(ctx, t0);
4547 gen_check_align(ctx, t0, 0x03);
4548 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4549 tcg_temp_free(t0);
4550 }
4551
4552 /* ecowx */
4553 static void gen_ecowx(DisasContext *ctx)
4554 {
4555 TCGv t0;
4556 /* Should check EAR[E] ! */
4557 gen_set_access_type(ctx, ACCESS_EXT);
4558 t0 = tcg_temp_new();
4559 gen_addr_reg_index(ctx, t0);
4560 gen_check_align(ctx, t0, 0x03);
4561 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4562 tcg_temp_free(t0);
4563 }
4564
4565 /* PowerPC 601 specific instructions */
4566
4567 /* abs - abs. */
4568 static void gen_abs(DisasContext *ctx)
4569 {
4570 TCGLabel *l1 = gen_new_label();
4571 TCGLabel *l2 = gen_new_label();
4572 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4573 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4574 tcg_gen_br(l2);
4575 gen_set_label(l1);
4576 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4577 gen_set_label(l2);
4578 if (unlikely(Rc(ctx->opcode) != 0))
4579 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4580 }
4581
4582 /* abso - abso. */
4583 static void gen_abso(DisasContext *ctx)
4584 {
4585 TCGLabel *l1 = gen_new_label();
4586 TCGLabel *l2 = gen_new_label();
4587 TCGLabel *l3 = gen_new_label();
4588 /* Start with XER OV disabled, the most likely case */
4589 tcg_gen_movi_tl(cpu_ov, 0);
4590 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4591 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4592 tcg_gen_movi_tl(cpu_ov, 1);
4593 tcg_gen_movi_tl(cpu_so, 1);
4594 tcg_gen_br(l2);
4595 gen_set_label(l1);
4596 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4597 tcg_gen_br(l3);
4598 gen_set_label(l2);
4599 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4600 gen_set_label(l3);
4601 if (unlikely(Rc(ctx->opcode) != 0))
4602 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4603 }
4604
4605 /* clcs */
4606 static void gen_clcs(DisasContext *ctx)
4607 {
4608 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4609 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4610 tcg_temp_free_i32(t0);
4611 /* Rc=1 sets CR0 to an undefined state */
4612 }
4613
4614 /* div - div. */
4615 static void gen_div(DisasContext *ctx)
4616 {
4617 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4618 cpu_gpr[rB(ctx->opcode)]);
4619 if (unlikely(Rc(ctx->opcode) != 0))
4620 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4621 }
4622
4623 /* divo - divo. */
4624 static void gen_divo(DisasContext *ctx)
4625 {
4626 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4627 cpu_gpr[rB(ctx->opcode)]);
4628 if (unlikely(Rc(ctx->opcode) != 0))
4629 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4630 }
4631
4632 /* divs - divs. */
4633 static void gen_divs(DisasContext *ctx)
4634 {
4635 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4636 cpu_gpr[rB(ctx->opcode)]);
4637 if (unlikely(Rc(ctx->opcode) != 0))
4638 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4639 }
4640
4641 /* divso - divso. */
4642 static void gen_divso(DisasContext *ctx)
4643 {
4644 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4645 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4646 if (unlikely(Rc(ctx->opcode) != 0))
4647 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4648 }
4649
4650 /* doz - doz. */
4651 static void gen_doz(DisasContext *ctx)
4652 {
4653 TCGLabel *l1 = gen_new_label();
4654 TCGLabel *l2 = gen_new_label();
4655 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4656 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4657 tcg_gen_br(l2);
4658 gen_set_label(l1);
4659 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4660 gen_set_label(l2);
4661 if (unlikely(Rc(ctx->opcode) != 0))
4662 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4663 }
4664
4665 /* dozo - dozo. */
4666 static void gen_dozo(DisasContext *ctx)
4667 {
4668 TCGLabel *l1 = gen_new_label();
4669 TCGLabel *l2 = gen_new_label();
4670 TCGv t0 = tcg_temp_new();
4671 TCGv t1 = tcg_temp_new();
4672 TCGv t2 = tcg_temp_new();
4673 /* Start with XER OV disabled, the most likely case */
4674 tcg_gen_movi_tl(cpu_ov, 0);
4675 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4676 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4677 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4678 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4679 tcg_gen_andc_tl(t1, t1, t2);
4680 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4681 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4682 tcg_gen_movi_tl(cpu_ov, 1);
4683 tcg_gen_movi_tl(cpu_so, 1);
4684 tcg_gen_br(l2);
4685 gen_set_label(l1);
4686 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4687 gen_set_label(l2);
4688 tcg_temp_free(t0);
4689 tcg_temp_free(t1);
4690 tcg_temp_free(t2);
4691 if (unlikely(Rc(ctx->opcode) != 0))
4692 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4693 }
4694
4695 /* dozi */
4696 static void gen_dozi(DisasContext *ctx)
4697 {
4698 target_long simm = SIMM(ctx->opcode);
4699 TCGLabel *l1 = gen_new_label();
4700 TCGLabel *l2 = gen_new_label();
4701 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4702 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4703 tcg_gen_br(l2);
4704 gen_set_label(l1);
4705 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4706 gen_set_label(l2);
4707 if (unlikely(Rc(ctx->opcode) != 0))
4708 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4709 }
4710
4711 /* lscbx - lscbx. */
4712 static void gen_lscbx(DisasContext *ctx)
4713 {
4714 TCGv t0 = tcg_temp_new();
4715 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4716 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4717 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4718
4719 gen_addr_reg_index(ctx, t0);
4720 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4721 tcg_temp_free_i32(t1);
4722 tcg_temp_free_i32(t2);
4723 tcg_temp_free_i32(t3);
4724 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4725 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4726 if (unlikely(Rc(ctx->opcode) != 0))
4727 gen_set_Rc0(ctx, t0);
4728 tcg_temp_free(t0);
4729 }
4730
4731 /* maskg - maskg. */
4732 static void gen_maskg(DisasContext *ctx)
4733 {
4734 TCGLabel *l1 = gen_new_label();
4735 TCGv t0 = tcg_temp_new();
4736 TCGv t1 = tcg_temp_new();
4737 TCGv t2 = tcg_temp_new();
4738 TCGv t3 = tcg_temp_new();
4739 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4740 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4741 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4742 tcg_gen_addi_tl(t2, t0, 1);
4743 tcg_gen_shr_tl(t2, t3, t2);
4744 tcg_gen_shr_tl(t3, t3, t1);
4745 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4746 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4747 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4748 gen_set_label(l1);
4749 tcg_temp_free(t0);
4750 tcg_temp_free(t1);
4751 tcg_temp_free(t2);
4752 tcg_temp_free(t3);
4753 if (unlikely(Rc(ctx->opcode) != 0))
4754 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4755 }
4756
4757 /* maskir - maskir. */
4758 static void gen_maskir(DisasContext *ctx)
4759 {
4760 TCGv t0 = tcg_temp_new();
4761 TCGv t1 = tcg_temp_new();
4762 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4763 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4764 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4765 tcg_temp_free(t0);
4766 tcg_temp_free(t1);
4767 if (unlikely(Rc(ctx->opcode) != 0))
4768 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4769 }
4770
4771 /* mul - mul. */
4772 static void gen_mul(DisasContext *ctx)
4773 {
4774 TCGv_i64 t0 = tcg_temp_new_i64();
4775 TCGv_i64 t1 = tcg_temp_new_i64();
4776 TCGv t2 = tcg_temp_new();
4777 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4778 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4779 tcg_gen_mul_i64(t0, t0, t1);
4780 tcg_gen_trunc_i64_tl(t2, t0);
4781 gen_store_spr(SPR_MQ, t2);
4782 tcg_gen_shri_i64(t1, t0, 32);
4783 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4784 tcg_temp_free_i64(t0);
4785 tcg_temp_free_i64(t1);
4786 tcg_temp_free(t2);
4787 if (unlikely(Rc(ctx->opcode) != 0))
4788 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4789 }
4790
4791 /* mulo - mulo. */
4792 static void gen_mulo(DisasContext *ctx)
4793 {
4794 TCGLabel *l1 = gen_new_label();
4795 TCGv_i64 t0 = tcg_temp_new_i64();
4796 TCGv_i64 t1 = tcg_temp_new_i64();
4797 TCGv t2 = tcg_temp_new();
4798 /* Start with XER OV disabled, the most likely case */
4799 tcg_gen_movi_tl(cpu_ov, 0);
4800 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4801 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4802 tcg_gen_mul_i64(t0, t0, t1);
4803 tcg_gen_trunc_i64_tl(t2, t0);
4804 gen_store_spr(SPR_MQ, t2);
4805 tcg_gen_shri_i64(t1, t0, 32);
4806 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4807 tcg_gen_ext32s_i64(t1, t0);
4808 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4809 tcg_gen_movi_tl(cpu_ov, 1);
4810 tcg_gen_movi_tl(cpu_so, 1);
4811 gen_set_label(l1);
4812 tcg_temp_free_i64(t0);
4813 tcg_temp_free_i64(t1);
4814 tcg_temp_free(t2);
4815 if (unlikely(Rc(ctx->opcode) != 0))
4816 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4817 }
4818
4819 /* nabs - nabs. */
4820 static void gen_nabs(DisasContext *ctx)
4821 {
4822 TCGLabel *l1 = gen_new_label();
4823 TCGLabel *l2 = gen_new_label();
4824 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4825 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4826 tcg_gen_br(l2);
4827 gen_set_label(l1);
4828 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4829 gen_set_label(l2);
4830 if (unlikely(Rc(ctx->opcode) != 0))
4831 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4832 }
4833
4834 /* nabso - nabso. */
4835 static void gen_nabso(DisasContext *ctx)
4836 {
4837 TCGLabel *l1 = gen_new_label();
4838 TCGLabel *l2 = gen_new_label();
4839 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4840 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4841 tcg_gen_br(l2);
4842 gen_set_label(l1);
4843 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4844 gen_set_label(l2);
4845 /* nabs never overflows */
4846 tcg_gen_movi_tl(cpu_ov, 0);
4847 if (unlikely(Rc(ctx->opcode) != 0))
4848 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4849 }
4850
4851 /* rlmi - rlmi. */
4852 static void gen_rlmi(DisasContext *ctx)
4853 {
4854 uint32_t mb = MB(ctx->opcode);
4855 uint32_t me = ME(ctx->opcode);
4856 TCGv t0 = tcg_temp_new();
4857 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4858 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4859 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4860 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4861 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4862 tcg_temp_free(t0);
4863 if (unlikely(Rc(ctx->opcode) != 0))
4864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4865 }
4866
4867 /* rrib - rrib. */
4868 static void gen_rrib(DisasContext *ctx)
4869 {
4870 TCGv t0 = tcg_temp_new();
4871 TCGv t1 = tcg_temp_new();
4872 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4873 tcg_gen_movi_tl(t1, 0x80000000);
4874 tcg_gen_shr_tl(t1, t1, t0);
4875 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4876 tcg_gen_and_tl(t0, t0, t1);
4877 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4878 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4879 tcg_temp_free(t0);
4880 tcg_temp_free(t1);
4881 if (unlikely(Rc(ctx->opcode) != 0))
4882 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4883 }
4884
4885 /* sle - sle. */
4886 static void gen_sle(DisasContext *ctx)
4887 {
4888 TCGv t0 = tcg_temp_new();
4889 TCGv t1 = tcg_temp_new();
4890 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4891 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4892 tcg_gen_subfi_tl(t1, 32, t1);
4893 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4894 tcg_gen_or_tl(t1, t0, t1);
4895 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4896 gen_store_spr(SPR_MQ, t1);
4897 tcg_temp_free(t0);
4898 tcg_temp_free(t1);
4899 if (unlikely(Rc(ctx->opcode) != 0))
4900 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4901 }
4902
4903 /* sleq - sleq. */
4904 static void gen_sleq(DisasContext *ctx)
4905 {
4906 TCGv t0 = tcg_temp_new();
4907 TCGv t1 = tcg_temp_new();
4908 TCGv t2 = tcg_temp_new();
4909 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4910 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4911 tcg_gen_shl_tl(t2, t2, t0);
4912 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4913 gen_load_spr(t1, SPR_MQ);
4914 gen_store_spr(SPR_MQ, t0);
4915 tcg_gen_and_tl(t0, t0, t2);
4916 tcg_gen_andc_tl(t1, t1, t2);
4917 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
4920 tcg_temp_free(t2);
4921 if (unlikely(Rc(ctx->opcode) != 0))
4922 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4923 }
4924
4925 /* sliq - sliq. */
4926 static void gen_sliq(DisasContext *ctx)
4927 {
4928 int sh = SH(ctx->opcode);
4929 TCGv t0 = tcg_temp_new();
4930 TCGv t1 = tcg_temp_new();
4931 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4932 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4933 tcg_gen_or_tl(t1, t0, t1);
4934 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4935 gen_store_spr(SPR_MQ, t1);
4936 tcg_temp_free(t0);
4937 tcg_temp_free(t1);
4938 if (unlikely(Rc(ctx->opcode) != 0))
4939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4940 }
4941
4942 /* slliq - slliq. */
4943 static void gen_slliq(DisasContext *ctx)
4944 {
4945 int sh = SH(ctx->opcode);
4946 TCGv t0 = tcg_temp_new();
4947 TCGv t1 = tcg_temp_new();
4948 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4949 gen_load_spr(t1, SPR_MQ);
4950 gen_store_spr(SPR_MQ, t0);
4951 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4952 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4953 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4954 tcg_temp_free(t0);
4955 tcg_temp_free(t1);
4956 if (unlikely(Rc(ctx->opcode) != 0))
4957 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4958 }
4959
4960 /* sllq - sllq. */
4961 static void gen_sllq(DisasContext *ctx)
4962 {
4963 TCGLabel *l1 = gen_new_label();
4964 TCGLabel *l2 = gen_new_label();
4965 TCGv t0 = tcg_temp_local_new();
4966 TCGv t1 = tcg_temp_local_new();
4967 TCGv t2 = tcg_temp_local_new();
4968 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4969 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4970 tcg_gen_shl_tl(t1, t1, t2);
4971 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4972 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4973 gen_load_spr(t0, SPR_MQ);
4974 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4975 tcg_gen_br(l2);
4976 gen_set_label(l1);
4977 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4978 gen_load_spr(t2, SPR_MQ);
4979 tcg_gen_andc_tl(t1, t2, t1);
4980 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4981 gen_set_label(l2);
4982 tcg_temp_free(t0);
4983 tcg_temp_free(t1);
4984 tcg_temp_free(t2);
4985 if (unlikely(Rc(ctx->opcode) != 0))
4986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4987 }
4988
4989 /* slq - slq. */
4990 static void gen_slq(DisasContext *ctx)
4991 {
4992 TCGLabel *l1 = gen_new_label();
4993 TCGv t0 = tcg_temp_new();
4994 TCGv t1 = tcg_temp_new();
4995 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4996 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4997 tcg_gen_subfi_tl(t1, 32, t1);
4998 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4999 tcg_gen_or_tl(t1, t0, t1);
5000 gen_store_spr(SPR_MQ, t1);
5001 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5002 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5003 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5004 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5005 gen_set_label(l1);
5006 tcg_temp_free(t0);
5007 tcg_temp_free(t1);
5008 if (unlikely(Rc(ctx->opcode) != 0))
5009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5010 }
5011
5012 /* sraiq - sraiq. */
5013 static void gen_sraiq(DisasContext *ctx)
5014 {
5015 int sh = SH(ctx->opcode);
5016 TCGLabel *l1 = gen_new_label();
5017 TCGv t0 = tcg_temp_new();
5018 TCGv t1 = tcg_temp_new();
5019 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5020 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5021 tcg_gen_or_tl(t0, t0, t1);
5022 gen_store_spr(SPR_MQ, t0);
5023 tcg_gen_movi_tl(cpu_ca, 0);
5024 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5025 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5026 tcg_gen_movi_tl(cpu_ca, 1);
5027 gen_set_label(l1);
5028 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5029 tcg_temp_free(t0);
5030 tcg_temp_free(t1);
5031 if (unlikely(Rc(ctx->opcode) != 0))
5032 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5033 }
5034
5035 /* sraq - sraq. */
5036 static void gen_sraq(DisasContext *ctx)
5037 {
5038 TCGLabel *l1 = gen_new_label();
5039 TCGLabel *l2 = gen_new_label();
5040 TCGv t0 = tcg_temp_new();
5041 TCGv t1 = tcg_temp_local_new();
5042 TCGv t2 = tcg_temp_local_new();
5043 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5044 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5045 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5046 tcg_gen_subfi_tl(t2, 32, t2);
5047 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5048 tcg_gen_or_tl(t0, t0, t2);
5049 gen_store_spr(SPR_MQ, t0);
5050 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5051 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5052 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5053 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5054 gen_set_label(l1);
5055 tcg_temp_free(t0);
5056 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5057 tcg_gen_movi_tl(cpu_ca, 0);
5058 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5059 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5060 tcg_gen_movi_tl(cpu_ca, 1);
5061 gen_set_label(l2);
5062 tcg_temp_free(t1);
5063 tcg_temp_free(t2);
5064 if (unlikely(Rc(ctx->opcode) != 0))
5065 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5066 }
5067
5068 /* sre - sre. */
5069 static void gen_sre(DisasContext *ctx)
5070 {
5071 TCGv t0 = tcg_temp_new();
5072 TCGv t1 = tcg_temp_new();
5073 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5074 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5075 tcg_gen_subfi_tl(t1, 32, t1);
5076 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5077 tcg_gen_or_tl(t1, t0, t1);
5078 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5079 gen_store_spr(SPR_MQ, t1);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 if (unlikely(Rc(ctx->opcode) != 0))
5083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5084 }
5085
5086 /* srea - srea. */
5087 static void gen_srea(DisasContext *ctx)
5088 {
5089 TCGv t0 = tcg_temp_new();
5090 TCGv t1 = tcg_temp_new();
5091 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5092 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5093 gen_store_spr(SPR_MQ, t0);
5094 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5095 tcg_temp_free(t0);
5096 tcg_temp_free(t1);
5097 if (unlikely(Rc(ctx->opcode) != 0))
5098 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5099 }
5100
5101 /* sreq */
5102 static void gen_sreq(DisasContext *ctx)
5103 {
5104 TCGv t0 = tcg_temp_new();
5105 TCGv t1 = tcg_temp_new();
5106 TCGv t2 = tcg_temp_new();
5107 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5108 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5109 tcg_gen_shr_tl(t1, t1, t0);
5110 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5111 gen_load_spr(t2, SPR_MQ);
5112 gen_store_spr(SPR_MQ, t0);
5113 tcg_gen_and_tl(t0, t0, t1);
5114 tcg_gen_andc_tl(t2, t2, t1);
5115 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5116 tcg_temp_free(t0);
5117 tcg_temp_free(t1);
5118 tcg_temp_free(t2);
5119 if (unlikely(Rc(ctx->opcode) != 0))
5120 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5121 }
5122
5123 /* sriq */
5124 static void gen_sriq(DisasContext *ctx)
5125 {
5126 int sh = SH(ctx->opcode);
5127 TCGv t0 = tcg_temp_new();
5128 TCGv t1 = tcg_temp_new();
5129 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5130 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5131 tcg_gen_or_tl(t1, t0, t1);
5132 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5133 gen_store_spr(SPR_MQ, t1);
5134 tcg_temp_free(t0);
5135 tcg_temp_free(t1);
5136 if (unlikely(Rc(ctx->opcode) != 0))
5137 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5138 }
5139
5140 /* srliq */
5141 static void gen_srliq(DisasContext *ctx)
5142 {
5143 int sh = SH(ctx->opcode);
5144 TCGv t0 = tcg_temp_new();
5145 TCGv t1 = tcg_temp_new();
5146 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5147 gen_load_spr(t1, SPR_MQ);
5148 gen_store_spr(SPR_MQ, t0);
5149 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5150 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5151 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5152 tcg_temp_free(t0);
5153 tcg_temp_free(t1);
5154 if (unlikely(Rc(ctx->opcode) != 0))
5155 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5156 }
5157
5158 /* srlq */
5159 static void gen_srlq(DisasContext *ctx)
5160 {
5161 TCGLabel *l1 = gen_new_label();
5162 TCGLabel *l2 = gen_new_label();
5163 TCGv t0 = tcg_temp_local_new();
5164 TCGv t1 = tcg_temp_local_new();
5165 TCGv t2 = tcg_temp_local_new();
5166 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5167 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5168 tcg_gen_shr_tl(t2, t1, t2);
5169 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5170 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5171 gen_load_spr(t0, SPR_MQ);
5172 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5173 tcg_gen_br(l2);
5174 gen_set_label(l1);
5175 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5176 tcg_gen_and_tl(t0, t0, t2);
5177 gen_load_spr(t1, SPR_MQ);
5178 tcg_gen_andc_tl(t1, t1, t2);
5179 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5180 gen_set_label(l2);
5181 tcg_temp_free(t0);
5182 tcg_temp_free(t1);
5183 tcg_temp_free(t2);
5184 if (unlikely(Rc(ctx->opcode) != 0))
5185 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5186 }
5187
5188 /* srq */
5189 static void gen_srq(DisasContext *ctx)
5190 {
5191 TCGLabel *l1 = gen_new_label();
5192 TCGv t0 = tcg_temp_new();
5193 TCGv t1 = tcg_temp_new();
5194 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5195 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5196 tcg_gen_subfi_tl(t1, 32, t1);
5197 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5198 tcg_gen_or_tl(t1, t0, t1);
5199 gen_store_spr(SPR_MQ, t1);
5200 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5201 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5202 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5203 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5204 gen_set_label(l1);
5205 tcg_temp_free(t0);
5206 tcg_temp_free(t1);
5207 if (unlikely(Rc(ctx->opcode) != 0))
5208 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5209 }
5210
5211 /* PowerPC 602 specific instructions */
5212
5213 /* dsa */
5214 static void gen_dsa(DisasContext *ctx)
5215 {
5216 /* XXX: TODO */
5217 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5218 }
5219
5220 /* esa */
5221 static void gen_esa(DisasContext *ctx)
5222 {
5223 /* XXX: TODO */
5224 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5225 }
5226
5227 /* mfrom */
5228 static void gen_mfrom(DisasContext *ctx)
5229 {
5230 #if defined(CONFIG_USER_ONLY)
5231 GEN_PRIV;
5232 #else
5233 CHK_SV;
5234 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5235 #endif /* defined(CONFIG_USER_ONLY) */
5236 }
5237
5238 /* 602 - 603 - G2 TLB management */
5239
5240 /* tlbld */
5241 static void gen_tlbld_6xx(DisasContext *ctx)
5242 {
5243 #if defined(CONFIG_USER_ONLY)
5244 GEN_PRIV;
5245 #else
5246 CHK_SV;
5247 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5248 #endif /* defined(CONFIG_USER_ONLY) */
5249 }
5250
5251 /* tlbli */
5252 static void gen_tlbli_6xx(DisasContext *ctx)
5253 {
5254 #if defined(CONFIG_USER_ONLY)
5255 GEN_PRIV;
5256 #else
5257 CHK_SV;
5258 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5259 #endif /* defined(CONFIG_USER_ONLY) */
5260 }
5261
5262 /* 74xx TLB management */
5263
5264 /* tlbld */
5265 static void gen_tlbld_74xx(DisasContext *ctx)
5266 {
5267 #if defined(CONFIG_USER_ONLY)
5268 GEN_PRIV;
5269 #else
5270 CHK_SV;
5271 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5272 #endif /* defined(CONFIG_USER_ONLY) */
5273 }
5274
5275 /* tlbli */
5276 static void gen_tlbli_74xx(DisasContext *ctx)
5277 {
5278 #if defined(CONFIG_USER_ONLY)
5279 GEN_PRIV;
5280 #else
5281 CHK_SV;
5282 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5283 #endif /* defined(CONFIG_USER_ONLY) */
5284 }
5285
5286 /* POWER instructions not in PowerPC 601 */
5287
5288 /* clf */
5289 static void gen_clf(DisasContext *ctx)
5290 {
5291 /* Cache line flush: implemented as no-op */
5292 }
5293
5294 /* cli */
5295 static void gen_cli(DisasContext *ctx)
5296 {
5297 #if defined(CONFIG_USER_ONLY)
5298 GEN_PRIV;
5299 #else
5300 /* Cache line invalidate: privileged and treated as no-op */
5301 CHK_SV;
5302 #endif /* defined(CONFIG_USER_ONLY) */
5303 }
5304
5305 /* dclst */
5306 static void gen_dclst(DisasContext *ctx)
5307 {
5308 /* Data cache line store: treated as no-op */
5309 }
5310
5311 static void gen_mfsri(DisasContext *ctx)
5312 {
5313 #if defined(CONFIG_USER_ONLY)
5314 GEN_PRIV;
5315 #else
5316 int ra = rA(ctx->opcode);
5317 int rd = rD(ctx->opcode);
5318 TCGv t0;
5319
5320 CHK_SV;
5321 t0 = tcg_temp_new();
5322 gen_addr_reg_index(ctx, t0);
5323 tcg_gen_shri_tl(t0, t0, 28);
5324 tcg_gen_andi_tl(t0, t0, 0xF);
5325 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5326 tcg_temp_free(t0);
5327 if (ra != 0 && ra != rd)
5328 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5329 #endif /* defined(CONFIG_USER_ONLY) */
5330 }
5331
5332 static void gen_rac(DisasContext *ctx)
5333 {
5334 #if defined(CONFIG_USER_ONLY)
5335 GEN_PRIV;
5336 #else
5337 TCGv t0;
5338
5339 CHK_SV;
5340 t0 = tcg_temp_new();
5341 gen_addr_reg_index(ctx, t0);
5342 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5343 tcg_temp_free(t0);
5344 #endif /* defined(CONFIG_USER_ONLY) */
5345 }
5346
5347 static void gen_rfsvc(DisasContext *ctx)
5348 {
5349 #if defined(CONFIG_USER_ONLY)
5350 GEN_PRIV;
5351 #else
5352 CHK_SV;
5353
5354 gen_helper_rfsvc(cpu_env);
5355 gen_sync_exception(ctx);
5356 #endif /* defined(CONFIG_USER_ONLY) */
5357 }
5358
5359 /* svc is not implemented for now */
5360
5361 /* BookE specific instructions */
5362
5363 /* XXX: not implemented on 440 ? */
5364 static void gen_mfapidi(DisasContext *ctx)
5365 {
5366 /* XXX: TODO */
5367 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5368 }
5369
5370 /* XXX: not implemented on 440 ? */
5371 static void gen_tlbiva(DisasContext *ctx)
5372 {
5373 #if defined(CONFIG_USER_ONLY)
5374 GEN_PRIV;
5375 #else
5376 TCGv t0;
5377
5378 CHK_SV;
5379 t0 = tcg_temp_new();
5380 gen_addr_reg_index(ctx, t0);
5381 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5382 tcg_temp_free(t0);
5383 #endif /* defined(CONFIG_USER_ONLY) */
5384 }
5385
5386 /* All 405 MAC instructions are translated here */
5387 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5388 int ra, int rb, int rt, int Rc)
5389 {
5390 TCGv t0, t1;
5391
5392 t0 = tcg_temp_local_new();
5393 t1 = tcg_temp_local_new();
5394
5395 switch (opc3 & 0x0D) {
5396 case 0x05:
5397 /* macchw - macchw. - macchwo - macchwo. */
5398 /* macchws - macchws. - macchwso - macchwso. */
5399 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5400 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5401 /* mulchw - mulchw. */
5402 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5403 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5404 tcg_gen_ext16s_tl(t1, t1);
5405 break;
5406 case 0x04:
5407 /* macchwu - macchwu. - macchwuo - macchwuo. */
5408 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5409 /* mulchwu - mulchwu. */
5410 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5411 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5412 tcg_gen_ext16u_tl(t1, t1);
5413 break;
5414 case 0x01:
5415 /* machhw - machhw. - machhwo - machhwo. */
5416 /* machhws - machhws. - machhwso - machhwso. */
5417 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5418 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5419 /* mulhhw - mulhhw. */
5420 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5421 tcg_gen_ext16s_tl(t0, t0);
5422 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5423 tcg_gen_ext16s_tl(t1, t1);
5424 break;
5425 case 0x00:
5426 /* machhwu - machhwu. - machhwuo - machhwuo. */
5427 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5428 /* mulhhwu - mulhhwu. */
5429 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5430 tcg_gen_ext16u_tl(t0, t0);
5431 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5432 tcg_gen_ext16u_tl(t1, t1);
5433 break;
5434 case 0x0D:
5435 /* maclhw - maclhw. - maclhwo - maclhwo. */
5436 /* maclhws - maclhws. - maclhwso - maclhwso. */
5437 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5438 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5439 /* mullhw - mullhw. */
5440 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5441 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5442 break;
5443 case 0x0C:
5444 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5445 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5446 /* mullhwu - mullhwu. */
5447 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5448 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5449 break;
5450 }
5451 if (opc2 & 0x04) {
5452 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5453 tcg_gen_mul_tl(t1, t0, t1);
5454 if (opc2 & 0x02) {
5455 /* nmultiply-and-accumulate (0x0E) */
5456 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5457 } else {
5458 /* multiply-and-accumulate (0x0C) */
5459 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5460 }
5461
5462 if (opc3 & 0x12) {
5463 /* Check overflow and/or saturate */
5464 TCGLabel *l1 = gen_new_label();
5465
5466 if (opc3 & 0x10) {
5467 /* Start with XER OV disabled, the most likely case */
5468 tcg_gen_movi_tl(cpu_ov, 0);
5469 }
5470 if (opc3 & 0x01) {
5471 /* Signed */
5472 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5473 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5474 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5475 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5476 if (opc3 & 0x02) {
5477 /* Saturate */
5478 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5479 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5480 }
5481 } else {
5482 /* Unsigned */
5483 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5484 if (opc3 & 0x02) {
5485 /* Saturate */
5486 tcg_gen_movi_tl(t0, UINT32_MAX);
5487 }
5488 }
5489 if (opc3 & 0x10) {
5490 /* Check overflow */
5491 tcg_gen_movi_tl(cpu_ov, 1);
5492 tcg_gen_movi_tl(cpu_so, 1);
5493 }
5494 gen_set_label(l1);
5495 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5496 }
5497 } else {
5498 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5499 }
5500 tcg_temp_free(t0);
5501 tcg_temp_free(t1);
5502 if (unlikely(Rc) != 0) {
5503 /* Update Rc0 */
5504 gen_set_Rc0(ctx, cpu_gpr[rt]);
5505 }
5506 }
5507
5508 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5509 static void glue(gen_, name)(DisasContext *ctx) \
5510 { \
5511 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5512 rD(ctx->opcode), Rc(ctx->opcode)); \
5513 }
5514
5515 /* macchw - macchw. */
5516 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5517 /* macchwo - macchwo. */
5518 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5519 /* macchws - macchws. */
5520 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5521 /* macchwso - macchwso. */
5522 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5523 /* macchwsu - macchwsu. */
5524 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5525 /* macchwsuo - macchwsuo. */
5526 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5527 /* macchwu - macchwu. */
5528 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5529 /* macchwuo - macchwuo. */
5530 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5531 /* machhw - machhw. */
5532 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5533 /* machhwo - machhwo. */
5534 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5535 /* machhws - machhws. */
5536 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5537 /* machhwso - machhwso. */
5538 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5539 /* machhwsu - machhwsu. */
5540 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5541 /* machhwsuo - machhwsuo. */
5542 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5543 /* machhwu - machhwu. */
5544 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5545 /* machhwuo - machhwuo. */
5546 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5547 /* maclhw - maclhw. */
5548 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5549 /* maclhwo - maclhwo. */
5550 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5551 /* maclhws - maclhws. */
5552 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5553 /* maclhwso - maclhwso. */
5554 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5555 /* maclhwu - maclhwu. */
5556 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5557 /* maclhwuo - maclhwuo. */
5558 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5559 /* maclhwsu - maclhwsu. */
5560 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5561 /* maclhwsuo - maclhwsuo. */
5562 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5563 /* nmacchw - nmacchw. */
5564 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5565 /* nmacchwo - nmacchwo. */
5566 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5567 /* nmacchws - nmacchws. */
5568 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5569 /* nmacchwso - nmacchwso. */
5570 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5571 /* nmachhw - nmachhw. */
5572 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5573 /* nmachhwo - nmachhwo. */
5574 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5575 /* nmachhws - nmachhws. */
5576 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5577 /* nmachhwso - nmachhwso. */
5578 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5579 /* nmaclhw - nmaclhw. */
5580 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5581 /* nmaclhwo - nmaclhwo. */
5582 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5583 /* nmaclhws - nmaclhws. */
5584 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5585 /* nmaclhwso - nmaclhwso. */
5586 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5587
5588 /* mulchw - mulchw. */
5589 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5590 /* mulchwu - mulchwu. */
5591 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5592 /* mulhhw - mulhhw. */
5593 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5594 /* mulhhwu - mulhhwu. */
5595 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5596 /* mullhw - mullhw. */
5597 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5598 /* mullhwu - mullhwu. */
5599 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5600
5601 /* mfdcr */
5602 static void gen_mfdcr(DisasContext *ctx)
5603 {
5604 #if defined(CONFIG_USER_ONLY)
5605 GEN_PRIV;
5606 #else
5607 TCGv dcrn;
5608
5609 CHK_SV;
5610 dcrn = tcg_const_tl(SPR(ctx->opcode));
5611 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5612 tcg_temp_free(dcrn);
5613 #endif /* defined(CONFIG_USER_ONLY) */
5614 }
5615
5616 /* mtdcr */
5617 static void gen_mtdcr(DisasContext *ctx)
5618 {
5619 #if defined(CONFIG_USER_ONLY)
5620 GEN_PRIV;
5621 #else
5622 TCGv dcrn;
5623
5624 CHK_SV;
5625 dcrn = tcg_const_tl(SPR(ctx->opcode));
5626 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5627 tcg_temp_free(dcrn);
5628 #endif /* defined(CONFIG_USER_ONLY) */
5629 }
5630
5631 /* mfdcrx */
5632 /* XXX: not implemented on 440 ? */
5633 static void gen_mfdcrx(DisasContext *ctx)
5634 {
5635 #if defined(CONFIG_USER_ONLY)
5636 GEN_PRIV;
5637 #else
5638 CHK_SV;
5639 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5640 cpu_gpr[rA(ctx->opcode)]);
5641 /* Note: Rc update flag set leads to undefined state of Rc0 */
5642 #endif /* defined(CONFIG_USER_ONLY) */
5643 }
5644
5645 /* mtdcrx */
5646 /* XXX: not implemented on 440 ? */
5647 static void gen_mtdcrx(DisasContext *ctx)
5648 {
5649 #if defined(CONFIG_USER_ONLY)
5650 GEN_PRIV;
5651 #else
5652 CHK_SV;
5653 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5654 cpu_gpr[rS(ctx->opcode)]);
5655 /* Note: Rc update flag set leads to undefined state of Rc0 */
5656 #endif /* defined(CONFIG_USER_ONLY) */
5657 }
5658
5659 /* mfdcrux (PPC 460) : user-mode access to DCR */
5660 static void gen_mfdcrux(DisasContext *ctx)
5661 {
5662 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5663 cpu_gpr[rA(ctx->opcode)]);
5664 /* Note: Rc update flag set leads to undefined state of Rc0 */
5665 }
5666
5667 /* mtdcrux (PPC 460) : user-mode access to DCR */
5668 static void gen_mtdcrux(DisasContext *ctx)
5669 {
5670 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5671 cpu_gpr[rS(ctx->opcode)]);
5672 /* Note: Rc update flag set leads to undefined state of Rc0 */
5673 }
5674
5675 /* dccci */
5676 static void gen_dccci(DisasContext *ctx)
5677 {
5678 CHK_SV;
5679 /* interpreted as no-op */
5680 }
5681
5682 /* dcread */
5683 static void gen_dcread(DisasContext *ctx)
5684 {
5685 #if defined(CONFIG_USER_ONLY)
5686 GEN_PRIV;
5687 #else
5688 TCGv EA, val;
5689
5690 CHK_SV;
5691 gen_set_access_type(ctx, ACCESS_CACHE);
5692 EA = tcg_temp_new();
5693 gen_addr_reg_index(ctx, EA);
5694 val = tcg_temp_new();
5695 gen_qemu_ld32u(ctx, val, EA);
5696 tcg_temp_free(val);
5697 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5698 tcg_temp_free(EA);
5699 #endif /* defined(CONFIG_USER_ONLY) */
5700 }
5701
5702 /* icbt */
5703 static void gen_icbt_40x(DisasContext *ctx)
5704 {
5705 /* interpreted as no-op */
5706 /* XXX: specification say this is treated as a load by the MMU
5707 * but does not generate any exception
5708 */
5709 }
5710
5711 /* iccci */
5712 static void gen_iccci(DisasContext *ctx)
5713 {
5714 CHK_SV;
5715 /* interpreted as no-op */
5716 }
5717
5718 /* icread */
5719 static void gen_icread(DisasContext *ctx)
5720 {
5721 CHK_SV;
5722 /* interpreted as no-op */
5723 }
5724
5725 /* rfci (supervisor only) */
5726 static void gen_rfci_40x(DisasContext *ctx)
5727 {
5728 #if defined(CONFIG_USER_ONLY)
5729 GEN_PRIV;
5730 #else
5731 CHK_SV;
5732 /* Restore CPU state */
5733 gen_helper_40x_rfci(cpu_env);
5734 gen_sync_exception(ctx);
5735 #endif /* defined(CONFIG_USER_ONLY) */
5736 }
5737
5738 static void gen_rfci(DisasContext *ctx)
5739 {
5740 #if defined(CONFIG_USER_ONLY)
5741 GEN_PRIV;
5742 #else
5743 CHK_SV;
5744 /* Restore CPU state */
5745 gen_helper_rfci(cpu_env);
5746 gen_sync_exception(ctx);
5747 #endif /* defined(CONFIG_USER_ONLY) */
5748 }
5749
5750 /* BookE specific */
5751
5752 /* XXX: not implemented on 440 ? */
5753 static void gen_rfdi(DisasContext *ctx)
5754 {
5755 #if defined(CONFIG_USER_ONLY)
5756 GEN_PRIV;
5757 #else
5758 CHK_SV;
5759 /* Restore CPU state */
5760 gen_helper_rfdi(cpu_env);
5761 gen_sync_exception(ctx);
5762 #endif /* defined(CONFIG_USER_ONLY) */
5763 }
5764
5765 /* XXX: not implemented on 440 ? */
5766 static void gen_rfmci(DisasContext *ctx)
5767 {
5768 #if defined(CONFIG_USER_ONLY)
5769 GEN_PRIV;
5770 #else
5771 CHK_SV;
5772 /* Restore CPU state */
5773 gen_helper_rfmci(cpu_env);
5774 gen_sync_exception(ctx);
5775 #endif /* defined(CONFIG_USER_ONLY) */
5776 }
5777
5778 /* TLB management - PowerPC 405 implementation */
5779
5780 /* tlbre */
5781 static void gen_tlbre_40x(DisasContext *ctx)
5782 {
5783 #if defined(CONFIG_USER_ONLY)
5784 GEN_PRIV;
5785 #else
5786 CHK_SV;
5787 switch (rB(ctx->opcode)) {
5788 case 0:
5789 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5790 cpu_gpr[rA(ctx->opcode)]);
5791 break;
5792 case 1:
5793 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5794 cpu_gpr[rA(ctx->opcode)]);
5795 break;
5796 default:
5797 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5798 break;
5799 }
5800 #endif /* defined(CONFIG_USER_ONLY) */
5801 }
5802
5803 /* tlbsx - tlbsx. */
5804 static void gen_tlbsx_40x(DisasContext *ctx)
5805 {
5806 #if defined(CONFIG_USER_ONLY)
5807 GEN_PRIV;
5808 #else
5809 TCGv t0;
5810
5811 CHK_SV;
5812 t0 = tcg_temp_new();
5813 gen_addr_reg_index(ctx, t0);
5814 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5815 tcg_temp_free(t0);
5816 if (Rc(ctx->opcode)) {
5817 TCGLabel *l1 = gen_new_label();
5818 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5819 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5820 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5821 gen_set_label(l1);
5822 }
5823 #endif /* defined(CONFIG_USER_ONLY) */
5824 }
5825
5826 /* tlbwe */
5827 static void gen_tlbwe_40x(DisasContext *ctx)
5828 {
5829 #if defined(CONFIG_USER_ONLY)
5830 GEN_PRIV;
5831 #else
5832 CHK_SV;
5833
5834 switch (rB(ctx->opcode)) {
5835 case 0:
5836 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5837 cpu_gpr[rS(ctx->opcode)]);
5838 break;
5839 case 1:
5840 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5841 cpu_gpr[rS(ctx->opcode)]);
5842 break;
5843 default:
5844 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5845 break;
5846 }
5847 #endif /* defined(CONFIG_USER_ONLY) */
5848 }
5849
5850 /* TLB management - PowerPC 440 implementation */
5851
5852 /* tlbre */
5853 static void gen_tlbre_440(DisasContext *ctx)
5854 {
5855 #if defined(CONFIG_USER_ONLY)
5856 GEN_PRIV;
5857 #else
5858 CHK_SV;
5859
5860 switch (rB(ctx->opcode)) {
5861 case 0:
5862 case 1:
5863 case 2:
5864 {
5865 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5866 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5867 t0, cpu_gpr[rA(ctx->opcode)]);
5868 tcg_temp_free_i32(t0);
5869 }
5870 break;
5871 default:
5872 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5873 break;
5874 }
5875 #endif /* defined(CONFIG_USER_ONLY) */
5876 }
5877
5878 /* tlbsx - tlbsx. */
5879 static void gen_tlbsx_440(DisasContext *ctx)
5880 {
5881 #if defined(CONFIG_USER_ONLY)
5882 GEN_PRIV;
5883 #else
5884 TCGv t0;
5885
5886 CHK_SV;
5887 t0 = tcg_temp_new();
5888 gen_addr_reg_index(ctx, t0);
5889 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5890 tcg_temp_free(t0);
5891 if (Rc(ctx->opcode)) {
5892 TCGLabel *l1 = gen_new_label();
5893 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5894 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5895 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5896 gen_set_label(l1);
5897 }
5898 #endif /* defined(CONFIG_USER_ONLY) */
5899 }
5900
5901 /* tlbwe */
5902 static void gen_tlbwe_440(DisasContext *ctx)
5903 {
5904 #if defined(CONFIG_USER_ONLY)
5905 GEN_PRIV;
5906 #else
5907 CHK_SV;
5908 switch (rB(ctx->opcode)) {
5909 case 0:
5910 case 1:
5911 case 2:
5912 {
5913 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5914 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5915 cpu_gpr[rS(ctx->opcode)]);
5916 tcg_temp_free_i32(t0);
5917 }
5918 break;
5919 default:
5920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5921 break;
5922 }
5923 #endif /* defined(CONFIG_USER_ONLY) */
5924 }
5925
5926 /* TLB management - PowerPC BookE 2.06 implementation */
5927
5928 /* tlbre */
5929 static void gen_tlbre_booke206(DisasContext *ctx)
5930 {
5931 #if defined(CONFIG_USER_ONLY)
5932 GEN_PRIV;
5933 #else
5934 CHK_SV;
5935 gen_helper_booke206_tlbre(cpu_env);
5936 #endif /* defined(CONFIG_USER_ONLY) */
5937 }
5938
5939 /* tlbsx - tlbsx. */
5940 static void gen_tlbsx_booke206(DisasContext *ctx)
5941 {
5942 #if defined(CONFIG_USER_ONLY)
5943 GEN_PRIV;
5944 #else
5945 TCGv t0;
5946
5947 CHK_SV;
5948 if (rA(ctx->opcode)) {
5949 t0 = tcg_temp_new();
5950 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5951 } else {
5952 t0 = tcg_const_tl(0);
5953 }
5954
5955 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5956 gen_helper_booke206_tlbsx(cpu_env, t0);
5957 tcg_temp_free(t0);
5958 #endif /* defined(CONFIG_USER_ONLY) */
5959 }
5960
5961 /* tlbwe */
5962 static void gen_tlbwe_booke206(DisasContext *ctx)
5963 {
5964 #if defined(CONFIG_USER_ONLY)
5965 GEN_PRIV;
5966 #else
5967 CHK_SV;
5968 gen_helper_booke206_tlbwe(cpu_env);
5969 #endif /* defined(CONFIG_USER_ONLY) */
5970 }
5971
5972 static void gen_tlbivax_booke206(DisasContext *ctx)
5973 {
5974 #if defined(CONFIG_USER_ONLY)
5975 GEN_PRIV;
5976 #else
5977 TCGv t0;
5978
5979 CHK_SV;
5980 t0 = tcg_temp_new();
5981 gen_addr_reg_index(ctx, t0);
5982 gen_helper_booke206_tlbivax(cpu_env, t0);
5983 tcg_temp_free(t0);
5984 #endif /* defined(CONFIG_USER_ONLY) */
5985 }
5986
5987 static void gen_tlbilx_booke206(DisasContext *ctx)
5988 {
5989 #if defined(CONFIG_USER_ONLY)
5990 GEN_PRIV;
5991 #else
5992 TCGv t0;
5993
5994 CHK_SV;
5995 t0 = tcg_temp_new();
5996 gen_addr_reg_index(ctx, t0);
5997
5998 switch((ctx->opcode >> 21) & 0x3) {
5999 case 0:
6000 gen_helper_booke206_tlbilx0(cpu_env, t0);
6001 break;
6002 case 1:
6003 gen_helper_booke206_tlbilx1(cpu_env, t0);
6004 break;
6005 case 3:
6006 gen_helper_booke206_tlbilx3(cpu_env, t0);
6007 break;
6008 default:
6009 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6010 break;
6011 }
6012
6013 tcg_temp_free(t0);
6014 #endif /* defined(CONFIG_USER_ONLY) */
6015 }
6016
6017
6018 /* wrtee */
6019 static void gen_wrtee(DisasContext *ctx)
6020 {
6021 #if defined(CONFIG_USER_ONLY)
6022 GEN_PRIV;
6023 #else
6024 TCGv t0;
6025
6026 CHK_SV;
6027 t0 = tcg_temp_new();
6028 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6029 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6030 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6031 tcg_temp_free(t0);
6032 /* Stop translation to have a chance to raise an exception
6033 * if we just set msr_ee to 1
6034 */
6035 gen_stop_exception(ctx);
6036 #endif /* defined(CONFIG_USER_ONLY) */
6037 }
6038
6039 /* wrteei */
6040 static void gen_wrteei(DisasContext *ctx)
6041 {
6042 #if defined(CONFIG_USER_ONLY)
6043 GEN_PRIV;
6044 #else
6045 CHK_SV;
6046 if (ctx->opcode & 0x00008000) {
6047 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6048 /* Stop translation to have a chance to raise an exception */
6049 gen_stop_exception(ctx);
6050 } else {
6051 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6052 }
6053 #endif /* defined(CONFIG_USER_ONLY) */
6054 }
6055
6056 /* PowerPC 440 specific instructions */
6057
6058 /* dlmzb */
6059 static void gen_dlmzb(DisasContext *ctx)
6060 {
6061 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6062 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6063 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6064 tcg_temp_free_i32(t0);
6065 }
6066
6067 /* mbar replaces eieio on 440 */
6068 static void gen_mbar(DisasContext *ctx)
6069 {
6070 /* interpreted as no-op */
6071 }
6072
6073 /* msync replaces sync on 440 */
6074 static void gen_msync_4xx(DisasContext *ctx)
6075 {
6076 /* interpreted as no-op */
6077 }
6078
6079 /* icbt */
6080 static void gen_icbt_440(DisasContext *ctx)
6081 {
6082 /* interpreted as no-op */
6083 /* XXX: specification say this is treated as a load by the MMU
6084 * but does not generate any exception
6085 */
6086 }
6087
6088 /* Embedded.Processor Control */
6089
6090 static void gen_msgclr(DisasContext *ctx)
6091 {
6092 #if defined(CONFIG_USER_ONLY)
6093 GEN_PRIV;
6094 #else
6095 CHK_SV;
6096 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6097 #endif /* defined(CONFIG_USER_ONLY) */
6098 }
6099
6100 static void gen_msgsnd(DisasContext *ctx)
6101 {
6102 #if defined(CONFIG_USER_ONLY)
6103 GEN_PRIV;
6104 #else
6105 CHK_SV;
6106 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6107 #endif /* defined(CONFIG_USER_ONLY) */
6108 }
6109
6110
6111 #if defined(TARGET_PPC64)
6112 static void gen_maddld(DisasContext *ctx)
6113 {
6114 TCGv_i64 t1 = tcg_temp_new_i64();
6115
6116 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6117 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6118 tcg_temp_free_i64(t1);
6119 }
6120
6121 /* maddhd maddhdu */
6122 static void gen_maddhd_maddhdu(DisasContext *ctx)
6123 {
6124 TCGv_i64 lo = tcg_temp_new_i64();
6125 TCGv_i64 hi = tcg_temp_new_i64();
6126 TCGv_i64 t1 = tcg_temp_new_i64();
6127
6128 if (Rc(ctx->opcode)) {
6129 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6130 cpu_gpr[rB(ctx->opcode)]);
6131 tcg_gen_movi_i64(t1, 0);
6132 } else {
6133 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6134 cpu_gpr[rB(ctx->opcode)]);
6135 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6136 }
6137 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6138 cpu_gpr[rC(ctx->opcode)], t1);
6139 tcg_temp_free_i64(lo);
6140 tcg_temp_free_i64(hi);
6141 tcg_temp_free_i64(t1);
6142 }
6143 #endif /* defined(TARGET_PPC64) */
6144
6145 static void gen_tbegin(DisasContext *ctx)
6146 {
6147 if (unlikely(!ctx->tm_enabled)) {
6148 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6149 return;
6150 }
6151 gen_helper_tbegin(cpu_env);
6152 }
6153
6154 #define GEN_TM_NOOP(name) \
6155 static inline void gen_##name(DisasContext *ctx) \
6156 { \
6157 if (unlikely(!ctx->tm_enabled)) { \
6158 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6159 return; \
6160 } \
6161 /* Because tbegin always fails in QEMU, these user \
6162 * space instructions all have a simple implementation: \
6163 * \
6164 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6165 * = 0b0 || 0b00 || 0b0 \
6166 */ \
6167 tcg_gen_movi_i32(cpu_crf[0], 0); \
6168 }
6169
6170 GEN_TM_NOOP(tend);
6171 GEN_TM_NOOP(tabort);
6172 GEN_TM_NOOP(tabortwc);
6173 GEN_TM_NOOP(tabortwci);
6174 GEN_TM_NOOP(tabortdc);
6175 GEN_TM_NOOP(tabortdci);
6176 GEN_TM_NOOP(tsr);
6177
6178 static void gen_tcheck(DisasContext *ctx)
6179 {
6180 if (unlikely(!ctx->tm_enabled)) {
6181 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6182 return;
6183 }
6184 /* Because tbegin always fails, the tcheck implementation
6185 * is simple:
6186 *
6187 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6188 * = 0b1 || 0b00 || 0b0
6189 */
6190 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6191 }
6192
6193 #if defined(CONFIG_USER_ONLY)
6194 #define GEN_TM_PRIV_NOOP(name) \
6195 static inline void gen_##name(DisasContext *ctx) \
6196 { \
6197 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6198 }
6199
6200 #else
6201
6202 #define GEN_TM_PRIV_NOOP(name) \
6203 static inline void gen_##name(DisasContext *ctx) \
6204 { \
6205 CHK_SV; \
6206 if (unlikely(!ctx->tm_enabled)) { \
6207 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6208 return; \
6209 } \
6210 /* Because tbegin always fails, the implementation is \
6211 * simple: \
6212 * \
6213 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6214 * = 0b0 || 0b00 | 0b0 \
6215 */ \
6216 tcg_gen_movi_i32(cpu_crf[0], 0); \
6217 }
6218
6219 #endif
6220
6221 GEN_TM_PRIV_NOOP(treclaim);
6222 GEN_TM_PRIV_NOOP(trechkpt);
6223
6224 #include "translate/fp-impl.inc.c"
6225
6226 #include "translate/vmx-impl.inc.c"
6227
6228 #include "translate/vsx-impl.inc.c"
6229
6230 #include "translate/dfp-impl.inc.c"
6231
6232 #include "translate/spe-impl.inc.c"
6233
6234 static opcode_t opcodes[] = {
6235 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6236 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6237 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6238 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6239 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6240 #if defined(TARGET_PPC64)
6241 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6242 #endif
6243 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6244 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6245 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6246 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6247 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6248 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6249 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6250 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6251 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6252 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6253 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6254 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6255 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6256 #if defined(TARGET_PPC64)
6257 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6258 #endif
6259 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6260 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6261 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6262 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6263 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6264 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6265 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6266 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6267 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6268 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6269 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6270 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6271 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6272 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6273 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6274 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6275 #if defined(TARGET_PPC64)
6276 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6277 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6278 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6279 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6280 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6281 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6282 #endif
6283 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6284 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6285 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6286 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6287 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6288 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6289 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6290 #if defined(TARGET_PPC64)
6291 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6292 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6293 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6294 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6295 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6296 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6297 PPC_NONE, PPC2_ISA300),
6298 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6299 PPC_NONE, PPC2_ISA300),
6300 #endif
6301 #if defined(TARGET_PPC64)
6302 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6303 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6304 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6305 #endif
6306 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6307 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6308 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6309 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6310 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6311 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6312 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6313 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6314 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6315 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6316 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6317 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6318 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6319 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6320 #if defined(TARGET_PPC64)
6321 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6322 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6323 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6324 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6325 #endif
6326 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6327 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6328 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6329 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6330 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6331 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6332 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6333 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6334 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6335 #if defined(TARGET_PPC64)
6336 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6337 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6338 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6339 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6340 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6341 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6342 #endif
6343 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6344 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6345 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6346 #if defined(TARGET_PPC64)
6347 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6348 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6349 #endif
6350 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6351 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6352 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6353 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6354 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6355 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6356 #if defined(TARGET_PPC64)
6357 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6358 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6359 #endif
6360 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6361 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6362 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6363 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6364 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6365 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6366 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6367 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6368 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6369 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6370 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6371 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6372 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6373 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6374 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6375 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6376 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6377 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6378 #if defined(TARGET_PPC64)
6379 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6380 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6381 PPC_SEGMENT_64B),
6382 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6383 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6384 PPC_SEGMENT_64B),
6385 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6386 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6387 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6388 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6389 #endif
6390 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6391 /* XXX Those instructions will need to be handled differently for
6392 * different ISA versions */
6393 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6394 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6395 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6396 #if defined(TARGET_PPC64)
6397 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6398 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6399 #endif
6400 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6401 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6402 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6403 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6404 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6405 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6406 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6407 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6408 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6409 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6410 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6411 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6412 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6413 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6414 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6415 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6416 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6417 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6418 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6419 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6420 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6421 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6422 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6423 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6424 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6425 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6426 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6427 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6428 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6429 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6430 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6431 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6432 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6433 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6434 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6435 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6436 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6437 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6438 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6439 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6440 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6441 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6442 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6443 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6444 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6445 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6446 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6447 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6448 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6449 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6450 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6451 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6452 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6453 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6454 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6455 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6456 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6457 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6458 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6459 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6460 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6461 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6462 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6463 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6464 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6465 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6466 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6467 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6468 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6469 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6470 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6471 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6472 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6473 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6474 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6475 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6476 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6477 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6478 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6479 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6480 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6481 PPC_NONE, PPC2_BOOKE206),
6482 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6483 PPC_NONE, PPC2_BOOKE206),
6484 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6485 PPC_NONE, PPC2_BOOKE206),
6486 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6487 PPC_NONE, PPC2_BOOKE206),
6488 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6489 PPC_NONE, PPC2_BOOKE206),
6490 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6491 PPC_NONE, PPC2_PRCNTL),
6492 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6493 PPC_NONE, PPC2_PRCNTL),
6494 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6495 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6496 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6497 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6498 PPC_BOOKE, PPC2_BOOKE206),
6499 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6500 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6501 PPC_BOOKE, PPC2_BOOKE206),
6502 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6503 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6504 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6505 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6506 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6507 #if defined(TARGET_PPC64)
6508 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6509 PPC2_ISA300),
6510 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6511 #endif
6512
6513 #undef GEN_INT_ARITH_ADD
6514 #undef GEN_INT_ARITH_ADD_CONST
6515 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6516 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6517 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6518 add_ca, compute_ca, compute_ov) \
6519 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6520 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6521 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6522 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6523 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6524 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6525 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6526 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6527 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6528 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6529 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6530
6531 #undef GEN_INT_ARITH_DIVW
6532 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6533 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6534 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6535 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6536 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6537 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6538 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6539 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6540 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6541 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6542 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6543 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6544
6545 #if defined(TARGET_PPC64)
6546 #undef GEN_INT_ARITH_DIVD
6547 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6548 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6549 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6550 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6551 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6552 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6553
6554 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6555 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6556 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6557 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6558 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6559 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6560
6561 #undef GEN_INT_ARITH_MUL_HELPER
6562 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6563 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6564 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6565 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6566 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6567 #endif
6568
6569 #undef GEN_INT_ARITH_SUBF
6570 #undef GEN_INT_ARITH_SUBF_CONST
6571 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6572 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6573 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6574 add_ca, compute_ca, compute_ov) \
6575 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6576 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6577 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6578 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6579 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6580 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6581 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6582 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6583 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6584 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6585 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6586
6587 #undef GEN_LOGICAL1
6588 #undef GEN_LOGICAL2
6589 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6590 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6591 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6592 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6593 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6594 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6595 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6596 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6597 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6598 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6599 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6600 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6601 #if defined(TARGET_PPC64)
6602 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6603 #endif
6604
6605 #if defined(TARGET_PPC64)
6606 #undef GEN_PPC64_R2
6607 #undef GEN_PPC64_R4
6608 #define GEN_PPC64_R2(name, opc1, opc2) \
6609 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6610 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6611 PPC_64B)
6612 #define GEN_PPC64_R4(name, opc1, opc2) \
6613 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6614 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6615 PPC_64B), \
6616 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6617 PPC_64B), \
6618 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6619 PPC_64B)
6620 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6621 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6622 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6623 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6624 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6625 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6626 #endif
6627
6628 #undef GEN_LD
6629 #undef GEN_LDU
6630 #undef GEN_LDUX
6631 #undef GEN_LDX_E
6632 #undef GEN_LDS
6633 #define GEN_LD(name, ldop, opc, type) \
6634 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6635 #define GEN_LDU(name, ldop, opc, type) \
6636 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6637 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6638 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6639 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6640 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6641 #define GEN_LDS(name, ldop, op, type) \
6642 GEN_LD(name, ldop, op | 0x20, type) \
6643 GEN_LDU(name, ldop, op | 0x21, type) \
6644 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6645 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6646
6647 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6648 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6649 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6650 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6651 #if defined(TARGET_PPC64)
6652 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6653 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6654 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6655 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6656 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6657
6658 /* HV/P7 and later only */
6659 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6660 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6661 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6662 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6663 #endif
6664 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6665 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6666
6667 #undef GEN_ST
6668 #undef GEN_STU
6669 #undef GEN_STUX
6670 #undef GEN_STX_E
6671 #undef GEN_STS
6672 #define GEN_ST(name, stop, opc, type) \
6673 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6674 #define GEN_STU(name, stop, opc, type) \
6675 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6676 #define GEN_STUX(name, stop, opc2, opc3, type) \
6677 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6678 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6679 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6680 #define GEN_STS(name, stop, op, type) \
6681 GEN_ST(name, stop, op | 0x20, type) \
6682 GEN_STU(name, stop, op | 0x21, type) \
6683 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6684 GEN_STX(name, stop, 0x17, op | 0x00, type)
6685
6686 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6687 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6688 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6689 #if defined(TARGET_PPC64)
6690 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6691 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6692 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6693 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6694 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6695 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6696 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6697 #endif
6698 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6699 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6700
6701 #undef GEN_CRLOGIC
6702 #define GEN_CRLOGIC(name, tcg_op, opc) \
6703 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6704 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6705 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6706 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6707 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6708 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6709 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6710 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6711 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6712
6713 #undef GEN_MAC_HANDLER
6714 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6715 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6716 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6717 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6718 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6719 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6720 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6721 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6722 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6723 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6724 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6725 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6726 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6727 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6728 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6729 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6730 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6731 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6732 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6733 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6734 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6735 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6736 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6737 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6738 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6739 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6740 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6741 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6742 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6743 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6744 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6745 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6746 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6747 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6748 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6749 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6750 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6751 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6752 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6753 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6754 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6755 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6756 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6757 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6758
6759 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6760 PPC_NONE, PPC2_TM),
6761 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6762 PPC_NONE, PPC2_TM),
6763 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6764 PPC_NONE, PPC2_TM),
6765 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6766 PPC_NONE, PPC2_TM),
6767 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6768 PPC_NONE, PPC2_TM),
6769 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6770 PPC_NONE, PPC2_TM),
6771 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6772 PPC_NONE, PPC2_TM),
6773 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6774 PPC_NONE, PPC2_TM),
6775 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6776 PPC_NONE, PPC2_TM),
6777 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6778 PPC_NONE, PPC2_TM),
6779 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6780 PPC_NONE, PPC2_TM),
6781
6782 #include "translate/fp-ops.inc.c"
6783
6784 #include "translate/vmx-ops.inc.c"
6785
6786 #include "translate/vsx-ops.inc.c"
6787
6788 #include "translate/dfp-ops.inc.c"
6789
6790 #include "translate/spe-ops.inc.c"
6791 };
6792
6793 #include "helper_regs.h"
6794 #include "translate_init.c"
6795
6796 /*****************************************************************************/
6797 /* Misc PowerPC helpers */
6798 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6799 int flags)
6800 {
6801 #define RGPL 4
6802 #define RFPL 4
6803
6804 PowerPCCPU *cpu = POWERPC_CPU(cs);
6805 CPUPPCState *env = &cpu->env;
6806 int i;
6807
6808 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6809 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6810 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6811 cs->cpu_index);
6812 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6813 TARGET_FMT_lx " iidx %d didx %d\n",
6814 env->msr, env->spr[SPR_HID0],
6815 env->hflags, env->immu_idx, env->dmmu_idx);
6816 #if !defined(NO_TIMER_DUMP)
6817 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6818 #if !defined(CONFIG_USER_ONLY)
6819 " DECR %08" PRIu32
6820 #endif
6821 "\n",
6822 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6823 #if !defined(CONFIG_USER_ONLY)
6824 , cpu_ppc_load_decr(env)
6825 #endif
6826 );
6827 #endif
6828 for (i = 0; i < 32; i++) {
6829 if ((i & (RGPL - 1)) == 0)
6830 cpu_fprintf(f, "GPR%02d", i);
6831 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6832 if ((i & (RGPL - 1)) == (RGPL - 1))
6833 cpu_fprintf(f, "\n");
6834 }
6835 cpu_fprintf(f, "CR ");
6836 for (i = 0; i < 8; i++)
6837 cpu_fprintf(f, "%01x", env->crf[i]);
6838 cpu_fprintf(f, " [");
6839 for (i = 0; i < 8; i++) {
6840 char a = '-';
6841 if (env->crf[i] & 0x08)
6842 a = 'L';
6843 else if (env->crf[i] & 0x04)
6844 a = 'G';
6845 else if (env->crf[i] & 0x02)
6846 a = 'E';
6847 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6848 }
6849 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6850 env->reserve_addr);
6851 for (i = 0; i < 32; i++) {
6852 if ((i & (RFPL - 1)) == 0)
6853 cpu_fprintf(f, "FPR%02d", i);
6854 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6855 if ((i & (RFPL - 1)) == (RFPL - 1))
6856 cpu_fprintf(f, "\n");
6857 }
6858 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6859 #if !defined(CONFIG_USER_ONLY)
6860 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6861 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6862 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6863 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6864
6865 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6866 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6867 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6868 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6869
6870 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6871 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6872 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6873 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6874
6875 #if defined(TARGET_PPC64)
6876 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6877 env->excp_model == POWERPC_EXCP_POWER8) {
6878 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6879 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6880 }
6881 #endif
6882 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6883 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6884 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6885 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6886 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6887
6888 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6889 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6890 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6891 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6892
6893 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6894 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6895 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6896 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6897
6898 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6899 " EPR " TARGET_FMT_lx "\n",
6900 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6901 env->spr[SPR_BOOKE_EPR]);
6902
6903 /* FSL-specific */
6904 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6905 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6906 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6907 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6908
6909 /*
6910 * IVORs are left out as they are large and do not change often --
6911 * they can be read with "p $ivor0", "p $ivor1", etc.
6912 */
6913 }
6914
6915 #if defined(TARGET_PPC64)
6916 if (env->flags & POWERPC_FLAG_CFAR) {
6917 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6918 }
6919 #endif
6920
6921 switch (env->mmu_model) {
6922 case POWERPC_MMU_32B:
6923 case POWERPC_MMU_601:
6924 case POWERPC_MMU_SOFT_6xx:
6925 case POWERPC_MMU_SOFT_74xx:
6926 #if defined(TARGET_PPC64)
6927 case POWERPC_MMU_64B:
6928 case POWERPC_MMU_2_03:
6929 case POWERPC_MMU_2_06:
6930 case POWERPC_MMU_2_06a:
6931 case POWERPC_MMU_2_07:
6932 case POWERPC_MMU_2_07a:
6933 #endif
6934 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6935 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6936 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6937 break;
6938 case POWERPC_MMU_BOOKE206:
6939 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6940 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6941 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6942 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6943
6944 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6945 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6946 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6947 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6948
6949 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6950 " TLB1CFG " TARGET_FMT_lx "\n",
6951 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6952 env->spr[SPR_BOOKE_TLB1CFG]);
6953 break;
6954 default:
6955 break;
6956 }
6957 #endif
6958
6959 #undef RGPL
6960 #undef RFPL
6961 }
6962
6963 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6964 fprintf_function cpu_fprintf, int flags)
6965 {
6966 #if defined(DO_PPC_STATISTICS)
6967 PowerPCCPU *cpu = POWERPC_CPU(cs);
6968 opc_handler_t **t1, **t2, **t3, *handler;
6969 int op1, op2, op3;
6970
6971 t1 = cpu->env.opcodes;
6972 for (op1 = 0; op1 < 64; op1++) {
6973 handler = t1[op1];
6974 if (is_indirect_opcode(handler)) {
6975 t2 = ind_table(handler);
6976 for (op2 = 0; op2 < 32; op2++) {
6977 handler = t2[op2];
6978 if (is_indirect_opcode(handler)) {
6979 t3 = ind_table(handler);
6980 for (op3 = 0; op3 < 32; op3++) {
6981 handler = t3[op3];
6982 if (handler->count == 0)
6983 continue;
6984 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6985 "%016" PRIx64 " %" PRId64 "\n",
6986 op1, op2, op3, op1, (op3 << 5) | op2,
6987 handler->oname,
6988 handler->count, handler->count);
6989 }
6990 } else {
6991 if (handler->count == 0)
6992 continue;
6993 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6994 "%016" PRIx64 " %" PRId64 "\n",
6995 op1, op2, op1, op2, handler->oname,
6996 handler->count, handler->count);
6997 }
6998 }
6999 } else {
7000 if (handler->count == 0)
7001 continue;
7002 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7003 " %" PRId64 "\n",
7004 op1, op1, handler->oname,
7005 handler->count, handler->count);
7006 }
7007 }
7008 #endif
7009 }
7010
7011 /*****************************************************************************/
7012 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
7013 {
7014 PowerPCCPU *cpu = ppc_env_get_cpu(env);
7015 CPUState *cs = CPU(cpu);
7016 DisasContext ctx, *ctxp = &ctx;
7017 opc_handler_t **table, *handler;
7018 target_ulong pc_start;
7019 int num_insns;
7020 int max_insns;
7021
7022 pc_start = tb->pc;
7023 ctx.nip = pc_start;
7024 ctx.tb = tb;
7025 ctx.exception = POWERPC_EXCP_NONE;
7026 ctx.spr_cb = env->spr_cb;
7027 ctx.pr = msr_pr;
7028 ctx.mem_idx = env->dmmu_idx;
7029 ctx.dr = msr_dr;
7030 #if !defined(CONFIG_USER_ONLY)
7031 ctx.hv = msr_hv || !env->has_hv_mode;
7032 #endif
7033 ctx.insns_flags = env->insns_flags;
7034 ctx.insns_flags2 = env->insns_flags2;
7035 ctx.access_type = -1;
7036 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7037 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
7038 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
7039 #if defined(TARGET_PPC64)
7040 ctx.sf_mode = msr_is_64bit(env, env->msr);
7041 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7042 #endif
7043 if (env->mmu_model == POWERPC_MMU_32B ||
7044 env->mmu_model == POWERPC_MMU_601 ||
7045 (env->mmu_model & POWERPC_MMU_64B))
7046 ctx.lazy_tlb_flush = true;
7047
7048 ctx.fpu_enabled = !!msr_fp;
7049 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7050 ctx.spe_enabled = !!msr_spe;
7051 else
7052 ctx.spe_enabled = false;
7053 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7054 ctx.altivec_enabled = !!msr_vr;
7055 else
7056 ctx.altivec_enabled = false;
7057 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7058 ctx.vsx_enabled = !!msr_vsx;
7059 } else {
7060 ctx.vsx_enabled = false;
7061 }
7062 #if defined(TARGET_PPC64)
7063 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7064 ctx.tm_enabled = !!msr_tm;
7065 } else {
7066 ctx.tm_enabled = false;
7067 }
7068 #endif
7069 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7070 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7071 else
7072 ctx.singlestep_enabled = 0;
7073 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7074 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7075 if (unlikely(cs->singlestep_enabled)) {
7076 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7077 }
7078 #if defined (DO_SINGLE_STEP) && 0
7079 /* Single step trace mode */
7080 msr_se = 1;
7081 #endif
7082 num_insns = 0;
7083 max_insns = tb->cflags & CF_COUNT_MASK;
7084 if (max_insns == 0) {
7085 max_insns = CF_COUNT_MASK;
7086 }
7087 if (max_insns > TCG_MAX_INSNS) {
7088 max_insns = TCG_MAX_INSNS;
7089 }
7090
7091 gen_tb_start(tb);
7092 tcg_clear_temp_count();
7093 /* Set env in case of segfault during code fetch */
7094 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7095 tcg_gen_insn_start(ctx.nip);
7096 num_insns++;
7097
7098 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7099 gen_debug_exception(ctxp);
7100 /* The address covered by the breakpoint must be included in
7101 [tb->pc, tb->pc + tb->size) in order to for it to be
7102 properly cleared -- thus we increment the PC here so that
7103 the logic setting tb->size below does the right thing. */
7104 ctx.nip += 4;
7105 break;
7106 }
7107
7108 LOG_DISAS("----------------\n");
7109 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7110 ctx.nip, ctx.mem_idx, (int)msr_ir);
7111 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7112 gen_io_start();
7113 if (unlikely(need_byteswap(&ctx))) {
7114 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7115 } else {
7116 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7117 }
7118 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7119 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7120 opc3(ctx.opcode), opc4(ctx.opcode),
7121 ctx.le_mode ? "little" : "big");
7122 ctx.nip += 4;
7123 table = env->opcodes;
7124 handler = table[opc1(ctx.opcode)];
7125 if (is_indirect_opcode(handler)) {
7126 table = ind_table(handler);
7127 handler = table[opc2(ctx.opcode)];
7128 if (is_indirect_opcode(handler)) {
7129 table = ind_table(handler);
7130 handler = table[opc3(ctx.opcode)];
7131 if (is_indirect_opcode(handler)) {
7132 table = ind_table(handler);
7133 handler = table[opc4(ctx.opcode)];
7134 }
7135 }
7136 }
7137 /* Is opcode *REALLY* valid ? */
7138 if (unlikely(handler->handler == &gen_invalid)) {
7139 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7140 "%02x - %02x - %02x - %02x (%08x) "
7141 TARGET_FMT_lx " %d\n",
7142 opc1(ctx.opcode), opc2(ctx.opcode),
7143 opc3(ctx.opcode), opc4(ctx.opcode),
7144 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7145 } else {
7146 uint32_t inval;
7147
7148 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7149 inval = handler->inval2;
7150 } else {
7151 inval = handler->inval1;
7152 }
7153
7154 if (unlikely((ctx.opcode & inval) != 0)) {
7155 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7156 "%02x - %02x - %02x - %02x (%08x) "
7157 TARGET_FMT_lx "\n", ctx.opcode & inval,
7158 opc1(ctx.opcode), opc2(ctx.opcode),
7159 opc3(ctx.opcode), opc4(ctx.opcode),
7160 ctx.opcode, ctx.nip - 4);
7161 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7162 break;
7163 }
7164 }
7165 (*(handler->handler))(&ctx);
7166 #if defined(DO_PPC_STATISTICS)
7167 handler->count++;
7168 #endif
7169 /* Check trace mode exceptions */
7170 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7171 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7172 ctx.exception != POWERPC_SYSCALL &&
7173 ctx.exception != POWERPC_EXCP_TRAP &&
7174 ctx.exception != POWERPC_EXCP_BRANCH)) {
7175 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7176 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7177 (cs->singlestep_enabled) ||
7178 singlestep ||
7179 num_insns >= max_insns)) {
7180 /* if we reach a page boundary or are single stepping, stop
7181 * generation
7182 */
7183 break;
7184 }
7185 if (tcg_check_temp_count()) {
7186 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7187 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7188 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7189 exit(1);
7190 }
7191 }
7192 if (tb->cflags & CF_LAST_IO)
7193 gen_io_end();
7194 if (ctx.exception == POWERPC_EXCP_NONE) {
7195 gen_goto_tb(&ctx, 0, ctx.nip);
7196 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7197 if (unlikely(cs->singlestep_enabled)) {
7198 gen_debug_exception(ctxp);
7199 }
7200 /* Generate the return instruction */
7201 tcg_gen_exit_tb(0);
7202 }
7203 gen_tb_end(tb, num_insns);
7204
7205 tb->size = ctx.nip - pc_start;
7206 tb->icount = num_insns;
7207
7208 #if defined(DEBUG_DISAS)
7209 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7210 && qemu_log_in_addr_range(pc_start)) {
7211 int flags;
7212 flags = env->bfd_mach;
7213 flags |= ctx.le_mode << 16;
7214 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7215 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7216 qemu_log("\n");
7217 }
7218 #endif
7219 }
7220
7221 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7222 target_ulong *data)
7223 {
7224 env->nip = data[0];
7225 }
QEmu