char: rename CHR_EVENT_RESET to CHR_EVENT_OPENED
[qemu.git] / hw / hpet_emul.h
blobcfd95b4ad47c18f027c931d13ca971291a7ab4e3
1 /*
2 * QEMU Emulated HPET support
4 * Copyright IBM, Corp. 2008
6 * Authors:
7 * Beth Kon <bkon@us.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #ifndef QEMU_HPET_EMUL_H
14 #define QEMU_HPET_EMUL_H
16 #define HPET_BASE 0xfed00000
17 #define HPET_CLK_PERIOD 10000000ULL /* 10000000 femtoseconds == 10ns*/
19 #define FS_PER_NS 1000000
20 #define HPET_NUM_TIMERS 3
21 #define HPET_TIMER_TYPE_LEVEL 0x002
23 #define HPET_CFG_ENABLE 0x001
24 #define HPET_CFG_LEGACY 0x002
26 #define HPET_ID 0x000
27 #define HPET_PERIOD 0x004
28 #define HPET_CFG 0x010
29 #define HPET_STATUS 0x020
30 #define HPET_COUNTER 0x0f0
31 #define HPET_TN_CFG 0x000
32 #define HPET_TN_CMP 0x008
33 #define HPET_TN_ROUTE 0x010
34 #define HPET_CFG_WRITE_MASK 0x3
37 #define HPET_TN_ENABLE 0x004
38 #define HPET_TN_PERIODIC 0x008
39 #define HPET_TN_PERIODIC_CAP 0x010
40 #define HPET_TN_SIZE_CAP 0x020
41 #define HPET_TN_SETVAL 0x040
42 #define HPET_TN_32BIT 0x100
43 #define HPET_TN_INT_ROUTE_MASK 0x3e00
44 #define HPET_TN_CFG_WRITE_MASK 0x3f4e
45 #define HPET_TN_INT_ROUTE_SHIFT 9
46 #define HPET_TN_INT_ROUTE_CAP_SHIFT 32
47 #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
49 struct HPETState;
50 typedef struct HPETTimer { /* timers */
51 uint8_t tn; /*timer number*/
52 QEMUTimer *qemu_timer;
53 struct HPETState *state;
54 /* Memory-mapped, software visible timer registers */
55 uint64_t config; /* configuration/cap */
56 uint64_t cmp; /* comparator */
57 uint64_t fsb; /* FSB route, not supported now */
58 /* Hidden register state */
59 uint64_t period; /* Last value written to comparator */
60 uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
61 * mode. Next pop will be actual timer expiration.
63 } HPETTimer;
65 typedef struct HPETState {
66 uint64_t hpet_offset;
67 qemu_irq *irqs;
68 HPETTimer timer[HPET_NUM_TIMERS];
70 /* Memory-mapped, software visible registers */
71 uint64_t capability; /* capabilities */
72 uint64_t config; /* configuration */
73 uint64_t isr; /* interrupt status reg */
74 uint64_t hpet_counter; /* main counter */
75 } HPETState;
77 #if defined TARGET_I386
78 extern uint32_t hpet_in_legacy_mode(void);
79 extern void hpet_init(qemu_irq *irq);
80 #endif
82 #endif