2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #define TARGET_LONG_BITS 32
32 #define ELF_MACHINE EM_XTENSA
34 #define CPUState struct CPUXtensaState
37 #include "qemu-common.h"
40 #define TARGET_HAS_ICE 1
42 #define NB_MMU_MODES 4
44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
46 #define TARGET_PAGE_BITS 12
49 /* Additional instructions */
50 XTENSA_OPTION_CODE_DENSITY
,
52 XTENSA_OPTION_EXTENDED_L32R
,
53 XTENSA_OPTION_16_BIT_IMUL
,
54 XTENSA_OPTION_32_BIT_IMUL
,
55 XTENSA_OPTION_32_BIT_IDIV
,
57 XTENSA_OPTION_MISC_OP
,
58 XTENSA_OPTION_COPROCESSOR
,
59 XTENSA_OPTION_BOOLEAN
,
60 XTENSA_OPTION_FP_COPROCESSOR
,
61 XTENSA_OPTION_MP_SYNCHRO
,
62 XTENSA_OPTION_CONDITIONAL_STORE
,
64 /* Interrupts and exceptions */
65 XTENSA_OPTION_EXCEPTION
,
66 XTENSA_OPTION_RELOCATABLE_VECTOR
,
67 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
68 XTENSA_OPTION_INTERRUPT
,
69 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
70 XTENSA_OPTION_TIMER_INTERRUPT
,
74 XTENSA_OPTION_ICACHE_TEST
,
75 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
77 XTENSA_OPTION_DCACHE_TEST
,
78 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
84 XTENSA_OPTION_HW_ALIGNMENT
,
85 XTENSA_OPTION_MEMORY_ECC_PARITY
,
87 /* Memory protection and translation */
88 XTENSA_OPTION_REGION_PROTECTION
,
89 XTENSA_OPTION_REGION_TRANSLATION
,
93 XTENSA_OPTION_WINDOWED_REGISTER
,
94 XTENSA_OPTION_PROCESSOR_INTERFACE
,
95 XTENSA_OPTION_MISC_SR
,
96 XTENSA_OPTION_THREAD_POINTER
,
97 XTENSA_OPTION_PROCESSOR_ID
,
99 XTENSA_OPTION_TRACE_PORT
,
138 #define PS_INTLEVEL 0xf
139 #define PS_INTLEVEL_SHIFT 0
145 #define PS_RING_SHIFT 6
148 #define PS_OWB_SHIFT 8
150 #define PS_CALLINC 0x30000
151 #define PS_CALLINC_SHIFT 16
152 #define PS_CALLINC_LEN 2
154 #define PS_WOE 0x40000
157 #define MAX_NINTERRUPT 32
160 #define MAX_NCCOMPARE 3
161 #define MAX_TLB_WAY_SIZE 8
163 #define REGION_PAGE_MASK 0xe0000000
170 /* Dynamic vectors */
171 EXC_WINDOW_OVERFLOW4
,
172 EXC_WINDOW_UNDERFLOW4
,
173 EXC_WINDOW_OVERFLOW8
,
174 EXC_WINDOW_UNDERFLOW8
,
175 EXC_WINDOW_OVERFLOW12
,
176 EXC_WINDOW_UNDERFLOW12
,
185 ILLEGAL_INSTRUCTION_CAUSE
= 0,
187 INSTRUCTION_FETCH_ERROR_CAUSE
,
188 LOAD_STORE_ERROR_CAUSE
,
189 LEVEL1_INTERRUPT_CAUSE
,
191 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
192 PRIVILEGED_CAUSE
= 8,
193 LOAD_STORE_ALIGNMENT_CAUSE
,
195 INSTR_PIF_DATA_ERROR_CAUSE
= 12,
196 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
197 INSTR_PIF_ADDR_ERROR_CAUSE
,
198 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
201 INST_TLB_MULTI_HIT_CAUSE
,
202 INST_FETCH_PRIVILEGE_CAUSE
,
203 INST_FETCH_PROHIBITED_CAUSE
= 20,
204 LOAD_STORE_TLB_MISS_CAUSE
= 24,
205 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
206 LOAD_STORE_PRIVILEGE_CAUSE
,
207 LOAD_PROHIBITED_CAUSE
= 28,
208 STORE_PROHIBITED_CAUSE
,
210 COPROCESSOR0_DISABLED
= 32,
224 typedef struct xtensa_tlb_entry
{
232 typedef struct xtensa_tlb
{
234 const unsigned way_size
[10];
236 unsigned nrefillentries
;
239 typedef struct XtensaGdbReg
{
245 typedef struct XtensaGdbRegmap
{
248 /* PC + a + ar + sr + ur */
249 XtensaGdbReg reg
[1 + 16 + 64 + 256 + 256];
252 typedef struct XtensaConfig
{
255 XtensaGdbRegmap gdb_regmap
;
260 uint32_t exception_vector
[EXC_MAX
];
263 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
264 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
265 uint32_t inttype_mask
[INTTYPE_MAX
];
268 interrupt_type inttype
;
269 } interrupt
[MAX_NINTERRUPT
];
271 uint32_t timerint
[MAX_NCCOMPARE
];
272 uint32_t clock_freq_khz
;
278 typedef struct CPUXtensaState
{
279 const XtensaConfig
*config
;
284 uint32_t phys_regs
[MAX_NAREG
];
286 xtensa_tlb_entry itlb
[7][MAX_TLB_WAY_SIZE
];
287 xtensa_tlb_entry dtlb
[10][MAX_TLB_WAY_SIZE
];
288 unsigned autorefill_idx
;
290 int pending_irq_level
; /* level of last raised IRQ */
292 QEMUTimer
*ccompare_timer
;
293 uint32_t wake_ccount
;
301 #define cpu_init cpu_xtensa_init
302 #define cpu_exec cpu_xtensa_exec
303 #define cpu_gen_code cpu_xtensa_gen_code
304 #define cpu_signal_handler cpu_xtensa_signal_handler
305 #define cpu_list xtensa_cpu_list
307 CPUXtensaState
*cpu_xtensa_init(const char *cpu_model
);
308 void xtensa_translate_init(void);
309 int cpu_xtensa_exec(CPUXtensaState
*s
);
310 void do_interrupt(CPUXtensaState
*s
);
311 void check_interrupts(CPUXtensaState
*s
);
312 void xtensa_irq_init(CPUState
*env
);
313 void xtensa_advance_ccount(CPUState
*env
, uint32_t d
);
314 void xtensa_timer_irq(CPUState
*env
, uint32_t id
, uint32_t active
);
315 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
316 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
317 void xtensa_sync_window_from_phys(CPUState
*env
);
318 void xtensa_sync_phys_from_window(CPUState
*env
);
319 uint32_t xtensa_tlb_get_addr_mask(const CPUState
*env
, bool dtlb
, uint32_t way
);
320 void split_tlb_entry_spec_way(const CPUState
*env
, uint32_t v
, bool dtlb
,
321 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
);
322 int xtensa_tlb_lookup(const CPUState
*env
, uint32_t addr
, bool dtlb
,
323 uint32_t *pwi
, uint32_t *pei
, uint8_t *pring
);
324 void xtensa_tlb_set_entry(CPUState
*env
, bool dtlb
,
325 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
326 int xtensa_get_physical_addr(CPUState
*env
,
327 uint32_t vaddr
, int is_write
, int mmu_idx
,
328 uint32_t *paddr
, uint32_t *page_size
, unsigned *access
);
331 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
333 static inline bool xtensa_option_bits_enabled(const XtensaConfig
*config
,
336 return (config
->options
& opt
) != 0;
339 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
341 return xtensa_option_bits_enabled(config
, XTENSA_OPTION_BIT(opt
));
344 static inline int xtensa_get_cintlevel(const CPUState
*env
)
346 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
347 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
348 level
= env
->config
->excm_level
;
353 static inline int xtensa_get_ring(const CPUState
*env
)
355 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
356 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
362 static inline int xtensa_get_cring(const CPUState
*env
)
364 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
365 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
366 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
372 static inline xtensa_tlb_entry
*xtensa_tlb_get_entry(CPUState
*env
,
373 bool dtlb
, unsigned wi
, unsigned ei
)
380 /* MMU modes definitions */
381 #define MMU_MODE0_SUFFIX _ring0
382 #define MMU_MODE1_SUFFIX _ring1
383 #define MMU_MODE2_SUFFIX _ring2
384 #define MMU_MODE3_SUFFIX _ring3
386 static inline int cpu_mmu_index(CPUState
*env
)
388 return xtensa_get_cring(env
);
391 #define XTENSA_TBFLAG_RING_MASK 0x3
392 #define XTENSA_TBFLAG_EXCM 0x4
393 #define XTENSA_TBFLAG_LITBASE 0x8
395 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
396 target_ulong
*cs_base
, int *flags
)
401 *flags
|= xtensa_get_ring(env
);
402 if (env
->sregs
[PS
] & PS_EXCM
) {
403 *flags
|= XTENSA_TBFLAG_EXCM
;
405 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
406 (env
->sregs
[LITBASE
] & 1)) {
407 *flags
|= XTENSA_TBFLAG_LITBASE
;
412 #include "exec-all.h"
414 static inline int cpu_has_work(CPUState
*env
)
416 return env
->pending_irq_level
;
419 static inline void cpu_pc_from_tb(CPUState
*env
, TranslationBlock
*tb
)