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xhci: Fix remainder field for TR_SETUP completion event.
[qemu.git] / hw / usb / hcd-xhci.c
blob37c14938a7afcac9de249f1025b8cdb78badefc0
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "qemu/osdep.h"
22 #include "hw/hw.h"
23 #include "qemu/timer.h"
24 #include "hw/usb.h"
25 #include "hw/pci/pci.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/msix.h"
28 #include "trace.h"
29 #include "qapi/error.h"
30
31 //#define DEBUG_XHCI
32 //#define DEBUG_DATA
33
34 #ifdef DEBUG_XHCI
35 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
36 #else
37 #define DPRINTF(...) do {} while (0)
38 #endif
39 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
40 __func__, __LINE__, _msg); abort(); } while (0)
41
42 #define MAXPORTS_2 15
43 #define MAXPORTS_3 15
44
45 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
46 #define MAXSLOTS 64
47 #define MAXINTRS 16
48
49 #define TD_QUEUE 24
50
51 /* Very pessimistic, let's hope it's enough for all cases */
52 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
53 /* Do not deliver ER Full events. NEC's driver does some things not bound
54 * to the specs when it gets them */
55 #define ER_FULL_HACK
56
57 #define LEN_CAP 0x40
58 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
59 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
60 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
61
62 #define OFF_OPER LEN_CAP
63 #define OFF_RUNTIME 0x1000
64 #define OFF_DOORBELL 0x2000
65 #define OFF_MSIX_TABLE 0x3000
66 #define OFF_MSIX_PBA 0x3800
67 /* must be power of 2 */
68 #define LEN_REGS 0x4000
69
70 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
71 #error Increase OFF_RUNTIME
72 #endif
73 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
74 #error Increase OFF_DOORBELL
75 #endif
76 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
77 # error Increase LEN_REGS
78 #endif
79
80 /* bit definitions */
81 #define USBCMD_RS (1<<0)
82 #define USBCMD_HCRST (1<<1)
83 #define USBCMD_INTE (1<<2)
84 #define USBCMD_HSEE (1<<3)
85 #define USBCMD_LHCRST (1<<7)
86 #define USBCMD_CSS (1<<8)
87 #define USBCMD_CRS (1<<9)
88 #define USBCMD_EWE (1<<10)
89 #define USBCMD_EU3S (1<<11)
90
91 #define USBSTS_HCH (1<<0)
92 #define USBSTS_HSE (1<<2)
93 #define USBSTS_EINT (1<<3)
94 #define USBSTS_PCD (1<<4)
95 #define USBSTS_SSS (1<<8)
96 #define USBSTS_RSS (1<<9)
97 #define USBSTS_SRE (1<<10)
98 #define USBSTS_CNR (1<<11)
99 #define USBSTS_HCE (1<<12)
100
101
102 #define PORTSC_CCS (1<<0)
103 #define PORTSC_PED (1<<1)
104 #define PORTSC_OCA (1<<3)
105 #define PORTSC_PR (1<<4)
106 #define PORTSC_PLS_SHIFT 5
107 #define PORTSC_PLS_MASK 0xf
108 #define PORTSC_PP (1<<9)
109 #define PORTSC_SPEED_SHIFT 10
110 #define PORTSC_SPEED_MASK 0xf
111 #define PORTSC_SPEED_FULL (1<<10)
112 #define PORTSC_SPEED_LOW (2<<10)
113 #define PORTSC_SPEED_HIGH (3<<10)
114 #define PORTSC_SPEED_SUPER (4<<10)
115 #define PORTSC_PIC_SHIFT 14
116 #define PORTSC_PIC_MASK 0x3
117 #define PORTSC_LWS (1<<16)
118 #define PORTSC_CSC (1<<17)
119 #define PORTSC_PEC (1<<18)
120 #define PORTSC_WRC (1<<19)
121 #define PORTSC_OCC (1<<20)
122 #define PORTSC_PRC (1<<21)
123 #define PORTSC_PLC (1<<22)
124 #define PORTSC_CEC (1<<23)
125 #define PORTSC_CAS (1<<24)
126 #define PORTSC_WCE (1<<25)
127 #define PORTSC_WDE (1<<26)
128 #define PORTSC_WOE (1<<27)
129 #define PORTSC_DR (1<<30)
130 #define PORTSC_WPR (1<<31)
131
132 #define CRCR_RCS (1<<0)
133 #define CRCR_CS (1<<1)
134 #define CRCR_CA (1<<2)
135 #define CRCR_CRR (1<<3)
136
137 #define IMAN_IP (1<<0)
138 #define IMAN_IE (1<<1)
139
140 #define ERDP_EHB (1<<3)
141
142 #define TRB_SIZE 16
143 typedef struct XHCITRB {
144 uint64_t parameter;
145 uint32_t status;
146 uint32_t control;
147 dma_addr_t addr;
148 bool ccs;
149 } XHCITRB;
150
151 enum {
152 PLS_U0 = 0,
153 PLS_U1 = 1,
154 PLS_U2 = 2,
155 PLS_U3 = 3,
156 PLS_DISABLED = 4,
157 PLS_RX_DETECT = 5,
158 PLS_INACTIVE = 6,
159 PLS_POLLING = 7,
160 PLS_RECOVERY = 8,
161 PLS_HOT_RESET = 9,
162 PLS_COMPILANCE_MODE = 10,
163 PLS_TEST_MODE = 11,
164 PLS_RESUME = 15,
165 };
166
167 typedef enum TRBType {
168 TRB_RESERVED = 0,
169 TR_NORMAL,
170 TR_SETUP,
171 TR_DATA,
172 TR_STATUS,
173 TR_ISOCH,
174 TR_LINK,
175 TR_EVDATA,
176 TR_NOOP,
177 CR_ENABLE_SLOT,
178 CR_DISABLE_SLOT,
179 CR_ADDRESS_DEVICE,
180 CR_CONFIGURE_ENDPOINT,
181 CR_EVALUATE_CONTEXT,
182 CR_RESET_ENDPOINT,
183 CR_STOP_ENDPOINT,
184 CR_SET_TR_DEQUEUE,
185 CR_RESET_DEVICE,
186 CR_FORCE_EVENT,
187 CR_NEGOTIATE_BW,
188 CR_SET_LATENCY_TOLERANCE,
189 CR_GET_PORT_BANDWIDTH,
190 CR_FORCE_HEADER,
191 CR_NOOP,
192 ER_TRANSFER = 32,
193 ER_COMMAND_COMPLETE,
194 ER_PORT_STATUS_CHANGE,
195 ER_BANDWIDTH_REQUEST,
196 ER_DOORBELL,
197 ER_HOST_CONTROLLER,
198 ER_DEVICE_NOTIFICATION,
199 ER_MFINDEX_WRAP,
200 /* vendor specific bits */
201 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
202 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
203 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
204 } TRBType;
205
206 #define CR_LINK TR_LINK
207
208 typedef enum TRBCCode {
209 CC_INVALID = 0,
210 CC_SUCCESS,
211 CC_DATA_BUFFER_ERROR,
212 CC_BABBLE_DETECTED,
213 CC_USB_TRANSACTION_ERROR,
214 CC_TRB_ERROR,
215 CC_STALL_ERROR,
216 CC_RESOURCE_ERROR,
217 CC_BANDWIDTH_ERROR,
218 CC_NO_SLOTS_ERROR,
219 CC_INVALID_STREAM_TYPE_ERROR,
220 CC_SLOT_NOT_ENABLED_ERROR,
221 CC_EP_NOT_ENABLED_ERROR,
222 CC_SHORT_PACKET,
223 CC_RING_UNDERRUN,
224 CC_RING_OVERRUN,
225 CC_VF_ER_FULL,
226 CC_PARAMETER_ERROR,
227 CC_BANDWIDTH_OVERRUN,
228 CC_CONTEXT_STATE_ERROR,
229 CC_NO_PING_RESPONSE_ERROR,
230 CC_EVENT_RING_FULL_ERROR,
231 CC_INCOMPATIBLE_DEVICE_ERROR,
232 CC_MISSED_SERVICE_ERROR,
233 CC_COMMAND_RING_STOPPED,
234 CC_COMMAND_ABORTED,
235 CC_STOPPED,
236 CC_STOPPED_LENGTH_INVALID,
237 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
238 CC_ISOCH_BUFFER_OVERRUN = 31,
239 CC_EVENT_LOST_ERROR,
240 CC_UNDEFINED_ERROR,
241 CC_INVALID_STREAM_ID_ERROR,
242 CC_SECONDARY_BANDWIDTH_ERROR,
243 CC_SPLIT_TRANSACTION_ERROR
244 } TRBCCode;
245
246 #define TRB_C (1<<0)
247 #define TRB_TYPE_SHIFT 10
248 #define TRB_TYPE_MASK 0x3f
249 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
250
251 #define TRB_EV_ED (1<<2)
252
253 #define TRB_TR_ENT (1<<1)
254 #define TRB_TR_ISP (1<<2)
255 #define TRB_TR_NS (1<<3)
256 #define TRB_TR_CH (1<<4)
257 #define TRB_TR_IOC (1<<5)
258 #define TRB_TR_IDT (1<<6)
259 #define TRB_TR_TBC_SHIFT 7
260 #define TRB_TR_TBC_MASK 0x3
261 #define TRB_TR_BEI (1<<9)
262 #define TRB_TR_TLBPC_SHIFT 16
263 #define TRB_TR_TLBPC_MASK 0xf
264 #define TRB_TR_FRAMEID_SHIFT 20
265 #define TRB_TR_FRAMEID_MASK 0x7ff
266 #define TRB_TR_SIA (1<<31)
267
268 #define TRB_TR_DIR (1<<16)
269
270 #define TRB_CR_SLOTID_SHIFT 24
271 #define TRB_CR_SLOTID_MASK 0xff
272 #define TRB_CR_EPID_SHIFT 16
273 #define TRB_CR_EPID_MASK 0x1f
274
275 #define TRB_CR_BSR (1<<9)
276 #define TRB_CR_DC (1<<9)
277
278 #define TRB_LK_TC (1<<1)
279
280 #define TRB_INTR_SHIFT 22
281 #define TRB_INTR_MASK 0x3ff
282 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
283
284 #define EP_TYPE_MASK 0x7
285 #define EP_TYPE_SHIFT 3
286
287 #define EP_STATE_MASK 0x7
288 #define EP_DISABLED (0<<0)
289 #define EP_RUNNING (1<<0)
290 #define EP_HALTED (2<<0)
291 #define EP_STOPPED (3<<0)
292 #define EP_ERROR (4<<0)
293
294 #define SLOT_STATE_MASK 0x1f
295 #define SLOT_STATE_SHIFT 27
296 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
297 #define SLOT_ENABLED 0
298 #define SLOT_DEFAULT 1
299 #define SLOT_ADDRESSED 2
300 #define SLOT_CONFIGURED 3
301
302 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
303 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
304
305 typedef struct XHCIState XHCIState;
306 typedef struct XHCIStreamContext XHCIStreamContext;
307 typedef struct XHCIEPContext XHCIEPContext;
308
309 #define get_field(data, field) \
310 (((data) >> field##_SHIFT) & field##_MASK)
311
312 #define set_field(data, newval, field) do { \
313 uint32_t val = *data; \
314 val &= ~(field##_MASK << field##_SHIFT); \
315 val |= ((newval) & field##_MASK) << field##_SHIFT; \
316 *data = val; \
317 } while (0)
318
319 typedef enum EPType {
320 ET_INVALID = 0,
321 ET_ISO_OUT,
322 ET_BULK_OUT,
323 ET_INTR_OUT,
324 ET_CONTROL,
325 ET_ISO_IN,
326 ET_BULK_IN,
327 ET_INTR_IN,
328 } EPType;
329
330 typedef struct XHCIRing {
331 dma_addr_t dequeue;
332 bool ccs;
333 } XHCIRing;
334
335 typedef struct XHCIPort {
336 XHCIState *xhci;
337 uint32_t portsc;
338 uint32_t portnr;
339 USBPort *uport;
340 uint32_t speedmask;
341 char name[16];
342 MemoryRegion mem;
343 } XHCIPort;
344
345 typedef struct XHCITransfer {
346 XHCIState *xhci;
347 USBPacket packet;
348 QEMUSGList sgl;
349 bool running_async;
350 bool running_retry;
351 bool complete;
352 bool int_req;
353 unsigned int iso_pkts;
354 unsigned int slotid;
355 unsigned int epid;
356 unsigned int streamid;
357 bool in_xfer;
358 bool iso_xfer;
359 bool timed_xfer;
360
361 unsigned int trb_count;
362 unsigned int trb_alloced;
363 XHCITRB *trbs;
364
365 TRBCCode status;
366
367 unsigned int pkts;
368 unsigned int pktsize;
369 unsigned int cur_pkt;
370
371 uint64_t mfindex_kick;
372 } XHCITransfer;
373
374 struct XHCIStreamContext {
375 dma_addr_t pctx;
376 unsigned int sct;
377 XHCIRing ring;
378 };
379
380 struct XHCIEPContext {
381 XHCIState *xhci;
382 unsigned int slotid;
383 unsigned int epid;
384
385 XHCIRing ring;
386 unsigned int next_xfer;
387 unsigned int comp_xfer;
388 XHCITransfer transfers[TD_QUEUE];
389 XHCITransfer *retry;
390 EPType type;
391 dma_addr_t pctx;
392 unsigned int max_psize;
393 uint32_t state;
394
395 /* streams */
396 unsigned int max_pstreams;
397 bool lsa;
398 unsigned int nr_pstreams;
399 XHCIStreamContext *pstreams;
400
401 /* iso xfer scheduling */
402 unsigned int interval;
403 int64_t mfindex_last;
404 QEMUTimer *kick_timer;
405 };
406
407 typedef struct XHCISlot {
408 bool enabled;
409 bool addressed;
410 dma_addr_t ctx;
411 USBPort *uport;
412 XHCIEPContext * eps[31];
413 } XHCISlot;
414
415 typedef struct XHCIEvent {
416 TRBType type;
417 TRBCCode ccode;
418 uint64_t ptr;
419 uint32_t length;
420 uint32_t flags;
421 uint8_t slotid;
422 uint8_t epid;
423 } XHCIEvent;
424
425 typedef struct XHCIInterrupter {
426 uint32_t iman;
427 uint32_t imod;
428 uint32_t erstsz;
429 uint32_t erstba_low;
430 uint32_t erstba_high;
431 uint32_t erdp_low;
432 uint32_t erdp_high;
433
434 bool msix_used, er_pcs, er_full;
435
436 dma_addr_t er_start;
437 uint32_t er_size;
438 unsigned int er_ep_idx;
439
440 XHCIEvent ev_buffer[EV_QUEUE];
441 unsigned int ev_buffer_put;
442 unsigned int ev_buffer_get;
443
444 } XHCIInterrupter;
445
446 struct XHCIState {
447 /*< private >*/
448 PCIDevice parent_obj;
449 /*< public >*/
450
451 USBBus bus;
452 MemoryRegion mem;
453 MemoryRegion mem_cap;
454 MemoryRegion mem_oper;
455 MemoryRegion mem_runtime;
456 MemoryRegion mem_doorbell;
457
458 /* properties */
459 uint32_t numports_2;
460 uint32_t numports_3;
461 uint32_t numintrs;
462 uint32_t numslots;
463 uint32_t flags;
464 uint32_t max_pstreams_mask;
465 OnOffAuto msi;
466 OnOffAuto msix;
467
468 /* Operational Registers */
469 uint32_t usbcmd;
470 uint32_t usbsts;
471 uint32_t dnctrl;
472 uint32_t crcr_low;
473 uint32_t crcr_high;
474 uint32_t dcbaap_low;
475 uint32_t dcbaap_high;
476 uint32_t config;
477
478 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
479 XHCIPort ports[MAXPORTS];
480 XHCISlot slots[MAXSLOTS];
481 uint32_t numports;
482
483 /* Runtime Registers */
484 int64_t mfindex_start;
485 QEMUTimer *mfwrap_timer;
486 XHCIInterrupter intr[MAXINTRS];
487
488 XHCIRing cmd_ring;
489 };
490
491 #define TYPE_XHCI "nec-usb-xhci"
492
493 #define XHCI(obj) \
494 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
495
496 typedef struct XHCIEvRingSeg {
497 uint32_t addr_low;
498 uint32_t addr_high;
499 uint32_t size;
500 uint32_t rsvd;
501 } XHCIEvRingSeg;
502
503 enum xhci_flags {
504 XHCI_FLAG_SS_FIRST = 1,
505 XHCI_FLAG_FORCE_PCIE_ENDCAP,
506 XHCI_FLAG_ENABLE_STREAMS,
507 };
508
509 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
510 unsigned int epid, unsigned int streamid);
511 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
512 unsigned int epid);
513 static void xhci_xfer_report(XHCITransfer *xfer);
514 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
515 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
516 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
517 unsigned int slotid, unsigned int epid);
518
519 static const char *TRBType_names[] = {
520 [TRB_RESERVED] = "TRB_RESERVED",
521 [TR_NORMAL] = "TR_NORMAL",
522 [TR_SETUP] = "TR_SETUP",
523 [TR_DATA] = "TR_DATA",
524 [TR_STATUS] = "TR_STATUS",
525 [TR_ISOCH] = "TR_ISOCH",
526 [TR_LINK] = "TR_LINK",
527 [TR_EVDATA] = "TR_EVDATA",
528 [TR_NOOP] = "TR_NOOP",
529 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
530 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
531 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
532 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
533 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
534 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
535 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
536 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
537 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
538 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
539 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
540 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
541 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
542 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
543 [CR_NOOP] = "CR_NOOP",
544 [ER_TRANSFER] = "ER_TRANSFER",
545 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
546 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
547 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
548 [ER_DOORBELL] = "ER_DOORBELL",
549 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
550 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
551 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
552 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
553 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
554 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
555 };
556
557 static const char *TRBCCode_names[] = {
558 [CC_INVALID] = "CC_INVALID",
559 [CC_SUCCESS] = "CC_SUCCESS",
560 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
561 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
562 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
563 [CC_TRB_ERROR] = "CC_TRB_ERROR",
564 [CC_STALL_ERROR] = "CC_STALL_ERROR",
565 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
566 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
567 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
568 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
569 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
570 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
571 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
572 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
573 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
574 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
575 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
576 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
577 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
578 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
579 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
580 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
581 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
582 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
583 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
584 [CC_STOPPED] = "CC_STOPPED",
585 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
586 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
587 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
588 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
589 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
590 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
591 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
592 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
593 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
594 };
595
596 static const char *ep_state_names[] = {
597 [EP_DISABLED] = "disabled",
598 [EP_RUNNING] = "running",
599 [EP_HALTED] = "halted",
600 [EP_STOPPED] = "stopped",
601 [EP_ERROR] = "error",
602 };
603
604 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
605 {
606 if (index >= llen || list[index] == NULL) {
607 return "???";
608 }
609 return list[index];
610 }
611
612 static const char *trb_name(XHCITRB *trb)
613 {
614 return lookup_name(TRB_TYPE(*trb), TRBType_names,
615 ARRAY_SIZE(TRBType_names));
616 }
617
618 static const char *event_name(XHCIEvent *event)
619 {
620 return lookup_name(event->ccode, TRBCCode_names,
621 ARRAY_SIZE(TRBCCode_names));
622 }
623
624 static const char *ep_state_name(uint32_t state)
625 {
626 return lookup_name(state, ep_state_names,
627 ARRAY_SIZE(ep_state_names));
628 }
629
630 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
631 {
632 return xhci->flags & (1 << bit);
633 }
634
635 static uint64_t xhci_mfindex_get(XHCIState *xhci)
636 {
637 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
638 return (now - xhci->mfindex_start) / 125000;
639 }
640
641 static void xhci_mfwrap_update(XHCIState *xhci)
642 {
643 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
644 uint32_t mfindex, left;
645 int64_t now;
646
647 if ((xhci->usbcmd & bits) == bits) {
648 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
649 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
650 left = 0x4000 - mfindex;
651 timer_mod(xhci->mfwrap_timer, now + left * 125000);
652 } else {
653 timer_del(xhci->mfwrap_timer);
654 }
655 }
656
657 static void xhci_mfwrap_timer(void *opaque)
658 {
659 XHCIState *xhci = opaque;
660 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
661
662 xhci_event(xhci, &wrap, 0);
663 xhci_mfwrap_update(xhci);
664 }
665
666 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
667 {
668 if (sizeof(dma_addr_t) == 4) {
669 return low;
670 } else {
671 return low | (((dma_addr_t)high << 16) << 16);
672 }
673 }
674
675 static inline dma_addr_t xhci_mask64(uint64_t addr)
676 {
677 if (sizeof(dma_addr_t) == 4) {
678 return addr & 0xffffffff;
679 } else {
680 return addr;
681 }
682 }
683
684 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
685 uint32_t *buf, size_t len)
686 {
687 int i;
688
689 assert((len % sizeof(uint32_t)) == 0);
690
691 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
692
693 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
694 buf[i] = le32_to_cpu(buf[i]);
695 }
696 }
697
698 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
699 uint32_t *buf, size_t len)
700 {
701 int i;
702 uint32_t tmp[5];
703 uint32_t n = len / sizeof(uint32_t);
704
705 assert((len % sizeof(uint32_t)) == 0);
706 assert(n <= ARRAY_SIZE(tmp));
707
708 for (i = 0; i < n; i++) {
709 tmp[i] = cpu_to_le32(buf[i]);
710 }
711 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
712 }
713
714 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
715 {
716 int index;
717
718 if (!uport->dev) {
719 return NULL;
720 }
721 switch (uport->dev->speed) {
722 case USB_SPEED_LOW:
723 case USB_SPEED_FULL:
724 case USB_SPEED_HIGH:
725 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
726 index = uport->index + xhci->numports_3;
727 } else {
728 index = uport->index;
729 }
730 break;
731 case USB_SPEED_SUPER:
732 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
733 index = uport->index;
734 } else {
735 index = uport->index + xhci->numports_2;
736 }
737 break;
738 default:
739 return NULL;
740 }
741 return &xhci->ports[index];
742 }
743
744 static void xhci_intx_update(XHCIState *xhci)
745 {
746 PCIDevice *pci_dev = PCI_DEVICE(xhci);
747 int level = 0;
748
749 if (msix_enabled(pci_dev) ||
750 msi_enabled(pci_dev)) {
751 return;
752 }
753
754 if (xhci->intr[0].iman & IMAN_IP &&
755 xhci->intr[0].iman & IMAN_IE &&
756 xhci->usbcmd & USBCMD_INTE) {
757 level = 1;
758 }
759
760 trace_usb_xhci_irq_intx(level);
761 pci_set_irq(pci_dev, level);
762 }
763
764 static void xhci_msix_update(XHCIState *xhci, int v)
765 {
766 PCIDevice *pci_dev = PCI_DEVICE(xhci);
767 bool enabled;
768
769 if (!msix_enabled(pci_dev)) {
770 return;
771 }
772
773 enabled = xhci->intr[v].iman & IMAN_IE;
774 if (enabled == xhci->intr[v].msix_used) {
775 return;
776 }
777
778 if (enabled) {
779 trace_usb_xhci_irq_msix_use(v);
780 msix_vector_use(pci_dev, v);
781 xhci->intr[v].msix_used = true;
782 } else {
783 trace_usb_xhci_irq_msix_unuse(v);
784 msix_vector_unuse(pci_dev, v);
785 xhci->intr[v].msix_used = false;
786 }
787 }
788
789 static void xhci_intr_raise(XHCIState *xhci, int v)
790 {
791 PCIDevice *pci_dev = PCI_DEVICE(xhci);
792
793 xhci->intr[v].erdp_low |= ERDP_EHB;
794 xhci->intr[v].iman |= IMAN_IP;
795 xhci->usbsts |= USBSTS_EINT;
796
797 if (!(xhci->intr[v].iman & IMAN_IE)) {
798 return;
799 }
800
801 if (!(xhci->usbcmd & USBCMD_INTE)) {
802 return;
803 }
804
805 if (msix_enabled(pci_dev)) {
806 trace_usb_xhci_irq_msix(v);
807 msix_notify(pci_dev, v);
808 return;
809 }
810
811 if (msi_enabled(pci_dev)) {
812 trace_usb_xhci_irq_msi(v);
813 msi_notify(pci_dev, v);
814 return;
815 }
816
817 if (v == 0) {
818 trace_usb_xhci_irq_intx(1);
819 pci_irq_assert(pci_dev);
820 }
821 }
822
823 static inline int xhci_running(XHCIState *xhci)
824 {
825 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full;
826 }
827
828 static void xhci_die(XHCIState *xhci)
829 {
830 xhci->usbsts |= USBSTS_HCE;
831 DPRINTF("xhci: asserted controller error\n");
832 }
833
834 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
835 {
836 PCIDevice *pci_dev = PCI_DEVICE(xhci);
837 XHCIInterrupter *intr = &xhci->intr[v];
838 XHCITRB ev_trb;
839 dma_addr_t addr;
840
841 ev_trb.parameter = cpu_to_le64(event->ptr);
842 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
843 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
844 event->flags | (event->type << TRB_TYPE_SHIFT);
845 if (intr->er_pcs) {
846 ev_trb.control |= TRB_C;
847 }
848 ev_trb.control = cpu_to_le32(ev_trb.control);
849
850 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
851 event_name(event), ev_trb.parameter,
852 ev_trb.status, ev_trb.control);
853
854 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
855 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
856
857 intr->er_ep_idx++;
858 if (intr->er_ep_idx >= intr->er_size) {
859 intr->er_ep_idx = 0;
860 intr->er_pcs = !intr->er_pcs;
861 }
862 }
863
864 static void xhci_events_update(XHCIState *xhci, int v)
865 {
866 XHCIInterrupter *intr = &xhci->intr[v];
867 dma_addr_t erdp;
868 unsigned int dp_idx;
869 bool do_irq = 0;
870
871 if (xhci->usbsts & USBSTS_HCH) {
872 return;
873 }
874
875 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
876 if (erdp < intr->er_start ||
877 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
878 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
879 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
880 v, intr->er_start, intr->er_size);
881 xhci_die(xhci);
882 return;
883 }
884 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
885 assert(dp_idx < intr->er_size);
886
887 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
888 * deadlocks when the ER is full. Hack it by holding off events until
889 * the driver decides to free at least half of the ring */
890 if (intr->er_full) {
891 int er_free = dp_idx - intr->er_ep_idx;
892 if (er_free <= 0) {
893 er_free += intr->er_size;
894 }
895 if (er_free < (intr->er_size/2)) {
896 DPRINTF("xhci_events_update(): event ring still "
897 "more than half full (hack)\n");
898 return;
899 }
900 }
901
902 while (intr->ev_buffer_put != intr->ev_buffer_get) {
903 assert(intr->er_full);
904 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
905 DPRINTF("xhci_events_update(): event ring full again\n");
906 #ifndef ER_FULL_HACK
907 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
908 xhci_write_event(xhci, &full, v);
909 #endif
910 do_irq = 1;
911 break;
912 }
913 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
914 xhci_write_event(xhci, event, v);
915 intr->ev_buffer_get++;
916 do_irq = 1;
917 if (intr->ev_buffer_get == EV_QUEUE) {
918 intr->ev_buffer_get = 0;
919 }
920 }
921
922 if (do_irq) {
923 xhci_intr_raise(xhci, v);
924 }
925
926 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
927 DPRINTF("xhci_events_update(): event ring no longer full\n");
928 intr->er_full = 0;
929 }
930 }
931
932 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
933 {
934 XHCIInterrupter *intr;
935 dma_addr_t erdp;
936 unsigned int dp_idx;
937
938 if (v >= xhci->numintrs) {
939 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
940 return;
941 }
942 intr = &xhci->intr[v];
943
944 if (intr->er_full) {
945 DPRINTF("xhci_event(): ER full, queueing\n");
946 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
947 DPRINTF("xhci: event queue full, dropping event!\n");
948 return;
949 }
950 intr->ev_buffer[intr->ev_buffer_put++] = *event;
951 if (intr->ev_buffer_put == EV_QUEUE) {
952 intr->ev_buffer_put = 0;
953 }
954 return;
955 }
956
957 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
958 if (erdp < intr->er_start ||
959 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
960 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
961 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
962 v, intr->er_start, intr->er_size);
963 xhci_die(xhci);
964 return;
965 }
966
967 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
968 assert(dp_idx < intr->er_size);
969
970 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
971 DPRINTF("xhci_event(): ER full, queueing\n");
972 #ifndef ER_FULL_HACK
973 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
974 xhci_write_event(xhci, &full);
975 #endif
976 intr->er_full = 1;
977 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
978 DPRINTF("xhci: event queue full, dropping event!\n");
979 return;
980 }
981 intr->ev_buffer[intr->ev_buffer_put++] = *event;
982 if (intr->ev_buffer_put == EV_QUEUE) {
983 intr->ev_buffer_put = 0;
984 }
985 } else {
986 xhci_write_event(xhci, event, v);
987 }
988
989 xhci_intr_raise(xhci, v);
990 }
991
992 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
993 dma_addr_t base)
994 {
995 ring->dequeue = base;
996 ring->ccs = 1;
997 }
998
999 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
1000 dma_addr_t *addr)
1001 {
1002 PCIDevice *pci_dev = PCI_DEVICE(xhci);
1003
1004 while (1) {
1005 TRBType type;
1006 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
1007 trb->addr = ring->dequeue;
1008 trb->ccs = ring->ccs;
1009 le64_to_cpus(&trb->parameter);
1010 le32_to_cpus(&trb->status);
1011 le32_to_cpus(&trb->control);
1012
1013 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
1014 trb->parameter, trb->status, trb->control);
1015
1016 if ((trb->control & TRB_C) != ring->ccs) {
1017 return 0;
1018 }
1019
1020 type = TRB_TYPE(*trb);
1021
1022 if (type != TR_LINK) {
1023 if (addr) {
1024 *addr = ring->dequeue;
1025 }
1026 ring->dequeue += TRB_SIZE;
1027 return type;
1028 } else {
1029 ring->dequeue = xhci_mask64(trb->parameter);
1030 if (trb->control & TRB_LK_TC) {
1031 ring->ccs = !ring->ccs;
1032 }
1033 }
1034 }
1035 }
1036
1037 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
1038 {
1039 PCIDevice *pci_dev = PCI_DEVICE(xhci);
1040 XHCITRB trb;
1041 int length = 0;
1042 dma_addr_t dequeue = ring->dequeue;
1043 bool ccs = ring->ccs;
1044 /* hack to bundle together the two/three TDs that make a setup transfer */
1045 bool control_td_set = 0;
1046
1047 while (1) {
1048 TRBType type;
1049 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
1050 le64_to_cpus(&trb.parameter);
1051 le32_to_cpus(&trb.status);
1052 le32_to_cpus(&trb.control);
1053
1054 if ((trb.control & TRB_C) != ccs) {
1055 return -length;
1056 }
1057
1058 type = TRB_TYPE(trb);
1059
1060 if (type == TR_LINK) {
1061 dequeue = xhci_mask64(trb.parameter);
1062 if (trb.control & TRB_LK_TC) {
1063 ccs = !ccs;
1064 }
1065 continue;
1066 }
1067
1068 length += 1;
1069 dequeue += TRB_SIZE;
1070
1071 if (type == TR_SETUP) {
1072 control_td_set = 1;
1073 } else if (type == TR_STATUS) {
1074 control_td_set = 0;
1075 }
1076
1077 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
1078 return length;
1079 }
1080 }
1081 }
1082
1083 static void xhci_er_reset(XHCIState *xhci, int v)
1084 {
1085 XHCIInterrupter *intr = &xhci->intr[v];
1086 XHCIEvRingSeg seg;
1087
1088 if (intr->erstsz == 0) {
1089 /* disabled */
1090 intr->er_start = 0;
1091 intr->er_size = 0;
1092 return;
1093 }
1094 /* cache the (sole) event ring segment location */
1095 if (intr->erstsz != 1) {
1096 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
1097 xhci_die(xhci);
1098 return;
1099 }
1100 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
1101 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
1102 le32_to_cpus(&seg.addr_low);
1103 le32_to_cpus(&seg.addr_high);
1104 le32_to_cpus(&seg.size);
1105 if (seg.size < 16 || seg.size > 4096) {
1106 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
1107 xhci_die(xhci);
1108 return;
1109 }
1110 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
1111 intr->er_size = seg.size;
1112
1113 intr->er_ep_idx = 0;
1114 intr->er_pcs = 1;
1115 intr->er_full = 0;
1116
1117 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
1118 v, intr->er_start, intr->er_size);
1119 }
1120
1121 static void xhci_run(XHCIState *xhci)
1122 {
1123 trace_usb_xhci_run();
1124 xhci->usbsts &= ~USBSTS_HCH;
1125 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1126 }
1127
1128 static void xhci_stop(XHCIState *xhci)
1129 {
1130 trace_usb_xhci_stop();
1131 xhci->usbsts |= USBSTS_HCH;
1132 xhci->crcr_low &= ~CRCR_CRR;
1133 }
1134
1135 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
1136 dma_addr_t base)
1137 {
1138 XHCIStreamContext *stctx;
1139 unsigned int i;
1140
1141 stctx = g_new0(XHCIStreamContext, count);
1142 for (i = 0; i < count; i++) {
1143 stctx[i].pctx = base + i * 16;
1144 stctx[i].sct = -1;
1145 }
1146 return stctx;
1147 }
1148
1149 static void xhci_reset_streams(XHCIEPContext *epctx)
1150 {
1151 unsigned int i;
1152
1153 for (i = 0; i < epctx->nr_pstreams; i++) {
1154 epctx->pstreams[i].sct = -1;
1155 }
1156 }
1157
1158 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
1159 {
1160 assert(epctx->pstreams == NULL);
1161 epctx->nr_pstreams = 2 << epctx->max_pstreams;
1162 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
1163 }
1164
1165 static void xhci_free_streams(XHCIEPContext *epctx)
1166 {
1167 assert(epctx->pstreams != NULL);
1168
1169 g_free(epctx->pstreams);
1170 epctx->pstreams = NULL;
1171 epctx->nr_pstreams = 0;
1172 }
1173
1174 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
1175 unsigned int slotid,
1176 uint32_t epmask,
1177 XHCIEPContext **epctxs,
1178 USBEndpoint **eps)
1179 {
1180 XHCISlot *slot;
1181 XHCIEPContext *epctx;
1182 USBEndpoint *ep;
1183 int i, j;
1184
1185 assert(slotid >= 1 && slotid <= xhci->numslots);
1186
1187 slot = &xhci->slots[slotid - 1];
1188
1189 for (i = 2, j = 0; i <= 31; i++) {
1190 if (!(epmask & (1u << i))) {
1191 continue;
1192 }
1193
1194 epctx = slot->eps[i - 1];
1195 ep = xhci_epid_to_usbep(xhci, slotid, i);
1196 if (!epctx || !epctx->nr_pstreams || !ep) {
1197 continue;
1198 }
1199
1200 if (epctxs) {
1201 epctxs[j] = epctx;
1202 }
1203 eps[j++] = ep;
1204 }
1205 return j;
1206 }
1207
1208 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
1209 uint32_t epmask)
1210 {
1211 USBEndpoint *eps[30];
1212 int nr_eps;
1213
1214 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
1215 if (nr_eps) {
1216 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
1217 }
1218 }
1219
1220 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
1221 uint32_t epmask)
1222 {
1223 XHCIEPContext *epctxs[30];
1224 USBEndpoint *eps[30];
1225 int i, r, nr_eps, req_nr_streams, dev_max_streams;
1226
1227 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
1228 eps);
1229 if (nr_eps == 0) {
1230 return CC_SUCCESS;
1231 }
1232
1233 req_nr_streams = epctxs[0]->nr_pstreams;
1234 dev_max_streams = eps[0]->max_streams;
1235
1236 for (i = 1; i < nr_eps; i++) {
1237 /*
1238 * HdG: I don't expect these to ever trigger, but if they do we need
1239 * to come up with another solution, ie group identical endpoints
1240 * together and make an usb_device_alloc_streams call per group.
1241 */
1242 if (epctxs[i]->nr_pstreams != req_nr_streams) {
1243 FIXME("guest streams config not identical for all eps");
1244 return CC_RESOURCE_ERROR;
1245 }
1246 if (eps[i]->max_streams != dev_max_streams) {
1247 FIXME("device streams config not identical for all eps");
1248 return CC_RESOURCE_ERROR;
1249 }
1250 }
1251
1252 /*
1253 * max-streams in both the device descriptor and in the controller is a
1254 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
1255 * streams the guest will ask for 5 rounded up to the next power of 2 which
1256 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
1257 *
1258 * For redirected devices however this is an issue, as there we must ask
1259 * the real xhci controller to alloc streams, and the host driver for the
1260 * real xhci controller will likely disallow allocating more streams then
1261 * the device can handle.
1262 *
1263 * So we limit the requested nr_streams to the maximum number the device
1264 * can handle.
1265 */
1266 if (req_nr_streams > dev_max_streams) {
1267 req_nr_streams = dev_max_streams;
1268 }
1269
1270 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
1271 if (r != 0) {
1272 DPRINTF("xhci: alloc streams failed\n");
1273 return CC_RESOURCE_ERROR;
1274 }
1275
1276 return CC_SUCCESS;
1277 }
1278
1279 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1280 unsigned int streamid,
1281 uint32_t *cc_error)
1282 {
1283 XHCIStreamContext *sctx;
1284 dma_addr_t base;
1285 uint32_t ctx[2], sct;
1286
1287 assert(streamid != 0);
1288 if (epctx->lsa) {
1289 if (streamid >= epctx->nr_pstreams) {
1290 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1291 return NULL;
1292 }
1293 sctx = epctx->pstreams + streamid;
1294 } else {
1295 FIXME("secondary streams not implemented yet");
1296 }
1297
1298 if (sctx->sct == -1) {
1299 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1300 sct = (ctx[0] >> 1) & 0x07;
1301 if (epctx->lsa && sct != 1) {
1302 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1303 return NULL;
1304 }
1305 sctx->sct = sct;
1306 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1307 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1308 }
1309 return sctx;
1310 }
1311
1312 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1313 XHCIStreamContext *sctx, uint32_t state)
1314 {
1315 XHCIRing *ring = NULL;
1316 uint32_t ctx[5];
1317 uint32_t ctx2[2];
1318
1319 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1320 ctx[0] &= ~EP_STATE_MASK;
1321 ctx[0] |= state;
1322
1323 /* update ring dequeue ptr */
1324 if (epctx->nr_pstreams) {
1325 if (sctx != NULL) {
1326 ring = &sctx->ring;
1327 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1328 ctx2[0] &= 0xe;
1329 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1330 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1331 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1332 }
1333 } else {
1334 ring = &epctx->ring;
1335 }
1336 if (ring) {
1337 ctx[2] = ring->dequeue | ring->ccs;
1338 ctx[3] = (ring->dequeue >> 16) >> 16;
1339
1340 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1341 epctx->pctx, state, ctx[3], ctx[2]);
1342 }
1343
1344 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1345 if (epctx->state != state) {
1346 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1347 ep_state_name(epctx->state),
1348 ep_state_name(state));
1349 }
1350 epctx->state = state;
1351 }
1352
1353 static void xhci_ep_kick_timer(void *opaque)
1354 {
1355 XHCIEPContext *epctx = opaque;
1356 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0);
1357 }
1358
1359 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1360 unsigned int slotid,
1361 unsigned int epid)
1362 {
1363 XHCIEPContext *epctx;
1364 int i;
1365
1366 epctx = g_new0(XHCIEPContext, 1);
1367 epctx->xhci = xhci;
1368 epctx->slotid = slotid;
1369 epctx->epid = epid;
1370
1371 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1372 epctx->transfers[i].xhci = xhci;
1373 epctx->transfers[i].slotid = slotid;
1374 epctx->transfers[i].epid = epid;
1375 usb_packet_init(&epctx->transfers[i].packet);
1376 }
1377 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1378
1379 return epctx;
1380 }
1381
1382 static void xhci_init_epctx(XHCIEPContext *epctx,
1383 dma_addr_t pctx, uint32_t *ctx)
1384 {
1385 dma_addr_t dequeue;
1386
1387 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1388
1389 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1390 epctx->pctx = pctx;
1391 epctx->max_psize = ctx[1]>>16;
1392 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1393 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
1394 epctx->lsa = (ctx[0] >> 15) & 1;
1395 if (epctx->max_pstreams) {
1396 xhci_alloc_streams(epctx, dequeue);
1397 } else {
1398 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1399 epctx->ring.ccs = ctx[2] & 1;
1400 }
1401
1402 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1403 }
1404
1405 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1406 unsigned int epid, dma_addr_t pctx,
1407 uint32_t *ctx)
1408 {
1409 XHCISlot *slot;
1410 XHCIEPContext *epctx;
1411
1412 trace_usb_xhci_ep_enable(slotid, epid);
1413 assert(slotid >= 1 && slotid <= xhci->numslots);
1414 assert(epid >= 1 && epid <= 31);
1415
1416 slot = &xhci->slots[slotid-1];
1417 if (slot->eps[epid-1]) {
1418 xhci_disable_ep(xhci, slotid, epid);
1419 }
1420
1421 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1422 slot->eps[epid-1] = epctx;
1423 xhci_init_epctx(epctx, pctx, ctx);
1424
1425 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1426 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1427
1428 epctx->mfindex_last = 0;
1429
1430 epctx->state = EP_RUNNING;
1431 ctx[0] &= ~EP_STATE_MASK;
1432 ctx[0] |= EP_RUNNING;
1433
1434 return CC_SUCCESS;
1435 }
1436
1437 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1438 {
1439 int killed = 0;
1440
1441 if (report && (t->running_async || t->running_retry)) {
1442 t->status = report;
1443 xhci_xfer_report(t);
1444 }
1445
1446 if (t->running_async) {
1447 usb_cancel_packet(&t->packet);
1448 t->running_async = 0;
1449 killed = 1;
1450 }
1451 if (t->running_retry) {
1452 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1];
1453 if (epctx) {
1454 epctx->retry = NULL;
1455 timer_del(epctx->kick_timer);
1456 }
1457 t->running_retry = 0;
1458 killed = 1;
1459 }
1460 g_free(t->trbs);
1461
1462 t->trbs = NULL;
1463 t->trb_count = t->trb_alloced = 0;
1464
1465 return killed;
1466 }
1467
1468 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1469 unsigned int epid, TRBCCode report)
1470 {
1471 XHCISlot *slot;
1472 XHCIEPContext *epctx;
1473 int i, xferi, killed = 0;
1474 USBEndpoint *ep = NULL;
1475 assert(slotid >= 1 && slotid <= xhci->numslots);
1476 assert(epid >= 1 && epid <= 31);
1477
1478 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1479
1480 slot = &xhci->slots[slotid-1];
1481
1482 if (!slot->eps[epid-1]) {
1483 return 0;
1484 }
1485
1486 epctx = slot->eps[epid-1];
1487
1488 xferi = epctx->next_xfer;
1489 for (i = 0; i < TD_QUEUE; i++) {
1490 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report);
1491 if (killed) {
1492 report = 0; /* Only report once */
1493 }
1494 epctx->transfers[xferi].packet.ep = NULL;
1495 xferi = (xferi + 1) % TD_QUEUE;
1496 }
1497
1498 ep = xhci_epid_to_usbep(xhci, slotid, epid);
1499 if (ep) {
1500 usb_device_ep_stopped(ep->dev, ep);
1501 }
1502 return killed;
1503 }
1504
1505 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1506 unsigned int epid)
1507 {
1508 XHCISlot *slot;
1509 XHCIEPContext *epctx;
1510 int i;
1511
1512 trace_usb_xhci_ep_disable(slotid, epid);
1513 assert(slotid >= 1 && slotid <= xhci->numslots);
1514 assert(epid >= 1 && epid <= 31);
1515
1516 slot = &xhci->slots[slotid-1];
1517
1518 if (!slot->eps[epid-1]) {
1519 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1520 return CC_SUCCESS;
1521 }
1522
1523 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1524
1525 epctx = slot->eps[epid-1];
1526
1527 if (epctx->nr_pstreams) {
1528 xhci_free_streams(epctx);
1529 }
1530
1531 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1532 usb_packet_cleanup(&epctx->transfers[i].packet);
1533 }
1534
1535 /* only touch guest RAM if we're not resetting the HC */
1536 if (xhci->dcbaap_low || xhci->dcbaap_high) {
1537 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1538 }
1539
1540 timer_free(epctx->kick_timer);
1541 g_free(epctx);
1542 slot->eps[epid-1] = NULL;
1543
1544 return CC_SUCCESS;
1545 }
1546
1547 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1548 unsigned int epid)
1549 {
1550 XHCISlot *slot;
1551 XHCIEPContext *epctx;
1552
1553 trace_usb_xhci_ep_stop(slotid, epid);
1554 assert(slotid >= 1 && slotid <= xhci->numslots);
1555
1556 if (epid < 1 || epid > 31) {
1557 DPRINTF("xhci: bad ep %d\n", epid);
1558 return CC_TRB_ERROR;
1559 }
1560
1561 slot = &xhci->slots[slotid-1];
1562
1563 if (!slot->eps[epid-1]) {
1564 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1565 return CC_EP_NOT_ENABLED_ERROR;
1566 }
1567
1568 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1569 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1570 "data might be lost\n");
1571 }
1572
1573 epctx = slot->eps[epid-1];
1574
1575 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1576
1577 if (epctx->nr_pstreams) {
1578 xhci_reset_streams(epctx);
1579 }
1580
1581 return CC_SUCCESS;
1582 }
1583
1584 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1585 unsigned int epid)
1586 {
1587 XHCISlot *slot;
1588 XHCIEPContext *epctx;
1589
1590 trace_usb_xhci_ep_reset(slotid, epid);
1591 assert(slotid >= 1 && slotid <= xhci->numslots);
1592
1593 if (epid < 1 || epid > 31) {
1594 DPRINTF("xhci: bad ep %d\n", epid);
1595 return CC_TRB_ERROR;
1596 }
1597
1598 slot = &xhci->slots[slotid-1];
1599
1600 if (!slot->eps[epid-1]) {
1601 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1602 return CC_EP_NOT_ENABLED_ERROR;
1603 }
1604
1605 epctx = slot->eps[epid-1];
1606
1607 if (epctx->state != EP_HALTED) {
1608 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1609 epid, epctx->state);
1610 return CC_CONTEXT_STATE_ERROR;
1611 }
1612
1613 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1614 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1615 "data might be lost\n");
1616 }
1617
1618 if (!xhci->slots[slotid-1].uport ||
1619 !xhci->slots[slotid-1].uport->dev ||
1620 !xhci->slots[slotid-1].uport->dev->attached) {
1621 return CC_USB_TRANSACTION_ERROR;
1622 }
1623
1624 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1625
1626 if (epctx->nr_pstreams) {
1627 xhci_reset_streams(epctx);
1628 }
1629
1630 return CC_SUCCESS;
1631 }
1632
1633 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1634 unsigned int epid, unsigned int streamid,
1635 uint64_t pdequeue)
1636 {
1637 XHCISlot *slot;
1638 XHCIEPContext *epctx;
1639 XHCIStreamContext *sctx;
1640 dma_addr_t dequeue;
1641
1642 assert(slotid >= 1 && slotid <= xhci->numslots);
1643
1644 if (epid < 1 || epid > 31) {
1645 DPRINTF("xhci: bad ep %d\n", epid);
1646 return CC_TRB_ERROR;
1647 }
1648
1649 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1650 dequeue = xhci_mask64(pdequeue);
1651
1652 slot = &xhci->slots[slotid-1];
1653
1654 if (!slot->eps[epid-1]) {
1655 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1656 return CC_EP_NOT_ENABLED_ERROR;
1657 }
1658
1659 epctx = slot->eps[epid-1];
1660
1661 if (epctx->state != EP_STOPPED) {
1662 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1663 return CC_CONTEXT_STATE_ERROR;
1664 }
1665
1666 if (epctx->nr_pstreams) {
1667 uint32_t err;
1668 sctx = xhci_find_stream(epctx, streamid, &err);
1669 if (sctx == NULL) {
1670 return err;
1671 }
1672 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1673 sctx->ring.ccs = dequeue & 1;
1674 } else {
1675 sctx = NULL;
1676 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1677 epctx->ring.ccs = dequeue & 1;
1678 }
1679
1680 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1681
1682 return CC_SUCCESS;
1683 }
1684
1685 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1686 {
1687 XHCIState *xhci = xfer->xhci;
1688 int i;
1689
1690 xfer->int_req = false;
1691 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
1692 for (i = 0; i < xfer->trb_count; i++) {
1693 XHCITRB *trb = &xfer->trbs[i];
1694 dma_addr_t addr;
1695 unsigned int chunk = 0;
1696
1697 if (trb->control & TRB_TR_IOC) {
1698 xfer->int_req = true;
1699 }
1700
1701 switch (TRB_TYPE(*trb)) {
1702 case TR_DATA:
1703 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1704 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1705 goto err;
1706 }
1707 /* fallthrough */
1708 case TR_NORMAL:
1709 case TR_ISOCH:
1710 addr = xhci_mask64(trb->parameter);
1711 chunk = trb->status & 0x1ffff;
1712 if (trb->control & TRB_TR_IDT) {
1713 if (chunk > 8 || in_xfer) {
1714 DPRINTF("xhci: invalid immediate data TRB\n");
1715 goto err;
1716 }
1717 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1718 } else {
1719 qemu_sglist_add(&xfer->sgl, addr, chunk);
1720 }
1721 break;
1722 }
1723 }
1724
1725 return 0;
1726
1727 err:
1728 qemu_sglist_destroy(&xfer->sgl);
1729 xhci_die(xhci);
1730 return -1;
1731 }
1732
1733 static void xhci_xfer_unmap(XHCITransfer *xfer)
1734 {
1735 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1736 qemu_sglist_destroy(&xfer->sgl);
1737 }
1738
1739 static void xhci_xfer_report(XHCITransfer *xfer)
1740 {
1741 uint32_t edtla = 0;
1742 unsigned int left;
1743 bool reported = 0;
1744 bool shortpkt = 0;
1745 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1746 XHCIState *xhci = xfer->xhci;
1747 int i;
1748
1749 left = xfer->packet.actual_length;
1750
1751 for (i = 0; i < xfer->trb_count; i++) {
1752 XHCITRB *trb = &xfer->trbs[i];
1753 unsigned int chunk = 0;
1754
1755 switch (TRB_TYPE(*trb)) {
1756 case TR_SETUP:
1757 chunk = trb->status & 0x1ffff;
1758 if (chunk > 8) {
1759 chunk = 8;
1760 }
1761 break;
1762 case TR_DATA:
1763 case TR_NORMAL:
1764 case TR_ISOCH:
1765 chunk = trb->status & 0x1ffff;
1766 if (chunk > left) {
1767 chunk = left;
1768 if (xfer->status == CC_SUCCESS) {
1769 shortpkt = 1;
1770 }
1771 }
1772 left -= chunk;
1773 edtla += chunk;
1774 break;
1775 case TR_STATUS:
1776 reported = 0;
1777 shortpkt = 0;
1778 break;
1779 }
1780
1781 if (!reported && ((trb->control & TRB_TR_IOC) ||
1782 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1783 (xfer->status != CC_SUCCESS && left == 0))) {
1784 event.slotid = xfer->slotid;
1785 event.epid = xfer->epid;
1786 event.length = (trb->status & 0x1ffff) - chunk;
1787 event.flags = 0;
1788 event.ptr = trb->addr;
1789 if (xfer->status == CC_SUCCESS) {
1790 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1791 } else {
1792 event.ccode = xfer->status;
1793 }
1794 if (TRB_TYPE(*trb) == TR_EVDATA) {
1795 event.ptr = trb->parameter;
1796 event.flags |= TRB_EV_ED;
1797 event.length = edtla & 0xffffff;
1798 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1799 edtla = 0;
1800 }
1801 xhci_event(xhci, &event, TRB_INTR(*trb));
1802 reported = 1;
1803 if (xfer->status != CC_SUCCESS) {
1804 return;
1805 }
1806 }
1807
1808 switch (TRB_TYPE(*trb)) {
1809 case TR_SETUP:
1810 reported = 0;
1811 shortpkt = 0;
1812 break;
1813 }
1814
1815 }
1816 }
1817
1818 static void xhci_stall_ep(XHCITransfer *xfer)
1819 {
1820 XHCIState *xhci = xfer->xhci;
1821 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1822 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1823 uint32_t err;
1824 XHCIStreamContext *sctx;
1825
1826 if (epctx->nr_pstreams) {
1827 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1828 if (sctx == NULL) {
1829 return;
1830 }
1831 sctx->ring.dequeue = xfer->trbs[0].addr;
1832 sctx->ring.ccs = xfer->trbs[0].ccs;
1833 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1834 } else {
1835 epctx->ring.dequeue = xfer->trbs[0].addr;
1836 epctx->ring.ccs = xfer->trbs[0].ccs;
1837 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1838 }
1839 }
1840
1841 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1842 XHCIEPContext *epctx);
1843
1844 static int xhci_setup_packet(XHCITransfer *xfer)
1845 {
1846 XHCIState *xhci = xfer->xhci;
1847 USBEndpoint *ep;
1848 int dir;
1849
1850 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1851
1852 if (xfer->packet.ep) {
1853 ep = xfer->packet.ep;
1854 } else {
1855 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid);
1856 if (!ep) {
1857 DPRINTF("xhci: slot %d has no device\n",
1858 xfer->slotid);
1859 return -1;
1860 }
1861 }
1862
1863 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1864 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1865 xfer->trbs[0].addr, false, xfer->int_req);
1866 usb_packet_map(&xfer->packet, &xfer->sgl);
1867 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1868 xfer->packet.pid, ep->dev->addr, ep->nr);
1869 return 0;
1870 }
1871
1872 static int xhci_complete_packet(XHCITransfer *xfer)
1873 {
1874 if (xfer->packet.status == USB_RET_ASYNC) {
1875 trace_usb_xhci_xfer_async(xfer);
1876 xfer->running_async = 1;
1877 xfer->running_retry = 0;
1878 xfer->complete = 0;
1879 return 0;
1880 } else if (xfer->packet.status == USB_RET_NAK) {
1881 trace_usb_xhci_xfer_nak(xfer);
1882 xfer->running_async = 0;
1883 xfer->running_retry = 1;
1884 xfer->complete = 0;
1885 return 0;
1886 } else {
1887 xfer->running_async = 0;
1888 xfer->running_retry = 0;
1889 xfer->complete = 1;
1890 xhci_xfer_unmap(xfer);
1891 }
1892
1893 if (xfer->packet.status == USB_RET_SUCCESS) {
1894 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1895 xfer->status = CC_SUCCESS;
1896 xhci_xfer_report(xfer);
1897 return 0;
1898 }
1899
1900 /* error */
1901 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1902 switch (xfer->packet.status) {
1903 case USB_RET_NODEV:
1904 case USB_RET_IOERROR:
1905 xfer->status = CC_USB_TRANSACTION_ERROR;
1906 xhci_xfer_report(xfer);
1907 xhci_stall_ep(xfer);
1908 break;
1909 case USB_RET_STALL:
1910 xfer->status = CC_STALL_ERROR;
1911 xhci_xfer_report(xfer);
1912 xhci_stall_ep(xfer);
1913 break;
1914 case USB_RET_BABBLE:
1915 xfer->status = CC_BABBLE_DETECTED;
1916 xhci_xfer_report(xfer);
1917 xhci_stall_ep(xfer);
1918 break;
1919 default:
1920 DPRINTF("%s: FIXME: status = %d\n", __func__,
1921 xfer->packet.status);
1922 FIXME("unhandled USB_RET_*");
1923 }
1924 return 0;
1925 }
1926
1927 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1928 {
1929 XHCITRB *trb_setup, *trb_status;
1930 uint8_t bmRequestType;
1931
1932 trb_setup = &xfer->trbs[0];
1933 trb_status = &xfer->trbs[xfer->trb_count-1];
1934
1935 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
1936
1937 /* at most one Event Data TRB allowed after STATUS */
1938 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1939 trb_status--;
1940 }
1941
1942 /* do some sanity checks */
1943 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1944 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1945 TRB_TYPE(*trb_setup));
1946 return -1;
1947 }
1948 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1949 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1950 TRB_TYPE(*trb_status));
1951 return -1;
1952 }
1953 if (!(trb_setup->control & TRB_TR_IDT)) {
1954 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1955 return -1;
1956 }
1957 if ((trb_setup->status & 0x1ffff) != 8) {
1958 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1959 (trb_setup->status & 0x1ffff));
1960 return -1;
1961 }
1962
1963 bmRequestType = trb_setup->parameter;
1964
1965 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1966 xfer->iso_xfer = false;
1967 xfer->timed_xfer = false;
1968
1969 if (xhci_setup_packet(xfer) < 0) {
1970 return -1;
1971 }
1972 xfer->packet.parameter = trb_setup->parameter;
1973
1974 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1975
1976 xhci_complete_packet(xfer);
1977 if (!xfer->running_async && !xfer->running_retry) {
1978 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0);
1979 }
1980 return 0;
1981 }
1982
1983 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1984 XHCIEPContext *epctx, uint64_t mfindex)
1985 {
1986 uint64_t asap = ((mfindex + epctx->interval - 1) &
1987 ~(epctx->interval-1));
1988 uint64_t kick = epctx->mfindex_last + epctx->interval;
1989
1990 assert(epctx->interval != 0);
1991 xfer->mfindex_kick = MAX(asap, kick);
1992 }
1993
1994 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1995 XHCIEPContext *epctx, uint64_t mfindex)
1996 {
1997 if (xfer->trbs[0].control & TRB_TR_SIA) {
1998 uint64_t asap = ((mfindex + epctx->interval - 1) &
1999 ~(epctx->interval-1));
2000 if (asap >= epctx->mfindex_last &&
2001 asap <= epctx->mfindex_last + epctx->interval * 4) {
2002 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
2003 } else {
2004 xfer->mfindex_kick = asap;
2005 }
2006 } else {
2007 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
2008 & TRB_TR_FRAMEID_MASK) << 3;
2009 xfer->mfindex_kick |= mfindex & ~0x3fff;
2010 if (xfer->mfindex_kick + 0x100 < mfindex) {
2011 xfer->mfindex_kick += 0x4000;
2012 }
2013 }
2014 }
2015
2016 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
2017 XHCIEPContext *epctx, uint64_t mfindex)
2018 {
2019 if (xfer->mfindex_kick > mfindex) {
2020 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2021 (xfer->mfindex_kick - mfindex) * 125000);
2022 xfer->running_retry = 1;
2023 } else {
2024 epctx->mfindex_last = xfer->mfindex_kick;
2025 timer_del(epctx->kick_timer);
2026 xfer->running_retry = 0;
2027 }
2028 }
2029
2030
2031 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2032 {
2033 uint64_t mfindex;
2034
2035 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
2036
2037 xfer->in_xfer = epctx->type>>2;
2038
2039 switch(epctx->type) {
2040 case ET_INTR_OUT:
2041 case ET_INTR_IN:
2042 xfer->pkts = 0;
2043 xfer->iso_xfer = false;
2044 xfer->timed_xfer = true;
2045 mfindex = xhci_mfindex_get(xhci);
2046 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
2047 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2048 if (xfer->running_retry) {
2049 return -1;
2050 }
2051 break;
2052 case ET_BULK_OUT:
2053 case ET_BULK_IN:
2054 xfer->pkts = 0;
2055 xfer->iso_xfer = false;
2056 xfer->timed_xfer = false;
2057 break;
2058 case ET_ISO_OUT:
2059 case ET_ISO_IN:
2060 xfer->pkts = 1;
2061 xfer->iso_xfer = true;
2062 xfer->timed_xfer = true;
2063 mfindex = xhci_mfindex_get(xhci);
2064 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
2065 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2066 if (xfer->running_retry) {
2067 return -1;
2068 }
2069 break;
2070 default:
2071 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
2072 return -1;
2073 }
2074
2075 if (xhci_setup_packet(xfer) < 0) {
2076 return -1;
2077 }
2078 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2079
2080 xhci_complete_packet(xfer);
2081 if (!xfer->running_async && !xfer->running_retry) {
2082 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid);
2083 }
2084 return 0;
2085 }
2086
2087 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2088 {
2089 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
2090 return xhci_submit(xhci, xfer, epctx);
2091 }
2092
2093 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
2094 unsigned int epid, unsigned int streamid)
2095 {
2096 XHCIStreamContext *stctx;
2097 XHCIEPContext *epctx;
2098 XHCIRing *ring;
2099 USBEndpoint *ep = NULL;
2100 uint64_t mfindex;
2101 int length;
2102 int i;
2103
2104 trace_usb_xhci_ep_kick(slotid, epid, streamid);
2105 assert(slotid >= 1 && slotid <= xhci->numslots);
2106 assert(epid >= 1 && epid <= 31);
2107
2108 if (!xhci->slots[slotid-1].enabled) {
2109 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
2110 return;
2111 }
2112 epctx = xhci->slots[slotid-1].eps[epid-1];
2113 if (!epctx) {
2114 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
2115 epid, slotid);
2116 return;
2117 }
2118
2119 /* If the device has been detached, but the guest has not noticed this
2120 yet the 2 above checks will succeed, but we must NOT continue */
2121 if (!xhci->slots[slotid - 1].uport ||
2122 !xhci->slots[slotid - 1].uport->dev ||
2123 !xhci->slots[slotid - 1].uport->dev->attached) {
2124 return;
2125 }
2126
2127 if (epctx->retry) {
2128 XHCITransfer *xfer = epctx->retry;
2129
2130 trace_usb_xhci_xfer_retry(xfer);
2131 assert(xfer->running_retry);
2132 if (xfer->timed_xfer) {
2133 /* time to kick the transfer? */
2134 mfindex = xhci_mfindex_get(xhci);
2135 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2136 if (xfer->running_retry) {
2137 return;
2138 }
2139 xfer->timed_xfer = 0;
2140 xfer->running_retry = 1;
2141 }
2142 if (xfer->iso_xfer) {
2143 /* retry iso transfer */
2144 if (xhci_setup_packet(xfer) < 0) {
2145 return;
2146 }
2147 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2148 assert(xfer->packet.status != USB_RET_NAK);
2149 xhci_complete_packet(xfer);
2150 } else {
2151 /* retry nak'ed transfer */
2152 if (xhci_setup_packet(xfer) < 0) {
2153 return;
2154 }
2155 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2156 if (xfer->packet.status == USB_RET_NAK) {
2157 return;
2158 }
2159 xhci_complete_packet(xfer);
2160 }
2161 assert(!xfer->running_retry);
2162 epctx->retry = NULL;
2163 }
2164
2165 if (epctx->state == EP_HALTED) {
2166 DPRINTF("xhci: ep halted, not running schedule\n");
2167 return;
2168 }
2169
2170
2171 if (epctx->nr_pstreams) {
2172 uint32_t err;
2173 stctx = xhci_find_stream(epctx, streamid, &err);
2174 if (stctx == NULL) {
2175 return;
2176 }
2177 ring = &stctx->ring;
2178 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
2179 } else {
2180 ring = &epctx->ring;
2181 streamid = 0;
2182 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
2183 }
2184 assert(ring->dequeue != 0);
2185
2186 while (1) {
2187 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
2188 if (xfer->running_async || xfer->running_retry) {
2189 break;
2190 }
2191 length = xhci_ring_chain_length(xhci, ring);
2192 if (length < 0) {
2193 break;
2194 } else if (length == 0) {
2195 break;
2196 }
2197 if (xfer->trbs && xfer->trb_alloced < length) {
2198 xfer->trb_count = 0;
2199 xfer->trb_alloced = 0;
2200 g_free(xfer->trbs);
2201 xfer->trbs = NULL;
2202 }
2203 if (!xfer->trbs) {
2204 xfer->trbs = g_new(XHCITRB, length);
2205 xfer->trb_alloced = length;
2206 }
2207 xfer->trb_count = length;
2208
2209 for (i = 0; i < length; i++) {
2210 TRBType type;
2211 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL);
2212 assert(type);
2213 }
2214 xfer->streamid = streamid;
2215
2216 if (epid == 1) {
2217 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
2218 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2219 } else {
2220 DPRINTF("xhci: error firing CTL transfer\n");
2221 }
2222 } else {
2223 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
2224 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2225 } else {
2226 if (!xfer->timed_xfer) {
2227 DPRINTF("xhci: error firing data transfer\n");
2228 }
2229 }
2230 }
2231
2232 if (epctx->state == EP_HALTED) {
2233 break;
2234 }
2235 if (xfer->running_retry) {
2236 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2237 epctx->retry = xfer;
2238 break;
2239 }
2240 }
2241
2242 ep = xhci_epid_to_usbep(xhci, slotid, epid);
2243 if (ep) {
2244 usb_device_flush_ep_queue(ep->dev, ep);
2245 }
2246 }
2247
2248 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2249 {
2250 trace_usb_xhci_slot_enable(slotid);
2251 assert(slotid >= 1 && slotid <= xhci->numslots);
2252 xhci->slots[slotid-1].enabled = 1;
2253 xhci->slots[slotid-1].uport = NULL;
2254 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2255
2256 return CC_SUCCESS;
2257 }
2258
2259 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2260 {
2261 int i;
2262
2263 trace_usb_xhci_slot_disable(slotid);
2264 assert(slotid >= 1 && slotid <= xhci->numslots);
2265
2266 for (i = 1; i <= 31; i++) {
2267 if (xhci->slots[slotid-1].eps[i-1]) {
2268 xhci_disable_ep(xhci, slotid, i);
2269 }
2270 }
2271
2272 xhci->slots[slotid-1].enabled = 0;
2273 xhci->slots[slotid-1].addressed = 0;
2274 xhci->slots[slotid-1].uport = NULL;
2275 return CC_SUCCESS;
2276 }
2277
2278 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2279 {
2280 USBPort *uport;
2281 char path[32];
2282 int i, pos, port;
2283
2284 port = (slot_ctx[1]>>16) & 0xFF;
2285 if (port < 1 || port > xhci->numports) {
2286 return NULL;
2287 }
2288 port = xhci->ports[port-1].uport->index+1;
2289 pos = snprintf(path, sizeof(path), "%d", port);
2290 for (i = 0; i < 5; i++) {
2291 port = (slot_ctx[0] >> 4*i) & 0x0f;
2292 if (!port) {
2293 break;
2294 }
2295 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2296 }
2297
2298 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2299 if (strcmp(uport->path, path) == 0) {
2300 return uport;
2301 }
2302 }
2303 return NULL;
2304 }
2305
2306 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2307 uint64_t pictx, bool bsr)
2308 {
2309 XHCISlot *slot;
2310 USBPort *uport;
2311 USBDevice *dev;
2312 dma_addr_t ictx, octx, dcbaap;
2313 uint64_t poctx;
2314 uint32_t ictl_ctx[2];
2315 uint32_t slot_ctx[4];
2316 uint32_t ep0_ctx[5];
2317 int i;
2318 TRBCCode res;
2319
2320 assert(slotid >= 1 && slotid <= xhci->numslots);
2321
2322 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2323 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
2324 ictx = xhci_mask64(pictx);
2325 octx = xhci_mask64(poctx);
2326
2327 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2328 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2329
2330 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2331
2332 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2333 DPRINTF("xhci: invalid input context control %08x %08x\n",
2334 ictl_ctx[0], ictl_ctx[1]);
2335 return CC_TRB_ERROR;
2336 }
2337
2338 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2339 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2340
2341 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2342 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2343
2344 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2345 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2346
2347 uport = xhci_lookup_uport(xhci, slot_ctx);
2348 if (uport == NULL) {
2349 DPRINTF("xhci: port not found\n");
2350 return CC_TRB_ERROR;
2351 }
2352 trace_usb_xhci_slot_address(slotid, uport->path);
2353
2354 dev = uport->dev;
2355 if (!dev || !dev->attached) {
2356 DPRINTF("xhci: port %s not connected\n", uport->path);
2357 return CC_USB_TRANSACTION_ERROR;
2358 }
2359
2360 for (i = 0; i < xhci->numslots; i++) {
2361 if (i == slotid-1) {
2362 continue;
2363 }
2364 if (xhci->slots[i].uport == uport) {
2365 DPRINTF("xhci: port %s already assigned to slot %d\n",
2366 uport->path, i+1);
2367 return CC_TRB_ERROR;
2368 }
2369 }
2370
2371 slot = &xhci->slots[slotid-1];
2372 slot->uport = uport;
2373 slot->ctx = octx;
2374
2375 /* Make sure device is in USB_STATE_DEFAULT state */
2376 usb_device_reset(dev);
2377 if (bsr) {
2378 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2379 } else {
2380 USBPacket p;
2381 uint8_t buf[1];
2382
2383 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2384 memset(&p, 0, sizeof(p));
2385 usb_packet_addbuf(&p, buf, sizeof(buf));
2386 usb_packet_setup(&p, USB_TOKEN_OUT,
2387 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2388 0, false, false);
2389 usb_device_handle_control(dev, &p,
2390 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2391 slotid, 0, 0, NULL);
2392 assert(p.status != USB_RET_ASYNC);
2393 }
2394
2395 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2396
2397 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2398 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2399 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2400 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2401
2402 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2403 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2404
2405 xhci->slots[slotid-1].addressed = 1;
2406 return res;
2407 }
2408
2409
2410 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2411 uint64_t pictx, bool dc)
2412 {
2413 dma_addr_t ictx, octx;
2414 uint32_t ictl_ctx[2];
2415 uint32_t slot_ctx[4];
2416 uint32_t islot_ctx[4];
2417 uint32_t ep_ctx[5];
2418 int i;
2419 TRBCCode res;
2420
2421 trace_usb_xhci_slot_configure(slotid);
2422 assert(slotid >= 1 && slotid <= xhci->numslots);
2423
2424 ictx = xhci_mask64(pictx);
2425 octx = xhci->slots[slotid-1].ctx;
2426
2427 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2428 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2429
2430 if (dc) {
2431 for (i = 2; i <= 31; i++) {
2432 if (xhci->slots[slotid-1].eps[i-1]) {
2433 xhci_disable_ep(xhci, slotid, i);
2434 }
2435 }
2436
2437 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2438 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2439 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2440 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2441 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2442 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2443
2444 return CC_SUCCESS;
2445 }
2446
2447 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2448
2449 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2450 DPRINTF("xhci: invalid input context control %08x %08x\n",
2451 ictl_ctx[0], ictl_ctx[1]);
2452 return CC_TRB_ERROR;
2453 }
2454
2455 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2456 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2457
2458 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2459 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
2460 return CC_CONTEXT_STATE_ERROR;
2461 }
2462
2463 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2464
2465 for (i = 2; i <= 31; i++) {
2466 if (ictl_ctx[0] & (1<<i)) {
2467 xhci_disable_ep(xhci, slotid, i);
2468 }
2469 if (ictl_ctx[1] & (1<<i)) {
2470 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2471 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2472 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2473 ep_ctx[3], ep_ctx[4]);
2474 xhci_disable_ep(xhci, slotid, i);
2475 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2476 if (res != CC_SUCCESS) {
2477 return res;
2478 }
2479 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2480 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2481 ep_ctx[3], ep_ctx[4]);
2482 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2483 }
2484 }
2485
2486 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2487 if (res != CC_SUCCESS) {
2488 for (i = 2; i <= 31; i++) {
2489 if (ictl_ctx[1] & (1u << i)) {
2490 xhci_disable_ep(xhci, slotid, i);
2491 }
2492 }
2493 return res;
2494 }
2495
2496 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2497 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2498 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2499 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2500 SLOT_CONTEXT_ENTRIES_SHIFT);
2501 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2502 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2503
2504 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2505
2506 return CC_SUCCESS;
2507 }
2508
2509
2510 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2511 uint64_t pictx)
2512 {
2513 dma_addr_t ictx, octx;
2514 uint32_t ictl_ctx[2];
2515 uint32_t iep0_ctx[5];
2516 uint32_t ep0_ctx[5];
2517 uint32_t islot_ctx[4];
2518 uint32_t slot_ctx[4];
2519
2520 trace_usb_xhci_slot_evaluate(slotid);
2521 assert(slotid >= 1 && slotid <= xhci->numslots);
2522
2523 ictx = xhci_mask64(pictx);
2524 octx = xhci->slots[slotid-1].ctx;
2525
2526 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2527 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2528
2529 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2530
2531 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2532 DPRINTF("xhci: invalid input context control %08x %08x\n",
2533 ictl_ctx[0], ictl_ctx[1]);
2534 return CC_TRB_ERROR;
2535 }
2536
2537 if (ictl_ctx[1] & 0x1) {
2538 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2539
2540 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2541 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2542
2543 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2544
2545 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2546 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2547 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2548 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2549
2550 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2551 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2552
2553 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2554 }
2555
2556 if (ictl_ctx[1] & 0x2) {
2557 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2558
2559 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2560 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2561 iep0_ctx[3], iep0_ctx[4]);
2562
2563 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2564
2565 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2566 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2567
2568 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2569 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2570
2571 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2572 }
2573
2574 return CC_SUCCESS;
2575 }
2576
2577 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2578 {
2579 uint32_t slot_ctx[4];
2580 dma_addr_t octx;
2581 int i;
2582
2583 trace_usb_xhci_slot_reset(slotid);
2584 assert(slotid >= 1 && slotid <= xhci->numslots);
2585
2586 octx = xhci->slots[slotid-1].ctx;
2587
2588 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2589
2590 for (i = 2; i <= 31; i++) {
2591 if (xhci->slots[slotid-1].eps[i-1]) {
2592 xhci_disable_ep(xhci, slotid, i);
2593 }
2594 }
2595
2596 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2597 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2598 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2599 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2600 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2601 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2602
2603 return CC_SUCCESS;
2604 }
2605
2606 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2607 {
2608 unsigned int slotid;
2609 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2610 if (slotid < 1 || slotid > xhci->numslots) {
2611 DPRINTF("xhci: bad slot id %d\n", slotid);
2612 event->ccode = CC_TRB_ERROR;
2613 return 0;
2614 } else if (!xhci->slots[slotid-1].enabled) {
2615 DPRINTF("xhci: slot id %d not enabled\n", slotid);
2616 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2617 return 0;
2618 }
2619 return slotid;
2620 }
2621
2622 /* cleanup slot state on usb device detach */
2623 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2624 {
2625 int slot, ep;
2626
2627 for (slot = 0; slot < xhci->numslots; slot++) {
2628 if (xhci->slots[slot].uport == uport) {
2629 break;
2630 }
2631 }
2632 if (slot == xhci->numslots) {
2633 return;
2634 }
2635
2636 for (ep = 0; ep < 31; ep++) {
2637 if (xhci->slots[slot].eps[ep]) {
2638 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2639 }
2640 }
2641 xhci->slots[slot].uport = NULL;
2642 }
2643
2644 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2645 {
2646 dma_addr_t ctx;
2647 uint8_t bw_ctx[xhci->numports+1];
2648
2649 DPRINTF("xhci_get_port_bandwidth()\n");
2650
2651 ctx = xhci_mask64(pctx);
2652
2653 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2654
2655 /* TODO: actually implement real values here */
2656 bw_ctx[0] = 0;
2657 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2658 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
2659
2660 return CC_SUCCESS;
2661 }
2662
2663 static uint32_t rotl(uint32_t v, unsigned count)
2664 {
2665 count &= 31;
2666 return (v << count) | (v >> (32 - count));
2667 }
2668
2669
2670 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2671 {
2672 uint32_t val;
2673 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2674 val += rotl(lo + 0x49434878, hi & 0x1F);
2675 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2676 return ~val;
2677 }
2678
2679 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2680 {
2681 PCIDevice *pci_dev = PCI_DEVICE(xhci);
2682 uint32_t buf[8];
2683 uint32_t obuf[8];
2684 dma_addr_t paddr = xhci_mask64(addr);
2685
2686 pci_dma_read(pci_dev, paddr, &buf, 32);
2687
2688 memcpy(obuf, buf, sizeof(obuf));
2689
2690 if ((buf[0] & 0xff) == 2) {
2691 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2692 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2693 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2694 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2695 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2696 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2697 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2698 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2699 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2700 }
2701
2702 pci_dma_write(pci_dev, paddr, &obuf, 32);
2703 }
2704
2705 static void xhci_process_commands(XHCIState *xhci)
2706 {
2707 XHCITRB trb;
2708 TRBType type;
2709 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2710 dma_addr_t addr;
2711 unsigned int i, slotid = 0;
2712
2713 DPRINTF("xhci_process_commands()\n");
2714 if (!xhci_running(xhci)) {
2715 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2716 return;
2717 }
2718
2719 xhci->crcr_low |= CRCR_CRR;
2720
2721 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2722 event.ptr = addr;
2723 switch (type) {
2724 case CR_ENABLE_SLOT:
2725 for (i = 0; i < xhci->numslots; i++) {
2726 if (!xhci->slots[i].enabled) {
2727 break;
2728 }
2729 }
2730 if (i >= xhci->numslots) {
2731 DPRINTF("xhci: no device slots available\n");
2732 event.ccode = CC_NO_SLOTS_ERROR;
2733 } else {
2734 slotid = i+1;
2735 event.ccode = xhci_enable_slot(xhci, slotid);
2736 }
2737 break;
2738 case CR_DISABLE_SLOT:
2739 slotid = xhci_get_slot(xhci, &event, &trb);
2740 if (slotid) {
2741 event.ccode = xhci_disable_slot(xhci, slotid);
2742 }
2743 break;
2744 case CR_ADDRESS_DEVICE:
2745 slotid = xhci_get_slot(xhci, &event, &trb);
2746 if (slotid) {
2747 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2748 trb.control & TRB_CR_BSR);
2749 }
2750 break;
2751 case CR_CONFIGURE_ENDPOINT:
2752 slotid = xhci_get_slot(xhci, &event, &trb);
2753 if (slotid) {
2754 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2755 trb.control & TRB_CR_DC);
2756 }
2757 break;
2758 case CR_EVALUATE_CONTEXT:
2759 slotid = xhci_get_slot(xhci, &event, &trb);
2760 if (slotid) {
2761 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2762 }
2763 break;
2764 case CR_STOP_ENDPOINT:
2765 slotid = xhci_get_slot(xhci, &event, &trb);
2766 if (slotid) {
2767 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2768 & TRB_CR_EPID_MASK;
2769 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2770 }
2771 break;
2772 case CR_RESET_ENDPOINT:
2773 slotid = xhci_get_slot(xhci, &event, &trb);
2774 if (slotid) {
2775 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2776 & TRB_CR_EPID_MASK;
2777 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2778 }
2779 break;
2780 case CR_SET_TR_DEQUEUE:
2781 slotid = xhci_get_slot(xhci, &event, &trb);
2782 if (slotid) {
2783 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2784 & TRB_CR_EPID_MASK;
2785 unsigned int streamid = (trb.status >> 16) & 0xffff;
2786 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2787 epid, streamid,
2788 trb.parameter);
2789 }
2790 break;
2791 case CR_RESET_DEVICE:
2792 slotid = xhci_get_slot(xhci, &event, &trb);
2793 if (slotid) {
2794 event.ccode = xhci_reset_slot(xhci, slotid);
2795 }
2796 break;
2797 case CR_GET_PORT_BANDWIDTH:
2798 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2799 break;
2800 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2801 xhci_via_challenge(xhci, trb.parameter);
2802 break;
2803 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2804 event.type = 48; /* NEC reply */
2805 event.length = 0x3025;
2806 break;
2807 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2808 {
2809 uint32_t chi = trb.parameter >> 32;
2810 uint32_t clo = trb.parameter;
2811 uint32_t val = xhci_nec_challenge(chi, clo);
2812 event.length = val & 0xFFFF;
2813 event.epid = val >> 16;
2814 slotid = val >> 24;
2815 event.type = 48; /* NEC reply */
2816 }
2817 break;
2818 default:
2819 trace_usb_xhci_unimplemented("command", type);
2820 event.ccode = CC_TRB_ERROR;
2821 break;
2822 }
2823 event.slotid = slotid;
2824 xhci_event(xhci, &event, 0);
2825 }
2826 }
2827
2828 static bool xhci_port_have_device(XHCIPort *port)
2829 {
2830 if (!port->uport->dev || !port->uport->dev->attached) {
2831 return false; /* no device present */
2832 }
2833 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2834 return false; /* speed mismatch */
2835 }
2836 return true;
2837 }
2838
2839 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2840 {
2841 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2842 port->portnr << 24 };
2843
2844 if ((port->portsc & bits) == bits) {
2845 return;
2846 }
2847 trace_usb_xhci_port_notify(port->portnr, bits);
2848 port->portsc |= bits;
2849 if (!xhci_running(port->xhci)) {
2850 return;
2851 }
2852 xhci_event(port->xhci, &ev, 0);
2853 }
2854
2855 static void xhci_port_update(XHCIPort *port, int is_detach)
2856 {
2857 uint32_t pls = PLS_RX_DETECT;
2858
2859 port->portsc = PORTSC_PP;
2860 if (!is_detach && xhci_port_have_device(port)) {
2861 port->portsc |= PORTSC_CCS;
2862 switch (port->uport->dev->speed) {
2863 case USB_SPEED_LOW:
2864 port->portsc |= PORTSC_SPEED_LOW;
2865 pls = PLS_POLLING;
2866 break;
2867 case USB_SPEED_FULL:
2868 port->portsc |= PORTSC_SPEED_FULL;
2869 pls = PLS_POLLING;
2870 break;
2871 case USB_SPEED_HIGH:
2872 port->portsc |= PORTSC_SPEED_HIGH;
2873 pls = PLS_POLLING;
2874 break;
2875 case USB_SPEED_SUPER:
2876 port->portsc |= PORTSC_SPEED_SUPER;
2877 port->portsc |= PORTSC_PED;
2878 pls = PLS_U0;
2879 break;
2880 }
2881 }
2882 set_field(&port->portsc, pls, PORTSC_PLS);
2883 trace_usb_xhci_port_link(port->portnr, pls);
2884 xhci_port_notify(port, PORTSC_CSC);
2885 }
2886
2887 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2888 {
2889 trace_usb_xhci_port_reset(port->portnr, warm_reset);
2890
2891 if (!xhci_port_have_device(port)) {
2892 return;
2893 }
2894
2895 usb_device_reset(port->uport->dev);
2896
2897 switch (port->uport->dev->speed) {
2898 case USB_SPEED_SUPER:
2899 if (warm_reset) {
2900 port->portsc |= PORTSC_WRC;
2901 }
2902 /* fall through */
2903 case USB_SPEED_LOW:
2904 case USB_SPEED_FULL:
2905 case USB_SPEED_HIGH:
2906 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2907 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2908 port->portsc |= PORTSC_PED;
2909 break;
2910 }
2911
2912 port->portsc &= ~PORTSC_PR;
2913 xhci_port_notify(port, PORTSC_PRC);
2914 }
2915
2916 static void xhci_reset(DeviceState *dev)
2917 {
2918 XHCIState *xhci = XHCI(dev);
2919 int i;
2920
2921 trace_usb_xhci_reset();
2922 if (!(xhci->usbsts & USBSTS_HCH)) {
2923 DPRINTF("xhci: reset while running!\n");
2924 }
2925
2926 xhci->usbcmd = 0;
2927 xhci->usbsts = USBSTS_HCH;
2928 xhci->dnctrl = 0;
2929 xhci->crcr_low = 0;
2930 xhci->crcr_high = 0;
2931 xhci->dcbaap_low = 0;
2932 xhci->dcbaap_high = 0;
2933 xhci->config = 0;
2934
2935 for (i = 0; i < xhci->numslots; i++) {
2936 xhci_disable_slot(xhci, i+1);
2937 }
2938
2939 for (i = 0; i < xhci->numports; i++) {
2940 xhci_port_update(xhci->ports + i, 0);
2941 }
2942
2943 for (i = 0; i < xhci->numintrs; i++) {
2944 xhci->intr[i].iman = 0;
2945 xhci->intr[i].imod = 0;
2946 xhci->intr[i].erstsz = 0;
2947 xhci->intr[i].erstba_low = 0;
2948 xhci->intr[i].erstba_high = 0;
2949 xhci->intr[i].erdp_low = 0;
2950 xhci->intr[i].erdp_high = 0;
2951 xhci->intr[i].msix_used = 0;
2952
2953 xhci->intr[i].er_ep_idx = 0;
2954 xhci->intr[i].er_pcs = 1;
2955 xhci->intr[i].er_full = 0;
2956 xhci->intr[i].ev_buffer_put = 0;
2957 xhci->intr[i].ev_buffer_get = 0;
2958 }
2959
2960 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2961 xhci_mfwrap_update(xhci);
2962 }
2963
2964 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2965 {
2966 XHCIState *xhci = ptr;
2967 uint32_t ret;
2968
2969 switch (reg) {
2970 case 0x00: /* HCIVERSION, CAPLENGTH */
2971 ret = 0x01000000 | LEN_CAP;
2972 break;
2973 case 0x04: /* HCSPARAMS 1 */
2974 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2975 | (xhci->numintrs<<8) | xhci->numslots;
2976 break;
2977 case 0x08: /* HCSPARAMS 2 */
2978 ret = 0x0000000f;
2979 break;
2980 case 0x0c: /* HCSPARAMS 3 */
2981 ret = 0x00000000;
2982 break;
2983 case 0x10: /* HCCPARAMS */
2984 if (sizeof(dma_addr_t) == 4) {
2985 ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
2986 } else {
2987 ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
2988 }
2989 break;
2990 case 0x14: /* DBOFF */
2991 ret = OFF_DOORBELL;
2992 break;
2993 case 0x18: /* RTSOFF */
2994 ret = OFF_RUNTIME;
2995 break;
2996
2997 /* extended capabilities */
2998 case 0x20: /* Supported Protocol:00 */
2999 ret = 0x02000402; /* USB 2.0 */
3000 break;
3001 case 0x24: /* Supported Protocol:04 */
3002 ret = 0x20425355; /* "USB " */
3003 break;
3004 case 0x28: /* Supported Protocol:08 */
3005 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3006 ret = (xhci->numports_2<<8) | (xhci->numports_3+1);
3007 } else {
3008 ret = (xhci->numports_2<<8) | 1;
3009 }
3010 break;
3011 case 0x2c: /* Supported Protocol:0c */
3012 ret = 0x00000000; /* reserved */
3013 break;
3014 case 0x30: /* Supported Protocol:00 */
3015 ret = 0x03000002; /* USB 3.0 */
3016 break;
3017 case 0x34: /* Supported Protocol:04 */
3018 ret = 0x20425355; /* "USB " */
3019 break;
3020 case 0x38: /* Supported Protocol:08 */
3021 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3022 ret = (xhci->numports_3<<8) | 1;
3023 } else {
3024 ret = (xhci->numports_3<<8) | (xhci->numports_2+1);
3025 }
3026 break;
3027 case 0x3c: /* Supported Protocol:0c */
3028 ret = 0x00000000; /* reserved */
3029 break;
3030 default:
3031 trace_usb_xhci_unimplemented("cap read", reg);
3032 ret = 0;
3033 }
3034
3035 trace_usb_xhci_cap_read(reg, ret);
3036 return ret;
3037 }
3038
3039 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
3040 {
3041 XHCIPort *port = ptr;
3042 uint32_t ret;
3043
3044 switch (reg) {
3045 case 0x00: /* PORTSC */
3046 ret = port->portsc;
3047 break;
3048 case 0x04: /* PORTPMSC */
3049 case 0x08: /* PORTLI */
3050 ret = 0;
3051 break;
3052 case 0x0c: /* reserved */
3053 default:
3054 trace_usb_xhci_unimplemented("port read", reg);
3055 ret = 0;
3056 }
3057
3058 trace_usb_xhci_port_read(port->portnr, reg, ret);
3059 return ret;
3060 }
3061
3062 static void xhci_port_write(void *ptr, hwaddr reg,
3063 uint64_t val, unsigned size)
3064 {
3065 XHCIPort *port = ptr;
3066 uint32_t portsc, notify;
3067
3068 trace_usb_xhci_port_write(port->portnr, reg, val);
3069
3070 switch (reg) {
3071 case 0x00: /* PORTSC */
3072 /* write-1-to-start bits */
3073 if (val & PORTSC_WPR) {
3074 xhci_port_reset(port, true);
3075 break;
3076 }
3077 if (val & PORTSC_PR) {
3078 xhci_port_reset(port, false);
3079 break;
3080 }
3081
3082 portsc = port->portsc;
3083 notify = 0;
3084 /* write-1-to-clear bits*/
3085 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
3086 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
3087 if (val & PORTSC_LWS) {
3088 /* overwrite PLS only when LWS=1 */
3089 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
3090 uint32_t new_pls = get_field(val, PORTSC_PLS);
3091 switch (new_pls) {
3092 case PLS_U0:
3093 if (old_pls != PLS_U0) {
3094 set_field(&portsc, new_pls, PORTSC_PLS);
3095 trace_usb_xhci_port_link(port->portnr, new_pls);
3096 notify = PORTSC_PLC;
3097 }
3098 break;
3099 case PLS_U3:
3100 if (old_pls < PLS_U3) {
3101 set_field(&portsc, new_pls, PORTSC_PLS);
3102 trace_usb_xhci_port_link(port->portnr, new_pls);
3103 }
3104 break;
3105 case PLS_RESUME:
3106 /* windows does this for some reason, don't spam stderr */
3107 break;
3108 default:
3109 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
3110 __func__, old_pls, new_pls);
3111 break;
3112 }
3113 }
3114 /* read/write bits */
3115 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
3116 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
3117 port->portsc = portsc;
3118 if (notify) {
3119 xhci_port_notify(port, notify);
3120 }
3121 break;
3122 case 0x04: /* PORTPMSC */
3123 case 0x08: /* PORTLI */
3124 default:
3125 trace_usb_xhci_unimplemented("port write", reg);
3126 }
3127 }
3128
3129 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
3130 {
3131 XHCIState *xhci = ptr;
3132 uint32_t ret;
3133
3134 switch (reg) {
3135 case 0x00: /* USBCMD */
3136 ret = xhci->usbcmd;
3137 break;
3138 case 0x04: /* USBSTS */
3139 ret = xhci->usbsts;
3140 break;
3141 case 0x08: /* PAGESIZE */
3142 ret = 1; /* 4KiB */
3143 break;
3144 case 0x14: /* DNCTRL */
3145 ret = xhci->dnctrl;
3146 break;
3147 case 0x18: /* CRCR low */
3148 ret = xhci->crcr_low & ~0xe;
3149 break;
3150 case 0x1c: /* CRCR high */
3151 ret = xhci->crcr_high;
3152 break;
3153 case 0x30: /* DCBAAP low */
3154 ret = xhci->dcbaap_low;
3155 break;
3156 case 0x34: /* DCBAAP high */
3157 ret = xhci->dcbaap_high;
3158 break;
3159 case 0x38: /* CONFIG */
3160 ret = xhci->config;
3161 break;
3162 default:
3163 trace_usb_xhci_unimplemented("oper read", reg);
3164 ret = 0;
3165 }
3166
3167 trace_usb_xhci_oper_read(reg, ret);
3168 return ret;
3169 }
3170
3171 static void xhci_oper_write(void *ptr, hwaddr reg,
3172 uint64_t val, unsigned size)
3173 {
3174 XHCIState *xhci = ptr;
3175 DeviceState *d = DEVICE(ptr);
3176
3177 trace_usb_xhci_oper_write(reg, val);
3178
3179 switch (reg) {
3180 case 0x00: /* USBCMD */
3181 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
3182 xhci_run(xhci);
3183 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
3184 xhci_stop(xhci);
3185 }
3186 if (val & USBCMD_CSS) {
3187 /* save state */
3188 xhci->usbsts &= ~USBSTS_SRE;
3189 }
3190 if (val & USBCMD_CRS) {
3191 /* restore state */
3192 xhci->usbsts |= USBSTS_SRE;
3193 }
3194 xhci->usbcmd = val & 0xc0f;
3195 xhci_mfwrap_update(xhci);
3196 if (val & USBCMD_HCRST) {
3197 xhci_reset(d);
3198 }
3199 xhci_intx_update(xhci);
3200 break;
3201
3202 case 0x04: /* USBSTS */
3203 /* these bits are write-1-to-clear */
3204 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
3205 xhci_intx_update(xhci);
3206 break;
3207
3208 case 0x14: /* DNCTRL */
3209 xhci->dnctrl = val & 0xffff;
3210 break;
3211 case 0x18: /* CRCR low */
3212 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
3213 break;
3214 case 0x1c: /* CRCR high */
3215 xhci->crcr_high = val;
3216 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
3217 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3218 xhci->crcr_low &= ~CRCR_CRR;
3219 xhci_event(xhci, &event, 0);
3220 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
3221 } else {
3222 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
3223 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3224 }
3225 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
3226 break;
3227 case 0x30: /* DCBAAP low */
3228 xhci->dcbaap_low = val & 0xffffffc0;
3229 break;
3230 case 0x34: /* DCBAAP high */
3231 xhci->dcbaap_high = val;
3232 break;
3233 case 0x38: /* CONFIG */
3234 xhci->config = val & 0xff;
3235 break;
3236 default:
3237 trace_usb_xhci_unimplemented("oper write", reg);
3238 }
3239 }
3240
3241 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3242 unsigned size)
3243 {
3244 XHCIState *xhci = ptr;
3245 uint32_t ret = 0;
3246
3247 if (reg < 0x20) {
3248 switch (reg) {
3249 case 0x00: /* MFINDEX */
3250 ret = xhci_mfindex_get(xhci) & 0x3fff;
3251 break;
3252 default:
3253 trace_usb_xhci_unimplemented("runtime read", reg);
3254 break;
3255 }
3256 } else {
3257 int v = (reg - 0x20) / 0x20;
3258 XHCIInterrupter *intr = &xhci->intr[v];
3259 switch (reg & 0x1f) {
3260 case 0x00: /* IMAN */
3261 ret = intr->iman;
3262 break;
3263 case 0x04: /* IMOD */
3264 ret = intr->imod;
3265 break;
3266 case 0x08: /* ERSTSZ */
3267 ret = intr->erstsz;
3268 break;
3269 case 0x10: /* ERSTBA low */
3270 ret = intr->erstba_low;
3271 break;
3272 case 0x14: /* ERSTBA high */
3273 ret = intr->erstba_high;
3274 break;
3275 case 0x18: /* ERDP low */
3276 ret = intr->erdp_low;
3277 break;
3278 case 0x1c: /* ERDP high */
3279 ret = intr->erdp_high;
3280 break;
3281 }
3282 }
3283
3284 trace_usb_xhci_runtime_read(reg, ret);
3285 return ret;
3286 }
3287
3288 static void xhci_runtime_write(void *ptr, hwaddr reg,
3289 uint64_t val, unsigned size)
3290 {
3291 XHCIState *xhci = ptr;
3292 int v = (reg - 0x20) / 0x20;
3293 XHCIInterrupter *intr = &xhci->intr[v];
3294 trace_usb_xhci_runtime_write(reg, val);
3295
3296 if (reg < 0x20) {
3297 trace_usb_xhci_unimplemented("runtime write", reg);
3298 return;
3299 }
3300
3301 switch (reg & 0x1f) {
3302 case 0x00: /* IMAN */
3303 if (val & IMAN_IP) {
3304 intr->iman &= ~IMAN_IP;
3305 }
3306 intr->iman &= ~IMAN_IE;
3307 intr->iman |= val & IMAN_IE;
3308 if (v == 0) {
3309 xhci_intx_update(xhci);
3310 }
3311 xhci_msix_update(xhci, v);
3312 break;
3313 case 0x04: /* IMOD */
3314 intr->imod = val;
3315 break;
3316 case 0x08: /* ERSTSZ */
3317 intr->erstsz = val & 0xffff;
3318 break;
3319 case 0x10: /* ERSTBA low */
3320 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3321 intr->erstba_low = val & 0xffffffc0; */
3322 intr->erstba_low = val & 0xfffffff0;
3323 break;
3324 case 0x14: /* ERSTBA high */
3325 intr->erstba_high = val;
3326 xhci_er_reset(xhci, v);
3327 break;
3328 case 0x18: /* ERDP low */
3329 if (val & ERDP_EHB) {
3330 intr->erdp_low &= ~ERDP_EHB;
3331 }
3332 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3333 break;
3334 case 0x1c: /* ERDP high */
3335 intr->erdp_high = val;
3336 xhci_events_update(xhci, v);
3337 break;
3338 default:
3339 trace_usb_xhci_unimplemented("oper write", reg);
3340 }
3341 }
3342
3343 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3344 unsigned size)
3345 {
3346 /* doorbells always read as 0 */
3347 trace_usb_xhci_doorbell_read(reg, 0);
3348 return 0;
3349 }
3350
3351 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3352 uint64_t val, unsigned size)
3353 {
3354 XHCIState *xhci = ptr;
3355 unsigned int epid, streamid;
3356
3357 trace_usb_xhci_doorbell_write(reg, val);
3358
3359 if (!xhci_running(xhci)) {
3360 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3361 return;
3362 }
3363
3364 reg >>= 2;
3365
3366 if (reg == 0) {
3367 if (val == 0) {
3368 xhci_process_commands(xhci);
3369 } else {
3370 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3371 (uint32_t)val);
3372 }
3373 } else {
3374 epid = val & 0xff;
3375 streamid = (val >> 16) & 0xffff;
3376 if (reg > xhci->numslots) {
3377 DPRINTF("xhci: bad doorbell %d\n", (int)reg);
3378 } else if (epid > 31) {
3379 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3380 (int)reg, (uint32_t)val);
3381 } else {
3382 xhci_kick_ep(xhci, reg, epid, streamid);
3383 }
3384 }
3385 }
3386
3387 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3388 unsigned width)
3389 {
3390 /* nothing */
3391 }
3392
3393 static const MemoryRegionOps xhci_cap_ops = {
3394 .read = xhci_cap_read,
3395 .write = xhci_cap_write,
3396 .valid.min_access_size = 1,
3397 .valid.max_access_size = 4,
3398 .impl.min_access_size = 4,
3399 .impl.max_access_size = 4,
3400 .endianness = DEVICE_LITTLE_ENDIAN,
3401 };
3402
3403 static const MemoryRegionOps xhci_oper_ops = {
3404 .read = xhci_oper_read,
3405 .write = xhci_oper_write,
3406 .valid.min_access_size = 4,
3407 .valid.max_access_size = 4,
3408 .endianness = DEVICE_LITTLE_ENDIAN,
3409 };
3410
3411 static const MemoryRegionOps xhci_port_ops = {
3412 .read = xhci_port_read,
3413 .write = xhci_port_write,
3414 .valid.min_access_size = 4,
3415 .valid.max_access_size = 4,
3416 .endianness = DEVICE_LITTLE_ENDIAN,
3417 };
3418
3419 static const MemoryRegionOps xhci_runtime_ops = {
3420 .read = xhci_runtime_read,
3421 .write = xhci_runtime_write,
3422 .valid.min_access_size = 4,
3423 .valid.max_access_size = 4,
3424 .endianness = DEVICE_LITTLE_ENDIAN,
3425 };
3426
3427 static const MemoryRegionOps xhci_doorbell_ops = {
3428 .read = xhci_doorbell_read,
3429 .write = xhci_doorbell_write,
3430 .valid.min_access_size = 4,
3431 .valid.max_access_size = 4,
3432 .endianness = DEVICE_LITTLE_ENDIAN,
3433 };
3434
3435 static void xhci_attach(USBPort *usbport)
3436 {
3437 XHCIState *xhci = usbport->opaque;
3438 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3439
3440 xhci_port_update(port, 0);
3441 }
3442
3443 static void xhci_detach(USBPort *usbport)
3444 {
3445 XHCIState *xhci = usbport->opaque;
3446 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3447
3448 xhci_detach_slot(xhci, usbport);
3449 xhci_port_update(port, 1);
3450 }
3451
3452 static void xhci_wakeup(USBPort *usbport)
3453 {
3454 XHCIState *xhci = usbport->opaque;
3455 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3456
3457 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3458 return;
3459 }
3460 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3461 xhci_port_notify(port, PORTSC_PLC);
3462 }
3463
3464 static void xhci_complete(USBPort *port, USBPacket *packet)
3465 {
3466 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3467
3468 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3469 xhci_ep_nuke_one_xfer(xfer, 0);
3470 return;
3471 }
3472 xhci_complete_packet(xfer);
3473 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid);
3474 }
3475
3476 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3477 {
3478 USBBus *bus = usb_bus_from_device(child);
3479 XHCIState *xhci = container_of(bus, XHCIState, bus);
3480
3481 xhci_detach_slot(xhci, child->port);
3482 }
3483
3484 static USBPortOps xhci_uport_ops = {
3485 .attach = xhci_attach,
3486 .detach = xhci_detach,
3487 .wakeup = xhci_wakeup,
3488 .complete = xhci_complete,
3489 .child_detach = xhci_child_detach,
3490 };
3491
3492 static int xhci_find_epid(USBEndpoint *ep)
3493 {
3494 if (ep->nr == 0) {
3495 return 1;
3496 }
3497 if (ep->pid == USB_TOKEN_IN) {
3498 return ep->nr * 2 + 1;
3499 } else {
3500 return ep->nr * 2;
3501 }
3502 }
3503
3504 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
3505 unsigned int slotid, unsigned int epid)
3506 {
3507 assert(slotid >= 1 && slotid <= xhci->numslots);
3508
3509 if (!xhci->slots[slotid - 1].uport) {
3510 return NULL;
3511 }
3512
3513 return usb_ep_get(xhci->slots[slotid - 1].uport->dev,
3514 (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1);
3515 }
3516
3517 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3518 unsigned int stream)
3519 {
3520 XHCIState *xhci = container_of(bus, XHCIState, bus);
3521 int slotid;
3522
3523 DPRINTF("%s\n", __func__);
3524 slotid = ep->dev->addr;
3525 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3526 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3527 return;
3528 }
3529 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3530 }
3531
3532 static USBBusOps xhci_bus_ops = {
3533 .wakeup_endpoint = xhci_wakeup_endpoint,
3534 };
3535
3536 static void usb_xhci_init(XHCIState *xhci)
3537 {
3538 DeviceState *dev = DEVICE(xhci);
3539 XHCIPort *port;
3540 int i, usbports, speedmask;
3541
3542 xhci->usbsts = USBSTS_HCH;
3543
3544 if (xhci->numports_2 > MAXPORTS_2) {
3545 xhci->numports_2 = MAXPORTS_2;
3546 }
3547 if (xhci->numports_3 > MAXPORTS_3) {
3548 xhci->numports_3 = MAXPORTS_3;
3549 }
3550 usbports = MAX(xhci->numports_2, xhci->numports_3);
3551 xhci->numports = xhci->numports_2 + xhci->numports_3;
3552
3553 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
3554
3555 for (i = 0; i < usbports; i++) {
3556 speedmask = 0;
3557 if (i < xhci->numports_2) {
3558 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3559 port = &xhci->ports[i + xhci->numports_3];
3560 port->portnr = i + 1 + xhci->numports_3;
3561 } else {
3562 port = &xhci->ports[i];
3563 port->portnr = i + 1;
3564 }
3565 port->uport = &xhci->uports[i];
3566 port->speedmask =
3567 USB_SPEED_MASK_LOW |
3568 USB_SPEED_MASK_FULL |
3569 USB_SPEED_MASK_HIGH;
3570 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3571 speedmask |= port->speedmask;
3572 }
3573 if (i < xhci->numports_3) {
3574 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3575 port = &xhci->ports[i];
3576 port->portnr = i + 1;
3577 } else {
3578 port = &xhci->ports[i + xhci->numports_2];
3579 port->portnr = i + 1 + xhci->numports_2;
3580 }
3581 port->uport = &xhci->uports[i];
3582 port->speedmask = USB_SPEED_MASK_SUPER;
3583 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3584 speedmask |= port->speedmask;
3585 }
3586 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3587 &xhci_uport_ops, speedmask);
3588 }
3589 }
3590
3591 static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
3592 {
3593 int i, ret;
3594 Error *err = NULL;
3595
3596 XHCIState *xhci = XHCI(dev);
3597
3598 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
3599 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
3600 dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
3601 dev->config[0x60] = 0x30; /* release number */
3602
3603 usb_xhci_init(xhci);
3604
3605 if (xhci->msi != ON_OFF_AUTO_OFF) {
3606 ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err);
3607 /* Any error other than -ENOTSUP(board's MSI support is broken)
3608 * is a programming error */
3609 assert(!ret || ret == -ENOTSUP);
3610 if (ret && xhci->msi == ON_OFF_AUTO_ON) {
3611 /* Can't satisfy user's explicit msi=on request, fail */
3612 error_append_hint(&err, "You have to use msi=auto (default) or "
3613 "msi=off with this machine type.\n");
3614 error_propagate(errp, err);
3615 return;
3616 }
3617 assert(!err || xhci->msi == ON_OFF_AUTO_AUTO);
3618 /* With msi=auto, we fall back to MSI off silently */
3619 error_free(err);
3620 }
3621
3622 if (xhci->numintrs > MAXINTRS) {
3623 xhci->numintrs = MAXINTRS;
3624 }
3625 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3626 xhci->numintrs++;
3627 }
3628 if (xhci->numintrs < 1) {
3629 xhci->numintrs = 1;
3630 }
3631 if (xhci->numslots > MAXSLOTS) {
3632 xhci->numslots = MAXSLOTS;
3633 }
3634 if (xhci->numslots < 1) {
3635 xhci->numslots = 1;
3636 }
3637 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) {
3638 xhci->max_pstreams_mask = 7; /* == 256 primary streams */
3639 } else {
3640 xhci->max_pstreams_mask = 0;
3641 }
3642
3643 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3644
3645 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
3646 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
3647 "capabilities", LEN_CAP);
3648 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
3649 "operational", 0x400);
3650 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
3651 "runtime", LEN_RUNTIME);
3652 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
3653 "doorbell", LEN_DOORBELL);
3654
3655 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3656 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3657 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3658 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3659
3660 for (i = 0; i < xhci->numports; i++) {
3661 XHCIPort *port = &xhci->ports[i];
3662 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3663 port->xhci = xhci;
3664 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
3665 port->name, 0x10);
3666 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3667 }
3668
3669 pci_register_bar(dev, 0,
3670 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
3671 &xhci->mem);
3672
3673 if (pci_bus_is_express(dev->bus) ||
3674 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
3675 ret = pcie_endpoint_cap_init(dev, 0xa0);
3676 assert(ret >= 0);
3677 }
3678
3679 if (xhci->msix != ON_OFF_AUTO_OFF) {
3680 /* TODO check for errors */
3681 msix_init(dev, xhci->numintrs,
3682 &xhci->mem, 0, OFF_MSIX_TABLE,
3683 &xhci->mem, 0, OFF_MSIX_PBA,
3684 0x90);
3685 }
3686 }
3687
3688 static void usb_xhci_exit(PCIDevice *dev)
3689 {
3690 int i;
3691 XHCIState *xhci = XHCI(dev);
3692
3693 trace_usb_xhci_exit();
3694
3695 for (i = 0; i < xhci->numslots; i++) {
3696 xhci_disable_slot(xhci, i + 1);
3697 }
3698
3699 if (xhci->mfwrap_timer) {
3700 timer_del(xhci->mfwrap_timer);
3701 timer_free(xhci->mfwrap_timer);
3702 xhci->mfwrap_timer = NULL;
3703 }
3704
3705 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap);
3706 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper);
3707 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime);
3708 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell);
3709
3710 for (i = 0; i < xhci->numports; i++) {
3711 XHCIPort *port = &xhci->ports[i];
3712 memory_region_del_subregion(&xhci->mem, &port->mem);
3713 }
3714
3715 /* destroy msix memory region */
3716 if (dev->msix_table && dev->msix_pba
3717 && dev->msix_entry_used) {
3718 memory_region_del_subregion(&xhci->mem, &dev->msix_table_mmio);
3719 memory_region_del_subregion(&xhci->mem, &dev->msix_pba_mmio);
3720 }
3721
3722 usb_bus_release(&xhci->bus);
3723 }
3724
3725 static int usb_xhci_post_load(void *opaque, int version_id)
3726 {
3727 XHCIState *xhci = opaque;
3728 PCIDevice *pci_dev = PCI_DEVICE(xhci);
3729 XHCISlot *slot;
3730 XHCIEPContext *epctx;
3731 dma_addr_t dcbaap, pctx;
3732 uint32_t slot_ctx[4];
3733 uint32_t ep_ctx[5];
3734 int slotid, epid, state, intr;
3735
3736 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3737
3738 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3739 slot = &xhci->slots[slotid-1];
3740 if (!slot->addressed) {
3741 continue;
3742 }
3743 slot->ctx =
3744 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
3745 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3746 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3747 if (!slot->uport) {
3748 /* should not happen, but may trigger on guest bugs */
3749 slot->enabled = 0;
3750 slot->addressed = 0;
3751 continue;
3752 }
3753 assert(slot->uport && slot->uport->dev);
3754
3755 for (epid = 1; epid <= 31; epid++) {
3756 pctx = slot->ctx + 32 * epid;
3757 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3758 state = ep_ctx[0] & EP_STATE_MASK;
3759 if (state == EP_DISABLED) {
3760 continue;
3761 }
3762 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3763 slot->eps[epid-1] = epctx;
3764 xhci_init_epctx(epctx, pctx, ep_ctx);
3765 epctx->state = state;
3766 if (state == EP_RUNNING) {
3767 /* kick endpoint after vmload is finished */
3768 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3769 }
3770 }
3771 }
3772
3773 for (intr = 0; intr < xhci->numintrs; intr++) {
3774 if (xhci->intr[intr].msix_used) {
3775 msix_vector_use(pci_dev, intr);
3776 } else {
3777 msix_vector_unuse(pci_dev, intr);
3778 }
3779 }
3780
3781 return 0;
3782 }
3783
3784 static const VMStateDescription vmstate_xhci_ring = {
3785 .name = "xhci-ring",
3786 .version_id = 1,
3787 .fields = (VMStateField[]) {
3788 VMSTATE_UINT64(dequeue, XHCIRing),
3789 VMSTATE_BOOL(ccs, XHCIRing),
3790 VMSTATE_END_OF_LIST()
3791 }
3792 };
3793
3794 static const VMStateDescription vmstate_xhci_port = {
3795 .name = "xhci-port",
3796 .version_id = 1,
3797 .fields = (VMStateField[]) {
3798 VMSTATE_UINT32(portsc, XHCIPort),
3799 VMSTATE_END_OF_LIST()
3800 }
3801 };
3802
3803 static const VMStateDescription vmstate_xhci_slot = {
3804 .name = "xhci-slot",
3805 .version_id = 1,
3806 .fields = (VMStateField[]) {
3807 VMSTATE_BOOL(enabled, XHCISlot),
3808 VMSTATE_BOOL(addressed, XHCISlot),
3809 VMSTATE_END_OF_LIST()
3810 }
3811 };
3812
3813 static const VMStateDescription vmstate_xhci_event = {
3814 .name = "xhci-event",
3815 .version_id = 1,
3816 .fields = (VMStateField[]) {
3817 VMSTATE_UINT32(type, XHCIEvent),
3818 VMSTATE_UINT32(ccode, XHCIEvent),
3819 VMSTATE_UINT64(ptr, XHCIEvent),
3820 VMSTATE_UINT32(length, XHCIEvent),
3821 VMSTATE_UINT32(flags, XHCIEvent),
3822 VMSTATE_UINT8(slotid, XHCIEvent),
3823 VMSTATE_UINT8(epid, XHCIEvent),
3824 VMSTATE_END_OF_LIST()
3825 }
3826 };
3827
3828 static bool xhci_er_full(void *opaque, int version_id)
3829 {
3830 struct XHCIInterrupter *intr = opaque;
3831 return intr->er_full;
3832 }
3833
3834 static const VMStateDescription vmstate_xhci_intr = {
3835 .name = "xhci-intr",
3836 .version_id = 1,
3837 .fields = (VMStateField[]) {
3838 /* registers */
3839 VMSTATE_UINT32(iman, XHCIInterrupter),
3840 VMSTATE_UINT32(imod, XHCIInterrupter),
3841 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3842 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3843 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3844 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3845 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3846
3847 /* state */
3848 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3849 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3850 VMSTATE_UINT64(er_start, XHCIInterrupter),
3851 VMSTATE_UINT32(er_size, XHCIInterrupter),
3852 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3853
3854 /* event queue (used if ring is full) */
3855 VMSTATE_BOOL(er_full, XHCIInterrupter),
3856 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3857 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3858 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3859 xhci_er_full, 1,
3860 vmstate_xhci_event, XHCIEvent),
3861
3862 VMSTATE_END_OF_LIST()
3863 }
3864 };
3865
3866 static const VMStateDescription vmstate_xhci = {
3867 .name = "xhci",
3868 .version_id = 1,
3869 .post_load = usb_xhci_post_load,
3870 .fields = (VMStateField[]) {
3871 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
3872 VMSTATE_MSIX(parent_obj, XHCIState),
3873
3874 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3875 vmstate_xhci_port, XHCIPort),
3876 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3877 vmstate_xhci_slot, XHCISlot),
3878 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3879 vmstate_xhci_intr, XHCIInterrupter),
3880
3881 /* Operational Registers */
3882 VMSTATE_UINT32(usbcmd, XHCIState),
3883 VMSTATE_UINT32(usbsts, XHCIState),
3884 VMSTATE_UINT32(dnctrl, XHCIState),
3885 VMSTATE_UINT32(crcr_low, XHCIState),
3886 VMSTATE_UINT32(crcr_high, XHCIState),
3887 VMSTATE_UINT32(dcbaap_low, XHCIState),
3888 VMSTATE_UINT32(dcbaap_high, XHCIState),
3889 VMSTATE_UINT32(config, XHCIState),
3890
3891 /* Runtime Registers & state */
3892 VMSTATE_INT64(mfindex_start, XHCIState),
3893 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState),
3894 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3895
3896 VMSTATE_END_OF_LIST()
3897 }
3898 };
3899
3900 static Property xhci_properties[] = {
3901 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState, msi, ON_OFF_AUTO_AUTO),
3902 DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState, msix, ON_OFF_AUTO_AUTO),
3903 DEFINE_PROP_BIT("superspeed-ports-first",
3904 XHCIState, flags, XHCI_FLAG_SS_FIRST, true),
3905 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags,
3906 XHCI_FLAG_FORCE_PCIE_ENDCAP, false),
3907 DEFINE_PROP_BIT("streams", XHCIState, flags,
3908 XHCI_FLAG_ENABLE_STREAMS, true),
3909 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
3910 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
3911 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3912 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3913 DEFINE_PROP_END_OF_LIST(),
3914 };
3915
3916 static void xhci_class_init(ObjectClass *klass, void *data)
3917 {
3918 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3919 DeviceClass *dc = DEVICE_CLASS(klass);
3920
3921 dc->vmsd = &vmstate_xhci;
3922 dc->props = xhci_properties;
3923 dc->reset = xhci_reset;
3924 set_bit(DEVICE_CATEGORY_USB, dc->categories);
3925 k->realize = usb_xhci_realize;
3926 k->exit = usb_xhci_exit;
3927 k->vendor_id = PCI_VENDOR_ID_NEC;
3928 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
3929 k->class_id = PCI_CLASS_SERIAL_USB;
3930 k->revision = 0x03;
3931 k->is_express = 1;
3932 }
3933
3934 static const TypeInfo xhci_info = {
3935 .name = TYPE_XHCI,
3936 .parent = TYPE_PCI_DEVICE,
3937 .instance_size = sizeof(XHCIState),
3938 .class_init = xhci_class_init,
3939 };
3940
3941 static void xhci_register_types(void)
3942 {
3943 type_register_static(&xhci_info);
3944 }
3945
3946 type_init(xhci_register_types)
QEmu