target/avr/cpu.c

   1 /*
   2  * QEMU AVR CPU
   3  *
   4  * Copyright (c) 2019-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/qemu-print.h"
  24 #include "exec/exec-all.h"
  25 #include "cpu.h"
  26 #include "disas/dis-asm.h"
  27
  28 static void avr_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     AVRCPU *cpu = AVR_CPU(cs);
  31
  32     cpu->env.pc_w = value / 2; /* internally PC points to words */
  33 }
  34
  35 static bool avr_cpu_has_work(CPUState *cs)
  36 {
  37     AVRCPU *cpu = AVR_CPU(cs);
  38     CPUAVRState *env = &cpu->env;
  39
  40     return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
  41             && cpu_interrupts_enabled(env);
  42 }
  43
  44 static void avr_cpu_synchronize_from_tb(CPUState *cs,
  45                                         const TranslationBlock *tb)
  46 {
  47     AVRCPU *cpu = AVR_CPU(cs);
  48     CPUAVRState *env = &cpu->env;
  49
  50     env->pc_w = tb->pc / 2; /* internally PC points to words */
  51 }
  52
  53 static void avr_cpu_reset(DeviceState *ds)
  54 {
  55     CPUState *cs = CPU(ds);
  56     AVRCPU *cpu = AVR_CPU(cs);
  57     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
  58     CPUAVRState *env = &cpu->env;
  59
  60     mcc->parent_reset(ds);
  61
  62     env->pc_w = 0;
  63     env->sregI = 1;
  64     env->sregC = 0;
  65     env->sregZ = 0;
  66     env->sregN = 0;
  67     env->sregV = 0;
  68     env->sregS = 0;
  69     env->sregH = 0;
  70     env->sregT = 0;
  71
  72     env->rampD = 0;
  73     env->rampX = 0;
  74     env->rampY = 0;
  75     env->rampZ = 0;
  76     env->eind = 0;
  77     env->sp = 0;
  78
  79     env->skip = 0;
  80
  81     memset(env->r, 0, sizeof(env->r));
  82 }
  83
  84 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  85 {
  86     info->mach = bfd_arch_avr;
  87     info->print_insn = avr_print_insn;
  88 }
  89
  90 static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
  91 {
  92     CPUState *cs = CPU(dev);
  93     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
  94     Error *local_err = NULL;
  95
  96     cpu_exec_realizefn(cs, &local_err);
  97     if (local_err != NULL) {
  98         error_propagate(errp, local_err);
  99         return;
 100     }
 101     qemu_init_vcpu(cs);
 102     cpu_reset(cs);
 103
 104     mcc->parent_realize(dev, errp);
 105 }
 106
 107 static void avr_cpu_set_int(void *opaque, int irq, int level)
 108 {
 109     AVRCPU *cpu = opaque;
 110     CPUAVRState *env = &cpu->env;
 111     CPUState *cs = CPU(cpu);
 112     uint64_t mask = (1ull << irq);
 113
 114     if (level) {
 115         env->intsrc |= mask;
 116         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 117     } else {
 118         env->intsrc &= ~mask;
 119         if (env->intsrc == 0) {
 120             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 121         }
 122     }
 123 }
 124
 125 static void avr_cpu_initfn(Object *obj)
 126 {
 127     AVRCPU *cpu = AVR_CPU(obj);
 128
 129     cpu_set_cpustate_pointers(cpu);
 130
 131     /* Set the number of interrupts supported by the CPU. */
 132     qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
 133                       sizeof(cpu->env.intsrc) * 8);
 134 }
 135
 136 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
 137 {
 138     ObjectClass *oc;
 139
 140     oc = object_class_by_name(cpu_model);
 141     if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
 142         object_class_is_abstract(oc)) {
 143         oc = NULL;
 144     }
 145     return oc;
 146 }
 147
 148 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 149 {
 150     AVRCPU *cpu = AVR_CPU(cs);
 151     CPUAVRState *env = &cpu->env;
 152     int i;
 153
 154     qemu_fprintf(f, "\n");
 155     qemu_fprintf(f, "PC:    %06x\n", env->pc_w * 2); /* PC points to words */
 156     qemu_fprintf(f, "SP:      %04x\n", env->sp);
 157     qemu_fprintf(f, "rampD:     %02x\n", env->rampD >> 16);
 158     qemu_fprintf(f, "rampX:     %02x\n", env->rampX >> 16);
 159     qemu_fprintf(f, "rampY:     %02x\n", env->rampY >> 16);
 160     qemu_fprintf(f, "rampZ:     %02x\n", env->rampZ >> 16);
 161     qemu_fprintf(f, "EIND:      %02x\n", env->eind >> 16);
 162     qemu_fprintf(f, "X:       %02x%02x\n", env->r[27], env->r[26]);
 163     qemu_fprintf(f, "Y:       %02x%02x\n", env->r[29], env->r[28]);
 164     qemu_fprintf(f, "Z:       %02x%02x\n", env->r[31], env->r[30]);
 165     qemu_fprintf(f, "SREG:    [ %c %c %c %c %c %c %c %c ]\n",
 166                  env->sregI ? 'I' : '-',
 167                  env->sregT ? 'T' : '-',
 168                  env->sregH ? 'H' : '-',
 169                  env->sregS ? 'S' : '-',
 170                  env->sregV ? 'V' : '-',
 171                  env->sregN ? '-' : 'N', /* Zf has negative logic */
 172                  env->sregZ ? 'Z' : '-',
 173                  env->sregC ? 'I' : '-');
 174     qemu_fprintf(f, "SKIP:    %02x\n", env->skip);
 175
 176     qemu_fprintf(f, "\n");
 177     for (i = 0; i < ARRAY_SIZE(env->r); i++) {
 178         qemu_fprintf(f, "R[%02d]:  %02x   ", i, env->r[i]);
 179
 180         if ((i % 8) == 7) {
 181             qemu_fprintf(f, "\n");
 182         }
 183     }
 184     qemu_fprintf(f, "\n");
 185 }
 186
 187 #include "hw/core/tcg-cpu-ops.h"
 188
 189 static struct TCGCPUOps avr_tcg_ops = {
 190     .initialize = avr_cpu_tcg_init,
 191     .synchronize_from_tb = avr_cpu_synchronize_from_tb,
 192     .cpu_exec_interrupt = avr_cpu_exec_interrupt,
 193     .tlb_fill = avr_cpu_tlb_fill,
 194
 195 #ifndef CONFIG_USER_ONLY
 196     .do_interrupt = avr_cpu_do_interrupt,
 197 #endif /* !CONFIG_USER_ONLY */
 198 };
 199
 200 static void avr_cpu_class_init(ObjectClass *oc, void *data)
 201 {
 202     DeviceClass *dc = DEVICE_CLASS(oc);
 203     CPUClass *cc = CPU_CLASS(oc);
 204     AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
 205
 206     mcc->parent_realize = dc->realize;
 207     dc->realize = avr_cpu_realizefn;
 208
 209     device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
 210
 211     cc->class_by_name = avr_cpu_class_by_name;
 212
 213     cc->has_work = avr_cpu_has_work;
 214     cc->dump_state = avr_cpu_dump_state;
 215     cc->set_pc = avr_cpu_set_pc;
 216     cc->memory_rw_debug = avr_cpu_memory_rw_debug;
 217     cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
 218     cc->vmsd = &vms_avr_cpu;
 219     cc->disas_set_info = avr_cpu_disas_set_info;
 220     cc->gdb_read_register = avr_cpu_gdb_read_register;
 221     cc->gdb_write_register = avr_cpu_gdb_write_register;
 222     cc->gdb_num_core_regs = 35;
 223     cc->gdb_core_xml_file = "avr-cpu.xml";
 224     cc->tcg_ops = &avr_tcg_ops;
 225 }
 226
 227 /*
 228  * Setting features of AVR core type avr5
 229  * --------------------------------------
 230  *
 231  * This type of AVR core is present in the following AVR MCUs:
 232  *
 233  * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c,
 234  * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162,
 235  * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a,
 236  * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa,
 237  * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb,
 238  * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323,
 239  * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p,
 240  * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
 241  * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa,
 242  * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1,
 243  * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644,
 244  * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p,
 245  * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p,
 246  * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p,
 247  * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2,
 248  * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216,
 249  * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000
 250  */
 251 static void avr_avr5_initfn(Object *obj)
 252 {
 253     AVRCPU *cpu = AVR_CPU(obj);
 254     CPUAVRState *env = &cpu->env;
 255
 256     set_avr_feature(env, AVR_FEATURE_LPM);
 257     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 258     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 259     set_avr_feature(env, AVR_FEATURE_SRAM);
 260     set_avr_feature(env, AVR_FEATURE_BREAK);
 261
 262     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 263     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 264     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 265     set_avr_feature(env, AVR_FEATURE_LPMX);
 266     set_avr_feature(env, AVR_FEATURE_MOVW);
 267     set_avr_feature(env, AVR_FEATURE_MUL);
 268 }
 269
 270 /*
 271  * Setting features of AVR core type avr51
 272  * --------------------------------------
 273  *
 274  * This type of AVR core is present in the following AVR MCUs:
 275  *
 276  * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p,
 277  * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
 278  * at90usb1287
 279  */
 280 static void avr_avr51_initfn(Object *obj)
 281 {
 282     AVRCPU *cpu = AVR_CPU(obj);
 283     CPUAVRState *env = &cpu->env;
 284
 285     set_avr_feature(env, AVR_FEATURE_LPM);
 286     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 287     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 288     set_avr_feature(env, AVR_FEATURE_SRAM);
 289     set_avr_feature(env, AVR_FEATURE_BREAK);
 290
 291     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 292     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 293     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 294     set_avr_feature(env, AVR_FEATURE_ELPMX);
 295     set_avr_feature(env, AVR_FEATURE_ELPM);
 296     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 297     set_avr_feature(env, AVR_FEATURE_LPMX);
 298     set_avr_feature(env, AVR_FEATURE_MOVW);
 299     set_avr_feature(env, AVR_FEATURE_MUL);
 300 }
 301
 302 /*
 303  * Setting features of AVR core type avr6
 304  * --------------------------------------
 305  *
 306  * This type of AVR core is present in the following AVR MCUs:
 307  *
 308  * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2
 309  */
 310 static void avr_avr6_initfn(Object *obj)
 311 {
 312     AVRCPU *cpu = AVR_CPU(obj);
 313     CPUAVRState *env = &cpu->env;
 314
 315     set_avr_feature(env, AVR_FEATURE_LPM);
 316     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 317     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 318     set_avr_feature(env, AVR_FEATURE_SRAM);
 319     set_avr_feature(env, AVR_FEATURE_BREAK);
 320
 321     set_avr_feature(env, AVR_FEATURE_3_BYTE_PC);
 322     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 323     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 324     set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL);
 325     set_avr_feature(env, AVR_FEATURE_ELPMX);
 326     set_avr_feature(env, AVR_FEATURE_ELPM);
 327     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 328     set_avr_feature(env, AVR_FEATURE_LPMX);
 329     set_avr_feature(env, AVR_FEATURE_MOVW);
 330     set_avr_feature(env, AVR_FEATURE_MUL);
 331 }
 332
 333 typedef struct AVRCPUInfo {
 334     const char *name;
 335     void (*initfn)(Object *obj);
 336 } AVRCPUInfo;
 337
 338
 339 static void avr_cpu_list_entry(gpointer data, gpointer user_data)
 340 {
 341     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 342
 343     qemu_printf("%s\n", typename);
 344 }
 345
 346 void avr_cpu_list(void)
 347 {
 348     GSList *list;
 349     list = object_class_get_list_sorted(TYPE_AVR_CPU, false);
 350     g_slist_foreach(list, avr_cpu_list_entry, NULL);
 351     g_slist_free(list);
 352 }
 353
 354 #define DEFINE_AVR_CPU_TYPE(model, initfn) \
 355     { \
 356         .parent = TYPE_AVR_CPU, \
 357         .instance_init = initfn, \
 358         .name = AVR_CPU_TYPE_NAME(model), \
 359     }
 360
 361 static const TypeInfo avr_cpu_type_info[] = {
 362     {
 363         .name = TYPE_AVR_CPU,
 364         .parent = TYPE_CPU,
 365         .instance_size = sizeof(AVRCPU),
 366         .instance_init = avr_cpu_initfn,
 367         .class_size = sizeof(AVRCPUClass),
 368         .class_init = avr_cpu_class_init,
 369         .abstract = true,
 370     },
 371     DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
 372     DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
 373     DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
 374 };
 375
 376 DEFINE_TYPES(avr_cpu_type_info)